MSI MS-95F4 Schematic 0C

4321 5

DATE EC NO.

108 976

EC NO.DATE

PART NO.

REL

A

? ?

13N0813

DEVELOPMENT NO.

Q/M

A

PEREGRINE - RoHs

B

Contents:

B

1. TITLE

2. CHANGE LOG

C

C

3. PEREGRINE BLOCK DIAGRAM

4. 405GP INTERFACE TO SDRAM & PCI

5. PPC405 MISC

D

D

6. 405GP PWR/GND & JTAG

7. 405GP BOOTSTRAP

8. 405GP SDRAM (16MB)

E

E

9. 405GP PERIPHERAL BUS

10. FLASH / RTC

11. CLOCK OSCILLATOR & DRIVER

F

12. UART

F

13. RS485 DRIVERS

14. I2C SEEPROM AND SWITCHES

15. ETHERNET PHY

G

G

16. USB & SMP CONNECTOR

17. VIDEO COMPRESSOR

18. COMPRESSOR SDRAM 1MX16X4b

19. POWER / FPGA DECOUPLING

H

H

20. SPARE PARTS

21. Voltage Checks

22. COMPONENT LIST

I

J

13N0813

MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/

CORNER

1 2 3 4 5 6 7 9 108

OUTSIDE MAX
INSIDE MAX

PART NO.

TITLE

SCALE: 1/1

0.13

2.0 APPROVED

13N0813

TITLE

PEREGRINE - ROHS

DESIGNER
CHECKED

SHEET

IBM CONFIDENTIAL

2-15-2005_18:30

RMP NOVEMBER 2004
???
???

1

???
???

OF

I

J

20

4321 5

DATE EC NO.

108 976

EC NO.DATE

PART NO.

REL

A

Change Log:

? ?

13N0813

DEVELOPMENT NO.

Q/M

A

* THIS DESIGN IS A CLEAN-UP FOR RoHs COMPLIANCE OF THE ORGINAL PEREGRINE DESIGN

Therefore, this design is started with ALL the changes through Peregrine Pass 1E. If you need to see
any of the changelog before this on Peregrine, please refer to the Peregrine Pass 1E schematics (13N0793).

B

Pass 2 - 13N0813

01/05 RMP UPDATED ALL COMPONENTS WITH ROHS COMPLIANT PART NUMBERS

B

01/05 RMP CHANGED VIDEO COMPRESSION FPGA FROM XILINX TO ALTERA - PG 17
01/05 RMP CHANGE USB PERIPHERAL FROM FX TO FX2 - PG 16
01/05 RMP ADDED 1.5V REGULATOR FOR ALTERA FPGA - PG 19
Changed I2C Address of PPC SEEPROM - pg 14 - 1/27/05 - RMP

C

D

C

D

E

F

E

F

G

H

I

G

H

I

J

13N0813

MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/

CORNER

1 2 3 4 5 6 7 9 108

OUTSIDE MAX
INSIDE MAX

PART NO.

CHANGE LOG

TITLE

SCALE: 1/1

0.13

2.0 APPROVED

PEREGRINE - ROHS

DESIGNER
CHECKED

SHEET

13N0813

2-15-2005_18:30

RMP NOVEMBER 2004
???
???

2

IBM CONFIDENTIAL

???
???

OF

20

J

4321 5

DATE EC NO.

108 976

EC NO.DATE

PART NO.

REL

? ?

13N0813

DEVELOPMENT NO.

Q/M

I2C/SMBus

A

A

Ethernet

SMP

B

RS485/RS232

B

USB

28.6 MHz
FPGA

16

C

USB

C

50 MHz

CPU

32

D

D

Com Port Block Diagram - NOT VALID FOR LOW COST PEREGRINE

E

MUX

RS485 Driver

Debug Header

Bus A

F

PPC_RESET_N

SYSTEM

MAX6315

PERIPHERAL_RESET_N

USBFPGA

Com1

405GP

SMP

Com2

E

F

RS485 Driver

G

CPU

PPC_NOT_READY_N

Bus B

G

I2C

JTAG

DUART

HOST ID

H

Com4

DUART

H

I

J

JTAG

13N0813

TRST_N

OR

JTAG_RST_N

FLASH

ETHERNET

Com5

NOTE: Low Cost Version has no serial connection to SMP
DUART, MUX, and RS485 Drivers NOPOPed for Low Cost

MUST CONFORM TO ENG

RESET

PEREGRINE BLOCK DIAGRAM

1 2 3 4 5 6 7 9 108

SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/

CORNER

OUTSIDE MAX
INSIDE MAX

PART NO.

13N0813

TITLE

SCALE: 1/1

0.13

2.0 APPROVED

PEREGRINE - ROHS

DESIGNER
CHECKED

SHEET

IBM CONFIDENTIAL

2-15-2005_18:30

RMP NOVEMBER 2004
???
???

3

???
???

OF

I

J

20

4321 5

DATE EC NO.

108 976

EC NO.DATE

PART NO.

REL

? ?

13N0813

DEVELOPMENT NO.

Q/M

A

A

3.3VC

B

B

R552

R553

R554

8.2K

R555

8.2K

R556

8.2K

R557

8.2K

R558

8.2K

R559

8.2K

R560

8.2K

R561

8.2K

R562

8.2K

R563

8.2K

R564

8.2K

R565

8.2K

R566

8.2K

8.2K

8.2K
U53

PCI_PAR

PCI_FRAME#

C

PCI_IRDY#
PCI_TRDY#

PCI_STOP#
PCI_DEVSEL#
PCI_SERR#
PCI_PERR#

5

PCI_RESET#

E26

J24

J23

G26

H23

H25
G24
G25

B24

PCI_PAR

PCI_FRAME_N

PCI_IRDY_N
PCI_TRDY_N

PCI_STOP_N
PCI_DEVSEL_N
PCI_SERR_N
PCI_PERR_N
PCI_RESET_N

Using PCI_RESET# for manufacturing test of insane LED

D

PCI_GNT0#
PCI_GNT1#
PCI_GNT2#
PCI_GNT3#
PCI_GNT4#
PCI_GNT5#

PCI_GNT0# when Internal Arbiter is Used
PCI_REQ# when using External Arbiter

E

PPC405GP-3BE200C

8 MEM_ADD0
8

8
8
8
8
8

F

8
8
8
8
8

MEM_ADD1
MEM_ADD2
MEM_ADD3
MEM_ADD4
MEM_ADD5
MEM_ADD6
MEM_ADD7
MEM_ADD8
MEM_ADD9
MEM_ADD10
MEM_ADD11
MEM_ADD12

8
8

8

G

8
8

MEM_BA0
MEM_BA1

MEM_RAS#
MEM_CAS#
MEM_WE#

R98
R97

R95
R91
R55

DQM Lines swapped to match Data Lines

22
22

22
22
22

8
8
8
8

RES_MEM_BA0
RES_MEM_BA1

RES_MEM_RAS#
RES_MEM_CAS#
RES_MEM_WE#

MEM_DQM3
MEM_DQM2
MEM_DQM1
MEM_DQM0

MEM_DQM_CB

AE22
AC21
AE21
AD21
AF22
AE20
AC19
AE19
AD19
AC18
AF19
AD18
AC17

AB24
AC24

AF24
AB23
AC16

AC12
AC10

AC6
AA3

AC15

M_ADDR0
M_ADDR1
M_ADDR2
M_ADDR3
M_ADDR4
M_ADDR5
M_ADDR6
M_ADDR7
M_ADDR8
M_ADDR9
M_ADDR10
M_ADDR11
M_ADDR12

M_BA0
M_BA1

M_RAS_N
M_CAS_N
M_WE_N

M_DQM0
M_DQM1
M_DQM2
M_DQM3

M_DQM_CB

H

Up to 4 banks possible - Only using 1
NOPOP resistors to allow for hot wiring later if needed.

MEM_CS0#

8

MEM_CS1#

MEM_CS3#

NOPOP
NOPOP
NOPOP

I

8

8

MEM_CLKEN0

MEM_CLK0

R99
R104
R105
R106

R102

R103

22

RES_MEM_BSEL0#

22

RES_MEM_BSEL1#

22

RES_MEM_BSEL2#

22

RES_MEM_BSEL3#

22

22

RES_MEM_CLKEN0

RES_MEM_CLK0

AD17
AF17
AE15
AC14

AB25
AC25

AC26
AA23

M_BANKSEL0_N
M_BANKSEL1_N
M_BANKSEL2_N
M_BANKSEL3_N

M_CLKEN0
M_CLKEN1

M_CLKOUT0
M_CLKOUT1

U53

M_DATA0
M_DATA1
M_DATA2
M_DATA3
M_DATA4
M_DATA5
M_DATA6
M_DATA7
M_DATA8

M_DATA9
M_DATA10
M_DATA11
M_DATA12
M_DATA13
M_DATA14
M_DATA15
M_DATA16
M_DATA17
M_DATA18
M_DATA19
M_DATA20
M_DATA21
M_DATA22
M_DATA23
M_DATA24
M_DATA25
M_DATA26
M_DATA27
M_DATA28
M_DATA29
M_DATA30
M_DATA31

M_ECC0
M_ECC1
M_ECC2
M_ECC3
M_ECC4
M_ECC5
M_ECC6
M_ECC7

M_CLK_IN

AC13
AE12
AD11
AC11
AF10
AE11
AD10
AF9
AD9
AE9
AD8
AF7
AC8
AD7
AE6
AE5
AE4
AD5
AD4
AC5
AD1
AB2
AA4
AA2
AB1
Y2
W4
W2
W3
V4
W1
V3

AE14
AF15
AF14
AD13
AF13
AF12
AE13
AD12

AF4

RN14

1 8

RES_MEM_DATA30 MEM_DATA30
RES_MEM_DATA29
RES_MEM_DATA28
RES_MEM_DATA27
RES_MEM_DATA26
RES_MEM_DATA25
RES_MEM_DATA24
RES_MEM_DATA23
RES_MEM_DATA22

RES_MEM_DATA20

RES_MEM_DATA18

RES_MEM_DATA16 MEM_DATA16

RES_MEM_DATA14

RES_MEM_DATA12

RES_MEM_DATA10

RES_MEM_DATA8
RES_MEM_DATA7
RES_MEM_DATA6
RES_MEM_DATA5
RES_MEM_DATA4
RES_MEM_DATA3
RES_MEM_DATA2
RES_MEM_DATA1

RN14

3 6

RN21

1 8

RN21

3 6

RN15

1 8

RN15

3 6

RN20

1 8

RN20

3 6

RN16

1 8

RN16

3 6

RN19

1 8

RN19

3 6

RN17

1 8

RN17

3 6

RN18

1 8

RN18

3 6

RES_MEM_DATA0

22RES_MEM_DATA31

2 7

22

4 5

22

2 7

22

4 5

22

2 7

22RES_MEM_DATA21

4 5

22RES_MEM_DATA19

2 7

22RES_MEM_DATA17

4 5

22RES_MEM_DATA15

2 7

22RES_MEM_DATA13

4 5

22RES_MEM_DATA11

2 7

22RES_MEM_DATA9

4 5

22

2 7

22

4 5

22

2 7

22

4 5

RN14

RN14

RN21

RN21

RN15

RN15

RN20

RN20

RN16

RN16

RN19

RN19

RN17

RN17

RN18

RN18

MEM_DATA31

22

MEM_DATA29

22

MEM_DATA28
MEM_DATA27

22

MEM_DATA26
MEM_DATA25

22

MEM_DATA24
MEM_DATA23

22

MEM_DATA22
MEM_DATA21

22

MEM_DATA20
MEM_DATA19

22

MEM_DATA18
MEM_DATA17

22

MEM_DATA15

22

MEM_DATA14
MEM_DATA13

22

MEM_DATA12
MEM_DATA11

22

MEM_DATA10
MEM_DATA9

22

MEM_DATA8

MEM_DATA7

22

MEM_DATA6
MEM_DATA5

22

MEM_DATA4
MEM_DATA3

22

MEM_DATA2
MEM_DATA1
MEM_DATA0

22

R365

10K

8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8

8
8

8
8
8
8
8
8

3.3VC

U23

T23

F23
H26
N23

M24

L11

L12

L13

L14

L15

L16

M11
M12
M13
M14
M15
M16

N11
N12
N13
N14
N15
N16
P11
P12
P13
P14
P15
P16
R11
R12
R13
R14
R15
R16

T11

T12

T13

T14

T15

T16

PCI_GNT0_REQ_N
PCI_GNT1_N
PCI_GNT2_N
PCI_GNT3_N
PCI_GNT4_N
PCI_GNT5_N

HS_RTN1
HS_RTN2
HS_RTN3
HS_RTN4
HS_RTN5
HS_RTN6
HS_RTN7
HS_RTN8
HS_RTN9
HS_RTN10
HS_RTN11
HS_RTN12
HS_RTN13
HS_RTN14
HS_RTN15
HS_RTN16
HS_RTN17
HS_RTN18
HS_RTN19
HS_RTN20
HS_RTN21
HS_RTN22
HS_RTN23
HS_RTN24
HS_RTN25
HS_RTN26
HS_RTN27
HS_RTN28
HS_RTN29
HS_RTN30
HS_RTN31
HS_RTN32
HS_RTN33
HS_RTN34
HS_RTN35
HS_RTN36

PPC405GP-3BE200C

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8

PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_C_BE0_N
PCI_C_BE1_N
PCI_C_BE2_N
PCI_C_BE3_N

PCI_IDSEL

PCI_CLK

P_WE_PCI_INT_N

PCI_REQ0_GNT_N

PCI_REQ1_N
PCI_REQ2_N
PCI_REQ3_N
PCI_REQ4_N
PCI_REQ5_N

SPARE_D20
SPARE_Y23
SPARE_Y26

Listed as Reserved in Datasheet

A17
B16
C17
A18
D17
C18
B18
A20
B21
A23
D21
B22
B23
C22
C26
F25
K26
L23
M25
M23
N25
M26
N26
P24
R24
R23
P23
R25
T24
U26
T25
V26

D19
F24
K24
R26

P26

B20
C23

C19
C21
B19
A24
G23
J25

D20
Y23
Y26

R373

From Walnut

5.1K
R366

Asynch Mode Use

10K

P_WE#
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#
PCI_REQ4#
PCI_REQ5#

PCI_REQ0# when Internal Arbiter is Used
PCI_GNT# when using External Arbiter

R94

R579

8.2K

R587

8.2K

PART NO.

R586

8.2K

R585

8.2K

3.3VC

R584

8.2K

R92

8.2K

8.2K

16,17

IBM CONFIDENTIAL

C

D

E

F

G

H

I

J

13N0813

MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/

CORNER

OUTSIDE MAX
INSIDE MAX

1 2 3 4 5 6 7 9 108

13N0813

TITLE

SCALE: 1/1

0.13

2.0 APPROVED

PEREGRINE - ROHS

DESIGNER
CHECKED

SHEET

2-17-2005_11:52

RMP NOVEMBER 2004
???
???

4

???
???

OF

J

20

4321 5

DATE EC NO.

108 976

EC NO.DATE

PART NO.

REL

3.3VC

R597

A

5

B

5

HOST_PWR#

HOST_RST#

R594

0

R551

R595

0

3.3VC

100M

HOST_PWR_REQ#

100M

HOST_PWRGD/RST#

16

Consider bi-directional buffers for next pass.

16

R610

mA

10

330

2CR2

+

VEN_P/D_NUM=597-2401-213
VENDOR=DIALIGHT
COLOR=YELLOW

1

-

R611

mA

10

3.3VC3.3VC

330

2CR3

+

VEN_P/D_NUM=597-2301-213
VENDOR=DIALIGHT
COLOR=GREEN

1

PowerInsane

-

? ?

13N0813

DEVELOPMENT NO.

Q/M

A

B

3.3VC

U53

C

2_5V

C523

100N

D

E

F

G

Internal Timer Input
Not currently used.

SYS_TIMER_CLK

P_HOLD_REQ
P_EXT_REQ#

P_HOLD_PRIORITY
P_BUS_REQ
P_ERROR

Peripheral Bus Controls
NEEDED?

PULLUP to 2.5V for PLL

BLM31A700S

L43

FERRITE

3.3VC

R522

3.3VC

R90

R578

3.3K

3.3K

3.3K

C522

C534

100N

16

R87

16

5

16
16
12

11 33MHZ_405GP

6,10

10U

R520

5

6
6
6
6

R88

1K

PPC_RESET_N
RISCWATCH_HALT#

6

R518

3.3K

USB_HUB_INT
HOST_RST#

HOST_PCI_RST_N

SER_CLK

USB_LATCH_EMPTY

RS232_DETECT
RTC_DUART_INT_N

JTAG_TDI
JTAG_TMS
JTAG_TCK
JTAG_RST_N

1K

R519

3.3K

3.3VC

3.3K

R521

3.3K

A25
D22

AB26

D25

D26

C25
E23

E24
D24

AA24

Y25

Y24
W25
W24

V23

V25

AE24
AC22
AD22
AE26

V1
Y4

T2
R3
B1

SYS_CLOCK
SYS_RESET_N
SYS_HALT_N
SYS_PLL_VDDA

CE0_TEST

DI1

Symbol is wrong on these three pins

DI2

DI1 DI2 RI - All test pins - No biggie.

RI
SYS_TIMER_CLK

IRQ6

GPIO23

IRQ5

GPIO22

IRQ4

GPIO21

IRQ3

GPIO20

IRQ2

GPIO19

IRQ1

GPIO18

IRQ0

GPIO17

JTAG_TDI
JTAG_TMS
JTAG_TCK
JTAG_TRST_N

P_HOLD_REQ
P_EXT_REQ_N

P_HOLD_PRIORITY
P_BUS_REQ
P_ERROR

U88

PPC405GP-3BE200C

SYS_ERROR

JTAG_TDO

P_EXT_RESET_N

P_HOLD_ACK

P_EXT_ACK_N

3.3VC

GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1

P_CLK

AD25

AB3
AC7
AF5
AE8
AC9
AF18
A22
C20
D18

E4

AD23

T3

U2
Y3

ERROR_LED

FPGA = 0, RTC = 1

All GPIO's are high impedance while in reset. refer to 405gp user manual sec 23.5.1

JTAG_TDO

PPC_NOT_READY_N

Output reset to external devices.

P_HOLD_ACK
P_EXT_ACK#

Strapping Pins

PERIPHERAL_RESET_N

U75

HOST_PWR#

X_DONE

I2C_SELECT

R649

49.9

Place close to 405GP

14

7

SER_DATA

FPGA_RTC

X_INIT
X_PROG
GPIO1

6

10,15

7

7,16

ERROR_LED#

43

PERCLK

5

17
5

14

12-14,17

5,7,10

17
7,17
7,16

17

3.3VC

U1

14

12
13

LVC08_TSSOP14_65MM

11

7

ERROR_LED_BUF

PCI_reset is being used as a GPIO

PCI_RESET#

16

4

3.3VC

R647

R646

15
15
15
15

15
15
15

15
15
15

15
15

ENET_PHY_RXD3
ENET_PHY_RXD2
ENET_PHY_RXD1
ENET_PHY_RXD0

ENET_PHY_RX_ERR
ENET_PHY_RX_CLK
ENET_PHY_RX_DV

ENET_PHY_CRS
ENET_PHY_TX_CLK
ENET_PHY_COL

ENET_PHY_MDC
ENET_PHY_MDIO

4.7K

4.7K

12 COM1_RX

12 COM1_CTS#

13 COM2_RX
13

UART_DSR_N = UART1_DSR_N

COM2 - DSR = CTS RTS = DTR

R517

3.3K

COM1_DCD#

COM1_RI#

UART_RX = UART1_RX

SERCLK

COM2_CTS#

U53

PPC405GP-3BE200C
AD20
AC20

AF23

AE23

U24

AF20

V24

W23

E25

AA25

H24

AD26

AE17

AE16
AE18

AB4

AD15

AC1
AC3 AD2

EMC_PHY_RXD3
EMC_PHY_RXD2
EMC_PHY_RXD1
EMC_PHY_RXD0

EMC_PHY_RX_ER
EMC_PHY_RX_CLK
EMC_PHY_RX_DV

EMC_PHY_CRS
EMC_PHY_TX_CLK
EMC_PHY_COL

EMC_MDC
EMC_MDIO

UART_SERCLK

UART0_RX
UART0_DCD_N
UART0_CTS_N
UART0_RI_N

UART_RX
UART_DSR_N UART1_DTR_N

EMC_TXD3
EMC_TXD2
EMC_TXD1
EMC_TXD0

EMC_TX_ER
EMC_TX_EN

UART0_TX
UART0_DSR_N
UART0_DTR_N

UART0_RTS_N

UART1_TX

IIC_SCL

IIC_SDA

P25
L24
L25
J26

K25
K23

AF3
AE3
AF2
AD16

AC2

AD6
AE7

Strapping Pins

ENET_PHY_TX_EN

Strapping Pins

COM1_TX
COM1_DSR#

COM1_DTR#
COM1_RTS#

COM2_TX
COM2_RTS#

I2C_SCL
I2C_SDA

7,15ENET_PHY_TXD3
7,15ENET_PHY_TXD2
7,15ENET_PHY_TXD1
7,15ENET_PHY_TXD0

7,15ENET_PHY_TX_ERR
7,15

7,12

7

7,12

7,13
7,13

14
14

3.3VC

4.7K

C

D

E

F

R648

G

VCC

5

S1

S2

S1

1

3
2

1

IN = 1

IN = 0

IN = 1

6

4

VCC

5

6

IN

D

IN

SER_CLK 5

3.3VC

FPGA_RTC

FPGA = 0, RTC = 1

5,7,10

H

I

IBM CONFIDENTIAL

PART NO.

H

I

10

17

10

CLK

X_CCLK

GND

VENDOR=ST_MICRO
VEN_P/D_NUM=STG3157CTR/LF

U87

DIO

J

13N0813

17

1 2 3 4 5 6 7 9 108

X_DOUT 5SER_DATA

S2

3
2

IN = 0

GND

VENDOR=ST_MICRO
VEN_P/D_NUM=STG3157CTR/LF

D

4

MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/

CORNER

OUTSIDE MAX
INSIDE MAX

PPC405 MISC

SCALE: 1/1

0.13

2.0 APPROVED

13N0813

TITLE

PEREGRINE - ROHS

DESIGNER
CHECKED

SHEET

2-17-2005_11:52

RMP NOVEMBER 2004
???
???

5

???
???

OF

J

20

4321 5

DATE EC NO.

108 976

EC NO.DATE

PART NO.

REL

? ?

13N0813

405GP POWER

2_5V

U53

2_5V

A

B

C

3.3VC

D

E

F

Place one set of THREE (100nF, 10nF, 2.2nF)
per side within 25mils of 405GP
Place 10uF within 100mils of 405GP

C7

10U

C8

10U

Place one set of THREE (100nF, 10nF, 2.2nF)
per side within 25mils of 405GP
Place 10uF within 100mils of 405GP

C9

10U

C59

C61

C66

C69

100N

100N

100N

100N

C60

C62

C65

C68

C328

100N

C330

100N

C332

100N

C334

100N

C329

10N

C331

10N

C333

10N

C335

10N

10N

C494

10N

10N

C496

10N

C63

C64

C72

2.2N

C495

2.2N

C67

2.2N

C497

2.2N

2.2N

2.2N

2.2N

2.2N

3.3VC

AB10
AB11
AB12
AB15
AB16
AB17

E10
E11
E12
E15
E16
E17
K22

K5

L22

L5

M22

M5

R22

R5

T22

T5

U22

U5

AA5

F5
G5
H5

W5

Y5

AB19
AB20
AB21

AB6
AB7
AB8

AA22

F22
G22
H22

W22

Y22

E19

E20

E21

E6
E7
E8
K2

P3
AE10
AD14

U25
N24

B17

C13

P2_5V_AB10
P2_5V_AB11
P2_5V_AB12
P2_5V_AB15
P2_5V_AB16
P2_5V_AB17
P2_5V_E10
P2_5V_E11
P2_5V_E12
P2_5V_E15
P2_5V_E16
P2_5V_E17
P2_5V_K22
P2_5V_K5
P2_5V_L22
P2_5V_L5
P2_5V_M22
P2_5V_M5
P2_5V_R22
P2_5V_R5
P2_5V_T22
P2_5V_T5
P2_5V_U22
P2_5V_U5

P3_3V_AA5
P3_3V_F5
P3_3V_G5
P3_3V_H5
P3_3V_W5
P3_3V_Y5
P3_3V_AB19
P3_3V_AB20
P3_3V_AB21
P3_3V_AB6
P3_3V_AB7
P3_3V_AB8
P3_3V_AA22
P3_3V_F22
P3_3V_G22
P3_3V_H22
P3_3V_W22
P3_3V_Y22
P3_3V_E19
P3_3V_E20
P3_3V_E21
P3_3V_E6
P3_3V_E7
P3_3V_E8
P3_3V_K2
P3_3V_P3
P3_3V_AE10
P3_3V_AD14
P3_3V_U25
P3_3V_N24
P3_3V_B17
P3_3V_C13

PPC405GP-3BE200C

GND_A1
GND_AE1
GND_AF1

GND_A2

GND_B2
GND_AE2

GND_C3
GND_AD3

GND_D4

GND_A11
GND_A16
GND_A21

GND_AC4

GND_E5

GND_A6

GND_J5

GND_AA1

GND_P5

GND_AA26

GND_V5

GND_AB14

GND_AB5

GND_AB18
GND_AB22
GND_AF11

GND_E9
GND_AB9

GND_AF16
GND_AF21

GND_E13
GND_AB13
GND_AF25

GND_AF6

GND_E14

GND_E18

GND_E22

GND_F1

GND_F26

GND_L1

GND_L26

GND_N22

GND_N5
GND_T1

GND_T26

GND_J22

GND_H1

GND_P22

GND_AF8

GND_V22

GND_W26

GND_D23

GND_A19
GND_AC23

GND_C24

GND_AD24

GND_B25
GND_AE25
GND_AF26

GND_A26

GND_B26

A1
AE1
AF1
A2
B2
AE2
C3
AD3
D4
A11
A16
A21
AC4
E5
A6
J5
AA1
P5
AA26
V5
AB14
AB5
AB18
AB22
AF11
E9
AB9
AF16
AF21
E13
AB13
AF25
AF6
E14
E18
E22
F1
F26
L1
L26
N22
N5
T1
T26
J22
H1
P22
AF8
V22
W26
D23
A19
AC23
C24
AD24
B25
AE25
AF26
A26
B26

3.3VC

R583

10K

0

R628

JTAG_TDO

5

JTAG_TDI

5

JTAG_TCK

5

JTAG_TMS

5

RISCWATCH_HALT#

5

R582

10K

R581

10K

R580

10K

NC

NC
NC

1

9

13

NOPOP

J5

C1

C9

C13

CONN2x8HDR_KEY
42F6867
79282-516

C10
C12C11

KEY

C16C15

C2
C4C3
C6C5
C8C7

2
43
65
87
10
1211

1615

NC
NC

R226

1K

R117

10K

3.3VC

PPC_RESET_N

5,10

DEBUG PORT405 RISCWatch and JTAG

TRST_N

3.3VC

U1

14

1
2

LVC08_TSSOP14_65MM

3

7

JTAG_RST_N

5

DEVELOPMENT NO.

Q/M

A

B

C

D

E

F

G

H

I

G

H

I

J

13N0813

405GP PWR/GND & JTAG

MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/

CORNER

1 2 3 4 5 6 7 9 108

OUTSIDE MAX
INSIDE MAX

PART NO.

13N0813

TITLE

SCALE: 1/1

0.13

2.0 APPROVED

PEREGRINE - ROHS

DESIGNER
CHECKED

SHEET

IBM CONFIDENTIAL

2-17-2005_11:52

RMP NOVEMBER 2004
???
???

6

???
???

OF

J

20

4321 5

DATE EC NO.

108 976

EC NO.DATE

PART NO.

REL

A

3.3VC 3.3VC 3.3VC3.3VC3.3VC 3.3VC 3.3VC 3.3VC 3.3VC

? ?

13N0813

DEVELOPMENT NO.

Q/M

A

405GP BOOTSTRAP #1

R64

B

C

PLL Tuning TX DTR RTS
Choice 3 (6 <= M <=7) 0 1 0
Choice 5 (7 < M <=12) 1 0 0
Choice 6 (12 < M <= 32) 1 0 1

PLL Forward Divide Ack0 Ack1
Bypass 0 0
DIV 3 0 1
DIV 4 1 0
DIV 6 1 1

PLL Feedback Divide Ack2 Ack3
DIV 1 0 0
DIV 2 0 1
DIV 3 1 0
DIV 4 1 1

5,12

5

5,12

9

9

9

9

COM1_TX

COM1_DTR#

COM1_RTS#

P_DMA_ACK0
P_DMA_ACK1

P_DMA_ACK2

P_DMA_ACK3

R65

3.3K

POP

R66

3.3K

NOPOP

3.3K

POP

R71

R67

3.3K

NOPOP

3.3K

POP

R68

3.3K

POP

R72

3.3K

NOPOP

R73

R69

3.3K

NOPOP

3.3K

POP

NOPOP

POP

NOPOP

POP

NOPOP

NOPOP

POP

R40

R48

R41

R47
R42

R43

R46

1K

1K

1K

1K
1K

1K

1K

Strap: 1
Strap: 0
Strap: 1

Strap: 0
Strap: 1

Strap: 1

Strap: 0

From Users Guide - Section 7

33 MHz Reference Clock

FWD Divide = 3
PLB Divider from CPU = 2
PLL Feedback Divide = 3

____

M = 18

VCO Stable (MHz) = 600
CPU Speed (MHz) = 200
PLB Speed (MHz) = 100
OPB Speed (MHz) = 50
EPB Speed (MHz) = 50

B

C

PLB Divider from CPU TxD3 TxD2
DIV 1 0 0
DIV 2 0 1

D

DIV 4 1 1

E

5,15

5,15

ENET_PHY_TXD3

POP

ENET_PHY_TXD2

NOPOP

R45

3.3VC

Strap: 0

Strap: 1

D

E

R44

3.3VC3.3VC3.3VC3.3VC3.3VC3.3VC3.3VC 3.3VC3.3VC3.3VC

1K

1K

405GP BOOTSTRAP #2

R85

3.3K

POP

R70

3.3K

POP

POP

NOPOP

NOPOP

NOPOP

R49

R50

R51

R53

1K

1K

1K

1K

Strap: 0
Strap: 1

Strap: 1

Strap: 0

F

3.3K

POP

R80

R86

3.3K

POP

R76

OPB Divider from PLB TxD1 TxD0
DIV 1 0 0

F

DIV 2 0 1
DIV 3 1 0
DIV 4 1 1

PCI Divide from PLB GPIO1 X_PROG
DIV 1 0 0
DIV 2 0 1
DIV 3 1 0
DIV 4 1 1

5,15

5,15

5,16

5,17

ENET_PHY_TXD1

ENET_PHY_TXD0

GPIO1

X_PROG

R74

3.3K

NOPOP

3.3K

POP

R75

R81

3.3K

NOPOP

3.3K

NOPOP

R82

R83

3.3K

NOPOP

3.3K

NOPOP

R84

3.3K

NOPOP

External Bus Divider from PLB TxErr TxEn

G

H

DIV 2 0 0
DIV 3 0 1
DIV 4 1 0
DIV 5 1 1

ROM Width TX DTR#
DIV 8 0 0
DIV 16 0 1
DIV 32 1 0
Reserved 1 1

ROM Location P_HOLD_ACK
Peripheral 0
PCI 1

PCI Synchronous Mode P_EXT_ACK#
Synch 0
Asynch 1

5,15

5,15

5,13

5,13

5

5,16

ENET_PHY_TX_ERR

POP

ENET_PHY_TX_EN

POP

COM2_TX

POP

COM2_RTS#

POP

P_HOLD_ACK

POP

P_EXT_ACK#

NOPOP

R61

R54

R56

R57

R58

R59

1K

1K

1K

1K

1K

1K

Strap: 0

G

Strap: 0

Strap: 0
Strap: 0

H

Strap: 0

Strap: 0

I

J

13N0813

PCI Arbititer Enable FPGA_RTC
Internal Disable 0
Internal Enable 1

1 2 3 4 5 6 7 9 108

5,10

FPGA_RTC

NOPOP

R60

1K

Strap: 1

405GP BOOTSTRAP

MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/

CORNER

OUTSIDE MAX
INSIDE MAX

PART NO.

13N0813

TITLE

SCALE: 1/1

0.13

2.0 APPROVED

PEREGRINE - ROHS

DESIGNER
CHECKED

SHEET

IBM CONFIDENTIAL

2-17-2005_11:52

RMP NOVEMBER 2004
???
???

7

???
???

OF

I

J

20

4321 5

DATE EC NO.

108 976

EC NO.DATE

PART NO.

REL

09/16/03 - JAD - Added MEM_ADD11 net to U83.21

SDRAM Addresssing Mode = 2 (page 15-7 in User's Guide)

12 Bit Row Address

A

B

C

D

E

9 Bit Column Address
2 Bit Bank Selection
Page Size = 2kb

12 bit addressing mode.

3.3VC

U83

1
15
29
43

3

9
35
41
49
55
75
81

MEM_ADD04
4
4
4
4
4
4
4
4
4
4

4
4

MEM_ADD1

MEM_ADD2

MEM_ADD3

MEM_ADD4

MEM_ADD5

MEM_ADD6

MEM_ADD7

MEM_ADD8

MEM_ADD9

MEM_ADD10

MEM_BA0
MEM_BA1

MEM_DQM04
MEM_DQM14
MEM_DQM24
MEM_DQM34

25
26
27
60
61
62
63
64
65
66
24

22
23

16
71
28
59

SDRAM2MX32
VCC0
VCC1
VCC2
VCC3

VCCQ1
VCCQ2
VCCQ3
VCCQ4
VCCQ5
VCCQ6
VCCQ7
VCCQ8

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10

BA0
BA1

DQM0
DQM1
DQM2
DQM3

8nS

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

2
4
5
7
8
10
11
13
74
76
77
79
80
82
83
85
31
33
34
36
37
39
40
42
45
47
48
50
51
53
54
56

MEM_DATA0
MEM_DATA1
MEM_DATA2
MEM_DATA3
MEM_DATA4
MEM_DATA5
MEM_DATA6
MEM_DATA7
MEM_DATA8
MEM_DATA9
MEM_DATA10
MEM_DATA11
MEM_DATA12
MEM_DATA13
MEM_DATA14
MEM_DATA15
MEM_DATA16
MEM_DATA17
MEM_DATA18
MEM_DATA19
MEM_DATA20
MEM_DATA21
MEM_DATA22
MEM_DATA23
MEM_DATA24
MEM_DATA25
MEM_DATA26
MEM_DATA27
MEM_DATA28
MEM_DATA29
MEM_DATA30
MEM_DATA31

4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4

10/08/03 - JAD - Changed U83 IBM P/N from 38L2979 to 36P3308 to upgrade

10/08/03 - JAD - Changed U83 Vendor & Vendor P/N from Samsung K4S643232F-TC7

? ?

the memory part from 8MB to 16MB

to Micron 48LC4M32B2-6F to indicate a representative part of the new IBM P/N.

13N0813

DEVELOPMENT NO.

Q/M

A

B

C

D

E

4

F

G

4
4
4
4
4

MEM_RAS#
MEM_CS0#
MEM_CAS#
MEM_WE#
MEM_CLK0
MEM_CLKEN0

3.3VC

19

RAS_N

20

CS_N

18

CAS_N

17

WE_N

68

CLK

67

CKE

44

GND1

58

GND2

72

GND3

86

GND4

P/D_NUM=36P3308
VENDOR=MICRON
VEN_P/D_NUM=48LC4M32B2-6F

A11/

GNDQ1
GNDQ2
GNDQ3
GNDQ4
GNDQ5
GNDQ6
GNDQ7
GNDQ8

NC

21

6
12
32
38
46
52
78
84

MEM_ADD11

4

F

G

3.3VC

H

C341

I

Place one set of THREE (100nF, 10nF, 2.2nF)
per side within 25mils of module

C340

10N

C75

10N

C76

100N

C502

100N

C503

2.2N

2.2N

C11

place within 50 mils

10U

H

I

IBM CONFIDENTIAL

PART NO.

405GP SDRAM (16MB)

J

13N0813

TITLE

J

13N0813

MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/

CORNER

1 2 3 4 5 6 7 9 108

OUTSIDE MAX
INSIDE MAX

SCALE: 1/1

0.13

2.0 APPROVED

PEREGRINE - ROHS

DESIGNER
CHECKED

SHEET

2-17-2005_11:52

RMP NOVEMBER 2004
???
???

8

???
???

OF

20

4321 5

DATE EC NO.

108 976

EC NO.DATE

PART NO.

REL

A

B

? ?

13N0813

DEVELOPMENT NO.

Q/M

A

B

ROM_DATA[0:31]

10,12,16,17

ROM_DATA0
ROM_DATA1
ROM_DATA2

C

D

3.3VC

E

F

10,12,16,17

G

17

17

17

17

10,17

P_WBE0#
P_WBE1#
P_WBE2#
P_WBE3#

P_R_W#
P_READY
P_BLAST#

P_DMAREQ0
P_DMAREQ1
P_DMAREQ2
P_DMAREQ3

R572

R577

3.3K

R576

3.3K

R575

R574

3.3K

R573

3.3K

3.3K

3.3K

DMA Channels - Not Used

ROM_DATA3
ROM_DATA4
ROM_DATA5
ROM_DATA6
ROM_DATA7
ROM_DATA8
ROM_DATA9
ROM_DATA10
ROM_DATA11
ROM_DATA12
ROM_DATA13
ROM_DATA14
ROM_DATA15
ROM_DATA16
ROM_DATA17
ROM_DATA18
ROM_DATA19
ROM_DATA20
ROM_DATA21
ROM_DATA22
ROM_DATA23
ROM_DATA24
ROM_DATA25
ROM_DATA26
ROM_DATA27
ROM_DATA28
ROM_DATA29
ROM_DATA30
ROM_DATA31

U4
U3
U1

T4

R2

P4

R4

P2

R1

P1
N3
N1

M1

N2

M3
M4

N4

M2

L3
L4

K1

L2

K3

J1

K4

J3
J2

J4
H3
G1
H2
H4

D2

E2
F4

D1

C1

E3
F2

C16
D14
C11

A7

P_DATA0
P_DATA1
P_DATA2
P_DATA3
P_DATA4
P_DATA5
P_DATA6
P_DATA7
P_DATA8
P_DATA9
P_DATA10
P_DATA11
P_DATA12
P_DATA13
P_DATA14
P_DATA15
P_DATA16
P_DATA17
P_DATA18
P_DATA19
P_DATA20
P_DATA21
P_DATA22
P_DATA23
P_DATA24
P_DATA25
P_DATA26
P_DATA27
P_DATA28
P_DATA29
P_DATA30
P_DATA31

P_WBE0_N
P_WBE1_N
P_WBE2_N
P_WBE3_N

P_R_W_N

P_READY
P_BLAST_N

P_DMAREQ0
P_DMAREQ1
P_DMAREQ2
P_DMAREQ3

PPC405GP-3BE200C

U53

P_ADDR0
P_ADDR1
P_ADDR2
P_ADDR3
P_ADDR4
P_ADDR5
P_ADDR6
P_ADDR7
P_ADDR8

P_ADDR9
P_ADDR10
P_ADDR11
P_ADDR12
P_ADDR13
P_ADDR14
P_ADDR15
P_ADDR16
P_ADDR17
P_ADDR18
P_ADDR19
P_ADDR20
P_ADDR21
P_ADDR22
P_ADDR23
P_ADDR24
P_ADDR25
P_ADDR26
P_ADDR27
P_ADDR28
P_ADDR29
P_ADDR30
P_ADDR31

P_PAR0
P_PAR1
P_PAR2
P_PAR3

P_CS0_N
P_CS1_N
P_CS2_N
P_CS3_N
P_CS4_N
P_CS5_N
P_CS6_N
P_CS7_N

P_OE_N

D5
A3
B4
B5
D6
B6
C6
D7
A5
B7
C7
D8
B8
C8
D9
A8
C9
D10
C10
A10
D11
B12
D13
D12
B13
A12
A13
C14
A14
A15
C15
D15

D3
G4
G3
E1

B3
C4
C5
A4
B9
B10
A9
B11

C2

ROM_ADDR0
ROM_ADDR1
ROM_ADDR2
ROM_ADDR3
ROM_ADDR4
ROM_ADDR5
ROM_ADDR6
ROM_ADDR7
ROM_ADDR8
ROM_ADDR9
ROM_ADDR10
ROM_ADDR11
ROM_ADDR12
ROM_ADDR13
ROM_ADDR14
ROM_ADDR15
ROM_ADDR16
ROM_ADDR17
ROM_ADDR18
ROM_ADDR19
ROM_ADDR20
ROM_ADDR21
ROM_ADDR22
ROM_ADDR23
ROM_ADDR24
ROM_ADDR25
ROM_ADDR26
ROM_ADDR27
ROM_ADDR28
ROM_ADDR29
ROM_ADDR30
ROM_ADDR31

GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

Parity Pins - Not Used

P_PAR0
P_PAR1
P_PAR2
P_PAR3

SMI#
I2C_INT#

CABLE_DET#

ROM_ADDR[0:31]

3.3VC

3.3VC

R621

R571

3.3K

10,12,16,17

3.3VC

3.3VC

R62

R77

3.3K

3.3K

NOPOP

R2

3.3K

NOPOP

P_OE#

R16

3.3K

3.3VC3.3VC 3.3VC

R22

10K

10,16,17

3.3K

0

0

3.3VC3.3VC

R5

R542

R603

R9

3.3K

3.3K

0

R543

8 bit

P_CS0#

8 bit

P_CS1#

RS232_SELECT

32 bit

P_CS3#

HOST_SMI#
HOST_I2C_INT#
CABLE_DETECT# 16

GPIO16 16

10

12,16

13,16

17

16
16

C

D

E

F

Bank 0 = Boot ROM
Bank 1 = USB / DUART

Bank 3 = Video Compressor

G

P_DMA_ACK0

R71KR201KR21

H

I

R6

1K

1K

P_DMA_ACK1
P_DMA_ACK2
P_DMA_ACK3

P_DMA_EOT_TC0
P_DMA_EOT_TC1
P_DMA_EOT_TC2
P_DMA_EOT_TC3

D16
B15
B14
C12

F3
G2
V2
Y1

DMA Acks are strapping

DMA Channels - Not Used

R568

R567

1K

R569

1K

R570

1K

P_DMA_ACK0
P_DMA_ACK1
P_DMA_ACK2
P_DMA_ACK3

P_DMA_EOT_TC0
P_DMA_EOT_TC1
P_DMA_EOT_TC2
P_DMA_EOT_TC3

1K

7
7
7
7

H

I

J

13N0813

405GP PERIPHERAL BUS

MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/

CORNER

1 2 3 4 5 6 7 9 108

OUTSIDE MAX
INSIDE MAX

PART NO.

13N0813

TITLE

SCALE: 1/1

0.13

2.0 APPROVED

PEREGRINE - ROHS

DESIGNER
CHECKED

SHEET

IBM CONFIDENTIAL

2-17-2005_11:52

RMP NOVEMBER 2004
???
???

9

???
???

OF

J

20

4321 5

DATE EC NO.

108 976

EC NO.DATE

PART NO.

REL

3.3VC

3.3VC

A

R618

PLACE=ROHS

PLACE=ROHS

SW1

2

1

MH2
MH3

B

MH1

3.3K
U90

MAX6315US29D3-T

3

M_R_N

1 2

GND RESET_N

Vth=2.93

P/D_NUM=77P2178

VCC

140 mS

R619

3.3K

4

POP

PPC_RESET_N

5,6

10/08/03 - JAD - Changed U27 IBM P/N from 73P9309 to 73P9331 in order

to upgrade the codebase from Harrier to Peregrine

10/08/03 - JAD - Changed U27 Coded P/N from 73P9310 to 73P9332 in order

to upgrade the codebase from Harrier to Peregrine

04/27/04 - JAD - Changed U27 IBM P/N from 73P9331 to 13N0778 in order

to update to the correct level of code for all future MSI shipments of Peregrine

04/27/04 - JAD - Changed U27 Coded P/N from 73P9332 to 13N0779 in order

to update to the correct level of code for all future MSI shipments of Peregrine
08/17/04 - JAD - Changed U27 IBM P/N from 13N0778 to 13N0787
08/17/04 - JAD - Changed U27 Coded P/N from 13N0779 to 13N0788

These code changes were made to include a RTC initialization routine

to correctly set up the RTC. There was significant fallout on the

manufacturing line due to the RTC coming up in a "TEST" mode

and not starting.
08/17/04 - JAD - Changed CR1 IBM P/N from 42G3656 to 29L2142 in order

to incorporate two additional parts (Vishay & Fairchild), as the Philips part

has been disqualified by procurment for internal IBM test failures

? ?

13N0813

DEVELOPMENT NO.

Q/M

A

B

3V_BAT

C

R596

Place caps within 25mils of module near power pin

2K

3.3VC

3.3VC

R598

V1=3.0V

V2=3.3v

R599

100K

3.3VC

U27

D

9,12,16,17

E

3.3VC

F

5,15

PPC_NOT_READY_N

R122

4.7K

R458

4.7K

ROM_ADDR[0:31]

ROM_ADDR31
ROM_ADDR30
ROM_ADDR29
ROM_ADDR28
ROM_ADDR27
ROM_ADDR26
ROM_ADDR25
ROM_ADDR24
ROM_ADDR23
ROM_ADDR22
ROM_ADDR21
ROM_ADDR20
ROM_ADDR19
ROM_ADDR18
ROM_ADDR17
ROM_ADDR16
ROM_ADDR15
ROM_ADDR14
ROM_ADDR13
ROM_ADDR12
ROM_ADDR11
ROM_ADDR10

FLASHWP_N

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21

45
25
24
23
22
21
20
19
18

8
7
6
5
4
3
2

1
48
17
16

9
10
13

12
14

FLASH

FEPROM4MX8

(BYTE MODE data)

DQ15_A1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
NC

RESET_N
WP_N

(A0)
(A1)
(A2)
(A3)
(A4)
(A5)
(A6)
(A7)
(A8)
(A9)
(A10)
(A11)
(A12)
(A13)
(A14)
(A15)
(A16)
(A17)
(A18)
(A19)
(A20)
(A21)
(UNDEFINED)

VCC

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14

BYTE_N

RY_BY_N

37

29
31
33
35
38
40
42
44
30
32
34
36
39
41
43

15

47

ROM_DATA7
ROM_DATA6
ROM_DATA5
ROM_DATA4
ROM_DATA3
ROM_DATA2
ROM_DATA1
ROM_DATA0

P_READY

C349

C93

100N

ROM_DATA[0:31]

R52

9,17

100

C507

10N

2.2N

9,12,16,17

12

5,7

R622

AIRQ_INT_N
RTC_INT_N

FPGA_RTC

5

5

CLK
DIO

R623

2K

The forward bias voltage of these diodes is less than 200mV.
There shouldn't be any curent drain from the battery when the system is powered since diode 13 is reverse bias.

1K

V13= -100mV

P/D_NUM=77P1775

CR1

1

V3=3.1V

3

2

DIO_BAT54C_NL

V23=200mV

C551

100K

R602

V

100N

100K

30

C552

PWR_RTC

100N

U89

Place caps as close as possible

1

VDD2

2

VEX

10

VDD

4

AIRQ_N

5

TIRQ_N

6

CE

7

CLK

8

DI

9

DO

VENDOR=EPSON
VEN_P/D_NUM=RTC-9701JEB-0

RTC-9701JE

VSOJ20

GND_13
GND_12

FOUT

FOE

13
12

3
11

0.8uA @ 3V Typ. (6.85 Years with 48mAh battery)

C

D

E

F

R232

G

Pin 14 hi = 16K boot block not protected
Pin 14 Low = 16K boot block protected

User Guide - Section 16.6.2 - Boot ROM must be attached to Bank 0.

H

1K

NOPOP

9,16,17

9,12,16,17

9

P_CS0#
P_OE#
P_R_W#

3.3VC

C493

Place within 100 mils of flash

10U

26

CE_N

28

OE_N

11

WE_N

CODED_P/N=TBD
VEN_P/D_NUM=M29W320DB70N6E
P/D_NUM=77P2396

GND0
GND1

46
27

G

H

Get new code PN

I

J

13N0813

MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/

CORNER

1 2 3 4 5 6 7 9 108

OUTSIDE MAX
INSIDE MAX

PART NO.

FLASH / RTC

SCALE: 1/1

0.13

2.0 APPROVED

13N0813

TITLE

PEREGRINE - ROHS

DESIGNER
CHECKED

SHEET

IBM CONFIDENTIAL

2-17-2005_11:52

RMP NOVEMBER 2004
???
???

10

???
???

OF

I

J

20

4321 5

DATE EC NO.

108 976

EC NO.DATE

PART NO.

REL

A

B

3.3VC

? ?

13N0813

DEVELOPMENT NO.

Q/M

A

B

L1

2

C

C3

100N

D

BLM21P300S

C4

100N

11

11

R36

R32 10K

R23 10K RES_CY2292_S2

10K

10KR35

25MHZ_XTALIN
25MHZ_XTALOUT

RES_2292_OE

RES_CY2292_S0

RES_CY2292_S1

VCC2

14

VCC14

4

XTALIN

5

XTALOUT

16

SHUTDOWN_N_OE

12

S0

13

S1

15

S2_SUSPEND_N

P/D_NUM=77P3140
PKG_TYPE=TSSOP16_65MM
CYPRESS
VEN_P/D_NUM=CY22392FXCT
CODED_P/N=TBD

U101

CY22392FC

XBUF

CLKA
CLKB
CLKC
CLKD
CLKE

GND3

GND11

6

10
9
1
7
8

3
11

R655

R656 40.2

R657

NOPOP

R658

NOPOP

R659
R660

40.2

NOPOP

24.9

24.9

24.9

24.9

C558

15P

C21

15P

NOPOP

C19

15P

NOPOP

CLK_25MHZ_BCMPWR3_3VC_CY2292

C14

15P

NOPOP

33MHZ_405GP

USB_FX2_24MHZ

15

5

16

C

D

405GP CLOCK = 33.1776MHz

(1.8432MHz*2*9)

DUART_XTAL1 = 23.5 MHz

E

3.3VC

F

150

R63

NOPOP

R4

100K

NOPOP

25MHZ_XTALOUT

11

11

25MHZ_XTALIN

E

F

G

Keep crystal circuit close to CY22392

C6

33P

NOPOP

H

Y1

1 4

25M

Hz

EPSON

MA-306_25.0000M-C

C10

G

33P

NOPOP

H

I

J

13N0813

CLOCK OSCILLATOR & DRIVER

MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/

CORNER

1 2 3 4 5 6 7 9 108

OUTSIDE MAX
INSIDE MAX

PART NO.

13N0813

TITLE

SCALE: 1/1

0.13

2.0 APPROVED

PEREGRINE - ROHS

DESIGNER
CHECKED

SHEET

IBM CONFIDENTIAL

2-17-2005_11:52

RMP NOVEMBER 2004
???
???

11

???
???

OF

I

J

20

4321 5

DATE EC NO.

108 976

EC NO.DATE

PART NO.

REL

3.3VC

A

R630

2K

PLACE=ROHS

12

B

DUART_XTAL1

PLACE=ROHS

14.7456M Hz

R631

100M

Y2

1 2

VEN_P/D_NUM=CS1014.7456MABJTR

VENDOR=CITIZEN

NOPOP

DUART_XTAL2

12

Make DUART_XTAL* nodes as short as possible!!!
Keep crystal circuit close to DUART

? ?

13N0813

DEVELOPMENT NO.

Q/M

A

B

C556

PLACE=ROHS

33P

C

D

E

C557

9,10,12,16,17

PLACE=ROHS

33P

ROM_ADDR[0:31]

ROM_ADDR12 = 0, selects duart

= 1, selects USB

9,16

9,10,12,16,17

ROM_ADDR12

P_CS1#

9,10,16,17

U79

12
13

3.3VC

14

7

ROM_ADDR[0:31]

ROM_DATA[0:31]

11

9,10,16,17

12

3.3VC

ROM_ADDR31
ROM_ADDR30
ROM_ADDR29
ROM_ADDR28

ROM_DATA7
ROM_DATA6
ROM_DATA5
ROM_DATA4
ROM_DATA3
ROM_DATA2
ROM_DATA1
ROM_DATA0

DUART_CS#
P_R_W#

DUART_INT_N

U99

42
19

28
27
26
11

44
45
46
47
48

1
2
3

10
15

30

VCC_42
VCC_19

A0
A1
A2
A3

D0
D1
D2
D3
D4
D5
D6
D7

CS#
R/W#

IRQ#

COM4

DUART

TXA

RXA
RTSA#
CTSA#

DTRA#
DSRA#

CDA#

RIA#

OP2A#

7
5
33
38
34
39
40
41
32

COM4_TX
COM4_RX
COM4_RTS#
COM4_CTS#
COM4_DTR#
COM4_DSR#
COM4_CD#
COM4_RI#

16
16
16
16
16
16
16

3.3VC

4.7K

C

R640

D

E

3.3VC

R632

F

RTC_DUART_INT_N

5

LVC08_TSSOP14_65MM

G

3.3VC

14

8

U1

9
10

7

3.3K

DUART_INT_N

RTC_INT_N

12

10

PLACE=ROHS

5,13,14,17

4.7K

NOPOP

4.7K

PERIPHERAL_RESET_N

3.3VC3.3VC

PLACE=ROHS

R633

4.7K

NOPOP

R634

4.7K

R635

R636

12
12

DUART_XTAL1
DUART_XTAL2

R644

PLACE=ROHS

R645

0

0

PLACE=ROHS

43

TXRDYA#

31

RXRDYA#

6

TXRDYB#

18

RXRDYB#

13

XTAL1

14

XTAL2

12

PWRSAVE

25

CLKSEL

37

HDCNTL#

36

RESET#

24

16/68#

17

GND

PLACE=ROHS

VENDOR=EXAR
VEN_P/D_NUM=XR16L2751CM-F

P/D_NUM=77P1880

COM5

TXB

RXB
RTSB#
CTSB#

DTRB#
DSRB#

CDB#

RIB#

OP2B#

8
4
22
23
35
20
16
21
9

COM5_TX
COM5_RX
COM5_RTS#
COM5_CTS#
COM5_DTR#

COM5_DSR#

COM5_CD#
COM5_RI#

13
13
13
13

16
16
16
16

5,7
5,7

5
5

3.3VC

COM1_TX
COM1_RTS#
COM1_RX
COM1_CTS#

J28

1

C1

2

C2

3

C3

4

C4

5

C5

6

C6

VENDOR=MOLEX
VEN_P/D_NUM=53780-0690

F

G

H

I

H

I

IBM CONFIDENTIAL

PART NO.

UART

J

13N0813

TITLE

J

13N0813

MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/

CORNER

1 2 3 4 5 6 7 9 108

OUTSIDE MAX
INSIDE MAX

SCALE: 1/1

0.13

2.0 APPROVED

PEREGRINE - ROHS

DESIGNER
CHECKED

SHEET

2-17-2005_11:52

RMP NOVEMBER 2004
???
???

12

???
???

OF

20

4321 5

DATE EC NO.

108 976

EC NO.DATE

PART NO.

REL

A

B

? ?

13N0813

DEVELOPMENT NO.

Q/M

A

B

C

5,12,14,17

9,16

D

12

12

12

E

12

F

RS232_SELECT

3.3VC

16
PWR

COM5_RX

COM5_CTS#

COM5_RTS#

COM5_TX

PLACE=ROHS

VEN_P/D_NUM=SN74CBTLV3257PWR

12

4

1A

7

2A

9

3A

4A

GND

8

VENDOR=TI

PERIPHERAL_RESET_N

U96

15

OE

1

S

COM5_232RX

2

1B1

3

1B2

COM5_232CTS#

5

2B1

6

2B2

COM5_232RTS#

11

3B1

10

3B2
4B1
4B2

COM5_232TX

14
13

16

16

16

16

R680

PLACE=ROHS

0

R679

0

PLACE=ROHS

PLACE=LC

USB_RST_N

4.7K

R678

PLACE=LC

3.3VC

R237

R650

1K

R485_A_RTS_N 485_A_RTS

PLACE=ROHS

10K

U34

AHC04_SO14N

PLACE=ROHS

R485

14

1 2

7

0

16

NOPOP

485_A_RX

485_A_CTS_N

485_A_TX

U5

RO VCC

1 8

RE_N

2

DE

3

DI GND

4

RS485DRIVER

PLACE=ROHS

B

-

A

+

SOIC8

ST_MICRO
ST1480ABDTR/LF

3.3VC

R457

PLACE=ROHS

3.3VC

R158

120

7
6
5

C96

R456

100N

PLACE=ROHS

PLACE=ROHS

27K

PLACE=ROHS

C52

4.7N

PLACE=ROHS

27K

C246

PLACE=ROHS

220P

485_N_BUS_A

485_P_BUS_A

RS 485 Bus A

16
16

C

D

E

F

G

3.3VC

R454

PLACE=ROHS

H

U6

R483

0

U34

5,7

I

COM2_RTS#

AHC04_SO14N

PLACE=ROHS

NOPOP

43

5,7

5

5

COM2_RX

COM2_CTS#

COM2_TX

R238

PLACE=ROHS

1K

RO VCC

1 8

RE_N

2

DE

3

DI GND

4

ST_MICRO
ST1480ABDTR/LF

RS485DRIVER

PLACE=ROHS

SOIC8

B

-

7

A

+

6
5

3.3VC

C97

PLACE=ROHS

100N

R455

R157

120

PLACE=ROHS

PLACE=ROHS

27K

C51

4.7N

PLACE=ROHS

27K

C241

PLACE=ROHS

220P

485_N_BUS_B
485_P_BUS_B

RS 485 Bus B

16
16

Keep inductor/capacitor filter near connector

IBM CONFIDENTIAL

G

H

I

J

13N0813

MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/

CORNER

1 2 3 4 5 6 7 9 108

OUTSIDE MAX
INSIDE MAX

RS485 DRIVERS

SCALE: 1/1

0.13

2.0 APPROVED

PART NO.

13N0813

TITLE

PEREGRINE - ROHS

2-17-2005_11:52

DESIGNER
CHECKED

SHEET

RMP NOVEMBER 2004
???
???

13

???
???

OF

J

20

4321 5

DATE EC NO.

108 976

EC NO.DATE

PART NO.

REL

3.3VC

A

10K

R514

I2C_SELECT

5

SEEPROM = 0, HOST = 1

3.3VC

B

3.3VC
U92

? ?

13N0813

DEVELOPMENT NO.

Q/M

A

B

VCC

IN

5

6

D

4

R495

POP

C

10K

R17

10K

POP

SCL

IN = 1

IN = 0

S1

1

S2

3
2

GND

TO HOST

HOST_I2C_SCL
HOST_I2C_SDA

16

16

C

Low C I2C Addr = 0xA4
RoHs I2C Addr = 0xA6

3.3VC

VENDOR=ST_MICRO

I2C_SCL

5

D

5

I2C_SDA

3.3VC

FROM 405GP

3.3VC
J1

1

C1

E

2

C2

3

C3

4

C4

CONN1X4

MAIN I2C BUS Debug Connector

VEN_P/D_NUM=STG3157CTR/LF

U93

VCC

5

IN

6

D

4

VEN_P/D_NUM=STG3157CTR/LF

SDA

IN = 1

IN = 0

VENDOR=ST_MICRO

S1

1

S2

3
2

GND

R609

POP

R608

100K

100K

POP

SEEPROM_SCL
SEEPROM_SDA

3.3VC

A1
A2SCL

GND

U91

2
36
4

EEPROM

VCC A0

8 1

WP

7

SDA

5

SERIAL-I2C

VENDOR=ST_MICRO

VEN_P/D_NUM=M24C64-WMN6T

0

R681

0

R682

PLACE=ROHS

100N

PLACE=LC

C553

3.3VC

D

E

3.3VC3.3VC3.3VC

NOPOP

3.3VC

U3

PCA9557

TSSOP16

IO_OVCC

IO_1
IO_2
IO_3
IO_4
IO_5
IO_6
IO_7

GND

616
7
9
10
11
12
13
14

8

R604

POP

3.3VC

2K

R605

POP

2K

3.3VC

VCC

IN

F

G

5

6

PLACE=LC

R638

0

SCL

IN = 1

1

U94

S1

R606

POP

3.3VC

R607

100K

POP

100K

5,12,13,17

PERIPHERAL_RESET_N

3
4
5

15

1
2

A0
A1
A2

RESET_N

SCL
SDA

R79

POP

R78

100K

POP

R93

100K

POP

R89

100K

POP

R109

100K

POP

R96

100K

POP

R112

100K

POP

R111

100K

POP

100K

HOST_ID0
HOST_ID1
HOST_ID2
HOST_ID3
HOST_ID4
HOST_ID5
HOST_ID6
HOST_ID7

16

16

16

16

16

16

16

16

These pins are used identify the host that harrier is plugged into.

F

G

Each host will have a unique ID

D

4

IN = 0

PLACE=ROHS

S2

3
2

GND

Crows = 0
Magpie = 1

H

I

J

13N0813

VENDOR=ST_MICRO

16

16

USB_SCL
USB_SDA

3.3VC

FROM EZUSB

1 2 3 4 5 6 7 9 108

VEN_P/D_NUM=STG3157CTR/LF

U95

VCC

5

IN

6

D

4

VEN_P/D_NUM=STG3157CTR/LF

SDA

IN = 1

IN = 0

PLACE=ROHS

VENDOR=ST_MICRO

PLACE=LC

R639

0

1

3
2

S1

S2

GND

I2C SEEPROM AND SWITCHES

MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/

CORNER

OUTSIDE MAX
INSIDE MAX

PART NO.

13N0813

TITLE

SCALE: 1/1

0.13

2.0 APPROVED

PEREGRINE - ROHS

DESIGNER
CHECKED

SHEET

IBM CONFIDENTIAL

2-17-2005_11:52

RMP NOVEMBER 2004
???
???

14

???
???

OF

H

I

J

20

4321 5

DATE EC NO.

108 976

EC NO.DATE

PART NO.

REL

A

B

3.3VC

+1%/-1%

49.9

+1%/-1%

49.9

? ?

13N0813

DEVELOPMENT NO.

Q/M

A

B

1N

1N

3
20
2
55
27
28
22
46
8
1
32
29
24
40
54
63
45
7

R34

+5%/-5%

+1%/-1%

49.9

R33

+5%/-5%

R612

0

3.3VC

100N

C5

Place all power caps as close to BCM5221 as possible.

3.3VC

C20

C518

ENET_PHY_RX_CLK

5

C13

5
5
5

5

5

100P

100N

3.3VC

10U

NOPOP

C17

place within one inch of BCM5221

5

2.2U

C1

C15

100N

MATCHING LENGTHS, SAME LAYER FOR PAIRS (50 Ohm SE, 100 Ohm Diff)

R613

0

C18

10N

R614

R615

0

C16

2.2UC2100N

ENET_PHY_TX

ENET_PHY_TX_N

ENET_PHY_RX

0

10N

ENET_PHY_RX_N

16
16

16

16

Please refer to "General Layout Notes" pg17 of BCM5221_apnote.pdf in /harrier/reference/

C

D

E

F

G

R15

C520

C

D

+1%/-1%

R8

1.27K

E

Place RDAC resistor as close as possible to BCM5221

3.3VC

NOPOP

4.7K

F

NOPOP

4.7K

G

NOPOP

R26

NOPOP

R27

4.7K

4.7K

NOPOP

4.7K

R25

NOPOP

4.7K

R24

R28

R29

PPC_NOT_READY_N

5,10

ENET_PHY_LNK_LED_N

16

ENET_PHY_ACT_LED_N

16

JTAG_EN_TP

3.3VC

CLK_25MHZ_BCM

11

ENET_PHY_TX_CLK

5

ENET_PHY_TXD3

C12

NOPOP

100P

5,7

ENET_PHY_TXD2

5,7

ENET_PHY_TXD1

5,7

ENET_PHY_TXD0

5,7

ENET_PHY_TX_EN

5,7

ENET_PHY_TX_ERR

5,7

----68 Ohm characteristic impedance-----

U2

9

RESET_N

17

ENERGY_DET

ENET_PHY_RDAC

4.7K

R30

-------------68 Ohm characteristic impedance--------------

4.7K

R31

NOPOP

NOPOP

23

RDAC

35

LNKLED_N

36

SPDLED_N

34

XMTLED_N

33

RCVLED_N

64

JTAG_EN

10

PHYAD0

11

PHYAD1

12

PHYAD2

13

PHYAD3

14

PHYAD4

39

FDX

37

F100

38

ANEN

21

SD+

19

SD-

15

TESTEN

18

MII_EN

16

LOW_PWR

BCM5221KPT TQFP64_5MM

ENET_PHY_MDC

5

ENET_PHY_MDIO

5

ENET_PHY_COL

5

ENET_PHY_CRS

5

place 1nF capacitors as close as possible to 49.9 ohm resistors

R11

33.2

4.7K

4

52565758596053

TXER

TXEN

TXD0

TXD1

TXD2

TXD3

TXC

5

REF_CLK

XTALO

BCM5221

MDC

MDIO

COL

CRS/CRS_DV

RXER

RXDV

4241616251494847444350

3.3VC

R19

1.5K

POP

R511

6

31

XTALI

TD+

RXD0

30

TD-

RXD1

RXD2

R1

22.1

26

RD+

RXD3

25

RD-

RXC

49.9 ohm resistors close to PHY

+1%/-1%

49.9

R18

REGDVDD
REGAVDD

DVDD_2
DVDD_55
AVDD_27
AVDD_28
BIASVDD

OVDD_46

OVDD_8

OVDD_1

AGND_32
AGND_29

BIASGND

DGND_40
DGND_54
DGND_63
DGND_45

XTALGND

R12

33.2

ENET_PHY_RXD3
ENET_PHY_RXD2
ENET_PHY_RXD1
ENET_PHY_RXD0

ENET_PHY_RX_DV

ENET_PHY_RX_ERR

3.3VC

C519

H

I

R13

R14
10K

NOPOP

10K

NOPOP

H

I

IBM CONFIDENTIAL

PART NO.

ETHERNET PHY

J

13N0813

TITLE

J

13N0813

MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/

CORNER

1 2 3 4 5 6 7 9 108

OUTSIDE MAX
INSIDE MAX

SCALE: 1/1

0.13

2.0 APPROVED

PEREGRINE - ROHS

DESIGNER
CHECKED

SHEET

2-17-2005_11:52

RMP NOVEMBER 2004
???
???

15

???
???

OF

20

4321 5

DATE EC NO.

108 976

EC NO.DATE

PART NO.

REL

? ?

13N0813

10-30-02-JWD-P_EXT_ACK# is used to detect BIST mode after reset.

Q/M

GPIO's 1 and 16 can be used for system specific requirements.

DEVELOPMENT NO.

3.3VC

VENDOR=IDT

3.3VC

VEN_P/D_NUM=IDTQS3VH253PAG8

A

16U102

J25

1

D-

D+

ID

100K

C521

PLACE=ROHS

J27

1
2
3
4
5

USB_CS#

3.3VC

1K

R525

USB_EXT_N
USB_EXT_P

3.3VC

U79

14

6

4
5

7

55

11
17
27
32
43

42
44

15
16

13
54

14

VCC_55

7

VCC_7
VCC_11
VCC_17
VCC_27
VCC_32
VCC_43

3

AVCC_3

5

XTALIN

4

XTALOUT
RESET_N
WAKEUP_N

SCL
SDA

IFCLK
CLKOUT

8

D_PLUS

9

D_MINUS

RSVD

PLACE=ROHS

R627

16

5.1K

16

ROM_ADDR12#

P_CS1#

CY7C68013-56LFC

R624

2 1

9,12

U78

ASEL

Internal = 0, External = 1

16

16

USB_INT_N

USB_EXT_N

10K

16

16

USB_INT_P

USB_EXT_P

3.3VC

U75

14

7

ROM_ADDR12

ROM_ADDR12 = 0, selects duart

PD7_FD15
PD6_FD14
PD5_FD13
PD4_FD12
PD3_FD11
PD2_FD10

PD1_FD9
PD0_FD8

PB7_FD7
PB6_FD6
PB5_FD5
PB4_FD4
PB3_FD3
PB2_FD2
PB1_FD1
PB0_FD0

SLRD
SLRW

RDY0_SLRD

RDY1_SLWR

CTL0_FLAGA
CTL1_FLAGB
CTL2_FLAGC

PA0_INT0_N
PA1_INT1_N

PA2_SLOE

AOE

PA3_WU2
PA4_FIFOADR0
PA5_FIFOADR1

PA6_PKTEND

PA7_FLAGD_SLCS_N

AGND_

GND_53
GND_56
GND_10
GND_12
GND_26
GND_28
GND_41

ROM_ADDR[0:31]

9,10,12,17

= 1, selects USB

52
51
50
49
48
47
46
45
25
24
23
22
21
20
19
18

1
2

29

USB_LATCH_EMPTY
30
31

33
34
35
36
37
38
39

PKTEND

40

6

53

IND2P_FE_BLM21PG221SN1D

56
10
12
26
28
41

KEY

71
72
73
74
75

14

HOST_ID0

B

14

14

14

14

14

C

14

14
12

HOST_ID1

HOST_ID2

HOST_ID3

HOST_ID4

HOST_ID5

HOST_ID6

HOST_ID7

COM4_RTS#

76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92

16
16

USB_INT_P

USB_INT_N

RS232_SELECT9,13

D

P_EXT_ACK#5,7

93
94
95
96
97
98
99

5

HOST_PCI_RST_N

100
101

5

RS232_DETECT

102
103

5,7

9

GPIO1

GPIO16

104
105
106

E

12
12
13
13
13
12
12
13

COM5_DTR#
COM5_DSR#
COM5_232TX
COM5_232CTS#
COM5_232RX
COM5_RI#
COM5_CD#
COM5_232RTS#

107
108
109
110
111
112
113
114
115

12

COM4_TX

F

12

COM4_RX

116
117
118
119

3.3VC

10K

R544

14

14

HOST_I2C_SDA

HOST_I2C_SCL

HOST_PWRGD/RST#

5

5

HOST_PWR_REQ#

120
121
122
123
124
125
126
127

G

POP

9

HOST_I2C_INT#

128
129

9

CABLE_DETECT#

130
131

12
12

COM4_CTS#
COM4_DTR#

132
133
134

9

NOPOP

SYS_ON

H

16

R3

1K

12

HOST_SMI#

PCI3_3V

COM4_DSR#

135
136
137
138
139
140

C71
C72
C73
C74
C75
C76
C77
C78
C79
C80
C81
C82
C83
C84
C85
C86
C87
C88
C89
C90
C91
C92
C93
C94
C95
C96
C97
C98
C99
C100
C101
C102
C103
C104
C105
C106
C107
C108
C109
C110
C111
C112
C113
C114
C115
C116
C117
C118
C119
C120
C121
C122
C123
C124
C125
C126
C127
C128
C129
C130
C131
C132
C133
C134
C135
C136
C137
C138
C139
C140

IRQ4

C1
C2
C3
C4
C5
C6
C7
C8

C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35

LCD Port (Raw Digital Video)

C36
C37
C38
C39
C40
C41
C42
C43
C44
C45
C46
C47
C48
C49
C50
C51
C52
C53
C54
C55
C56
C57
C58
C59
C60
C61
C62
C63
C64
C65
C66
C67
C68
C69
C70

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

67
68
69
70

1
2
3
4
5
6
7
8
9

65
66

RN62
RN62
RN62
RN62

RN63
RN63
RN63
RN63

RN64
RN64
RN64
RN64

4
3
2
1

4
3
2
1

4
3
2
1

5

220

6

220

7

220

8

220

5

220

6

220

7

220

8

220

5

220

6

220

7

220

8

220

R536

220

RN65
RN65
RN65
RN65

RN66
RN66
RN66
RN66

RN67
RN67
RN67
RN67

4
3
2
1

4
3
2
1

4
3
2
1

5

220

6

220

7

220

8

220

5

220

6

220

7

220

8

220

5

220

6

220

7

220

8

220

485_N_BUS_B
485_P_BUS_B

485_N_BUS_A
485_P_BUS_A

ERROR_LED_BUF

COM4_CD#

ENET_PHY_RX_N

ENET_PHY_RX

ENET_PHY_TX_N

ENET_PHY_TX

ENET_PHY_LNK_LED_N

ENET_PHY_ACT_LED_N

DV_RED6
DV_RED7
DV_RED2

DV_RED3

DV_RED4

DV_RED5
DV_GRN6
DV_GRN7

DV_BLU7

DV_HSYNC

DV_VSYNC

DV_DE

DV_CLK

DV_RED1
DV_GRN3
DV_GRN4
DV_GRN5

DV_BLU1
DV_BLU4
DV_GRN1
DV_GRN2

DV_BLU3
DV_BLU6
DV_BLU2
DV_BLU5

13
13

13
13

5

12

15
15

15
15

15

15

17
17
17
17

17
17
17
17

17
17
17
17

17

17
17

17

17

17
17
17
17

17
17
17
17

3V_BAT

R534

10K

3.3VC

R535

10K

R625

10K

11

13

Add PU to reset 100k to 3.3

C542

100N

USB_FX2_24MHZ

USB_RST_N

14
14

16

16

USB_SCL
USB_SDA
USBD

USBD_N

PLACE=ROHS

SH1
SH2
SH3
SH4

SH2
SH3
SH4

VBUSSH1

GND

USB Mini-B

VEN_P/D_NUM=440247-2

VENDOR=AMP

16

C543

2.2U

R661

PLACE=ROHS

1U

KEY

VENDOR=MOLEX
VEN_P/D_NUM=500599-1409

BSEL

16

I

SMP Connector

5,16

PKTEND

USB_HUB_INT

P/D_NUM=23K8778

NOPOP

15
14

2
6
5
4

3
10
11
12
13

RN59 0
RN59 0
RN59 0
RN59 0
RN58 0
RN58 0
RN58 0
RN58
RN60
RN60
RN60
RN60
RN61
RN61
RN61
RN61

USB_HUB_INT

16

L48

220

EA_N
EB_N
S0
S1
I0A
I1A
I2A
I3A
I0B
I1B
I2B
I3B

SYS_ON

NOPOP

4
3
2
1
4
3
2
1
1
2
3
4
1
2
3
4

ohms

VCC

GND

8

NOPOP

NOPOP

5
6
7
8
5
6
7
8

0

8

0

7

0

6

0

5

0

8

0

7

0

6

0

5

0

P_OE#
P_WE#

YA

YB

NOPOP

5

USBD_N

7

9

USBD

16

QS253_TSSOP16_65MM

16

NOPOP

NOPOP

NOPOP

NOPOP

ROM_DATA0
ROM_DATA1
ROM_DATA2
ROM_DATA3
ROM_DATA4
ROM_DATA5
ROM_DATA6
ROM_DATA7

9,10,17

4,17

5,16

3.3VC

U79

14

8

9
10

7

16

ROM_DATA[0:31]

3.3VC

6 5

7

14

U75

9,10,12,17

P_R_W#

PerR/W

USB_CS#

9,10,12,17

__

16

A

B

C

D

E

F

G

H

I

J

13N0813

10K

R626

NOPOP

USB & SMP CONNECTOR

MUST CONFORM TO ENG
SPEC: 80X2324

**Select PE[7..0] alternate function and make PE[7..0] outputs. (per data sheet pg25)

***Turn off the CLKOE bit in firmware so the CPU clock is not driven on CLKOUT

****If system is off, Remove power from USB pull-up.

1 2 3 4 5 6 7 9 108

TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/

CORNER

OUTSIDE MAX
INSIDE MAX

PART NO.

13N0813

TITLE

SCALE: 1/1

0.13

2.0 APPROVED

PEREGRINE - ROHS

DESIGNER
CHECKED

SHEET

IBM CONFIDENTIAL

2-17-2005_11:53

RMP NOVEMBER 2004
???
???

16

???
???

OF

J

20

4321 5

DATE EC NO.

108 976

EC NO.DATE

PART NO.

REL

AVCC

U80

18

A

B

C

D

E

F

18
18
18
18
18
18
18
18
18
18
18
18
18
18

COMP_SRD_0
COMP_SRD_1
COMP_SRD_2
COMP_SRD_3
COMP_SRD_4
COMP_SRD_5
COMP_SRD_6
COMP_SRD_7
COMP_SRD_8
COMP_SRD_9
COMP_SRD_10
COMP_SRD_11
COMP_SRD_12
COMP_SRD_13
COMP_SRD_14

FPGA_DATA0

17

FPGA_NCONFIG

17

17
17
17
17

FPGA_NCE
FPGA_MSEL0
FPGA_MSEL1
FPGA_DCLK

D4

IO_LVDS14_INIT_DONE

C3

IO_LVDS14_N

C2

IO_LVDS13_CLKUSR

B1

IO_LVDS13_N

G5

IO_VREF0B1

F4

IO_F4

D3

IO_LVDS12_DQ0L0

E4

IO_LVDS12_N_DQ0L1

F5

IO_DPCLK1_DQS0L

E3

IO_LVDS11_DQ0L2

D2

IO_LVDS11_N_DQ0L3

E2

IO_LVDS10

D1

IO_LVDS10_N

F3

IO_LVDS9

G3

IO_LVDS9_N

F2

IO_LVDS8

E1

IO_LVDS8_N

G2

IO_LVDS7

F1

IO_LVDS7_N_DM0L

H5

IO_VREF1B1

G4

IO_NCSO

H2

DATA0

H3

NCONFIG

H6

VCCA_PLL1

G1

CLK0_LVDSCLK1P

H1

CLK1_LVDSCLK1N

J6

GNDA_PLL1

J5

GNDG_PLL1

H4

NCEO

J4

NCE

J3

MSEL0

J2

MSEL1

K4

DCLK

K3

IO_ASDO

J1

IO_PLL1_OUTP

K2

IO_PLL1_OUTN

L3

IO_L3

K1

IO_LVDS6

L1

IO_LVDS6_N

L2

IO_LVDS5

M1

IO_LVDS5_N

N1

IO_LVDS4

M2

IO_LVDS4_N

N2

IO_LVDS3_DQ0L4

M3

IO_LVDS3_N_DQ0L5

L5

IO_DPCLK0

M4

IO_LVDS2_DQ0L6

N3

IO_LVDS2_N_DQ0L7

K5

IO_VREF2B1

L4

IO_L4

R1

IO_LVDS1

P2

IO_LVDS1_N

P3

IO_LVDS0

N4

IO_LVDS0_N

VREF0B1

VREF1B1

VREF2B1

CYCLONE

IO1

V

1.5

VREF2B3

VREF1B3

VREF0B3

IO_LVDS51_N

IO_LVDS51

IO_LVDS50_N

IO_LVDS50

IO_LVDS49_N_DQ1R7

IO_LVDS49

IO_VREF2B3

IO_DQ1R6

IO_DPCLK5_DQS1R

IO_LVDS48_N_DQ1R5

IO_LVDS48_DQ1R4

IO_LVDS47_N

IO_LVDS47

IO_LVDS46_N

IO_LVDS46

IO_LVDS45_N

IO_LVDS45

IO_LVDS44_N

IO_LVDS44

IO_PLL2_OUTN
IO_PLL2_OUTP

CONF_DONE

NSTATUS

GNDG_PLL2

GNDA_PLL2

CLK3_LVDSCLK2N

CLK2_LVDSCLK2P

VCCA_PLL2

IO_VREF1B3

IO_LVDS43_N_DM1R

IO_LVDS43

IO_LVDS42_N

IO_LVDS42

IO_LVDS41_N

IO_LVDS41

IO_LVDS40_N

IO_LVDS40

IO_LVDS39_N

IO_LVDS39

IO_LVDS38_N

IO_LVDS38_DQ1R3

IO_DPCLK4

IO_LVDS37_N_DQ1R2

IO_LVDS37_DQ1R1

IO_DQ1R0

IO_VREF0B3

IO_LVDS36_N

IO_LVDS36

IO_LVDS35_N

IO_LVDS35

TCK
TMS
TDO

TDI

N13
P14
P15
R16
N15
N16
K12
K14
L12
N14
M13
M14
L13
M15
M16
L14
L15
L16
K16

K15
J16
K13
J13
J14
J15
H15
J12
J11
H16
G16
H11
H14
H12

G14
G13
G15
F16
F14
F13
F15
E16
E15
D16
D15
E14
F12
E13
D14
H13
G12
B16
C15
C14
D13

AVCC

P_WBE3#
P_WBE2#
P_WBE1#
P_WBE0#

P_R_W#

P_CS3#

P_OE#
P_WE#

P_READY

PERIPHERAL_RESET_N

DV_BLU6
DV_BLU2

DV_BLU5

COMP_SRCLK

FPGA_CONF_DONE

FPGA_NSTATUS

TSK_CK
TST_MS
TST_D0

PERCLK
DV_CLK

TST_D1

DV_GRN1
DV_BLU4
DV_GRN2
DV_GRN5
DV_GRN3
DV_RED1
DV_GRN4

DV_VSYNC
DV_HSYNC

DV_GRN6
DV_RED5

DV_BLU7
DV_DE

DV_GRN7
DV_RED4

DV_BLU3
DV_BLU1

DV_RED6
DV_RED2
DV_RED7
DV_RED3

9
9
9
9

9,10,12,16

9

9,10,16

4,16,17

9,10

5,12-14

16

16

16

18

17
17
17
17
17

5

16

17

16

16

16
16

16
16
16

16
16

16

16

16
16

16
16

16
16

16

16

16
16

1_5V

3.3VC

A7

VCCINT_A7

A10

VCCINT_A10

G8

VCCINT_G8

G10

VCCINT_G10

H7

VCCINT_H7

H9

VCCINT_H9

J8

VCCINT_J8

J10

VCCINT_J10

K7

VCCINT_K7

K9

VCCINT_K9

T7

VCCINT_T7

T10

VCCINT_T10

C1

VCCIOB1_C1

G6

VCCIOB1_G6

P1

VCCIOB1_P1

T3

VCCIOB4_T3

L7

VCCIOB4_L7

L10

VCCIOB4_L10

T14

VCCIOB4_T14

P16

VCCIOB3_P16

K11

VCCIOB3_K11

C16

VCCIOB3_C16

A14

VCCIOB2_A14

F10

VCCIOB2_F10

F7

VCCIOB2_F7

A3

VCCIOB2_A3

U80

CYCLONE

PWR & GND

V

1.5

VENDOR=ALTERA
VEN_P/D_NUM=EP1C6F256C6

P/D_NUM=77P3150

GND_A1

GND_A16

GND_A5

GND_A12

GND_F6
GND_F8
GND_F9

GND_F11

GND_G7
GND_G9

GND_G11

GND_H8

GND_H10

GND_J7

GND_J9
GND_K6
GND_K8

GND_K10

GND_L6

GND_L8

GND_L9

GND_L11

GND_T1
GND_T5

GND_T12
GND_T16

A1
A16
A5
A12
F6
F8
F9
F11
G7
G9
G11
H8
H10
J7
J9
K6
K8
K10
L6
L8
L9
L11
T1
T5
T12
T16

9,10,12,16

ROM_ADDR[0:31]

9,10,12,16

ROM_DATA[0:31]

ROM_ADDR31
ROM_ADDR30
ROM_ADDR29
ROM_ADDR28
ROM_ADDR27
ROM_ADDR26
ROM_ADDR25
ROM_ADDR24

ROM_DATA31
ROM_DATA30
ROM_DATA29
ROM_DATA28
ROM_DATA27
ROM_DATA26
ROM_DATA25
ROM_DATA24
ROM_DATA23
ROM_DATA22
ROM_DATA21
ROM_DATA20
ROM_DATA19
ROM_DATA18
ROM_DATA17
ROM_DATA16
ROM_DATA15
ROM_DATA11
ROM_DATA13
ROM_DATA12

ROM_DATA10
ROM_DATA14
ROM_DATA9
ROM_DATA8
ROM_DATA7
ROM_DATA6
ROM_DATA5
ROM_DATA4
ROM_DATA3
ROM_DATA2
ROM_DATA1
ROM_DATA0

R2

T2

R3

P4

R4

T4

R5

P5
M5
M6

N5
N6

P6

R6

M7

T6

R7

P7

N7
R8

T8

N8

P8
M8

M10

R9

T9

P9

N9

R10

T11
N10
P10

R11
P11
N11
N12

M9
M11
M12

P12
R12

T13
R13
R14
P13

T15
R15

? ?

IO_LVDS71
IO_LVDS71_N
IO_LVDS70
IO_LVDS70_N
IO_LVDS69
IO_LVDS69_N
IO_LVDS68_DQ1B7
IO_LVDS68_N_DQ1B6
IO_DPCLK7_DQS1B
IO_VREF2B4
IO_LVDS67
IO_LVDS67_N_DQ1B5
IO_LVDS66_DQ1B4
IO_LVDS66_N
IO_M7
IO_LVDS65
IO_LVDS65_N
IO_LVDS64
IO_LVDS64_N
IO_LVDS63
IO_LVDS63_N

IO_LVDS62
IO_LVDS62_N
IO_M8
IO_VREF1B4
IO_LVDS61_DM1B
IO_LVDS61_N
IO_LVDS60
IO_LVDS60_N
IO_LVDS59
IO_LVDS59_N
IO_LVDS58
IO_LVDS58_N

IO_LVDS57
IO_LVDS57_N
IO_LVDS56
IO_LVDS56_N
IO_M9
IO_VREF0B4
IO_DPCLK6
IO_LVDS55_DQ1B3
IO_LVDS55_N_DQ1B2
IO_LVDS54_DQ1B1
IO_LVDS54_N_DQ1B0
IO_LVDS53
IO_LVDS53_N
IO_LVDS52
IO_LVDS52_N

U80

CYCLONE

IO2

V

1.5

VREF2B4

VREF0B2

VREF1B2

VREF1B4

VREF2B2

VREF0B4

VENDOR=ALTERA
VEN_P/D_NUM=EP1C6F256C6

IO_LVDS34_N

IO_LVDS34

IO_LVDS33_N

IO_LVDS33

IO_LVDS32_N_DQ0T0

IO_LVDS32_DQ0T1

IO_LVDS31_N_DQ0T2

IO_LVDS31_DQ0T3

IO_DPCLK3_DQS0T

IO_VREF0B2

IO_E9

IO_LVDS30_N

IO_LVDS30

IO_LVDS29_N

IO_LVDS29

IO_LVDS28_N

IO_LVDS28

IO_LVDS27_N

IO_LVDS27

IO_LVDS26_N

IO_LVDS26

IO_LVDS25_N_DM0T

IO_LVDS25

IO_VREF1B2

IO_E8

IO_LVDS24_N

IO_LVDS24

IO_LVDS23_N

IO_LVDS23

IO_LVDS22_N

IO_LVDS22

IO_LVDS21_N

IO_LVDS21

IO_E7

IO_LVDS20_N

IO_LVDS20

IO_LVDS19_N

IO_LVDS19

IO_VREF2B2

IO_DPCLK2

IO_LVDS18_N_DQ0T4

IO_LVDS18_DQ0T5

IO_LVDS17_N_DQ0T6

IO_LVDS17_DQ0T7

IO_LVDS16_N

IO_LVDS16
IO_LVDS15_N_DEV_OE
IO_LVDS15_DEV_CLRN

13N0813

DEVELOPMENT NO.

B15
A15
B14
C13
B13
A13
B12
C12
E12
E11
E9
D12
D11
C11
B11

A11
B10
C10
D10
A9
B9
D9
C9
E10
E8
C8
D8

A8
B8
D7
C7
B7
A6
E7
B6
C6
D6
D5
E6
E5
C5
B5
A4
B4
C4
B3
A2
B2

COMP_SRD_15
COMP_SRRAS­COMP_SRCAS­COMP_SRWE­COMP_SRCKE
COMP_SRCS­COMP_SRBA1
COMP_SRBA0
COMP_SRDQMH
COMP_SRDQML

COMP_SRA_11
COMP_SRA_10
COMP_SRA_8
COMP_SRA_9
COMP_SRA_7
COMP_SRA_6
COMP_SRA_5
COMP_SRA_4
COMP_SRA_3
COMP_SRA_2
COMP_SRA_1
COMP_SRA_0

Q/M

18
18
18
18
18

18
18
18
18
18
18
18
18
18
18
18
18

A

B

18

C

18
18
18
18

D

E

F

P/D_NUM=77P3150

VENDOR=ALTERA
VEN_P/D_NUM=EP1C6F256C6
P/D_NUM=77P3150

G

3.3VC

3.3VC

10K

H

R100

0

R107

0

R592

0

POP

POP

POP

R101

0

R108

X_DOUT

5

5
5

X_CCLK
X_INIT

X_DONE
X_PROG

5

I

5,7

R591

R528

POP

POP

0

R588

10K

10K

R589

10K

R590

10K

FPGA_DATA0

FPGA_DCLK

FPGA_NSTATUS

FPGA_CONF_DONE

FPGA_NCONFIG

17

17

17
17

17

FPGA_MSEL0

17

FPGA_MSEL1

17

NOPOP

4.7K

4.7K

4.7K

R674

4.7K

R676

R675

NOPOP

R677

MSEL0

0
1
X

MSEL1

0
0
0

Config

AS
PS

JTAG

17
17
17
17

TST_MS
TSK_CK
TST_D1

TST_D0

10K

3.3VC

R673

10K

R671

R672

1K

3.3VC

J26

1

VCC

2

MS

3

CK

4

D1

5

D0

6

GND

VEN_P/D_NUM=22-28-4063
VENDOR=MOLEX

3.3K

3.3VC

R10

17

FPGA_NCE

R664

P_WE#

10K

4,16,17

G

H

I

J

13N0813

NOPOP

VIDEO COMPRESSOR

MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/

CORNER

1 2 3 4 5 6 7 9 108

OUTSIDE MAX
INSIDE MAX

PART NO.

13N0813

TITLE

SCALE: 1/1

0.13

2.0 APPROVED

PEREGRINE - ROHS

DESIGNER
CHECKED

SHEET

IBM CONFIDENTIAL

2-17-2005_11:53

RMP NOVEMBER 2004
???
???

17

???
???

OF

J

20

4321 5

DATE EC NO.

108 976

EC NO.DATE

PART NO.

REL

? ?

13N0813

DEVELOPMENT NO.

Q/M

12/08/03 - JAD - (Page 18) Changed U9 IBM P/N to 38L4886 from 38L4885 to reflect a change to 128Mb

memory technology, as the old 64Mb supply has become EXTREMELY constrained

A

A

B

B

3.3VC

C

C

1U

100N

10N

Place Caps as close as possible to SDRAM

C29

U9

1

14

VDD_1

VDD_2

27

VDD_3

D

Termination resistor values seems high. Verify signal quality. Try lower values and compare.

RN35

17
17
17

17

17

17

E

17

17
17

17
17
17

17

17

17

F

17

17

17

17

17
17
17

COMP_SRA_11
COMP_SRA_10
COMP_SRA_9
COMP_SRA_8
COMP_SRA_7
COMP_SRA_6
COMP_SRA_5
COMP_SRA_4
COMP_SRA_3
COMP_SRA_2
COMP_SRA_1
COMP_SRA_0

COMP_SRBA1
COMP_SRBA0
COMP_SRDQMH
COMP_SRDQML

COMP_SRCS­COMP_SRCLK
COMP_SRCKE

COMP_SRWE­COMP_SRCAS­COMP_SRRAS-

RN35

100

RN34

100

RN33

100

RN33

100

RN42

100

RN32

100

RN31

100

18

45

45

36

27

18

18

RN32

100

RN35

100

RN34

100

RN33

100

RN32

100

RN42

100

RN31

100

45

36

36

36

18

27

27

100

RN35

100

RN34

100

RN33

100

RN32

100

RN31

100

RN42

100

RN31

100

18

22

A10

34

A9

36

27

27

27

45

45

18

33
32
31
30
29
26
25
24
23

21
20
39
15

19
38
37

16
17
18

A8
A7
A6
A5
A4
A3
A2
A1
A0

BA1
BA0
DQMH
DQML

CS
CLK
CKE

WE
CAS
RAS

1Mx16x4b

2Mx16x4b

SDRAM

TSOP54

VSS_1

VSS_2

284154

VSS_3

3

9

VDDQ_1

VSSQ_1

VSSQ_2

6

12

49

43

VDDQ_2

VDDQ_3

VSSQ_4

VSSQ_3

52

46

VDDQ_4

DQ15A11
DQ14
DQ13
DQ12
DQ11
DQ10

DQ9
DQ8

DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

NC1
NC2

5335
51
50
48
47
45
44
42

13
11
10

8
7
5
4
2

36
40

C27

3 6

2 7

3 6

2 7

RN47

100

RN44

100

RN30

100

RN29

100

C28

2 7

RN44

1 8

RN44

4 5

RN30

2 7

RN29

1 8

100

RN29

4 5

100

RN47

100

100

100

100

RN47

1 8

100

RN47

4 5

100
RN44

3 6

100

RN30

1 8

100

RN30

4 5

100

RN29

3 6

100

COMP_SRD_15
COMP_SRD_14
COMP_SRD_13
COMP_SRD_12
COMP_SRD_11
COMP_SRD_10
COMP_SRD_9
COMP_SRD_8

COMP_SRD_7
COMP_SRD_6
COMP_SRD_5
COMP_SRD_4
COMP_SRD_3
COMP_SRD_2
COMP_SRD_1
COMP_SRD_0

17
17
17

17
17
17

17

17

17

17

17

17
17

17

17

17

D

E

F

G

G

SDRAM1MX16X4B
SDRAM2MX16X4B

VEN_P/D_NUM=MT48LC8M16A2TG-75
P/D_NUM=38L4886
DEVICE=SDRAM2MX16X4
QDEVICE=SDRAM2MX16X4

H

H

I

I

J

13N0813

COMPRESSOR SDRAM 1MX16X4b

MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/

CORNER

1 2 3 4 5 6 7 9 108

OUTSIDE MAX
INSIDE MAX

PART NO.

13N0813

TITLE

SCALE: 1/1

0.13

2.0 APPROVED

PEREGRINE - ROHS

DESIGNER
CHECKED

SHEET

IBM CONFIDENTIAL

2-17-2005_11:53

RMP NOVEMBER 2004
???
???

18

???
???

OF

J

20

4321 5

DATE EC NO.

108 976

EC NO.DATE

PART NO.

REL

A

2_5V

R669

10K

B

1.5V@500mA for FPGA

U100

VREG8P_MIC5239YM

5

V

1

EN

3

IN

FLG_ADJ

OUT

2

4

1_5V

2.5V for PPC 405GP @ 2 amp max "continuous"

? ?

13N0813

DEVELOPMENT NO.

Q/M

A

B

R670

GND7

10U

C590

100N

C594

C

D

GND8GND6GND5

7

865

+1%/-1%

R668

+1%/-1%

232

1.05K

C593

10U

C591

100N

3.3VC

C208

10U

VENDOR=MURATA
VEN_P/D_NUM=GRM32DR61C106KA01L

U85

L6932D2.5

1

EN

2

IN

GND_5

GND_6

GND_7

7

GND_8

8

5

6

VEN_P/D_NUM=E-L6932D2.5TR
VENDOR=ST_MICRO

OUT

PGOOD

3
4

C207

10U

100N

C46

100N

C47

100N

C88

100N

C89

2_5V

VENDOR=AVX
VEN_P/D_NUM=0603YC104KAT2A

C

D

Filter for FPGA Analog Vcc

Place as close as possible to PLL VCCA and GNDA

AVCC

E

F

C598

1_5V

IND2P_FE_BLM21AF121SN1D

100N

L49

120

200mA

ohms

C618

C600

1N

100N

E

F

G

Decoupling for FPGA

G

Place as close to FPGA Pins as possible

1_5V

H

C615

1N

C616

1N

C617

1N

C604

C602

100N

100N

C603

100N

C623

C624

1N

1N

C625

1N

C608

100N

C609

100N

C610

100N

H

I

J

13N0813

1N

C601

100N

C605

100N

C606

C607

100N

100N

C629

1N

C628

1N

C627

1N

C626

1N

C613

100N

C612

100N

C611

C614

100N

100N

3.3VC

C621

1N

C620

1N

C619

C622

1N

POWER and FPGA DECOUPLING

ROOM=FPGA

MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/

CORNER

1 2 3 4 5 6 7 9 108

OUTSIDE MAX
INSIDE MAX

PART NO.

13N0813

TITLE

SCALE: 1/1

0.13

2.0 APPROVED

PEREGRINE - ROHS

DESIGNER
CHECKED

SHEET

IBM CONFIDENTIAL

2-17-2005_11:53

RMP NOVEMBER 2004
???
???

19

???
???

OF

I

J

20

4321 5

DATE EC NO.

108 976

EC NO.DATE

PART NO.

REL

A

3.3VC

U79

3.3VC

1
2

14

7

3

U1

14

4
5

LVC08_TSSOP14_65MM

B

6

7

Decided not to reduce logic any more due to layout problems. Spare gate are good to have anyway!

? ?

13N0813

DEVELOPMENT NO.

Q/M

A

B

Bypass Capacitors, place every inch

3.3VC

U34

65

C

AHC04_SO14N

PLACE=ROHS

D

AHC04_SO14N

PLACE=ROHS

U34

89

AHC04_SO14N

U34

PLACE=ROHS

1011

AHC04_SO14N

PLACE=ROHS

U34

1213

U75

14

89

7

3.3VC3.3VC

U75

14

3.3VC

U75

14

1011

7

1213

7

C559

100N

C568

100N

C560

100N

C569

100N

C561

100N

C571

100N

C562

100N

C572

100N

C563

100N

C573

100N

C564

C574

100N

100N

C565

C575

100N

100N

C566

C576

100N

100N

C567

100N

C577

100N

C570

100N

C578

100N

C

D

E

C579

100N

C580

100N

C581

100N

C582

100N

C583

100N

C584

100N

C585

100N

C586

100N

C587

100N

C588

E

100N

For cap check

VCCIO 1_5V2_5V3.3VC

3.3

F

1.53 1.53.3 2.5

AVCC3V_BAT

F

G

Dummy part place holder for bom

TRACK1

G

DUMMY_PART

H

I

H

I

J

13N0813

MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/

CORNER

1 2 3 4 5 6 7 9 108

OUTSIDE MAX
INSIDE MAX

SPARE PARTS

SCALE: 1/1

0.13

2.0 APPROVED

IBM CONFIDENTIAL

PART NO.

13N0813

TITLE

PEREGRINE - ROHS

2-17-2005_11:53

DESIGNER
CHECKED

SHEET

RMP NOVEMBER 2004
???
???

20

???
???

OF

J

20

4321 5

DATE EC NO.

108 976

EC NO.DATE

PART NO.

REL

A

? ?

13N0813

DEVELOPMENT NO.

Q/M

A

For cap check

VCCIO 1_5V3.3VC AVCC3V_BAT

3.3

B

2_5V

2.5 1.51.533.3

B

PWR_RTC

PWR3_3VC_CY2292

CLK_25MHZ_BCM

33MHZ_405GP
USB_FX2_24MHZ
48MHZ

25MHZ_XTALIN

C

D

25MHZ_XTALOUT

DUART_XTAL1

DUART_XTAL2

$13N3056

$13N3051

485_P_BUS_B
485_N_BUS_A

$15N4363
ENET_PHY_RX_CLK

$15N4355

PERIPHERAL_RESET_N
$5N5834

ENET_PHY_RX_CLK

C

D

E

F

E

F

G

H

I

G

H

I

J

13N0813

MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/

CORNER

1 2 3 4 5 6 7 9 108

OUTSIDE MAX
INSIDE MAX

PART NO.

13N0813

TITLE

SCALE: 1/1

0.13

2.0 APPROVED

PEREGRINE - ROHS

VOLTAGE CHECK

DESIGNER
CHECKED

SHEET

IBM CONFIDENTIAL

RMP NOVEMBER 2004
???
???

21

???
???

OF

20

J

4321 5

DATE EC NO.

108 976

EC NO.DATE

PART NO.

15 Feb 2005
18:02:48

A

PEREGRINE

C

C1______ 15
C10_____ 11
C11_____ 8
C12_____ 15
C13_____ 15

B

C14_____ 11
C15_____ 15
C16_____ 15
C17_____ 15
C18_____ 15
C19_____ 11
C2______ 15
C20_____ 15
C207____ 19
C208____ 19
C21_____ 11

C

C241____ 13
C246____ 13
C27_____ 18
C28_____ 18
C29_____ 18
C3______ 11
C328____ 6
C329____ 6
C330____ 6

D

C331____ 6
C332____ 6
C333____ 6
C334____ 6
C335____ 6
C340____ 8
C341____ 8
C349____ 10
C4______ 11
C46_____ 19

E

C47_____ 19
C493____ 10
C494____ 6
C495____ 6
C496____ 6
C497____ 6
C5______ 15
C502____ 8
C503____ 8
C507____ 10

F

C51_____ 13
C518____ 15
C519____ 15
C52_____ 13
C520____ 15
C521____ 16
C522____ 5
C523____ 5
C534____ 5
C542____ 16
C543____ 16

G

C551____ 10
C552____ 10
C553____ 14
C556____ 12
C557____ 12
C558____ 11
C559____ 20
C560____ 20
C561____ 20
C562____ 20

H

C563____ 20
C564____ 20
C565____ 20
C566____ 20
C567____ 20
C568____ 20
C569____ 20
C570____ 20
C571____ 20
C572____ 20

I

C573____ 20
C574____ 20
C575____ 20
C576____ 20
C577____ 20
C578____ 20
C579____ 20
C580____ 20
C581____ 20

J

C582____ 20
C583____ 20
C584____ 20
C585____ 20

13N0813

REL

C586____ 20
C587____ 20
C588____ 20
C59_____ 6
C590____ 19
C591____ 19
C593____ 19
C594____ 19
C598____ 19
C6______ 11
C60_____ 6
C600____ 19
C601____ 19
C602____ 19
C603____ 19
C604____ 19
C605____ 19
C606____ 19
C607____ 19
C608____ 19
C609____ 19
C61_____ 6
C610____ 19
C611____ 19
C612____ 19
C613____ 19
C614____ 19
C615____ 19
C616____ 19
C617____ 19
C618____ 19
C619____ 19
C62_____ 6
C620____ 19
C621____ 19
C622____ 19
C623____ 19
C624____ 19
C625____ 19
C626____ 19
C627____ 19
C628____ 19
C629____ 19
C63_____ 6
C64_____ 6
C65_____ 6
C66_____ 6
C67_____ 6
C68_____ 6
C69_____ 6
C7______ 6
C72_____ 6
C75_____ 8
C76_____ 8
C8______ 6
C88_____ 19
C89_____ 19
C9______ 6
C93_____ 10
C96_____ 13
C97_____ 13

CR

CR1_____ 10
CR2_____ 5
CR3_____ 5

J

J1______ 14
J25_____ 16
J26_____ 17
J27_____ 16
J28_____ 12
J5______ 6

L

L1______ 11
L43_____ 5
L48_____ 16
L49_____ 19

R

R1______ 15
R10_____ 17
R100____ 17
R101____ 17
R102____ 4
R103____ 4
R104____ 4
R105____ 4
R106____ 4
R107____ 17
R108____ 17
R109____ 14
R11_____ 15
R111____ 14

1 2 3 4 5 6 7 9 108

R112____ 14
R117____ 6
R12_____ 15
R122____ 10
R13_____ 15
R14_____ 15
R15_____ 15
R157____ 13
R158____ 13
R16_____ 9
R17_____ 14
R18_____ 15
R19_____ 15
R2______ 9
R20_____ 9
R21_____ 9
R22_____ 9
R226____ 6
R23_____ 11
R232____ 10
R237____ 13
R238____ 13
R24_____ 15
R25_____ 15
R26_____ 15
R27_____ 15
R28_____ 15
R29_____ 15
R3______ 16
R30_____ 15
R31_____ 15
R32_____ 11
R33_____ 15
R34_____ 15
R35_____ 11
R36_____ 11
R365____ 4
R366____ 4
R373____ 4
R4______ 11
R40_____ 7
R41_____ 7
R42_____ 7
R43_____ 7
R44_____ 7
R45_____ 7
R454____ 13
R455____ 13
R456____ 13
R457____ 13
R458____ 10
R46_____ 7
R47_____ 7
R48_____ 7
R483____ 13
R485____ 13
R49_____ 7
R495____ 14
R5______ 9
R50_____ 7
R51_____ 7
R511____ 15
R514____ 14
R517____ 5
R518____ 5
R519____ 5
R52_____ 10
R520____ 5
R521____ 5
R522____ 5
R525____ 16
R528____ 17
R53_____ 7
R534____ 16
R535____ 16
R536____ 16
R54_____ 7
R542____ 9
R543____ 9
R544____ 16
R55_____ 4
R551____ 5
R552____ 4
R553____ 4
R554____ 4
R555____ 4
R556____ 4
R557____ 4
R558____ 4
R559____ 4
R56_____ 7
R560____ 4
R561____ 4
R562____ 4
R563____ 4
R564____ 4
R565____ 4
R566____ 4

R567____ 9
R568____ 9
R569____ 9
R57_____ 7
R570____ 9
R571____ 9
R572____ 9
R573____ 9
R574____ 9
R575____ 9
R576____ 9
R577____ 9
R578____ 5
R579____ 4
R58_____ 7
R580____ 6
R581____ 6
R582____ 6
R583____ 6
R584____ 4
R585____ 4
R586____ 4
R587____ 4
R588____ 17
R589____ 17
R59_____ 7
R590____ 17
R591____ 17
R592____ 17
R594____ 5
R595____ 5
R596____ 10
R597____ 5
R598____ 10
R599____ 10
R6______ 9
R60_____ 7
R602____ 10
R603____ 9
R604____ 14
R605____ 14
R606____ 14
R607____ 14
R608____ 14
R609____ 14
R61_____ 7
R610____ 5
R611____ 5
R612____ 15
R613____ 15
R614____ 15
R615____ 15
R618____ 10
R619____ 10
R62_____ 9
R621____ 9
R622____ 10
R623____ 10
R624____ 16
R625____ 16
R626____ 16
R627____ 16
R628____ 6
R63_____ 11
R630____ 12
R631____ 12
R632____ 12
R633____ 12
R634____ 12
R635____ 12
R636____ 12
R638____ 14
R639____ 14
R64_____ 7
R640____ 12
R644____ 12
R645____ 12
R646____ 5
R647____ 5
R648____ 5
R649____ 5
R65_____ 7
R650____ 13
R655____ 11
R656____ 11
R657____ 11
R658____ 11
R659____ 11
R66_____ 7
R660____ 11
R661____ 16
R664____ 17
R668____ 19
R669____ 19
R67_____ 7
R670____ 19
R671____ 17
R672____ 17

R673____ 17
R674____ 17
R675____ 17
R676____ 17
R677____ 17
R678____ 13
R679____ 13
R68_____ 7
R680____ 13
R681____ 14
R682____ 14
R69_____ 7
R7______ 9
R70_____ 7
R71_____ 7
R72_____ 7
R73_____ 7
R74_____ 7
R75_____ 7
R76_____ 7
R77_____ 9
R78_____ 14
R79_____ 14
R8______ 15
R80_____ 7
R81_____ 7
R82_____ 7
R83_____ 7
R84_____ 7
R85_____ 7
R86_____ 7
R87_____ 5
R88_____ 5
R89_____ 14
R9______ 9
R90_____ 5
R91_____ 4
R92_____ 4
R93_____ 14
R94_____ 4
R95_____ 4
R96_____ 14
R97_____ 4
R98_____ 4
R99_____ 4

RN

RN14____ 4
RN15____ 4
RN16____ 4
RN17____ 4
RN18____ 4
RN19____ 4
RN20____ 4
RN21____ 4
RN29____ 18
RN30____ 18
RN31____ 18
RN32____ 18
RN33____ 18
RN34____ 18
RN35____ 18
RN42____ 18
RN44____ 18
RN47____ 18
RN58____ 16
RN59____ 16
RN60____ 16
RN61____ 16
RN62____ 16
RN63____ 16
RN64____ 16
RN65____ 16
RN66____ 16
RN67____ 16

SW

SW1_____ 10

TR

TRACK1__ 20

U

U1______ 5
U1______ 6
U1______ 12
U1______ 20
U100____ 19
U101____ 11
U102____ 16
U2______ 15
U27_____ 10
U3______ 14
U34_____ 13
U34_____ 20
U5______ 13

U53_____ 4
U53_____ 5
U53_____ 6
U53_____ 9
U6______ 13
U75_____ 5
U75_____ 16
U75_____ 20
U78_____ 16
U79_____ 12
U79_____ 16
U79_____ 20
U80_____ 17
U83_____ 8
U85_____ 19
U87_____ 5
U88_____ 5
U89_____ 10
U9______ 18
U90_____ 10
U91_____ 14
U92_____ 14
U93_____ 14
U94_____ 14
U95_____ 14
U96_____ 13
U99_____ 12

Y

Y1______ 11
Y2______ 12

MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/

CORNER

? ?

OUTSIDE MAX
INSIDE MAX

13N0813

DEVELOPMENT NO.

PART NO.

13N0813

TITLE

SCALE: 1/1

0.13

2.0 APPROVED

PEREGRINE - ROHS

COMPONENT LIST: A-Y2

DESIGNER
CHECKED

SHEET

IBM CONFIDENTIAL

RMP NOVEMBER 2004
???
???

22

???
???

OF

20

Q/M

A

B

C

D

E

F

G

H

I

J