MSI MS-95F3 Schematic 0C
REL
961 2 3 4 5 7 8 10
EC NO.DATEQTYREL FOR ASM
PART NO.
A
DEVELOPMENT NO. Q/M
A
CROW-R SCHEMATICS
B
CONTENTS
Pass2
1. TABLE OF CONTENTS - (MJS)
B
2. CHANGE LOG
C
C
3. CROW BLOCK DIAGRAM
4. PCI EDGE CONNECTOR
5. VIDEO PCI INTERFACE AND DVO
6. VIDEO PWR AND GND
D
7.
VIDEO MEMORY
D
8. ANALOG VIDEO CONNECTOR
9.
10.
CONNECTORS
RS232 DRIVER
11.
E
12.
13.
14.
MECHANICAL PARTS
E
3.3V CONT POWER
1.2V, 1.8V, POWER
SPARE PARTS
15. COMPONENT LIST: A-Y
F
F
G
H
G
H
I
TOC Generated 28 Jan 2005
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
6 9
OUTSIDE MAX
INSIDE MAX
0.13
2.0
I
PART NO.
39M4939
TITLE
1/1SCALE:
TABLE OF CONTENTS
DESIGNER
CHECKED
APPROVED
6-27-2005_9:24
MJS
SHEET OF
1
108754321
Physical DesignRobert Piper
Les Garrett
15
JJ
REL
961 2 3 4 5 7 8 10
EC NO.DATEQTYREL FOR ASM
PART NO.
A
DEVELOPMENT NO. Q/M
A
Change Log:
PASS 1
CHANGED VIDEO TO RN50 - 1/28/05 - RMP
B
CHANGED TO DDR2 MEMORY - 1/28/05 - RMP
Removed COM3 Debug header - 1/28/05 - RMP
PASS 2
Header Code J1MHA Assembly P/N: 39M4941
B
CHANGED TO DDR1 MEMORY - 5/28/05 - RMP
C
Fixed Memory address wiring - 5/28/05 - RMP
C
Added Regulator for DDR1 memory - 5/28/05 - RMP
D
D
E
F
E
F
G
H
G
H
I
PART NO.
I
39M4939
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
6 9
OUTSIDE MAX
INSIDE MAX
0.13
2.0
TITLE
1/1SCALE:
DESIGNER
CHECKED
APPROVED
CHANGE LOG
6-27-2005_9:24
SHEET OF
2
108754321
Physical DesignRobert Piper
Les Garrett
15
JJ
REL
961 2 3 4 5 7 8 10
EC NO.DATEQTYREL FOR ASM
PART NO.
A
DEVELOPMENT NO. Q/M
A
SMP
CONDOR
RS232
B
I2C/USB/misc
Digital Video
B
C
C
Ethernet
Analog Video
D
Video
D
Video
E
Harrier
F
MUX
Com Port Block Diagram
PCI
Crow
E
F
RS232 Driver
External
Debug Header
Bus A
External
G
G
Com1
405GP
Com2
Internal
Bus B
H
H
RS232 Driver
I
RS232 Driver
I
External
PART NO.
39M4939
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
6 9
OUTSIDE MAX
INSIDE MAX
0.13
2.0
TITLE
1/1SCALE:
DESIGNER
CHECKED
APPROVED
CROW BLOCK DIAGRAM
6-27-2005_9:24
Les Garrett
SHEET OF
3
108754321
Physical DesignRobert Piper
JJ
15
REL
961 2 3 4 5 7 8 10
EC NO.DATEQTYREL FOR ASM
PART NO.
A
4/7/02 JWD- Added PRSNT, PME test point, Changed M66EN pull-down to 0-Ohm
DEVELOPMENT NO. Q/M
A
PRIMARY PCI
J31
B
5
5
5
5
5
5
5
5
5
5
5
5
C
5
5
5
5
5
Maximum PCI Power
Aux3 ±5% 375mA max. =1.237 W
3.3 V ±0.3 V 7.6 A max.
5 V ±5% 5 A max.
D
12 V ±5% 500 mA
-12 V ±10% 100 mA
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
E
PCI_3.3V
5
5
5
PPCI_AD0
PPCI_AD1
PPCI_AD2
PPCI_AD3
PPCI_AD4
PPCI_AD5
PPCI_AD6
PPCI_AD7
PPCI_AD8
PPCI_AD9
PPCI_AD10
PPCI_AD11
PPCI_AD12
PPCI_AD13
PPCI_AD14
PPCI_AD15
PPCI_AD16
PPCI_AD17
PPCI_AD18
PPCI_AD19
PPCI_AD20
PPCI_AD21
PPCI_AD22
PPCI_AD23
PPCI_AD24
PPCI_AD25
PPCI_AD26
PPCI_AD27
PPCI_AD28
PPCI_AD29
PPCI_AD30
PPCI_AD31
PPCI_C/BE0_N
PPCI_C/BE1_N
PPCI_C/BE2_N
PPCI_C/BE3_N
A58
B58
A57
B56
A55
B55
A54
B53
B52
A49
B48
A47
B47
A46
B45
A44
A32
B32
A31
B30
A29
B29
A28
B27
A25
B24
A23
B23
A22
B21
A20
B20
A52
B44
B33
B26
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C/BE0#
C/BE1#
C/BE2#
C/BE3#
RSV1
RSV2
RSV3
RSV4
3.3Vaux
PME#
PRSNT1#
PRSNT2#
LOCK#
PERR#
SERR#
REQ64#
ACK64#
SBO#
SDONE
TRST#
TCK
TMS
TDO
TDI
A9
B10
A11
B14
A14
A19
B9
B11
B39
B40
B42
A60
B60
A41
A40
A1
B2
A3
B4
A4
PRSNT1# PRSNT2# Expansion Configuration
Open Open No expansion board present
Ground Open Expansion board present, 25 W maximum
Open Ground Expansion board present, 15 W maximum
Ground Ground Expansion board present, 7.5 W maximum
5
0
R527
0
0
R73
PPCI_SERR#
R72
NOPOP
NOPOP
5/23/02 JWD - Added 0 OHM NOPOP per ATI request
B
C
D
E
CLK
-12V
A6
B7
A7
B8
B16
A15
B49
B1
A2
B3
B15
B17
A18
B22
A24
B28
A30
B34
A35
A37
B38
A42
B46
A48
A56
B57
PPCI_INTA#
PPCI_CLK
PPCI_RST_N
M66EN
5
5
5
11
F
G
H
I
5
C188
C184
C180 C179
C178 C177
C185
C194
C174 C173
C169
C183
5
5
100N
100N 100N
100N 100N
100N
100N
100N 100N
100N 100N
100N
5
5
F
5
5
5
5
G
H
I
PCI_5V
C650 C526
100N
PCI_5V
C172
C525 C524
100N 100N
C171C170
100N100N
C195
100N
C196
100N
C191
100N
C523
100N
C192 C189
100N
C522
100N
C190
100N
100N
100N
C649
PCI_3.3V
100N
100N
PPCI_PAR
PPCI_FRAME_N
PPCI_TRDY_N
PPCI_IRDY_N
PPCI_STOP_N
PPCI_DEVSEL_N
PPCI_IDSEL
PPCI_REQ0_N
PPCI_GNT0_N
PCI_3.3V
PCI_5V
A43
A34
A36
B35
A38
B37
A26
B18
A17
A21
B25
A27
B31
A33
B36
A39
B41
B43
A45
A53
B54
A10
A16
B19
A59
B59
A5
B5
B6
A8
A61
B61
A62
B62
PAR
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
IDSEL
REQ#
GNT#
3.3V0
3.3V1
3.3V2
3.3V3
3.3V4
3.3V5
3.3V6
3.3V7
3.3V8
3.3V9
3.3V10
3.3V11
VIO_0
VIO_1
VIO_2
VIO_3
VIO_4
5V0
5V1
5V2
5V3
5V4
5V5
5V6
5V7
INTA#
INTB#
INTC#
INTD#
RESET#
M66EN
+12V
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
CONN2x60
PCI UNIVERSAL
SILKSCREEN:
ADD SILKSCREEN PIN NUMBER EVERY
5 PINS ON BOTH "A" AND "B" SIDES.
6 9
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
OUTSIDE MAX
INSIDE MAX
0.13
2.0
PART NO.
39M4939
TITLE
1/1SCALE:
DESIGNER
CHECKED
APPROVED
PCI EDGE CONNECTOR
6-27-2005_9:24
Physical DesignRobert Piper
Les Garrett
SHEET OF
4
108754321
15
JJ
REL
961 2 3 4 5 7 8 10
EC NO.DATEQTYREL FOR ASM
PART NO.
A
PCI Buffers
U76
P/D_NUM=77P3820
PPCI_AD9
4
4
4
B
4
4
4
4
4
4
C
4
4
4
4
4
4
4
4
D
4
4
4
E
4
4
4
4
4
4
4
4
4
F
4
4
4
4
4
G
4
4
4
4
4
H
4
4
4
4
4
4
4
4
I
4
PPCI_AD7
PPCI_AD6
PPCI_AD2
PPCI_AD1
PPCI_AD0
PPCI_AD3
PPCI_AD4
PPCI_AD5
PPCI_C/BE0_N
R522
PPCI_AD14
PPCI_PAR
PPCI_AD15
PPCI_AD12
PPCI_AD10
PPCI_AD8
PPCI_AD11
PPCI_AD13
PPCI_C/BE1_N
PPCI_SERR#
R521
P/D_NUM=77P3820
PPCI_AD18
PPCI_C/BE2_N
PPCI_IRDY_N
PPCI_DEVSEL_N
PPCI_CLK
PPCI_INTA#
PPCI_STOP_N
PPCI_TRDY_N
PPCI_FRAME_N
PPCI_AD16
R520
R661
PPCI_AD25
PPCI_C/BE3_N
PPCI_AD23
PPCI_AD22
PPCI_AD17
PPCI_AD19
PPCI_AD20
PPCI_AD21
PPCI_IDSEL
PPCI_AD24
R519
R660
P/D_NUM=77P3820
PPCI_RST_N
PPCI_GNT0_N
PPCI_AD31
PPCI_AD29
PPCI_AD28
PPCI_AD26
PPCI_AD27
PPCI_AD30
PPCI_REQ0_N
R81
R518
R659
-The Clock (PCI_CLK) has been buffered.
1K
1K
1K
1K
1K
1K
100
1K
1K
3
1A1
4
1A2
7
1A3
8
1A4
11
1A5
14
2A1
17
2A2
18
2A3
21
2A4
22
2A5
1
1OE#
13 12
2OE# GND
3384
PI3C3384QEX
U72
3
1A1
4
1A2
7
1A3
8
1A4
11
1A5
14
2A1
17
2A2
18
2A3
21
2A4
22
2A5
1
1OE#
13 12
2OE# GND
3384
PI3C3384QEX
U73
3
1A1
4
1A2
7
1A3
8
1A4
11
1A5
14
2A1
17
2A2
18
2A3
21
2A4
22
2A5
1
1OE#
13 12
2OE# GND
3384
PI3C3384QEX
U74
3
1A1
4
1A2
7
1A3
8
1A4
11
1A5
14
2A1
17
2A2
18
2A3
21
2A4
22
2A5
1
1OE#
13 12
2OE# GND
3384
PI3C3384QEX
U75
3
1A1
4
1A2
7
1A3
8
1A4
11
1A5
14
2A1
17
2A2
18
2A3
21
2A4
22
2A5
1
1OE#
13 12
2OE# GND
3384
PI3C3384QEX
VCC
1B1
1B2
1B3
1B4
1B5
2B1
2B2
2B3
2B4
2B5
VCC
1B1
1B2
1B3
1B4
1B5
2B1
2B2
2B3
2B4
2B5
VCC
1B1
1B2
1B3
1B4
1B5
2B1
2B2
2B3
2B4
2B5
VCC
1B1
1B2
1B3
1B4
1B5
2B1
2B2
2B3
2B4
2B5
VCC
1B1
1B2
1B3
1B4
1B5
2B1
2B2
2B3
2B4
2B5
24
2
5
6
9
10
15
16
19
20
23
24P/D_NUM=77P3820
2
5
6
9
10
15
16
19
20
23
24
2
5
6
9
10
15
16
19
20
23
24P/D_NUM=77P3820
2
5
6
9
10
15
16
19
20
23
24
2
5
6
9
10
15
16
19
20
23
PCI_3.3V
3V_PPCI_AD9
3V_PPCI_AD7
3V_PPCI_AD6
3V_PPCI_AD2
3V_PPCI_AD1
3V_PPCI_AD0
3V_PPCI_AD3
3V_PPCI_AD4
3V_PPCI_AD5
3V_PPCI_C/BE0_N
PCI_3.3V
3V_PPCI_AD14
3V_PPCI_PAR
3V_PPCI_AD15
3V_PPCI_AD12
3V_PPCI_AD10
3V_PPCI_AD8
3V_PPCI_AD11
3V_PPCI_AD13
3V_PPCI_C/BE1_N
3V_PPCI_SERR#
PCI_3.3V
3V_PPCI_AD18
3V_PPCI_C/BE2_N
3V_PPCI_IRDY_N
3V_PPCI_DEVSEL_N
3V_PPCI_CLK
3V_PPCI_INTA#
3V_PPCI_STOP_N
3V_PPCI_TRDY_N
3V_PPCI_FRAME_N
3V_PPCI_AD16
PCI_3.3V
3V_PPCI_AD25
3V_PPCI_C/BE3_N
3V_PPCI_AD23
3V_PPCI_AD22
3V_PPCI_AD17
3V_PPCI_AD19
3V_PPCI_AD20
3V_PPCI_AD21
3V_PPCI_IDSEL
3V_PPCI_AD24
PCI_3.3V
3V_PPCI_RST_N
3V_PPCI_GNT0_N
3V_PPCI_AD31
3V_PPCI_AD29
3V_PPCI_AD28
3V_PPCI_AD26
3V_PPCI_AD27
3V_PPCI_AD30
3V_PPCI_REQ0_N
R80
100
54
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5,9
5
5
5
5
5
5
5
5
R24
R25
0 0
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5,9
5
5
5
5
5
5
5
5
5
5
SR4
3V_PPCI_AD0
3V_PPCI_AD1
3V_PPCI_AD2
3V_PPCI_AD3
3V_PPCI_AD4
3V_PPCI_AD5
3V_PPCI_AD6
3V_PPCI_AD7
3V_PPCI_AD8
3V_PPCI_AD9
3V_PPCI_AD10
3V_PPCI_AD11
3V_PPCI_AD12
3V_PPCI_AD13
3V_PPCI_AD14
3V_PPCI_AD15
3V_PPCI_AD16
3V_PPCI_AD17
3V_PPCI_AD18
3V_PPCI_AD19
3V_PPCI_AD20
3V_PPCI_AD21
3V_PPCI_AD22
3V_PPCI_AD23
3V_PPCI_AD24
3V_PPCI_AD25
3V_PPCI_AD26
3V_PPCI_AD27
3V_PPCI_AD28
3V_PPCI_AD29
3V_PPCI_AD30
3V_PPCI_AD31
3V_PPCI_IDSEL
3V_PPCI_C/BE0_N
3V_PPCI_C/BE1_N
3V_PPCI_C/BE2_N
3V_PPCI_C/BE3_N
3V_PPCI_CLK
3V_PPCI_RST_N
3V_PPCI_DEVSEL_N
3V_PPCI_FRAME_N
3V_PPCI_INTA#
3V_PPCI_IRDY_N
3V_PPCI_PAR
3V_PPCI_SERR#
3V_PPCI_STOP_N
3V_PPCI_TRDY_N
3V_PPCI_REQ0_N
3V_PPCI_GNT0_N
TP_PPCI_VREF
TP_TESTEN
1K
RN50_XTALIN
5
RN50_XTALOUT
5
0
R22
R23
0
AB21
AA21
Y21
AB20
AA20
Y20
AB19
Y19
AB18
AA18
Y18
AB17
AA17
Y17
AB16
AA16
Y13
AA12
Y12
AB11
AA11
Y11
AB10
AA10
Y9
AB8
AA8
Y8
AB7
AA7
Y7
AA6
Y10
AA19
AB15
AA13
AA9
Y16
AB5
Y15
Y14
W18
AB13
AA15
Y6
AA5
AA14
AB14
Y5
W5
Y3
AA3
V22
U21
V21
Place all components close to BGA
C657
RN50_XTALIN
5
Y1
27
MHz
5 RN50_XTALOUT
423
1MEG
1
R64
10P
C656
10P
UPDATE P/N
AD_0
AD_1
AD_2
AD_3
AD_4
AD_5
AD_6
AD_7
AD_8
AD_9
AD_10
AD_11
AD_12
AD_13
AD_14
AD_15
AD_16
AD_17
AD_18
AD_19
AD_20
AD_21
AD_22
AD_23
AD_24
AD_25
AD_26
AD_27
AD_28
AD_29
AD_30
AD_31
IDSEL
CBE0_N
CBE1_N
CBE2_N
CBE3_N
PCICLK
RESET_N
DEVSEL_N
FRAME_N
INTROUT_N
IRDY_N
PAR
SERR_N
STOP_N
TRDY_N
REQ_N
GNT_N
NC_W5
TEST_MCLK
TEST_YCLK
TESTEN
XTALIN
XTALOUT
U1
ATI_RN50
SIGNAL
1 of 4
V
3.3
DVO INTERFACE
PCI INTERFACE
INTERFACE
TEST
XTAL
DAC2 INTERFACE DAC INTERFACE GPIO INTERFACE
LCDCNTL_0
LCDCNTL_1
LCDCNTL_2
LCDCNTL_3
LCDDATA_0
LCDDATA_1
LCDDATA_2
LCDDATA_3
LCDDATA_4
LCDDATA_5
LCDDATA_6
LCDDATA_7
LCDDATA_8
LCDDATA_9
LCDDATA_10
LCDDATA_11
LCDDATA_12
LCDDATA_13
LCDDATA_14
LCDDATA_15
LCDDATA_16
LCDDATA_17
LCDDATA_18
LCDDATA_19
LCDDATA_20
LCDDATA_21
LCDDATA_22
LCDDATA_23
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
HSYNC
VSYNC
VGADDCCLK
VGADDCDAT
RSET
R2
G2
B2
H2SYNC
V2SYNC
CRT2DDCCLK
CRT2DDCDAT
R2SET
B21
C21
A20
B20
C20
A19
B19
C19
A18
B18
C18
A17
B17
C17
A16
B16
C16
A15
B15
C15
A14
B14
C14
A13
B13
C13
B12
C12
A12
C11
B11
A11
C10
B10
A10
C9
B9
A9
C8
B8
A8
C7
B7
F22
R
G21
G
G22
B
T22
U22
T20
T21
F21
K21
L22
L21
P21
P20
R20
R21
K22
EXT_TMDS_VSYNC
EXT_TMDS_HSYNC
EXT_TMDS_DE
EXT_TMDS_CLK
TP_EXT_TMDS_BLU0
EXT_TMDS_BLU1
EXT_TMDS_BLU2
EXT_TMDS_BLU3
EXT_TMDS_BLU4
EXT_TMDS_BLU5
EXT_TMDS_BLU6
EXT_TMDS_BLU7
TP_EXT_TMDS_GRN0
EXT_TMDS_GRN1
EXT_TMDS_GRN2
EXT_TMDS_GRN3
EXT_TMDS_GRN4
EXT_TMDS_GRN5
EXT_TMDS_GRN6
EXT_TMDS_GRN7
TP_EXT_TMDS_RED0
EXT_TMDS_RED1
EXT_TMDS_RED2
EXT_TMDS_RED3
EXT_TMDS_RED4
EXT_TMDS_RED5
EXT_TMDS_RED6
EXT_TMDS_RED7
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
VEEPROM_DAT
VEEPROM_CLK
GPIO_7
GPIO_8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
VIDEO_RED
VIDEO_GREEN
VIDEO_BLUE
VIDEO_HSYNC
VIDEO_VSYNC
ATI_DDCCLK
ATI_DDCDAT
SR2
+1%/-1%
TP_RED2
TP_GREEN2
TP_BLUE2
TP_H2SYNC
TP_V2SYNC
TP_DDC_CLK
TP_DDC_DAT
R2SET
6 9
5
5
5
5
5,11
5
5
5
5
5
5
5
5
499
5,8
5,8
5,8
8
8
8
8
5
5
5
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
5
5
5
5
VID_R_ROM_CS
7
GPIO_8
5
VEEPROM_CLK
VEEPROM_DAT
STRAPS
PCIFBSKEW(1:0)
X1CLK_SKEW(1:0)
ROMIDCFG(2:0)
BUSCFG GPIO(4)
VGA_DISABLE
The default values outlines in the table above are with respect to these logics-not the video chip.
PCI_3.3V
R626
10K
VEN_P/D_NUM=M25P10-AVMN6P
PCI_3.3V
EEPROM_AT24C01A-10SU-1_8
PIN DESCRIPTION
GPIO(1:0)
GPIO(3:2) CLOCK PHASE ADJUSTMENT BETWEEN X1 CLK AND X2 CLK
GPIO(13:11)
GPIO(8)ID_DISABLE
PCI CLOCK FEEDBACK PHASE ADJUSTMENT FOR PCI66
00 = 0 tap delay from default
01 = -1 tap delay from default
10 = +1 taps delay from default
11 = -2 taps delay from default
00- 0 TAP DELAY
01-1 TAP DELAY
10-2 TAP DELAY
11-3 TAP DELAY
IF NO ROM ATTACHED, CONTROLS CHIP IDS.
IF ROM ATTACHED IDENTIFIES ROM TYPE
000-NO ROM (VIDEO BIOS INTEGRATED INTO SYSTEM BIOS)
001-RESERVED
010-RESERVED
011-RESERVED
100-RESERVED
101-SERIAL AT25F1024ROM (ATMEL), CHIP ID IS FROM ROM
110-SERIAL ST MICRO M25P10/M25P05 ROM (ST), CHIP ID FROM ROM
111-SERIAL NEXFLASH NX25F011B/NX25F015B ROM (ISSI)
CHIP ID IS FROM ROM
0-NORMAL OPERATION
1-SHUTS THE CHIP DOWN BY NOT RESPONDING TO ANY CONFIG
CYCLES. IN A SYSTEM WITH TWO GRAPHICS CHIPS, ONE ON THE
MOTHERBOARD, THE OTHER ON AN ADD-IN CARD, THE STRAP CAN BE
USED TO DISABLE ONE OF THE TWO THROUGH A JUMER
BUS_CFG
0 = PCI 66MHz (default)
1 = PCI 33MHz(PLL bypass)
0-VGA CONTROLLER CAPABILITY ENABLINGGPIO(7)
1-THE DEVICE WILL NOT BE RECOGNIZED AS THE SYSTEM VGA COTROLLER
PCI_3.3V
Change Part
U90
EEPROM_SERIAL_SPI
1 8
S_N VCC
2
Q
3
W_N
4
GND
P/D_NUM=77P4341
U89
EEPROM
8 1
7
5
A0_NC
VCC
WP_NC
A2_NC
SCL
SDA
SERIAL-I2C
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
A1
GND
2
36
4
OUTSIDE MAX
INSIDE MAX
HOLD_N
7
6
C
5
D
C661
NOPOP
R530
R529
R5372KR5382KR539
GPIO_10
GPIO_9
100N
PCI_3.3V
NOPOP
R531
4.7K
0.13
2.0
NOPOP
4.7K
4.7K
2K
DEFAULT
INTERNAL
PULL-DWN
INTERNAL
PULL-DWN
000
INTERNAL
PULL-DWN
1
INTERNAL
PULL-DWN
5
5
Check POP/ NOPOP
5
5
5
5
5,11
5
5
5
5
5
5
5
5
5
5
5,8
5,8
5,8
5
1/1SCALE:
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_8
VIDEO_RED
VIDEO_GREEN
VIDEO_BLUE
R2SET
DEVELOPMENT NO. Q/M
PCI_3.3V
R627
NOPOP
4.7K
R628
POP
4.7K
R629
NOPOP
NOPOP
R632
4.7K
POP
NOPOP
R638
4.7K
NOPOP
POP
R643
4.7K
NOPOP
R646
4.7K
POP
POP
R652
4.7K
NOPOP
R655
4.7K
4.7K
POP
R635
4.7K
NOPOP
NOPOP
NOPOP
R649
4.7K
NOPOP
NOPOP
PART NO.
R573
R574
R575
R557
R630
4.7K
R636
4.7K
R639
4.7K
R641
4.7K
R644
4.7K
R650
4.7K
R653
4.7K
R656
4.7K
+1%/-1%
+1%/-1%
+1%/-1%
+1%/-1%
R633
4.7K
NOPOP
NOPOP
R645
4.7K
R647
4.7K
POP
POP
R631
4.7K
NOPOP
R634
4.7K
NOPOP
R637
4.7K
R640
4.7K
NOPOP
R642
4.7K
NOPOP
R648
4.7K
NOPOP
R651
4.7K
NOPOP
R654
4.7K
75
75
75
499
39M4939
TITLE
VIDEO PCI INTERFACE AND DVO
6-27-2005_9:24
DESIGNER
CHECKED
APPROVED
SHEET OF
5
108754321
Physical DesignRobert Piper
Les Garrett
15
A
B
C
D
E
F
G
H
I
JJ
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