4321 5
DATE EC NO.
108 976
EC NO.DATE
PART NO.
REL
A
? ?
???????
DEVELOPMENT NO.
Q/M
A
LAWRENCIUM - PASS1
B
Contents:
B
103
1. TITLE
2. CHANGE LOG
C
C
3. BLOCK DIAGRAM
4. FPGA / CONFIGURATOR
5. FPGA MEMORY INTERFACE
6. FPGA POWER
D
7. USB FX2
Lr
D
8. VIDEO RAM / NIOS RAM
9. SYSTEM CONNECTOR
LAWRENCIUM
10. CHECK VOLTAGE
E
E
(262)
F
F
G
Engineers:
H
I
Jim Dalton
Ryan Kather
3-7609
4-5586
G
H
I
IBM CONFIDENTIAL
PART NO.
J
MUST CONFORM TO ENG
SPEC: 80X2324
PRELIMINARY
1 2 3 4 5 6 7 9 108
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
OUTSIDE MAX
INSIDE MAX
0.13
2.0 APPROVED
SCALE: 1/1
TITLE
TITLE
DESIGNER
CHECKED
SHEET
LAWRENCIUM
2-3-2005_9:08
RMK 11/02/2004
1
???
???
OF
JWD
10
J
4321 5
DATE EC NO.
108 976
EC NO.DATE
PART NO.
REL
A
? ?
???????
DEVELOPMENT NO.
Q/M
A
Change Log:
B
B
C
D
E
C
D
E
USE LEAD REDUCED PARTS WHERE EVER POSSIBLE
F
F
There is a field for this in DxDatabook
Use R402 where ever possible as long as power permits (2.3mW for 4.7K@3.3V)
Comb through PCB.ERR, verify that all open nets are supposed to be open
G
G
Are all gates connected to power and ground?
Place all unused gates on last page. See if any logic can be reduced.
Just make sure that the Polyclad Turbo 370 laminate material is called out somewhere in the gerbers
H
H
(readme and board files if possible) since we don't have mechanical assembly drawings at this stage
I
IBM CONFIDENTIAL
PART NO.
I
J
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
1 2 3 4 5 6 7 9 108
OUTSIDE MAX
INSIDE MAX
CHANGE LOG
SCALE: 1/1
0.13
2.0 APPROVED
TITLE
DESIGNER
CHECKED
SHEET
LAWRENCIUM
2-3-2005_9:08
RMK 11/02/2004
2
???
???
OF
JWD
10
J
4321 5
DATE EC NO.
108 976
EC NO.DATE
PART NO.
REL
A
B
? ?
???????
DEVELOPMENT NO.
Q/M
A
B
C
D
E
C
D
E
F
G
F
G
H
I
H
I
IBM CONFIDENTIAL
PART NO.
J
BLOCK DIAGRAM
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
1 2 3 4 5 6 7 9 108
OUTSIDE MAX
INSIDE MAX
0.13
2.0 APPROVED
SCALE: 1/1
TITLE
DESIGNER
CHECKED
SHEET
LAWRENCIUM
2-3-2005_9:08
RMK 11/02/2004
3
???
???
OF
JWD
17
J
4321 5
DATE EC NO.
108 976
EC NO.DATE
PART NO.
REL
?
???????
DEVELOPMENT NO.
Q/M
To program configurator, pull MSEL0 and MSEL1 low
A
A
and use the AS Mode header instead of the JTAG one
Configurator operates in AS Mode
?
3.3VC
JTAG header for debug purposes, NOPOP for production
C5
B
J1
FPGA_TCK
4
FPGA_TDO
4
FPGA_TMS
4
FPGA_TDI
4
C
1
C1
3
C3
5
C5
7
C7
9
C9
CONN2X5
C2
C4
C6
C8
C10
2
4
6
8
10
3.3VC
4,9
4,9
4,9
100N
FPGA_ASDO
FPGA_CSO_N
FPGA_DCLK
1
2
9
15
7
16
VCC_1
VCC_2
VCC_9
ASDI
CS_N
DCLK
FEPROM_SERIAL
U1
SO16
DATA
NC_3
NC_4
NC_5
NC_6
NC_11
NC_12
NC_13
NC_14
8
3
4
5
6
11
12
13
14
FPGA_DATA0
4,9
B
C
10
GND
FEPROM_EPCS16SI16N
3.3VC
3.3VC
USB_FX2_DATA[0:15]
R98 R95
D
FPGA_TCK
4
FPGA_TMS
4
FPGA_TDI
4
FPGA_TDO
4
E
F
G
8
1_5VC
H
R51
4.7K
3.3VC
U5
SUPERVISORY
4 2
VCC
V
3.0
VID_MEM_CLK
RESET_N
GNDRESET_IN
R92
R88
13
R90
10K
3.3VC
4.7K
R94
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
4
NIOS_RESET_N
R96
10K10K
DVO_RED7
DVO_RED6
DVO_RED5
DVO_RED4
DVO_RED3
DVO_GREEN7
DVO_GREEN6
DVO_GREEN5
DVO_GREEN4
DVO_GREEN3
DVO_GREEN2
DVO_BLUE7
DVO_BLUE6
DVO_BLUE5
DVO_BLUE4
DVO_BLUE3
DVO_HSYNC
DVO_VSYNC
DVO_DE
CKVM_RESERVED131
CKVM_RESERVED96
R76 22
FPGA_24_MHZ
10K
9
J13
NSTATUS
J14
TCK
J15
TMS
H14
TDI
H15
TDO
N13
IO_N13
P14
IO_P14
P15
IO_P15
R16
IO_R16
N15
IO_N15
N16
IO_N16
K14
IO_K14
N14
IO_N14
M13
IO_M13
M14
IO_M14
L13
IO_L13
M15
IO_M15
M16
IO_M16
L14
IO_L14
L15
IO_L15
L16
IO_L16
K16
IO_K16
K12
IO_K12_VREF2B3
L12
IO_L12_DPCLK5
H12
IO_H12_VREF1B3
K15
IO_K15_PLL2_OUTN
J16
IO_J16_PLL2_OUTP
H16
CLK3
G16
CLK2
U9
CYCLONE256P
BANK3
0000
V
IO_G12_VREF0B3
IO_F12_DPCLK4
DEVICE=CYCLONE_EP1C12F256C6
IO_G14
IO_G13
IO_G15
IO_F16
IO_F14
IO_F13
IO_F15
IO_E16
IO_E15
IO_D16
IO_A4
IO_A2
IO_E13
IO_D14
IO_H13
IO_B16
IO_C15
IO_C14
IO_D13
ToDo: Find out if the MAC will require any special function pins i.e. PLL out??
G14
G13
G15
F16
F14
F13
F15
E16
E15
D16
A4
A2
E13
D14
H13
B16
C15
C14
D13
G12
F12
R25 22
R23 22
R22 22
CKVM_RESERVED125
CKVM_RESERVED126
CKVM_RESERVED127
MII_RXD0
MII_RXD1
MII_RXD2
MII_RXD3
MII_RXCLK
MII_TXCLK
22R26
22R24
MII_CD
MII_CRS
MII_MDC
MII_MDIO
MII_RXDV
MII_RXERR
22R21
9
9
9
9
9
9
MII_TXD0
MII_TXD1
MII_TXD2
MII_TXD3
9
9
9
9
9
9
MII_TXEN
MII_TXERR
9
9
9
9
9
9
9
9
9
9
FPGA_CE_N
R100
10K
4,9
4,9
9
9
9
4,9
4,9
FPGA_CONF_DONE
9
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
8
NIOS_MEM_CLK
10K
FPGA_CSO_N
FPGA_DATA0
FPGA_NCONFIG
FPGA_MSEL0
FPGA_MSEL1
FPGA_DCLK
FPGA_ASDO
FX2_24_MHZ
USB_FX2_RESET_N
USB_FX2_IFCLK
USB_FX2_SLRD
USB_FX2_SLWR
USB_FX2_FLAGA
USB_FX2_FLAGB
USB_FX2_FLAGC
USB_FX2_SLOE
USB_FX2_SLCS_N
USB_FX2_ADDR0
USB_FX2_ADDR1
USB_FX2_PA0_INT0_N
USB_FX2_PA1_INT1_N
USB_FX2_PA3
9
9
9
4
9
R75 24
CKVM_RESERVED128
CKVM_RESERVED129
CKVM_RESERVED130
FPGA_24_MHZ
DVO_CLK
9
10K
CKVM_RESERVED63
9
CKVM_RESERVED64
9
R104 22
CKVM_RESERVED133
INIT_DONE can be used as IO
CLKUSR can be used as IO
D4
INIT_DONE
C2
CLKUSR
G4
NCSO
H2
DATA0
H3
NCONFIG
H4
N.C.
NCEO
J4
NCE
J3
MSEL0
J2
MSEL1
K4
DCLK
K3
ASDO
K13
CONF_DONE
C3
IO_C3
B1
IO_B1
F4
IO_F4
D3
IO_D3
E4
IO_E4
E3
IO_E3
D2
IO_D2
E2
IO_E2
D1
IO_D1
F3
IO_F3
G3
IO_G3
F2
IO_F2
E1
IO_E1
G2
IO_G2
F1
IO_F1
G5
IO_G5_VREF0B1
F5
IO_F5_DPCLK1
H5
IO_H5_VREF1B1
G1
CLK0
H1
CLK1
J1
IO_J1_PLL1_OUTP
K2
IO_K2_PLL1_OUTN
U9
CYCLONE256P
BANK1
0000
V
IO_K5_VREF2B1
IO_L5_DPCLK0
DEVICE=CYCLONE_EP1C12F256C6
IO_L3
IO_K1
IO_L1
IO_L2
IO_M1
IO_N1
IO_M2
IO_N2
IO_M3
IO_M4
IO_N3
IO_L4
IO_R1
IO_P2
IO_P3
IO_N4
L3
K1
L1
L2
M1
N1
M2
N2
M3
M4
N3
L4
R1
P2
P3
N4
K5
L5
USB_FX2_DATA15
USB_FX2_DATA14
USB_FX2_DATA13
USB_FX2_DATA12
USB_FX2_DATA11
USB_FX2_DATA10
USB_FX2_DATA9
USB_FX2_DATA8
USB_FX2_DATA7
USB_FX2_DATA6
USB_FX2_DATA5
USB_FX2_DATA4
USB_FX2_DATA3
USB_FX2_DATA2
USB_FX2_DATA1
USB_FX2_DATA0
CKVM_RESERVED135
CKVM_RESERVED43
9
9
7
D
E
F
G
H
R50
36.5K
I
J
RESET_IN threshold is 1.27V.
3.3VC
L1
CLOCK_VCC
IND2P_FE_BLM18BD601SN1D
1 2 3 4 5 6 7 9 108
600
ohms
C37
1U
R52
3.3VC
C32
4.7K
100N
1
OE/NC
OS1
OSC
24
MHz
OUT
GNDVCC
3
24
R91 24
FPGA_24_MHZ
4
FPGA / CONFIGURATOR
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
OUTSIDE MAX
INSIDE MAX
PART NO.
TITLE
SCALE: 1/1
0.13
2.0 APPROVED
DESIGNER
CHECKED
SHEET
IBM CONFIDENTIAL
LAWRENCIUM
2-9-2005_15:14
RMK 11/02/2004
4
???
???
OF
JWD
I
J
4
10
4321 5
DATE EC NO.
108 976
EC NO.DATE
PART NO.
REL
NIOS_MEM_ADDR[0:11]
8
NIOS_MEM_ADDR0
NIOS_MEM_ADDR1
A
B
NIOS_MEM_DATA[0:15]
8
NIOS_MEM_ADDR2
NIOS_MEM_ADDR3
NIOS_MEM_ADDR4
NIOS_MEM_ADDR5
NIOS_MEM_ADDR6
NIOS_MEM_ADDR7
NIOS_MEM_ADDR8
NIOS_MEM_ADDR9
NIOS_MEM_ADDR10
NIOS_MEM_ADDR11
NIOS_MEM_BA0_N
8
NIOS_MEM_BA1_N
8
NIOS_MEM_LDQM
8
NIOS_MEM_UDQM
8
NIOS_MEM_DATA0
R119 22
22R118
22R28
R29 22
R117 22
22R30
22R116
R32 22
R31 22
22R33
22R34
R115 22
R35 22
22R114
22R112
R36 22
R113 22
R2
T2
R3
P4
R4
T4
R5
P5
N5
N6
P6
R6
M7
T6
R7
P7
N7
IO_R2
IO_T2
IO_R3
IO_P4
IO_R4
IO_T4
IO_R5
IO_P5
IO_N5
IO_N6
IO_P6
IO_R6
IO_M7
IO_T6
IO_R7
IO_P7
IO_N7
CYCLONE256P
U9
BANK4
0000
V
IO_R11
IO_P11
IO_N11
IO_N12
IO_M9
IO_P12
IO_R12
IO_T13
IO_R13
IO_R14
IO_P13
IO_T15
IO_R15
IO_M11_VREF0B4
IO_M12_DPCLK6
R11
P11
N11
N12
M9
P12
R12
CKVM_RESERVED54
T13
R13
R14
P13
T15
R15
M11
M12
LOCAL_IIC_SCL
LOCAL_IIC_SDA
CKVM_RESERVED55
R105 22
R45 22
R46 22
NIC_RESET_N
I2C_SDA
I2C_SCL
PWR_GOOD
22R106
22R103
9
9
9
9
5,7
5,7
9
9
NIOS_MEM_CS_N
NIOS_MEM_RAS_N
NIOS_MEM_CAS_N
NIOS_MEM_WE_N
CKVM_RESERVED132
NIOS_MEM_CKE
FPGA_CKVM_PRESENCE_N
8
8
8
8
9
8
R55
2.2K
3.3VC
U7
2
5
4
CKVM_PRESENCE_N
3
LVC1G17_SC70_5
9
? ?
???????
DEVELOPMENT NO.
Q/M
A
B
NIOS_MEM_DATA1
CKVM_RESERVED53
9
C
D
NIOS_MEM_DATA2
NIOS_MEM_DATA3
NIOS_MEM_DATA4
NIOS_MEM_DATA5
NIOS_MEM_DATA6
NIOS_MEM_DATA7
NIOS_MEM_DATA8
NIOS_MEM_DATA9
NIOS_MEM_DATA10
NIOS_MEM_DATA11
NIOS_MEM_DATA12
NIOS_MEM_DATA13
NIOS_MEM_DATA14
NIOS_MEM_DATA15
R120 22
22R37
22R110
R111 22
R38 22
22R39
22R40
R109 22
R108 22
22R41
22R107
R42 22
R44 22
22R43
22R102
M6
IO_M6_VREF2B4
M5
IO_M5_DPCLK7
R8
IO_R8
T8
IO_T8
M8
IO_M8
N8
IO_N8
P8
IO_P8
R9
IO_R9
T9
IO_T9
P9
IO_P9
N9
IO_N9
R10
IO_R10
T11
IO_T11
N10
IO_N10
P10
IO_P10
M10
IO_M10_VREF1B4
C
D
DEVICE=CYCLONE_EP1C12F256C6
E
20
R54
mA
3.3VC
110
2CR2
1
VID_MEM_ADDR[0:11]
8
VID_MEM_ADDR0
VID_MEM_ADDR1
VID_MEM_ADDR2
VID_MEM_ADDR3
F
3.3VC
C6
G
H
3.3VC
U3
EEPROM
81
VCCE0_NC
SDA
7
5
2
E1_NC
3 6
E2_NC SCL
4
GND
SERIAL-I2C
EEPROM_M24512-WMW6G
WC_N
100N
LOCAL_IIC_SCL
LOCAL_IIC_SDA
5,7
5,7
VID_MEM_DATA[0:15]
8
VID_MEM_ADDR4
VID_MEM_ADDR5
VID_MEM_ADDR6
VID_MEM_ADDR7
VID_MEM_ADDR8
VID_MEM_ADDR9
VID_MEM_ADDR10
VID_MEM_ADDR11
CKVM_RESERVED65
9
VID_MEM_DATA0
VID_MEM_DATA1
VID_MEM_DATA2
VID_MEM_DATA3
VID_MEM_DATA4
VID_MEM_DATA5
VID_MEM_DATA6
VID_MEM_DATA7
VID_MEM_DATA8
VID_MEM_DATA9
VID_MEM_DATA10
VID_MEM_DATA11
VID_MEM_DATA12
VID_MEM_DATA13
VID_MEM_DATA14
R79 22
22R58
22R77
R81 22
R20 22
22R19
22R60
R59 22
R12 22
22R57
22R18
R61 22
R56 22
22R85
22R16
R63 22
R15 22
22R62
22R65
R13 22
R14 22
22R64
22R67
R9 22
R66 22
22R11
R10 22
B15
IO_B15
A15
IO_A15
B14
IO_B14
C13
IO_C13
B13
IO_B13
A13
IO_A13
B12
IO_B12
C12
IO_C12
E9
IO_E9
D12
IO_D12
D11
IO_D11
C11
IO_C11
B11
IO_B11
E11
IO_E11_VREF0B2
E12
IO_E12_DPCLK3
A11
IO_A11
B10
IO_B10
C10
IO_C10
D10
IO_D10
A9
IO_A9
B9
IO_B9
D9
IO_D9
C9
IO_C9
C8
IO_C8
D8
IO_D8
E8
IO_E8
A8
IO_A8
B8
IO_B8
CYCLONE256P
U9
BANK2
0000
V
IO_D7
IO_C7
IO_B7
IO_A6
IO_E7
IO_B6
IO_C6
IO_D6
IO_D5
IO_C5
IO_B5
IO_D15
IO_B4
IO_C4
IO_B3
IO_E14
DEV_CLRN
IO_E6_VREF2B2
IO_E5_DPCLK2
D7
C7
B7
A6
E7
B6
C6
D6
D5
C5
B5
CKVM_RESERVED56
D15
CKVM_RESERVED57
B4
CKVM_RESERVED58
C4
B3
E14
B2
E6
E5
CKVM_RESERVED59
CKVM_RESERVED60
CKVM_RESERVED61
CKVM_RESERVED62
22R7
R8 22
R68 22
22R69
22R70
R6 22
R5 22
22R71
R4 22
9
9
9
9
9
9
9
VID_MEM_CS_N
VID_MEM_RAS_N
VID_MEM_CAS_N
VID_MEM_WE_N
VID_MEM_BA0_N
VID_MEM_BA1_N
VID_MEM_LDQM
VID_MEM_UDQM
CKVM_RESERVED118
VID_MEM_CKE
ERROR_LED_N
HEARTBEAT_LED_N
8
8
8
8
8
8
8
8
9
8
LED2P_SML-511DW_ORA
20
R53
mA
3.3VC
2CR1
1
110
LED2P_SML-512MW_GRN
E
F
G
H
VID_MEM_DATA15
I
22R17
E10
IO_E10_VREF1B2
I
DEVICE=CYCLONE_EP1C12F256C6
IBM CONFIDENTIAL
PART NO.
J
FPGA MEMORY INTERFACE
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
1 2 3 4 5 6 7 9 108
OUTSIDE MAX
INSIDE MAX
0.13
2.0 APPROVED
SCALE: 1/1
TITLE
DESIGNER
CHECKED
SHEET
LAWRENCIUM
2-9-2005_15:14
RMK 11/02/2004
5
???
???
OF
JWD
10
J
4321 5
DATE EC NO.
108 976
EC NO.DATE
PART NO.
REL
A
B
1_5VC
? ?
???????
DEVELOPMENT NO.
Q/M
A
B
L2
FPGA_VCCA
IND2P_FE_BLM18BD601SN1D
C
1_5VC
D
E
C72
3.3VC
C50
C11 C73
100N
100N
C40C52
C47 C61
100N 100N
C41C44
C58 C54
100N 100N
C74C43
C46 C12
100N 100N
C68C75
C10 C14
100N 100N
C63
C53 C49
C13C16
100N
100N
C34
100N
C33
1_5VC
C17
C67
C69
2.2U4.7U
3.3VC
C23C25
600
C4
ohms
C26
2.2U
C60
C28C59
100N
C27
100N
100N100N
3.3VC
1_5VC
H6
VCCA_PLL1
J6
GNDA_PLL1
J5
GNDG_PLL1
H11
VCCA_PLL2
J12
GNDG_PLL2
J11
GNDA_PLL2
A7
VCCINT_A7
A10
VCCINT_A10
G8
VCCINT_G8
G10
VCCINT_G10
H7
VCCINT_H7
H9
VCCINT_H9
J8
VCCINT_J8
J10
VCCINT_J10
K7
VCCINT_K7
K9
VCCINT_K9
T7
VCCINT_T7
T10
VCCINT_T10
C1
VCCIO1_C1
G6
VCCIO1_G6
P1
VCCIO1_P1
CYCLONE256P
PWR & GND
0000
U9
GND_A1
GND_A16
V
GND_A5
GND_A12
GND_F6
GND_F8
GND_F9
GND_F11
GND_G7
GND_G9
GND_G11
GND_H8
GND_H10
GND_J7
GND_J9
GND_K6
GND_K8
GND_K10
GND_L6
GND_L8
GND_L9
GND_L11
GND_T1
GND_T5
GND_T12
GND_T16
A1
A16
A5
A12
F6
F8
F9
F11
G7
G9
G11
H8
H10
J7
J9
K6
K8
K10
L6
L8
L9
L11
T1
T5
T12
T16
C
D
E
100N100N
F
G
100N100N
100N100N
100N100N
100N100N
100N
100N
100N
100N
1U
4.7U
4.7U
4.7U
T3
VCCIO4_T3
L7
VCCIO4_L7
L10
VCCIO4_L10
T14
VCCIO4_T14
P16
VCCIO3_P16
K11
VCCIO3_K11
C16
VCCIO3_C16
A14
VCCIO2_A14
F10
VCCIO2_F10
F7
VCCIO2_F7
A3
VCCIO2_A3
DEVICE=CYCLONE_EP1C12F256C6
F
G
H
I
H
I
IBM CONFIDENTIAL
PART NO.
J
FPGA POWER
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
1 2 3 4 5 6 7 9 108
OUTSIDE MAX
INSIDE MAX
0.13
2.0 APPROVED
SCALE: 1/1
TITLE
DESIGNER
CHECKED
SHEET
LAWRENCIUM
2-9-2005_15:13
RMK 11/02/2004
6
???
???
OF
JWD
10
J
4321 5
DATE EC NO.
108 976
EC NO.DATE
PART NO.
REL
A
B
? ?
???????
DEVELOPMENT NO.
Q/M
A
B
3.3VC
3.3VC
C
C3
D
E
F
C39
1U
4
C71
1U
USB_FX2_RESET_N
C57 C56
100N 100N
R74
C62 C15
100N 100N
C55C36
1U
4.7K
C51
100N
1U
3.3VC
100N
3.3VC
C42
100N
R101 1K
C48
100N
FX2_24_MHZ
4
LOCAL_IIC_SCL5
LOCAL_IIC_SDA5
USB_FX2_IFCLK
4
USB_P
9
USB_N
9
55
VCC_55
7
VCC_7
11
VCC_11
17
VCC_17
27
VCC_27
32
VCC_32
43
VCC_43
3
AVCC_3
5
XTALIN
4
XTALOUT
42
RESET_N
44
WAKEUP_N
15
SCL
16
SDA
13
IFCLK
54
CLKOUT
8
D_PLUS
9
D_MINUS
U10
CY7C68013-56LFC
PD7_FD15
PD6_FD14
PD5_FD13
PD4_FD12
PD3_FD11
PD2_FD10
PD1_FD9
PD0_FD8
PB7_FD7
PB6_FD6
PB5_FD5
PB4_FD4
PB3_FD3
PB2_FD2
PB1_FD1
PB0_FD0
RDY0_SLRD
RDY1_SLWR
CTL0_FLAGA
CTL1_FLAGB
CTL2_FLAGC
52
51
50
49
48
47
46
45
25
24
23
22
21
20
19
18
1
2
29
30
31
USB_FX2_DATA15
USB_FX2_DATA14
USB_FX2_DATA13
USB_FX2_DATA12
USB_FX2_DATA11
USB_FX2_DATA10
USB_FX2_DATA9
USB_FX2_DATA8
USB_FX2_DATA7
USB_FX2_DATA6
USB_FX2_DATA5
USB_FX2_DATA4
USB_FX2_DATA3
USB_FX2_DATA2
USB_FX2_DATA1
USB_FX2_DATA0
USB_FX2_SLRD
USB_FX2_SLWR
USB_FX2_FLAGA
USB_FX2_FLAGB
USB_FX2_FLAGC
USB_FX2_DATA[0:15]
4,7
4,7
4,7
4,7
4,7
USB_FX2_SLRD
4,7
USB_FX2_SLWR
4,7
USB_FX2_FLAGA
4,7
4
4,7
4,7
4,7
4,7
4,7
4,7
4,7
USB_FX2_FLAGB
USB_FX2_FLAGC
USB_FX2_PA0_INT0_N
USB_FX2_PA1_INT1_N
USB_FX2_SLOE
USB_FX2_PKTEND
7
USB_FX2_SLCS_N
USB_FX2_PA3
R73 4.7K
4.7KR72
4.7KR84
R3 4.7K
R80 4.7K
4.7KR82
4.7KR93
R78 4.7K
R27 4.7K
4.7KR89
R86 4.7K
C
D
E
F
14
RSVD
G
PA7_FLAGD_SLCS_N
3.3VC
R49
3.3VC
4.7K
EEPROM
1
E0_NC
2
E1_NC
3 6
E2_NC SCL
4
GND
U2
VCC
WC_N
SDA
R47R48
2.2K
3.3VC
2.2K
P/D_NUM=TBD
C70
3.3VC
100N
8
7
5
H
I
PA0_INT0_N
PA1_INT1_N
PA2_SLOE
PA3_WU2
PA4_FIFOADR0
PA5_FIFOADR1
PA6_PKTEND
AGND_
GND_53
GND_56
GND_10
GND_12
GND_26
GND_28
GND_41
33
34
35
36
37
38
39
40
6
53
56
10
12
26
28
41
USB_FX2_PA0_INT0_N
USB_FX2_PA1_INT1_N
USB_FX2_SLOE
USB_FX2_PA3
USB_FX2_ADDR0
USB_FX2_ADDR1
USB_FX2_PKTEND
USB_FX2_SLCS_N
4,7
4,7
4,7
4,7
4
4
7
4,7
USB_P DIFFERENTIAL_PAIR=USB
USB_N DIFFERENTIAL_PAIR=USB
G
H
I
64K SERIAL-I2C
24C64
38L4878
M24C64-WMN6T
IBM CONFIDENTIAL
PART NO.
J
USB FX2
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
1 2 3 4 5 6 7 9 108
OUTSIDE MAX
INSIDE MAX
0.13
2.0 APPROVED
SCALE: 1/1
TITLE
DESIGNER
CHECKED
SHEET
LAWRENCIUM
2-9-2005_15:13
RMK 11/02/2004
7
???
???
OF
JWD
10
J
4321 5
DATE EC NO.
108 976
EC NO.DATE
PART NO.
REL
A
B
? ?
???????
DEVELOPMENT NO.
Q/M
A
B
3.3VC3.3VC
C
U8
C66
4.7U
D
E
NIOS_MEM_ADDR[0:11]
5
C64
100N
NIOS_MEM_ADDR0
NIOS_MEM_ADDR1
NIOS_MEM_ADDR2
NIOS_MEM_ADDR3
NIOS_MEM_ADDR4
NIOS_MEM_ADDR5
NIOS_MEM_ADDR6
NIOS_MEM_ADDR7
NIOS_MEM_ADDR8
NIOS_MEM_ADDR9
NIOS_MEM_ADDR10
NIOS_MEM_ADDR11
100N
A9
E7
J9
B3
D3
A7
C7
H7
H8
J8
J7
J3
J2
H3
H2
H1
G3
H9
G2
SDRAM8MX16
VCC_A9
VCC_E7
VCC_J9
VCCQ1
VCCQ2
VCCQ3
VCCQ4
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
A8
B9
B8
C9
C8
D9
D8
E9
E1
D2
D1
C2
C1
B2
B1
A2
NIOS_MEM_DATA0
NIOS_MEM_DATA1
NIOS_MEM_DATA2
NIOS_MEM_DATA3
NIOS_MEM_DATA4
NIOS_MEM_DATA5
NIOS_MEM_DATA6
NIOS_MEM_DATA7
NIOS_MEM_DATA8
NIOS_MEM_DATA9
NIOS_MEM_DATA10
NIOS_MEM_DATA11
NIOS_MEM_DATA12
NIOS_MEM_DATA13
NIOS_MEM_DATA14
NIOS_MEM_DATA15
NIOS_MEM_DATA[0:15]
5
C45C31
4.7U
VID_MEM_ADDR[0:11]
5
C65
C76
100N
VID_MEM_ADDR0
VID_MEM_ADDR1
VID_MEM_ADDR2
VID_MEM_ADDR3
VID_MEM_ADDR4
VID_MEM_ADDR5
VID_MEM_ADDR6
VID_MEM_ADDR7
VID_MEM_ADDR8
VID_MEM_ADDR9
VID_MEM_ADDR10
VID_MEM_ADDR11
100N
A9
E7
J9
B3
D3
A7
C7
H7
H8
J8
J7
J3
J2
H3
H2
H1
G3
H9
G2
SDRAM8MX16
VCC_A9
VCC_E7
VCC_J9
VCCQ1
VCCQ2
VCCQ3
VCCQ4
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
U6
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
A8
B9
B8
C9
C8
D9
D8
E9
E1
D2
D1
C2
C1
B2
B1
A2
VID_MEM_DATA0
VID_MEM_DATA1
VID_MEM_DATA2
VID_MEM_DATA3
VID_MEM_DATA4
VID_MEM_DATA5
VID_MEM_DATA6
VID_MEM_DATA7
VID_MEM_DATA8
VID_MEM_DATA9
VID_MEM_DATA10
VID_MEM_DATA11
VID_MEM_DATA12
VID_MEM_DATA13
VID_MEM_DATA14
VID_MEM_DATA15
VID_MEM_DATA[0:15]
5
C
D
E
NIOS_MEM_BA0_N
5
NIOS_MEM_BA1_N
5
NIOS_MEM_LDQM
5
F
G
NIOS_MEM_UDQM
5
NIOS_MEM_RAS_N
5
NIOS_MEM_CS_N
5
NIOS_MEM_CAS_N
5
NIOS_MEM_WE_N
5
NIOS_MEM_CLK
4
NIOS_MEM_CKE
5
G7
BA0
G8
BA1
E8
LDQM
F1
UDQM
F8
RAS_N
G9
CS_N
F7
CAS_N
F9
WE_N
F2
CLK
F3
CKE
A1
GND_A1
J1
GND_J1
E3
GND_E3
SDRAM_EDS1216AABH-75-E
NC_G1
NC_E2
GNDQ_A3
GNDQ_C3
GNDQ_B7
GNDQ_D7
G1
E2
A3
C3
B7
D7
VID_MEM_BA0_N
5
VID_MEM_BA1_N
5
VID_MEM_LDQM
5
VID_MEM_UDQM
5
VID_MEM_RAS_N
5
VID_MEM_CS_N
5
VID_MEM_CAS_N
5
VID_MEM_WE_N
5
VID_MEM_CLK
4
VID_MEM_CKE
5
G7
BA0
G8
BA1
E8
LDQM
F1
UDQM
F8
RAS_N
G9
CS_N
F7
CAS_N
F9
WE_N
F2
CLK
F3
CKE
A1
GND_A1
J1
GND_J1
E3
GND_E3
SDRAM_EDS1216AABH-75-E
NC_G1
NC_E2
GNDQ_A3
GNDQ_C3
GNDQ_B7
GNDQ_D7
G1
E2
A3
C3
B7
D7
F
G
H
I
H
I
IBM CONFIDENTIAL
PART NO.
J
VIDEO RAM / NIOS RAM
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
1 2 3 4 5 6 7 9 108
OUTSIDE MAX
INSIDE MAX
0.13
2.0 APPROVED
SCALE: 1/1
TITLE
DESIGNER
CHECKED
SHEET
LAWRENCIUM
2-9-2005_15:13
RMK 11/02/2004
8
???
???
OF
JWD
10
J
4321 5
DATE EC NO.
108 976
EC NO.DATE
PART NO.
REL
A
3.3VC
J2
? ?
???????
DEVELOPMENT NO.
Q/M
A
KEY
71
C71
5,9
B
R83
4.7K
ISP
4.7K
R99
R97
1K 1K
5
3.3VC
R87
C
MII_MDC
4
MII_MDIO
4
D
E
F
G
H
Have the system connect 3.3v non-continuous power to this pin
FPGA_MSEL0
4
MSEL0 and MSEL1 are here for development purposes
Connect like this on development card:
3_3V
FPGA_MSEL1
4
CKVM_PRESENCE_N
FPGA_DCLK
4
FPGA_CONF_DONE
4
FPGA_NCONFIG
4
FPGA_DATA0
4
FPGA_ASDO
4
FPGA_CE_N
4
FPGA_CSO_N
4
MII_CD
4
MII_CRS
4
MII_RXDV
4
MII_RXERR
4
MII_TXEN
4
MII_TXERR
4
CKVM_RESERVED96
4
MII_RXD0
4
MII_RXD1
4
MII_RXD2
4
MII_RXD3
4
MII_RXCLK
4
MII_TXCLK
4
MII_TXD0
4
MII_TXD1
4
MII_TXD2
4
MII_TXD3
4
CKVM_RESERVED118
CKVM_RESERVED123
CKVM_RESERVED125
4
CKVM_RESERVED126
4
CKVM_RESERVED127
4
CKVM_RESERVED128
4
CKVM_RESERVED129
4
CKVM_RESERVED130
4
CKVM_RESERVED131
4
CKVM_RESERVED132
5
CKVM_RESERVED133
4
NIOS_RESET_N
4
CKVM_RESERVED135
4
PWR_GOOD
5
CKVM_RESERVED_140
3.3VC
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
C72
C73
C74
C75
C76
C77
C78
C79
C80
C81
C82
C83
C84
C85
C86
C87
C88
C89
C90
C91
C92
C93
C94
C95
C96
C97
C98
C99
C100
C101
C102
C103
C104
C105
C106
C107
C108
C109
C110
C111
C112
C113
C114
C115
C116
C117
C118
C119
C120
C121
C122
C123
C124
C125
C126
C127
C128
C129
C130
C131
C132
C133
C134
C135
C136
C137
C138
C139
C140
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
C41
C42
C43
C44
C45
C46
C47
C48
C49
C50
C51
C52
C53
C54
C55
C56
C57
C58
C59
C60
C61
C62
C63
C64
C65
C66
C67
C68
C69
C70
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
67
68
69
70
1
2
3
4
5
6
7
8
9
65
66
DVO_RED6
DVO_RED7
DVO_RED3
DVO_RED4
DVO_RED5
DVO_GREEN6
DVO_GREEN7
DVO_BLUE7
DVO_HSYNC
DVO_VSYNC
DVO_DE
DVO_CLK
DVO_GREEN3
DVO_GREEN4
DVO_GREEN5
DVO_BLUE4
DVO_BLUE3
DVO_BLUE6
DVO_BLUE5
USB_P
USB_N
3.3VC
CKVM_RESERVED43
I2C_SDA
I2C_SCL
NIC_RESET_N
CKVM_RESERVED53
CKVM_RESERVED54
CKVM_RESERVED55
CKVM_RESERVED56
CKVM_RESERVED57
CKVM_RESERVED58
CKVM_RESERVED59
CKVM_RESERVED60
CKVM_RESERVED61
CKVM_RESERVED62
CKVM_RESERVED63
CKVM_RESERVED64
CKVM_RESERVED65
CKVM_RESERVED66
CKVM_RESERVED67
CKVM_RESERVED68
CKVM_RESERVED69
CKVM_PRESENCE_N
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
7
7
4
5
5
5
5
5
5
5
5
5
5
5
5
5
4
4
5
5,9
3.3VC
C38
3.3VC
C8
1U
10U
C18
C2
C29
C1 C7
10U
1U
10U
C24
10U10U
10U
C35
1U
C20
1U
B
C
D
E
F
G
H
KEY
VENDOR=MOLEX
I
FPGA_MSELx
VEN_P/D_NUM=500596-1409
P/D_NUM=23K8777
I
IBM CONFIDENTIAL
PART NO.
J
SYSTEM CONNECTOR
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
1 2 3 4 5 6 7 9 108
OUTSIDE MAX
INSIDE MAX
0.13
2.0 APPROVED
SCALE: 1/1
TITLE
DESIGNER
CHECKED
SHEET
LAWRENCIUM
2-9-2005_15:13
RMK 11/02/2004
9
???
???
OF
JWD
10
J
4321 5
DATE EC NO.
108 976
EC NO.DATE
PART NO.
REL
A
B
? ?
???????
DEVELOPMENT NO.
Q/M
A
B
C
D
CLOCK_VCC
NET_VOLTAGE=3.3
VOLTAGE=3.3
FPGA_VCCA
E
NET_VOLTAGE=1.5
VOLTAGE=1.5
C
D
E
1_5VC
VOLTAGE=1.5
NET_VOLTAGE=1.5
3.3VC
F
VOLTAGE=3.3
NET_VOLTAGE=3.3
G
3.3VC
C30
10U
U4
VREG8P_E-L6932D1_2TR
V
5
1
EN
2
IN
GND7
GND8GND6GND5
7
ADJ
OUT
865
3
4
R2
2.49K
R1
10K
C9
10N
C21
C22
10U
1_5VC
F
C19
100N100N
G
H
I
H
I
IBM CONFIDENTIAL
PART NO.
J
MUST CONFORM TO ENG
SPEC: 80X2324
TOLERANCE UNLESS NOTED
LINEAR
ANGLES
RADII UNLESS NOTED
EDGE/
CORNER
1 2 3 4 5 6 7 9 108
OUTSIDE MAX
INSIDE MAX
0.13
2.0 APPROVED
SCALE: 1/1
TITLE
DESIGNER
CHECKED
SHEET
LAWRENCIUM
2-9-2005_15:13
RMK 11/02/2004
10
???
???
OF
JWD
10
J
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