MSI MS-95C0 9154_0A_012304

A B C

Battery / Intrusion Detect / RAID Key / VAux Pwrgood

Parallel Port / ID Button / Rear Cyclops / Speaker

REV

D

REVISIONS

DESCRIPTIONECO DATE

APPROVED

1

Planar

CPU1

Serial Port

USB 2.0

CPU0

PWB PN: D1656
PWA PN: H1754

(2)

(Nocona/

Jayhawk)

System

Kbd/Mse

Kbd/Mse

H
D

2

M

FLOPPY

USB

C

o

IDE

n
n

VIDEO

87373

CPLD

LPC Bus

ICH5

Video

DVI

Hublink 1.5

PCI 33MHz

USB

(6.4GB/s, 6.4GB/s)

800 MHz

Lindenhurst

MCH

A

C

s

/
B

G

4

ESM 4G RAC

LPC

Smart

3

VU

Firmware

Hub

ESM
BMC

ATI

Video

(RADEON)

Connector

PCI 33MHz

PCI 33MHz

,
X

8
X

e

I
C
P

PCIeX 8X, 4GB/s

(Nocona/

Jayhawk)

1U/2U/5U

B-

B-

hi

lo

PCIeX 4X

PCIeX 4X, 2GB/s

PCI 33MHz

V1.8 - 5/22/03

DDR2 400 Ch. A (6.4Gb/s)

DDR2 400 Ch. B (6.4GB/s)

32/66MHz

2GB/s

PXH

32/66MHz

D

D

I

M

M

M

M

3

2

A

A

TABOR

TABOR

D

I

I
M
M

1
A

D

D

D

I

I

I

M

M

M

M

M

M

3

2

1

B

B

B

Gbit Port 1#

Gbit Port 1#

IPMB

HS3 Connector

PCI Microchannel

TABLE OF CONTENTS

Page 1.
Page 2.
Page 3.
Page 4.
Page 5.
Page 6.
Page 7.
Page 8.
Page 9.
Page 10.
Page 11.
Page 12.
Page 13.
Page 14.
Page 15.
Page 16.
Page 17.
Page 18.
Page 19.
Page 20.
Page 21.
Page 22.
Page 23.
Page 24.
Page 25.
Page 26.
Page 27.
Page 28.
Page 29.
Page 30.
Page 31.
Page 32.
Page 33.
Page 34.
Page 35.
Page 36.
Page 37.
Page 38.
Page 39.
Page 40.
Page 41.
Page 42.
Page 43.
Page 44.
Page 45.
Page 46.
Page 47.
Page 48.
Page 49.
Page 50.
Page 51.
Page 52.
Page 53.
Page 54.
Page 55.FWH
Page 56.
Page 57.
Page 58.
Page 59.

BLOCK DIAGRAM
CLOCK DIAGRAM
Clock Synth.
Differential Buffer DB800
System CPLD
Voltage Regulators
VRD
VRD
VRD

---blank--­Processors
Processors
Processors

---blank--­ITP 32 & Level Translation Circuits
MCH, memory
MCH, GTL, Exp, Hub-link
MCH, power
Decoupling Caps
DDR2
DDR2
DDR2, routing diagram
DDR2, VRef
Gigabit Ethernet
Gigabit Ethernet
Gigabit Ethernet
PXH
PXH
PXH
PXH
Connectors
Connectors
ICH5
ICH5
Keyboard, Mouse, COM Ports, I2C MUX/Table
Radeon Video
Radeon Video
Radeon Video
Radeon Video
Super I/O, 373

Fans and fan LED's
BMC

BMC
BMC
BMC
BMC, Serial Port Muxing
BMC - Serial Port MUXing Diagram
RAC

1.2V Vtt generation
Fan PWM Controllers
MicroVu
VAux reset

USB / Buttons
Spares / Coupons / Hardware
PCI bus p/u's / PCI Debug Slot
Debug Features

1

2

3

1U PWA assembly

2U/5U PWA assembly

4

EXPORT RESTRICTION:

THE EXPORT OF THE INFORMATION, SCHEMATICS AND OTHER TECHNICAL DATA CONTAINED IN THIS DOCUMENT
IS CONTROLLED BY THE U.S. GOVERNMENT. THE EXPORT, DEEMED EXPORT OR OTHER TRANSFER OF THIS DATA
TO CERTAIN COUNTRIES AND INDIVIDUALS IS RESTRICTED. ANY TRANSFER, EXPORT OR REEXPORT, MUST BE
IN COMPLIANCE WITH THE U.S. EXPORT ADMINISTRATION REGULATIONS.

P# F1667
P# H1754

PROPRIETARY NOTE

THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS
AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS
ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER
CORP., EXCEPT AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN
ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE
REPRODUCED IN WHOLE OR IN PART AND MUST BE RETURNED TO DELL
COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION
OF THE PURPOSE OF THE LOAN. NEITHER THIS ITEM NOR THE
INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS
NOT HAVING A NEED FOR SUCH USE OR DISCLOSURE CONSISTENT WITH
THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF
DELL COMPUTER CORPORATION.

DRAWN
DESIGNED
CHECKED
APPROVED
APPROVED
APPROVED
APPROVED
RELEASED

Uniplanar Team:

-Shawn Dube

-Jinsaku Masuyama

-Garnett Thompson

-TJ Thompson

XLBOM Build option table

0 Production Build
9 Prototype Build

A CURRENT ISSUE OF THIS DRAWING MUST
INCLUDE A COPY OF THE FOLLOWING
ECO'S:
ECO

ECO
ECO
ECO
ECO
ECO
ECO
ECO

TITLE

LINDY PLANAR

DWG NO.

D1660 X03

DATE

1/13/2004 1 OF 61

DATE
DATE
DATE
DATE
DATE
DATE
DATE
DATE

COMPUTER
CORPORATION
AUSTIN,TEXAS

SHEET

REV.

DCBA

4

B D

CA

CLOCK DISTRIBUTION

BLOCK DIAGRAM

1-23-2004_12:58

1

2

1

2

3

4 4

USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH

OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE

AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE

AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL

REV.

X03

A B

TITLE

LINDY PLANAR

DWG NO.

D1660

DATE

DC

COMPUTER
CORPORATION
AUSTIN,TEXAS

SHEET

2 OF 611/13/2004

3

B D

V_3P3_CLK

3

21

4.7K

R1476

R1477

R1420

21

ICH_SEG2_SDA

4,35

1

+3.3V

1 2

C1093

L103

BLM18BD601SN1

L105

BLM18BD601SN1

0.1uF 16V

21

21

1 2

C1094

0.1uF 16V

21

C1209

1 2

C1103

10uF 6.3V

1 2

C1102

0.1uF 16V

1 2

C1101

0.1uF 16V

1 2

C1100

0.1uF 16V

0.1uF 16V

1 2

C1104

0.1uF 16V

1 2

C1099

1 2

C1098

0.1uF 16V

0.1uF 16V

1 2

C1096

V_3P3_CLK

1 2

C1097

0.1uF 16V

0.1uF 16V

3

4,35

ICH_SEG2_SCL

0-5%

R1421

1 2

0-5%

ICH_SEG2_409_SDA

ICH_SEG2_409_SCL

NP*

1 2

4.7K

NP*

CA

1-23-2004_12:58

ECAD Note:

3

3

VCC routing should be from plane, through high-f cap, to pin

1

x00_tj_050503

+3.3V

C1105

21

10uF 6.3V

SUB*_U1084

300OHM, 300 mA

1 2

0.1uF 16V

1 2

ILB_1206

L129

1 2

C1092

0.1uF 16V

V_3P3_CLK_VDD48

PROPAGATION_DELAY=L:S::1000
NET_PHYSICAL_TYPE=50MIL

CK_FSA

5

CK_FSB

5

1 2

C758

R1419

0-5%

V_3P3_CLK_VDDA

10uF 6.3V

1 2

21

12

R1002

x02_sd

R46

4.7K

1 2

PROPAGATION_DELAY=L:S::1000
NET_PHYSICAL_TYPE=50MIL

R1022

0-5%

CK_VTT_PWRGD_N

5,59

CK_PWRDWN_N

4,5,59

21

C1326

475-1%

IREF = 2.32mA

U1084
300 ohm, 25%, 300mA, 1206

Vishay ILB1206RK301V
KOA CZB2BFL-301P

21

C757

x03_tj_121503

0.1uF 16V

14.31818MHz

50V-10%

2 1

27pF

R606

2.2-5%

1 2

R947

NP

2 1

1M-5%

C1090

X10

21

C756

50V-10%

21

C759

0.1uF 16V

C1091

27pF

12

V_3P3_CLK

3

2

May need to tune caps during UT

3

Spread spectrum Controlled through I2C

21

4.7K

R1008

R1018

0.1uF 16V

NP*

x00_tj_051203

21

C777

1 2

1 2

NP*

4.7K

21

R1007

C778

4.7K

R1475

1 2

C779

ICH_SEG2_409_SDA

3

ICH_SEG2_409_SCL

3

1K-1%

1000pF

1000pF

50V-10%

PART_NUMBER=79015

50V-10%

PART_NUMBER=79015

21

1 2

C780

1000pF

1000pF

50V-10%

PART_NUMBER=79015

PART_NUMBER=79015

CK_XTAL_IN
CK_XTAL_OUT

CK_FSA_R
CK_FSB_R
CK_IREF

CK409B for Proto builds

x00_tj_052003

3
10
16
24
55
34
42
48
36

50V-10%

4

5

51
56
52
35
21

30
28

6
11
17
25
39
33
53
45
54

CK409B

VDD_REF
VDD_PCI_1
VDD_PCI_2
VDD_3V66
VDD_ANLG
VDD_48MHZ
VDD_CPU_1
VDD_CPU_2
VDD_SRC

XTALIN
XTALOUT

FS_A
FS_B
IREF
VTT_PWRGD
PWR_DOWN

SDATA
SCLK

GND_REF
GND_PCI_1
GND_PCI_2
GND_3V66
GND_SRC
GND_48MHZ
GND_IREF
GND_CPU
GND_ANLG

SMBus address = D2h

All clk _R nets have a hidden prop-delay max of 500mil

3V66_4/VCH

CK409 - TSSOP56

1

CK_14M_ICHS_R

REF0

2

CK_14M_SIO_R

REF1

7

PCI0
PCI1
PCI2
PCI3
PCI4
PCI5
PCI6

USB
DOT

SRC_P
SRC_N

8
9
12
13
14
15
18
19
20

31
32

38
37

22
23
26
27
29

41
40
44
43
47
46
50
49

CK_33M_ICHS_R
CK_33M_SIO_R

CK_33M_FWH_R

CK_33M_SLOT3_R
CK_33M_PCI0_DEBUG_R
CK_33M_BMC_R
CK_33M_CPLD_R
CK_33M_DBG_LPC_R
CK_33M_VIDEO_R
CK_33M_RAC_R

CK_48M_USB_ICHS_R
CK_48M_SIO_R

CK_100M_DB800_P_R
CK_100M_DB800_N_R

CK_66M_MCH_R
CK_66M_ICH_R
CK_66M_3V66_2
CK_66M_LAI_R

R1017

1K-1%

CK_167M_CPU1_P_R
CK_167M_CPU1_N_R
CK_167M_CPU2_P_R
CK_167M_CPU2_N_R
CK_167M_MCH_P_R
CK_167M_MCH_N_R
CK_167M_ITP_P_R
CK_167M_ITP_N_R

PCI_F0
PCI_F1
PCI_F2

3V66_0
3V66_1
3V66_2
3V66_3

CPU_P0
CPU_N0
CPU_P1
CPU_N1
CPU_P2
CPU_N2
CPU_P3
CPU_N3

SUB=SUB23_U1438

21

R1417

1 2

1K-1%

R956

1 2

33-5%

R957

1 2

33-5%

R1361

1 2

33-5%

+3.3V

R1473

1 2

CK_14M_ICHS

CK_14M_SIO

NC_CK_48M_SIO

R962

NP*

33-5%

R963

33-5%

R593

21

1K-1%

CK-409 support
Place close to ICH

4.7K

4.7K

R1474

POP0121POP01

CPU_STOP#

PCI_STOP#

Populate with CK409B (ITP diferential pair)

Differential pair routing guideline:

6 mil traces / 14 mil spacing

Spacing to other traces: 5W

33

40

R959

21

21

Pop 33ohm, 49.9ohm if CK409B used

33-5%

R142921R1712

1 2

49.9-1%

NP01

21

CK_100M_DB800_P
CK_100M_DB800_N

49.9-1%

R965

33-5%

R966

33-5%

R967

33-5%

NP01

R950

33-5%

21

33-5%

CK_48M_USB_ICHS

R960

33-5%

R961

21

33-5%

R952

33-5%

21

R968

33-5%

21

R969

33-5%

21

R951

21

21

21

21

21

21

R1036

4
4

49.9-1%
21

R1037

49.9-1%

21

R1039

33

49.9-1%
21

R1035

21

R1033

NP01

21

R1038

49.9-1%

49.9-1%

R1034

1 2

49.9-1%

NP01

21

R1040

49.9-1%

49.9-1%

R964

33-5%

R955

33-5%

R954

33-5%

R1362

1 2

33-5%

R949

33-5%

R1416

1K-1%
R1363

33-5%

R1364

1 2

33-5%

R1366

33-5%

R1367

1 2

33-5%

R38

33-5%

21

21

21

21

21

21

21

NP*

CK_33M_ICHS

CK_33M_SIO

CK_33M_FWH

CK_33M_SLOT1

CK_33M_PCI0_DEBUG

21

CK_33M_BMC

CK_33M_CPLD

CK_33M_SMARTVU

CK_33M_VIDEO

CK_33M_RAC

CK_66M_MCH

CK_66M_ICH

CK_167M_CPU1_P

CK_167M_CPU1_N

CK_167M_CPU2_P

CK_167M_CPU2_N

CK_167M_MCH_P

CK_167M_MCH_N

CK_167M_ITP_P

CK_167M_ITP_N

33

40

55

31

58

44

5,59

To CPLD and Mictor header

59

36

50

17

33

11

11

11

11

17

17

15

15

x00_tj_051503

CK409B / CK409 Operation

FSA

0

1

4 4

Freq. latched on VTT_PWRGD

FSB SPEEDFSB

0

100 MHz
200 MHz

10

133 MHz

0

11

166 MHz

ROOM=CLOCK1

2

3

subsys done

A B

Clock CK409B

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

TITLE

LINDY PLANAR

DWG NO.

D1660

DATE

DC

COMPUTER
CORPORATION
AUSTIN,TEXAS

REV.

SHEET

3 OF 611/13/2004

X03

B D

CA

1-23-2004_12:58

1

ICH_SEG2_SDA

3,35

ICH_SEG2_SCL

3,35

L108

+3.3V

C1114

1 2

BLM18BD601SN1

L107

BLM18BD601SN1

0.1uF 16V

21

21

1 2

C1111

0.1uF 16V

21

C1210

1 2

C1110

10uF 6.3V

0.1uF 16V

1 2

C1109

1 2

C1108

0.1uF 16V

1 2

C1112

0.1uF 16V

C1113

0.1uF 16V

2

21

R996

R591

1 2

8.2K-5%

x00_tj_051203

R999

10K-1%

21

R590

8.2K-5%

8.2K-5%

1 2

R998

10K-1%

1 2

C1327

0.1uF 16V

NP*

21

R997

10K-1%

21

NP

R1480

10K-1%

1 2

3,5,59

3
3

4

4.7K

4

4

4

4
4,31
4,31

x00_sd_051703

CK_100M_DB800_N
CK_100M_DB800_P

ICH_SEG2_800_SCL
ICH_SEG2_800_SDA

SRC_BYPASS/PLL
SRC_PLL_LOW_BW

SRC_STOP_N
SRC_DIV2_N

CK_PWRDWN_N

NC_SRC_LOCK

DB800_OE0

DB800_OE4
DB800_OE5
SLOT7_PWRGD
SLOT6_PWRGD

5

SRC_IN

4

SRC_IN

23

SCLK

24

SDATA

22

BYPASS/PLL

28

PLL_BW

27

SRC_STOP

1

SRC_DIV2

26

PWRDWN

45

LOCK

6

OE_0

14

OE_1

15

OE_2

7

OE_3

43

OE_4

35

OE_5

36

OE_6

44

OE_7

3

GND_3

10

GND_10

18

GND_18

25

GND_25

32

GND_32

40

GND_40

47

GNDA

SMBus address = DCh

V_3P3_SRC

4

V_3P3_SRC

4

21

R592

V_3P3_SRC

4

21

21

3

DB800_OE0

4

DB800_OE4

4

DB800_OE5

4

SLOT7_PWRGD

4,31

SLOT6_PWRGD

4,31

x00_sd_051703

NP

R111

R100

1 2

R112

8.2K-5%

NP

21

R101

1K-1%

R113

1 2

8.2K-5%

NP

R103

1K-1%

1 2

21

R114

8.2K-5%

NP

21

R105

1K-1%

R115

1 2

8.2K-5%

NP

R107

1K-1%

1 2

8.2K-5%1K-1%

R1423

0-5%

R1422

1 2

0-5%

21

1 2

C786

C784

1000pF

50V-10%

PART_NUMBER=79015

0.1uF 16V

x00_tj_051203

DB800

ICS9DB108

PROPAGATION_DELAY=L:S::500
NET_PHYSICAL_TYPE=50MIL

V_3P3_SRC

4

21

ICH_SEG2_800_SDA

ICH_SEG2_800_SCL

1 2

1000pF

50V-10%

PART_NUMBER=79015

8

DIF_0

9

DIF_0

12

DIF_1

13

DIF_1

16

DIF_2

17

DIF_2

20

DIF_3

21

DIF_3

30

DIF_4

29

DIF_4

34

DIF_5

33

DIF_5

38

DIF_6

37

DIF_6

42

DIF_7

41

DIF_7

46

IREF

2

VDD_2

11

VDD_11

19

VDD_19

31

VDD_31

39

VDD_39

48

DB800_VDDA

VDDA

21

4.7K

4.7K

R1479

R1478

1 2

NP*

NP*

4

4

Note: If clock ordering changes, BIOS requirements must change

V_3P3_SRC

CK_100M_SATA_P_R
CK_100M_SATA_N_R

CK_100M_MCH_P_R
CK_100M_MCH_N_R

CK_100M_PXH_PLANAR_P_R
CK_100M_PXH_PLANAR_N_R

CK_100M_DOBSON_P_R
CK_100M_DOBSON_N_R

CK_100M_PXH_P_R
CK_100M_PXH_N_R

CK_100M_EXP_LAI_P_R
CK_100M_EXP_LAI_N_R

CK_100M_SLOT1_P_R
CK_100M_SLOT1_N_R

CK_100M_SLOT2_P_R
CK_100M_SLOT2_N_R

R1003

1 2

475-1%

V_3P3_SRC

0.1uF 16V

10uF 6.3V

C1202

21

4

4

x00_tj_050103

SUB*_U1084

L130

1 2

ILB_1206

300OHM, 300 mA

C1107

12

NP

IREF = 2.32mA

+3.3V

0.1uF 16V

12

R976

1 2

33-5%
R977

1 2

33-5%

R980

1 2

33-5%

R975

1 2

33-5%

R973

1 2

33-5%

R971

1 2

33-5%

R1368

33-5%

R1370

33-5%

C1106

NP

21

21

R978

1 2

33-5%

R979

1 2

33-5%

R981

1 2

33-5%

R974

1 2

33-5%

R972

1 2

33-5%

R970

1 2

33-5%

R1369

33-5%

R1371

33-5%

CK_100M_SATA_P

CK_100M_SATA_N

CK_100M_MCH_P

CK_100M_MCH_N

CK_100M_PXH_PLANAR_P

CK_100M_PXH_PLANAR_N
CK_100M_DOBSON_P

CK_100M_DOBSON_N

CK_100M_PXH_P

CK_100M_PXH_N

CK_100M_EXP_SPARE_P

CK_100M_EXP_SPARE_N

21

R1432

49.9-1%
21

R1431

49.9-1%

CK_100M_SLOT7_P

CK_100M_SLOT7_N

CK_100M_SLOT6_P

CK_100M_SLOT6_N

49.9-1%

21

21

21

R1051

1 2

R1050

49.9-1%

R1052

1 2

49.9-1%

1 2

R1048

49.9-1%

R1049

1 2

49.9-1%

1 2

R1046

49.9-1%

R1047

1 2

49.9-1%

1 2

49.9-1%

R1045

1 2

R1044

1 2

49.9-1%

R1043

49.9-1%

1 2

R1042

1 2

49.9-1%

R1041

1 2

49.9-1%

R1434

49.9-1%

R1433

49.9-1%

21

33

33

17

17

27

27

31

31

31

31

31

31

31

31

31

31

1

2

3

U1084
300 ohm, 25%, 300mA, 1206

Vishay ILB1206RK301V

SATAOE0
OE1 MCH
OE2

Planar PXH
OE3

Dobson
OE4

4 4

PXH
OE5

LAI
OE6

Slot1 ***Note--BIOS should disable for 2U
OE7

Slot2

1U Prod 2U/5U Prod 1U Proto 2U/5U Proto

X X X X
X X X X

X X
X X

X X

XXXX

***Note--BIOS should disable for 2UX X

subsys done

A B

KOA CZB2BFL-301P

ROOM=CLOCK2

DB800 Differential buffer

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

TITLE

LINDY PLANAR

DWG NO.

D1660

DATE

DC

COMPUTER
CORPORATION
AUSTIN,TEXAS

REV.

SHEET

4 OF 611/13/2004

X03

B D

todo check ich_pme will be driven or floated high in time

CA

1-23-2004_12:58

1 2

R1769

R1770

21

NP13

NP02

U64

x02_sd

7,8,59

5

OUTIN

NCEN

R6006

1 2

PFAULT_LATCH_N

33-5%
R6007

21

33-5%

PFAULT_RESET

+3.3V_AUX

1142

R575

1 2

100-1%

21

C559

1000pF

50V-10%

PART_NUMBER=79015

ICH_THRMTRIP

51

43

1 2

2.7K-5%

todo....need to check that 3904 has drive strength and gain

NET_PHYSICAL_TYPE=PWR

+1.8V_AUX

0.1uF 16V
10V-10%

C1624

1uF

21

44,46

5

+3.3V_AUX

U38

CK_CPLD

3144

VHC14VHC14

U38

RC = 0.1 us

F = 2.0MHz

5,59

1

ICH_THRMTRIP_N

3

R92

Q104

3904

2

CPLD_H_VID_PWRGOOD_N

5,59

CPLD_H_FORCEPR

5

0.1uF 16V
C1626

C1625

21

21

x00_tj_042803

H2_CPU_PRES_N

5,12,46

H1_CPU_PRES_N

5,12,46

H2_VTT_EN

5,12

H1_VTT_EN

5,12

ROOM=SYSCPLD

BUF_CK_CPLD

CPLD_DDR2_RESET

33

+3.3V_AUX

8

RN87

1

5

567

4.7K

432

R1439

1 2

2.7K-5%

R1438

2.7K-5%

R426

1 2

2.7K-5%

5,32,46

todo, consider slew rate limiting

+1.8V

1 2

301-1%

R1359

3

2

Q11

3904

3

+1.8V

301-1%

1

DDR2_RESET_N_1

R1

21

DDR2_RESET_N_2

3

2

2.7K-5%

21

Q66

3904

R583

Q65

3904

1

1

21

H_VTT_PWRGOOD

2

H_FORCEPR_N

Q84

3

3904

1

2

+3.3V_AUX

R1834

BACKPLANE_PRES_N
RISER_PRES_N

5,31

x00_sd_052203
x00_tj_052903

1 2

20,21

20,21

12

11,12

21

4.7K

4.7K

R1835

R129

1 2

33-5%

33-5%

1 2

33-5%

1 2

33-5%
33-5%

1 2

1 2

R1541

R1542

R1543

R1545

R1544

R1546

R6003

R6004

R6002

R6005

21

33-5%

R1376

1 2

33-5%

R1353

1 2

1K-5%

R1375

1 2

33-5%

R1374

21

33-5%

R1373

1 2

.01uF 16V

33-5%

R1381

R1377

21
R1378

R1379

R1380

21

50V-5%

50V-5%

1 2

47pF

C134521C1346

x03_GT_010704

R6016

33-5%
R6017

33-5%

x03b_GT_012204

PCI_RST_PXH_N

PCI_RST_DEBUG_N

21

SHIFTY_RISER_CLK

33-5%

1 2

SHIFTY_RISER_LATCH

33-5%

21

SHIFTY_RISER_DATA_DN

33-5%

1 2

SHIFTY_BCKPLN_CLK

33-5%

21

SHIFTY_BCKPLN_LATCH

33-5%

1 2

SHIFTY_BCKPLN_DATA_DN

33-5%

21

SHIFTY_BMC_CLK

33-5%

1 2

SHIFTY_BMC_LATCH

33-5%

21

SHIFTY_BMC_DATA_DN

33-5%

1 2

SHIFTY_BMC_DATA_UP

33-5%

point-to-point, no cap needed

50V-5%

50V-5%

50V-5%

1 2 C900

47pF

47pF

1 2 C1342

47pF

1 2 C1343

21 C1341

point-to-point, no cap needed

point-to-point, no cap needed

.01uF 16V

47pF

PCI_RST_RAC_N

PCI_RST_MCH_N

PCI_RST_SIO_FWH_N

PCI_RST_RISER_N

PCI_RST_BACKPLANE_N

50V-5%

1 2

47pF

21

C1349

C1347

27

58,59

31

31

31

32

32

32

46

46

46

5

SYSTEM_PWRGOOD_PXH

SYSTEM_PWRGOOD_NIC

SYSTEM_PWRGOOD_FETS

SYSTEM_PWRGOOD_BACKPLANE

SYSTEM_PWRGOOD_RISER

SYSTEM_PWRGOOD_CHIPSET

50V-5%

47pF

21 C1344

50

17

x03b_GT_012204

40,55

31

32

PROG-PART SPEC 14967
DISK PROG
BLANK PART

x02_sd

28

24,25

24,35,41

32

31

17,33

x00_sd_051903
x00_sd_051903

just for dumbview
just for dumbview

P3975SYSTEM_CPLD

P3976
1Y852

+3.3V_AUX

22uF 6.3V

C742

21

SYSTEM_PWRGOOD_ESM

44,46,50

SYSTEM_PWRGOOD_NIC_R

5

SYSTEM_PWRGOOD_FETS_R

5

SYSTEM_PWRGOOD_BACKPLANE_R

5

SYSTEM_PWRGOOD_RISER_R

5

SYSTEM_PWRGOOD_CHIPSET_R

5,59

SYSTEM_PWRGOOD_PXH_R

5

PCI_RST_MCH_N_R

5

PCI_RST_PLANAR_N_R

5

PCI_RST_RISER_N_R

5

PCI_RST_BACKPLANE_N_R

5

PCI_RST_RAC_N_R

5

BACKPLANE_PRES_N

5,32,46

RISER_PRES_N

5,31

SHIFTY_RISER_DATA_UP

31,59

CK_FSA

3

SHIFTY_RISER_DATA_DN_R

5,59

SHIFTY_RISER_CLK_R

5,59

SHIFTY_RISER_LATCH_R

5,59

CK_FSB

3

BUF_CK_CPLD

5

CK_33M_CPLD

3,59

INTRUSION_COVER_VAUX_N

x03b_sd

41

CK_32K_VAUX_SYSCPLD

33

SHIFTY_BMC_DATA_UP

5

SHIFTY_BMC_DATA_DN_R

5

CPLD_DDR2_RESET

5,59

3.3VAUX_PWRGOOD

41

H2_PROCHOT_3V

15

H1_PROCHOT_3V

15

H2_THERMTRIP_3V

15,46

H1_THERMTRIP_3V

15,46

H2_IERR_3V

15,46

H1_IERR_3V

15,46

ITP_DBR_N

15

SHIFTY_BMC_CLK_R

5

SHIFTY_BMC_LATCH_R

5

ICH_THRMTRIP

5

SHIFTY_BCKPLN_CLK_R

5,59

SHIFTY_BCKPLN_LATCH_R

5,59

SHIFTY_BCKPLN_DATA_DN_R

5,59

SHIFTY_BCKPLN_DATA_UP

32,59

5V_PWRGOOD

6,59

5V_RISER_PWRGOOD

6

RISER_PWRGOOD

31,59

DC2DC_CPUVTT_EN

6,51,59

DC2DC_1V5_EN

6,59

DC2DC_1V8_EN

6,59

DC2DC_3V3_EN

6,59

DC2DC_5V_EN

6,59

0.1uF 16V

0.1uF 16V

0.1uF 16V
1 2

C15

C13

1 2

21

x02_tj_092203

+3.3V_AUX

NC_SC_NC18
NC_SC_NC20
NC_SC_NC31
NC_SC_NC33
NC_SC_NC34
NC_SC_NC42
NC_SC_NC44
NC_SC_NC46
NC_SC_NC48
NC_SC_NC66
NC_SC_NC75
NC_SC_NC106
NC_SC_NC107
NC_SC_NC114

0.1uF 16V

C1421C16

1 2

1K-5%

1uF 6.3V

R1382

21

17
16
15
14
13
12
11
10

19
21
22
23
24
25
26
28
30
32
35
38

143
140
138
136
134
133
132
131
130
129

39
40
41
43
45
49
50
51
52
53
54
56
57

18
20
31
33
34
42
44
46
48
66

75
106
107
114

29

36

47

62

72

89

90

99
108
123
144

C277

IO_1_1
IO_1_2
IO_1_3
IO_1_4
IO_1_5
IO_1_6
IO_1_11
IO_1_12

9

IO_1_13

7

IO_1_14

6

IO_1_15_GTS1

5

IO_1_16_GTS0
IO_2_1

IO_2_2
IO_2_3
IO_2_4
IO_2_5
IO_2_6
IO_2_11
IO_2_12
IO_2_13_GCK0
IO_2_14_GCK1
IO_2_15_CDRST
IO_2_16_GCK2

4

IO_3_1

3

IO_3_2_GTS3

2

IO_3_3_GTS2
IO_3_4_GSR
IO_3_5
IO_3_6
IO_3_7
IO_3_11
IO_3_12
IO_3_13
IO_3_14
IO_3_15
IO_3_16

IO_4_1_DGE
IO_4_2
IO_4_3
IO_4_4
IO_4_5
IO_4_6
IO_4_7
IO_4_11
IO_4_12
IO_4_13
IO_4_14
IO_4_15
IO_4_16

NC_18
NC_20
NC_31
NC_33
NC_34
NC_42
NC_44
NC_46
NC_48
NC_66
NC_75
NC_106
NC_107
NC_114

GND_29
GND_36
GND_47
GND_62
GND_72
GND_89
GND_90
GND_99
GND_108
GND_123
GND_144

1uF 6.3V

1uF 6.3V

C27821C279

1 2

SYSTEM_CPLD

XC2C128 TQFP144

SUB*_P3975

256 macrocell flavor

1uF 6.3V

C659

1 2

IO_5_1
IO_5_2
IO_5_3
IO_5_4
IO_5_5
IO_5_6

IO_5_7
IO_5_11
IO_5_12
IO_5_13
IO_5_14
IO_5_15
IO_5_16

IO_6_1

IO_6_2

IO_6_3

IO_6_4

IO_6_5

IO_6_6
IO_6_11
IO_6_12
IO_6_13
IO_6_14
IO_6_15
IO_6_16

IO_7_1

IO_7_2

IO_7_3

IO_7_4

IO_7_5

IO_7_6

IO_7_7
IO_7_11
IO_7_12
IO_7_13
IO_7_14
IO_7_15
IO_7_16

IO_8_1

IO_8_2

IO_8_3

IO_8_4

IO_8_5

IO_8_6
IO_8_11
IO_8_12
IO_8_13
IO_8_14
IO_8_15
IO_8_16

TCK
TDI
TDO
TMS

VCC_JTAG

VCC_1
VCC_37
VCC_84

VCCIO1_27
VCCIO1_55
VCCIO1_73
VCCIO1_93

VCCIO2_109
VCCIO2_127
VCCIO2_141

NC_135
NC_137
NC_139
NC_142

94
95
96
97
98
100
101
102
103
104
105
110
111

92
91
88
87
86
85
83
82
81
80
79
78

112
113
115
116
117
118
119
120
121
124
125
126
128

77
76
74
71
70
69
68
64
61
60
59
58

67
63
122
65
8

1
37
84

27
55
73
93

109
127
141

135
137
139
142

PS1_PWRGOOD

PS2_PWRGOOD
DEBUG_JUMPER_1
DEBUG_JUMPER_0

DEBUG_LED_3

DEBUG_LED_2

DEBUG_LED_1

DEBUG_LED_0

ICH_PWRBTN_N

ICH_PME_N

PFAULT_LATCH_N_R

PFAULT_RESET

RISER_EXP_PME_N

VRD1_THERMTRIP_N

PCI_RST_ICH_N

VCORE_EN_R VCORE_EN
VCORE1_PWRGOOD
VCORE2_PWRGOOD
CPLD_H_FORCEPR

VRD2_THERMTRIP_N

ICH_PWR_ON_REQ

RESET_BTN_N
PS1_ENABLE_N
PS2_ENABLE_N

B_1U_2U5U

LPC_LFRAME_N

LPC_LAD3
LPC_LAD2
LPC_LAD1

CPLD_H_VID_PWRGOOD_N

NC_SC_NC135
NC_SC_NC137
NC_SC_NC139
NC_SC_NC142

LPC_LAD0

PME_NIC_CPLD_N

H2_CPU_PRES_N
H1_CPU_PRES_N

H2_VTT_EN
H1_VTT_EN

RISER_PCI_PME_N

CK_VTT_PWRGD_N

DC2DC_5V_RISER_EN
I2C_SEG2_VAUX_SDA

I2C_SEG2_VAUX_SCL

H1_BSEL0_3V_N
H1_BSEL1_3V_N
H2_BSEL0_3V_N
H2_BSEL1_3V_N

CPU_VTT_PWRGOOD

1V5_PWRGOOD

1V8_PWRGOOD

3V3_PWRGOOD

CK_PWRDWN_N

CPLD_TCK
CPLD_TDI
CPLD_TD1
CPLD_TMS

PFAULT_LATCH_N_R

5

PROPAGATION_DELAY=L:S::2000

PFAULT_RESET_R

44,46

PROPAGATION_DELAY=L:S::2500

31,59
31,59
59
59

x00_sd_52903 - removed 2 leds

59
59
59
59
33,41,44,56,59
33
5
5

x03b_sd

31
9,46

33,59

7,59
8,59
5
9,46
33,40,41,44,59
56
31,59
31,59

33,40,44,55,59
33,40,44,55,59
33,40,44,55,59
33,40,44,55,59
33,40,44,55,59
5,59
28
5,12,46
5,12,46
5,12
5,12
31
3,59

6
44,45,59
44,45,59
15
15
15
15
6,51
6,59
6,59
6,59
3,4,59

5,40,46
5,40
46
5,31,32,40,46

x02_sd

x03b_sd

33-5%

21

R1865

+3.3V_AUX

+3.3V_AUX

2

+3.3V_AUX

NP*

R1790

1 2

8.2K-5%8.2K-5%

21

R1791

NP*

8.2K-5%

8.2K-5%

GND

TPS72118DBV

SYSTEM_PWRGOOD_PXH_R

5

PROPAGATION_DELAY=L:S::2000

SYSTEM_PWRGOOD_NIC_R

5

PROPAGATION_DELAY=L:S::2000

SYSTEM_PWRGOOD_FETS_R

5

PROPAGATION_DELAY=L:S::2000

1

2

3

SYSTEM_PWRGOOD_BACKPLANE_R

5

PROPAGATION_DELAY=L:S::2000

SYSTEM_PWRGOOD_RISER_R

5

PROPAGATION_DELAY=L:S::2000

SYSTEM_PWRGOOD_CHIPSET_R

5,59

PROPAGATION_DELAY=L:S::2000

PCI_RST_RAC_N_R

5

PROPAGATION_DELAY=L:S::2000

PCI_RST_MCH_N_R

5

PROPAGATION_DELAY=L:S::2000

PCI_RST_PLANAR_N_R

5

PROPAGATION_DELAY=L:S::2000

PCI_RST_RISER_N_R

5

PROPAGATION_DELAY=L:S::2000

PCI_RST_BACKPLANE_N_R

5

PROPAGATION_DELAY=L:S::2000

PCI_RST_PLANAR_N_R

5

PROPAGATION_DELAY=L:S::2000

PCI_RST_PLANAR_N_R

5

PROPAGATION_DELAY=L:S::2000

SHIFTY_RISER_CLK_R

5,59

PROPAGATION_DELAY=L:S::2000

SHIFTY_RISER_LATCH_R

5,59

PROPAGATION_DELAY=L:S::2000

SHIFTY_RISER_DATA_DN_R

5,59

PROPAGATION_DELAY=L:S::2000

SHIFTY_BCKPLN_CLK_R

5,59

PROPAGATION_DELAY=L:S::2200

SHIFTY_BCKPLN_LATCH_R

5,59

PROPAGATION_DELAY=L:S::2200

SHIFTY_BCKPLN_DATA_DN_R

5,59

PROPAGATION_DELAY=L:S::2200

SHIFTY_BMC_CLK_R

5

PROPAGATION_DELAY=L:S::2200

SHIFTY_BMC_LATCH_R

5

PROPAGATION_DELAY=L:S::2200

SHIFTY_BMC_DATA_DN_R

5

PROPAGATION_DELAY=L:S::2200

SHIFTY_BMC_DATA_UP_R

46

PROPAGATION_DELAY=L:S::2200

x03_GT_010704

+3.3V_AUX

J14

1

CPLD_TCK

5,40,46

CPLD_TDO

5,32,40

CPLD_TDI

5,40

4 4

5,31,32,40,46

CPLD_TMS

2
3
4
5
6

CPLD JTAG Chain

subsys done

DELETED DDR CLOCK CHIP AND PCI CLOCK CHIP

ADDED COOLRUNNER II CPLD FROM YOSIMITE

A B

NP*

p/u for TCK at SIO

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

31,46

CPLD_TD2

CPLD_BYPASS

1 2

CPLD_TDO

NP*

5,32,40

TITLE

LINDY PLANAR

DWG NO.

D1660

DATE

DC

COMPUTER
CORPORATION
AUSTIN,TEXAS

REV.

SHEET

5 OF 611/13/2004

X03

1

2

3

TYPE
INPUT
OUTPUT
DESTINATION

70W VERTICAL
+12V
+1.8V
DDR II, MCH

ROOM=DC2DC_1P8V

1

+12V

R546

+1.8V

R463

1 2

0-5%

1 2

0-5%

R73

8.2K-5%

1 2

1V8_PWRGOOD

5,59

X03_GT_011804

21

R132

1 2

C1805

X03_GT_010704

Enable is driven to required state
from CPLD at all times.

0.1uF 16V

3.3K-5%

2

+12V

12

+

+

C605

270uF

16V-20%

2 1

C606

270uF

16V-20%

+1.8V DC2DC

R290

1 2

NC_DC2DC_1P8V_2

422-1%

+12V

+1.8V

DC2DC_1V8_EN

5,59

21

C588

R547

0-5%

1000pF

1 2

50V-10%

PART_NUMBER=79015

NP

MH1
MH2

MOD., 24 PIN, 72W, VERTICAL

DC2DC_1P8V

1

+RS

2

RSVD

3

-RS

4

PWRGD

5

PWRGD_SET

K

7

VSS_0

8

VSS_1

9

OUTEN

10

-SENCE

11

+SENSE

12

12V_IN_0

13

12V_IN_1

14

12V_IN_2

15

VOUT_0

16

VOUT_1

17

VSS_2

18

VOUT_2

19

VSS_3

20

VOUT_3

21

VSS_4

22

VOUT_4

23

VSS_5

24

VOUT_5

GND_MH1
GND_MH2

DC/DC CONVERTER

x00_gt_062603

+1.8V

16V-10%

16V-10%

4.7uF

C600

21

+1.8V

12

+

680uF

C268

6.3V-20%

25V-20%

4.7uF

C601

.1uF

21

x00_tj_051203

x02_tj_121503

12

+

680uF

C26912C270

C611

21

6.3V-20%

+

680uF

6.3V-20%

B D

TYPE
INPUT
OUTPUT
DESTINATION

100W HORIZONTAL
+12V
+3.3V
RISER's

ROOM=DC2DC_3P3V

+12V

R74

todo should this really be NC? -shawn

3V3_PWRGOOD

5,6,59

X03_GT_011804

Enable is driven to required state
from CPLD at all times.

1 2

21

R133

31

+3.3V DC2DC

8.2K-5%

+3.3V

3.3K-5%

x00_sd_051703

3P3V_RISER_SENSE

R1580

2-1%

R1430

1 2

2-1%

21

RISER

+3.3V

C1568

+12V

2 1

+

270uF

C1627

16V-20%

X00_GT_052203

1 2

0.1uF 16V

2

VCC

RESET

GND

3

DS1818

R1572

1 2

21.5K-1%

DC2DC_3V3_EN

5,59

C1501

21

0-5%

R301

U24

1

3V3_PWRGOOD

SUB=SUB*_Y1351

R1488

21

10K-1%

NC_DC2DC_3P3V_6

+12V

+3.3V

1 2

1000pF

50V-10%

PART_NUMBER=79015

NP

5,6,59

DC2DC_3P3V

1

+RS

K

3

-RS

4

PWRGD

5

PWRGD_SET

6

RESERVED

7

VSS_7

8

VSS_8

9

OUTEN

10

-SENSE

11

+SENSE

12

12VIN_12

13

12VIN_13

14

12VIN_14

15

VCC_15

16

VCC_16

17

VSS_17

18

VCC_18

19

VSS_19

20

VCC_20

21

VSS_21

22

VCC_22

23

VSS_23

24

VCC_24

100W-25A DC-DC

MOD.-25 pin, HORIZONTAL

+3.3V

16V-10%

4.7uF

+3.3V

4V-20%

820uF

+

21

1 2

16V-10%

C602

C287

CA

4.7uF
21

4V-20%

820uF

+

x00_tj_051203

25V-20%

C603

.1uF

21

1 2

C288

TYPE
INPUT
OUTPUT
DESTINATION

ROOM=DC2DC_5V

5,6,59

X03_GT_011804

SENSE_5V_BACKPLANE_1U

32

SENSE_5V_BACKPLANE_2U5U

32

VCC

C619

5V_PWRGOOD

R1752

2-1%

R562

1 2

0-5%

+12V

R75

1 2

21

R134

21

x03_sd_sense

BACKPLANE

+12V

+

C610

270uF

2 1

16V-20%

100W VERTICAL
+12V
+5V
BACKPLANE

8.2K-5%

Enable is driven to required state
from CPLD at all times.

3.3K-5%

x03b_sd

NP13

R1750

1 2

0-5%

R1751

21

2-1%

R273

21

1 2

511-1%

10K-1%

VCC

2

VCC

RESET

GND

3

DS1818

U59

R274

1

5V_PWRGOOD

SUB=SUB*_1F826

10-1%

1 2

C1650

0.1uF 16V

Sub to DS1811R-5 (+5V, 5% part)

+5V DC2DC

R462

12

0-5%

NC_DC2DC_5V_6

DC2DC_5V_EN

5,6,59

DC2DC_5V_SENSE_GND

6

DC2DC_5V_SENSE

6

21

C590

1000pF

NP

DC2DC_5V_SENSE

R275

NP*

21

DC2DC_5V_SENSE_GND

6

6

5,6,59

R466

1 2

0-5%

+12V

VCC

50V-10%

NP

R1848

1 2

5,6,59
5,6,59

309-1%

DC2DC_5V

1

+RS

K

3

-RS

4

PWRGD

5

RSVD_1

6

RSVD_2

7

VSS_0

8

VSS_1

9

OUTEN

10

-SENCE

11

+SENSE

12

12V_IN_0

13

12V_IN_1

14

12V_IN_2

15

VOUT_0

16

VOUT_1

17

VSS_2

18

VOUT_2

19

VSS_3

20

VOUT_3

21

VSS_4

22

VOUT_4

23

VSS_5

24

VOUT_5

MH1

GND_MH1

MH2

GND_MH2

DC/DC CONVERTER

MOD. 073_20821_03

SUB=SUB*_H0778

DC2DC_5V_EN

5V_PWRGOOD

+12V

NP

R1849

1 2

0-5%

1-23-2004_12:58

VCC

x00_tj_051203

16V-10%

16V-10%

4.7uF

VCC

12

C271

VCC

NP

40W-15A DC-DC

4.7uF

C60421C607

21

+

680uF

C272

6.3V-20%

DC2DC_5V_1U

1

VCC_1

2

VCC_2

3

VCC_3

4

TRIM

5

OUTEN

6

PWRGD

7

VSS_7

8

VSS_8

9

PWRGD_SET

10

12VIN_10

11

12VIN_11

SIP11

25V-20%

.1uF

12

+

680uF

X00_GT_061203

1

C620

21

6.3V-20%

2

TYPE
INPUT
OUTPUT
DESTINATION

40W VERTICAL
+12V
+1.2V
CPU1, CPU2, MCH

ROOM=DC2DC_CPU_VTT

Enable is driven to required state

3

from CPLD at all times.

CPU_VTT_PWRGOOD

5,51

+12V

16V-20%

NP

1 2

270uF

+

C138

+12V

NP

R1137

8.2K-5%2.7K-5%

1 2

DC2DC_CPUVTT_EN

5,51,59

NP

R1148

1 2

ECAD: Place 1 560uF cap by each CPU

& one by regulator

NP*

R543

1 2

27.4K-1%

x02_tj_091903

+CPU_VTT

+12V

CPU VTT

NP

R225

NP*

1 2

26.7-1%

DC2DC_CPUVTT

1

VCC_1

2

VCC_2

3

VCC_3

4

TRIM

5

OUTEN

6

PWRGD

7

VSS_7

8

VSS_8

9

PWRGD_SET

10

12VIN_10

11

12VIN_11

40W-15A DC-DC

SIP11

+CPU_VTT

10V-10%

.1uF

+CPU_VTT

+

C349

2 1

2 1

C591

560uF

4V-20%

16V-10%

4.7uF
21

C350

C608

2 1

+

560uF

4V-20%

TYPE
INPUT +12V
OUTPUT
DESTINATION

ROOM=DC2DC_1P5V

Enable is driven to required state
from CPLD at all times.

1V5_PWRGOOD

5,59

+12V

16V-20%

270uF

+

1 2

C1566

X03_GT_011804

40W HORIZONTAL

+1.5V
MCH, ICH5

+1.5V DC2DC

+1.5V

+12V

R77

8.2K-5%

1 2

21

R136

Substitute from 3.92K to 3.57K to tweak 1.5V to 1.53V

5,59

3.3K-5%

x03_tj_010904

DC2DC_1V5_EN

R70

1 2

+12V

3.57K-1%

R1489

26.7K-1%

SUB*_5N443

Substitute 26.1K, 1%

DC2DC_1P5V

1
2
3
4
5
6
7
8

21

9
10
11

40W-15A DC-DC

MOD.-13 pin, HORIZONTAL

VCC_1
VCC_2
VCC_3
TRIM
OUTEN
PWRGD
VSS_7
VSS_8
PWRGD_SET
12VIN_10
12VIN_11

+1.5V

4V-20%

820uF

+

1 2

C1497

10V-10%

2 1

.1uF

16V-10%

C1575

4.7uF

TYPE
INPUT
OUTPUT
DESTINATION

ROOM=DC2DC_RISER5V

Enable is driven to required state
from CPLD at all times.

+12V

R76

8.2K-5%

1 2

DC2DC_5V_RISER_EN

5

21

R135

3.3K-5%

21

C1585

5,6

+12V

16V-20%

1 2

270uF

+

5V_RISER_PWRGOOD

X03_GT_011804

C1569

40W HORIZONTAL
+12V
+5V
MCH, ICH5

+5.0V Riser

R32

1 2

+12V

309-1%

R106

1 2

0-5%

MOD.-13 pin, HORIZONTAL

5V DC2DC

DC2DC_RISER5V

1

VCC_1

2

VCC_2

3

VCC_3

4

TRIM

5

OUTEN

6

PWRGD

7

VSS_7

8

VSS_8

9

PWRGD_SET

10

12VIN_10

11

12VIN_11

40W-15A DC-DC

+5.0V Riser

U34

2

VCC

1

5V_RISER_PWRGOOD

RESET

GND

SUB=SUB*_1F826

3

1 2

DS1818

C1651

0.1uF 16V

Sub to DS1811R-5 (+5V, 5% part)

+5.0V Riser

12

+

680uF

C633

6.3V-20%

10V-10%

2 1

.1uF

16V-10%

C1576

4.7uF

5,6

C1586

21

4 4

3

subsys done

A B

DC2DC REGULATORS

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

TITLE

LINDY PLANAR

DWG NO.

D1660

DATE

DC

COMPUTER
CORPORATION
AUSTIN,TEXAS

REV.

SHEET

6 OF 611/13/2004

X03

B D

+12V +12V

SUB*_16155

VRD BOM Changes:

X02_TJ_081803

X02_TJ_110503

1

VRD1_PWM3A

7

VRD1_PWM4A

7

+3.3V

8.2K-5%
R4502

X02_TJ_081803

21

VCORE1_PWRGOOD

21

220K

R197221R1973

VRD1_VCC

220K

5,7,59

7

X03_GT_011804

Q86

3

FT2N7002LT1

1

2

VRD1_PWM1A

7

DRV1_OD

7

5.1-5%

2 1

R260

20%

R1985

21

10-1%

X03_GT_011804

1 3

1N914

D9

2-1%

R240

21

1
2
3
4

.22uF 25V

C484

21

Phase 1

ROOM = VRD1_PHASE1

VRD1_PHASE1B_SENSE

7

.22uF 25V

50V-10%

x03_sd

1000pF

C852

C491

1 2

20%

VRD1_DRV1

BST
IN
OD
VCC

ADP3418

21

C466

.1uF

25V-20%

DRVH

SW
PGND
DRVL

NP*

21

8
7
6
5

R433

VRD1_UGATE1

VRD1_LGATE1

4.7K

1 2

R451

1 2

4.7K

Q41

9

4

D

3

2

G

S

1

NC

FDS7096N3

SUB*_N1930

PKG_TYPE=SO8_P9DR_FRCHLD

Q21

4

3

2

1

FDS7066SN3

SUB*_T1564

5

6

.22uF 25V

7

1 2

20%

8

9

5

D

6

7

G

S

8

NC

PKG_TYPE=SO8_P9DR_FRCHLD

25V-20%

.1uF

21

C488

C1680

25V-20%

.1uF

21

16V-10%

4.7uF

21

C1682

C1681

Q24

9

4

D

3

2

G

S

1

NC

FDS7096N3

SUB*_N1930

PKG_TYPE=SO8_P9DR_FRCHLD

Q20

9

4

D

3

2

G

S

1

FDS7066SN3

SUB*_T1564

PKG_TYPE=SO8_P9DR_FRCHLD

5

6

7

8

5

6

7

8

NC

+12V

2

DRV1_OD_R

7

PWM Control Circuitry

ROOM = VRD1_CTRL

x00_sd_061603 - providing sensing

H1_VSSSENSE

12

VRD1_VSSSENSE_MID

3

0-5%

1 2

R1851

R304

0-5%

21

SUB=SUB*_4053P

DRV1_OD_R

7

.047uF 25V

SUB=SUB*_75EEC

1 2

20%

4 4

5,8,59

X00_GT_052203

R1820

NP

1 2

VRD1_VSSSENSE

1uF

1 2

C1728

25V-10%

249K-1%

1 2

C714

R255

+CPU_VID1

H1_VCCSENSE

12

X00_GT_052203

0-5%

50V-10%

1000pF

127K-1%

1 2

R233

X03_GT_011804

R1980

21

1 2

R1846

21

C1807

DRV1_OD

x03b_GT_012204

27pF

50V-10%

220K

VCORE_EN

C1727

100-5%

21

VCORE1_PWRGOOD

5,7,59

VRD1_VSSSENSE

H1_VID0

7,12

H1_VID1

7,12

H1_VID2

7,12

H1_VID3

7,12

H1_VID4

7,12

H1_VID5

7,12

100K-1%

C300

2 1

47pF

50V-5%

R311

0-5%

12

330pF 50V

VRD1_VCCSENSE

C708

R250

24K-5%

1 2

R1821

NP

1 2

0-5% 0-5%

21

C462

R289

21

12

.1uF

NP*

NP

7

25V-20%

680pF 50V

SUB=NP

R6019

1 2

VRD1_VCC

7

VRD1_CTRL

11

EN

10

PWRGD

15

ILIMIT

12

DELAY

9

COMP

7

FBRTN

5

VID0

4

VID1

3

VID2

2

VID3

1

VID4

6

VID5

19

GND

ADP3168

C479

12

R278

21

1K-1%

R288

1 2

100K-1%

x03b_GT_012204

SUB*_16155

X02_TJ_110503

+12V

10-5%

VCC

RAMPADJ

RT

PWM1
PWM2
PWM3
PWM4

SW1
SW2
SW3
SW4

CSSUM
CSREF

CSCOMP

FB

R305

300-5%

1 2

50V-10%

1000pF

21

1 2

R13

NP

C1810NP1 2

28

14
13

27
26
25
24

23
22
21
20

17
16
18

8

3

2

100-5%

Q87
FT2N7002LT1

R1987

1

10-1%

1N914

2-1%

VRD1_PWM3A

7

DRV1_OD

7

5.1-5%

2 1

R261

487K-1%

1 2

R271

1 2

200K-1%

VRD1_PWM1A
VRD1_PWM2A
VRD1_PWM3A
VRD1_PWM4A

R310

1 2

0-5%

50V-10%

3300pF

C720

1 2

SUB*_1U388

R147

21

15.8K-1%

R1992

x03b_GT_012204

21

X03_GT_011804

.22uF 25V

20%

1 3

D7

1 2

R243

16V-10%

.47uF

R299

7
7
7
7

R315

1 2

R303

21

0-5%

0-5%

73.2K-1%

73.2K-1%

1 2

R291

.01uF 16V

C710

1 2

R85

1 2

41.2K-1%

R306

1 2

0-5%

THERMISTOR

Phase 3

ROOM = VRD1_PHASE3

x03_sd

50V-10%

1000pF

C854

C490

NP*

21

21

VRD1_PHASE3B_SENSE

7

C467

21

.1uF

25V-20%

VRD1_DRV3

1

BST

2

IN

3

OD

4

VCC

ADP3418

.22uF 25V

C483

1 2

20%

C9

21

X00_GT_062103
Redraw Only- NEED INDEPENDENT CHECK before MODEM!

R314

21

0-5%

73.2K-1%

73.2K-1%
1 2

1 2

1 2

R286

R284

R285

NP

R81

1 2

24.9K-1%

8

DRVH

7

SW

6

PGND

5

DRVL

R457

1 2

VRD1_PHASE1B_SENSE

VRD1_PHASE2B_SENSE

VRD1_PHASE3B_SENSE

VRD1_PHASE4B_SENSE

X03_GT_011804

3

D

Q7

2N7002

NP

1

G

2

S

R437

4.7K
1 2

R407

1 2

0-5%

NP

.047uF

16V-10%

R484

4.7K

VRD1_LGATE3

4.7K

7

7
7

+CPU_VID1

7

C334

1 2

21

Q38

9

4

D

3

2

G

S

1

NC

FDS7096N3

SUB*_N1930

PKG_TYPE=SO8_P9DR_FRCHLD

VRD1_UGATE3

Q40

4

3

2

1

FDS7066SN3

ALT_LLINE

5

6

7

8

16V-10%

.22uF 25V

C481

1 2

20%

4.7uF

2 1

C1692

25V-20%

2 1

.1uF

25V-20%

2 1

.1uF

C1693

C1694

Redraw Only- NEED INDEPENDENT CHECK before MODEM!

9

5

D

6

7

G

S

8

NC

SUB*_T1564

PKG_TYPE=SO8_P9DR_FRCHLD

FDS7066N3 is local. Waiting on library symbol.

X03_GT_011904

R1717

NP

7

VRD1_PWM1A

1 2

NP

68K-5%

R1718

68K-5%

GPO_ALT_LLINE_N

7,8

33

21

VRD1_PWM3A

VRD1_PWM4A

+3.3V_AUX

U61

131412

x00_sd_052903

25V-20%

.1uF

.22uF 25V

C489

20%

21

Q39

9

4

D

3

2

G

S

1

NC

FDS7096N3

SUB*_N1930

PKG_TYPE=SO8_P9DR_FRCHLD

Q25

4

3

2

G

1

FDS7066SN3

SUB*_T1564

PKG_TYPE=SO8_P9DR_FRCHLD

7

7

VHC14

SUB=SUB*_P1355

12

C336

16V-10%

4.7uF

C1683

21

25V-20%

C1684

.1uF

21

5

6

7

8

20%

9

5

D

6

7

S

8

NC

ALT_LLINE

16V-10%

4.7uF

+

560uF

4V-20%

C1685

+CPU_VID1

21

0.6uH, 27Amp

VERTICAL

R152

1 2

C276

1 2

16V-10%

4.7uF

.22uF 25V

C487

21

7,8

2 1

C303

SUB=SUB*_N1453

L3

12

3-5%

.001UF

50V-10%

16V-10%

C1695

2 1

25V-20%

2 1

.1uF

SUB*_16155

X02_TJ_110503

SUB=SUB*_P1355

C1697

+CPU_VID1

C337

12

+

SUB*_16155

X02_TJ_110503

560uF

4V-20%

4.7uF

2 1

C305

25V-20%

2 1

.1uF

C1696

L1

VERTICAL

1 2

0.6uH, 27Amp
SUB=SUB*_N1453

3-5%

R171

1 2

21

C282

.001UF

50V-10%

Input Filtering

+12V

SUB=SUB*_P1355

12

+

C582

270uF

16V-20%

C725

INTEGRATED VRD 10.1 VOLTAGE

REGULATOR FOR PROC_1

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

A B

12

+

Q88

3

FT2N7002LT1

1

2

1N914

2-1%

7
7

5.1-5%

2 1

R258

+12V

Q89

3

FT2N7002LT1

1

2

5.1-5%

R257

560uF

4V-20%

CA

1 3

21

VRD1_PWM2A
DRV1_OD

7
7

C2

1 2

R1986

10-1%

D11

R244

.22uF 25V

20%

R1988

10-1%

1N914

2-1%

VRD1_PWM4A
DRV1_OD

12

.22uF 25V

20%

.1uF

Phase 2

21

X03_GT_011804

.22uF 25V

C579

1 2

20%

C471

.1uF

25V-20%

VRD1_PHASE2

1

BST

2

IN

3

OD

4

VCC

ADP3418

C482

21

21

X03_GT_011804

.22uF 25V

20%

D10

31

1 2

R236

VRD1_DRV4

1

VRD1_UGATE4

BST

2

IN

3

OD

4

VCC

C8

21

21

C3

.1uF

50V-20%

50V-20%

SUB=SUB*_4053P

ROOM = VRD1_PHASE2

VRD1_PHASE2B_SENSE

7

50V-10%

1000pF

C853

NP*

21

x03_sd

21

8

DRVH

7

SW

6

PGND

5

DRVL

VRD1_LGATE2

R454

R434

4.7K

4.7K

1 2

1 2

Phase 4

ROOM = VRD1_PHASE4

VRD1_PHASE4B_SENSE

7

50V-10%

1000pF

C855

C578

NP*

21

21

x03_sd

C465

1 2

.1uF

25V-20%

8

DRVH

7

SW

6

PGND

5

DRVL

ADP3418

C21

1 2

1uF

25V-10%

VRD1_LGATE4

21

R430

21

R428

4.7K

1uF

C12

1 2

25V-10%

SUB=SUB*_4053P

4.7K

Q36

9

4

D

3

2

G

S

1

NC

FDS7096N3

SUB*_N1930

PKG_TYPE=SO8_P9DR_FRCHLD

4

3

2

G

1

FDS7066SN3

SUB*_T1564

Q34

4

3

2

G

1

FDS7096N3

SUB*_N1930

PKG_TYPE=SO8_P9DR_FRCHLD

5

6

.22uF 25V

7

20%

8

Q37

9

5

D

6

7

S

8

NC

PKG_TYPE=SO8_P9DR_FRCHLD

9

5

D

6

7

S

8

20%

NC

Q33

4

3

2

G

1

FDS7066SN3

SUB*_T1564

16V-10%

25V-20%

4.7uF

C1686

2 1

25V-20%

1 2

C581

C1687

2 1

.1uF

16V-10%

4.7uF

C1698

2 1

.22uF 25V

25V-20%

C485

1 2

.1uF

9

5

D

6

7

S

8

NC

PKG_TYPE=SO8_P9DR_FRCHLD

2 1

.1uF

25V-20%

.1uF

C1699

12

C1688

12

C1700

Q27

9

4

D

3

2

G

S

1

NC

FDS7096N3

SUB*_N1930

PKG_TYPE=SO8_P9DR_FRCHLD

Q26

9

4

D

3

2

G

S

1

FDS7066SN3

SUB*_T1564

PKG_TYPE=SO8_P9DR_FRCHLD

Q35

9

4

D

3

2

G

S

1

NC

FDS7096N3

SUB*_N1930

PKG_TYPE=SO8_P9DR_FRCHLD

Q32

4

3

2

1

FDS7066SN3

TITLE

DWG NO.

DATE

1-23-2004_12:58

SUB=SUB*_P1355

C343

16V-10%

25V-20%

4.7uF

C1689

.22uF 25V

20%

21

C580

2 1

25V-20%

.1uF

2 1

.1uF

C1690

5

6

7

8

5

6

7

8

NC

SUB=SUB*_P1355

5

6

7

.22uF 25V

8

20%

9

5

D

6

7

G

S

8

NC

SUB*_T1564

PKG_TYPE=SO8_P9DR_FRCHLD

16V-10%

C486

21

4.7uF

C1701

2 1

25V-20%

.1uF

25V-20%

.1uF

C1702

12

VID Termination

+CPU_VTT

LINDY PLANAR

DC

D1660

R28

1 2
499-1%

R27

1 2
499-1%

R26

1 2
499-1%

R25

1 2
499-1%

R16

1 2
499-1%

R15

1 2
499-1%

H1_VID0

H1_VID1

H1_VID2

H1_VID3

H1_VID4

H1_VID5

COMPUTER
CORPORATION

AUSTIN,TEXAS

SHEET

12

C1691

2 1

C338

12

7 OF 611/13/2004

+

560uF

4V-20%

+CPU_VID1

12

+

560uF

C1703

REV.

16V-10%

4.7uF

2 1

C308

L2

1 2

0.6uH, 27Amp

3-5%

R163

1 2

C281

1 2

.001UF

16V-10%

4.7uF

2 1

C302

4V-20%

+CPU_VID1

L4

1 2

21

3-5%

R153

21

C280

7,12

7,12

7,12

7,12

7,12

7,12

X03

VERTICAL

SUB=SUB*_N1453

50V-10%

VERTICAL

0.6uH, 27Amp
SUB=SUB*_N1453

.001UF

50V-10%

1

2

3

B D

CA

+12V

SUB*_P1355

Q90

3

SUB*_16155

VRD BOM Changes:

X02_TJ_081803

X02_TJ_110503

1

VRD2_VCC

21

220K

220K

R197021R1971

VRD2_PWM3A

8

VRD2_PWM4A

8

+3.3V

8.2K-5%
R4503

X02_TJ_081803

21

VCORE2_PWRGOOD

2

8

DRV2_OD_R

R1981

220K

5,8,59

X03_GT_011804

21

21

27pF

C1808

8

X03_GT_011804

DRV2_OD

8

x03b_GT_012204

50V-10%

FT2N7002LT1

1

2

8
8

5.1-5%

2 1

R264

SUB*_16155

X02_TJ_110503

R1989

10-1%

1N914

2-1%

VRD2_PWM1A
DRV2_OD

.22uF 25V

20%

21

X03_GT_011804

21

VRD2_PHASE1B_SENSE

8

.22uF 25V

1 3

20%

D25

R247

VRD2_DRV1

21

1

BST

2

IN

3

OD

4

VCC

ADP3418

C599

+12V

Q91

3

FT2N7002LT1

2

PWM Control Circuitry

ROOM = VRD2_CTRL

VCORE_EN

5,7,59

R1822

NP

H2_VSSSENSE

12

R318

3

1 2

0-5%

SUB=SUB*_4053P

DRV2_OD_R

8

SUB*_75EEC

.047uF 25V

C715

1 2

20%

4 4

+CPU_VID2

12

1 2

VRD2_VSSSENSE

50V-10%

1000pF

1uF

1 2

C1729

25V-10%

249K-1%

1 2

127K-1%

R256

H2_VCCSENSE

X00_GT_052203

0-5%

C1730

21

PART_NUMBER=79015

1 2

R235

subsys done

21

.1uF

C473

25V-20%

100-5%

1 2

R1847

11

EN

10

VCORE2_PWRGOOD

5,8,59

VRD2_VSSSENSE

H2_VID0

8,12

H2_VID1

8,12

H2_VID2

8,12

H2_VID3

8,12

H2_VID4

8,12

H2_VID5

8,12

C301

2 1

47pF

50V-5%

R252

12

24K-5% 1K-1%

330pF 50V

R348

1 2

VRD2_VCCSENSE

0-5%

R1823

NP

1 2

0-5% 0-5%

100K-1%

R297

21

C709

12

15

12

19

NP*

9

7

5
4
3
2
1
6

NP

PWRGD

ILIMIT

DELAY

COMP

FBRTN

VID0
VID1
VID2
VID3
VID4
VID5

GND

R1993

1 2

x03b_GT_012204

VRD2_VCC

8

VRD2_CTRL

RAMPADJ

ADP3168

C480

12

680pF 50V

R279

R296

NP

1 2

100K-1%

CSCOMP

21

VCC

PWM1
PWM2
PWM3
PWM4

SW1
SW2
SW3
SW4

CSSUM
CSREF

RT

FB

R328

28

14
13

27
26
25
24

23
22
21
20

17
16
18

8

1 2

+12V

1 2

10-5%

300-5%

50V-10%

1000pF

21

R14

VRD2_PWM1A
VRD2_PWM2A
VRD2_PWM3A
VRD2_PWM4A

R347

1 2

0-5%

NP

100-5%

C1811NP1 2

50V-10%

487K-1%

3300pF

R1994

x03b_GT_012204

Phase 1

ROOM = VRD2_PHASE1

50V-10%

x03_sd

1000pF

C856

C648

1 2

21

C476

.1uF

25V-20%

DRVH

SW
PGND
DRVL

8
7
6
5

NP*

21

R487

VRD2_UGATE1

VRD2_LGATE1

4.7K

1 2

Phase 3

R6018

1

10-1%

VRD2_PWM3A

8

DRV2_OD

8

5.1-5%

2 1

R267

1 2

R272

R300

1 2

200K-1%

8
8
8
8

1 2

R316

21

0-5%

73.2K-1%

1 2

.01uF 16V

C721

1 2

SUB*_1U388

R148

15.8K-1% 0-5%

THERMISTOR

21

X03_GT_011804

1 3

1N914

D12

1 2

2-1%

R248

1
2
3
4

16V-10%

.47uF

R350

0-5%

73.2K-1%
1 2

R298

C711

1 2

41.2K-1%

1 2

21

ROOM = VRD2_PHASE3

VRD2_PHASE3B_SENSE

8

.22uF 25V

20%

VRD2_DRV3

BST
IN
OD
VCC

C11

21

R349

0-5%

73.2K-1%

R295

R87

1 2

R332

R494

1 2

C647

21

25V-20%

ADP3418

.22uF 25V

20%

21

73.2K-1%

1 2

R293

Q70

4

3

2

G

1

FDS7096N3

SUB*_N1930

4.7K

50V-10%

x03_sd

1000pF

21

C477

21

.1uF

8

DRVH

7

SW

6

PGND

5

DRVL

C598

1 2

VRD2_PHASE1B_SENSE

VRD2_PHASE2B_SENSE

VRD2_PHASE3B_SENSE

VRD2_PHASE4B_SENSE

1 2

R294

X03_GT_011804

R86

1 2

24.9K-1%

9

5

D

6

7

S

8

NC

PKG_TYPE=SO8_P9DR_FRCHLD

C858

NP*

VRD2_UGATE3

R500

1 2

Q43

9

4

D

3

2

G

S

1

FDS7066SN3

SUB*_T1564

PKG_TYPE=SO8_P9DR_FRCHLD

VRD2_LGATE3

R493

4.7K

4.7K
1 2

NP

3

2

20%

NC

8

8
8

8

D

S

16V-10%

4.7uF

.22uF 25V

C624

1 2

5

6

7

8

Q62

9

4

D

3

2

G

S

1

NC

FDS7096N3

SUB*_N1930

PKG_TYPE=SO8_P9DR_FRCHLD

+CPU_VID2

Q8

2N7002

NP

1

G

C1704

2 1

25V-20%

.1uF

5

6

7

8

R501

4.7K

1 2

25V-20%

C1706

2 1

.1uF

C1705

2 1

.22uF 25V

1 2

20%

Q67

9

4

D

3

2

G

S

1

NC

FDS7066SN3

SUB*_T1564

PKG_TYPE=SO8_P9DR_FRCHLD

8

R418

0-5%

NP

.047uF

16V-10%

21

16V-10%

4.7uF

C1732

2 1

25V-20%

C594

5

6

7

8

VRD2_PWM1A

C335
1 2

ALT_LLINE

4

3

2

1

FDS7096N3

25V-20%

2 1

.1uF

Q44

G

4

3

2

1

.1uF

C1722

NP

NP

7

9

5

D

6

7

S

8

NC

SUB*_N1930

PKG_TYPE=SO8_P9DR_FRCHLD

Q42

9

5

D

6

7

G

S

8

NC

FDS7066SN3

SUB*_T1564

PKG_TYPE=SO8_P9DR_FRCHLD

C1723

2 1

X03_GT_011904

R1715

1 2

68K-5%

R1716

21

68K-5%

16V-10%

4.7uF

.22uF 25V

C646

1 2

20%

Q63

9

4

D

3

2

G

S

1

NC

FDS7096N3

SUB*_N1930

PKG_TYPE=SO8_P9DR_FRCHLD

4

3

2

1

VRD2_PWM3A

VRD2_PWM4A

25V-20%

C1707

2 1

25V-20%

2 1

.1uF

5

6

7

8

20%

Q45

9

D

G

S

NC

FDS7066SN3

SUB*_T1564

PKG_TYPE=SO8_P9DR_FRCHLD

8

8

2 1

.1uF

C1708

.22uF 25V

21

5

6

7

8

16V-10%

4.7uF

2 1

12

C344

C1709

+CPU_VID2

VERTICAL

C326

+

560uF

4V-20%

0.6uH, 27Amp

L17

SUB*_16155

SUB=SUB*_N1453

X02_TJ_110503

12

3-5%

R172

1 2

C283

1 2

.001UF

50V-10%

SUB*_P1355

16V-10%

4.7uF

2 1

+

560uF

4V-20%

+CPU_VID2

C328

SUB*_16155

X02_TJ_110503

16V-10%

4.7uF

2 1

C623

25V-20%

C1724

25V-20%

2 1

.1uF

.1uF

C1725

C424

2 1

12

C1726

L5

1 2

0.6uH, 27Amp

3-5%

R182

1 2

21

C299

.001UF

FDS7066N3 is local. Waiting on library symbol.

INTEGRATED VRD 10.1 VOLTAGE

REGULATOR FOR PROC_2

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

A B

+12V

Q92

3

FT2N7002LT1

R1990

1N914

2-1%

10-1%

1 3

D38

R249

21

1

2

21

VRD2_PWM2A

8

DRV2_OD

8

5.1-5%
2 1

R263

.22uF 25V

C595

20%

21

+12V

Q93

3

FT2N7002LT1

R1991

21

1

10-1%

2

.22uF 25V

20%

1N914

D34

31

1 2

2-1%

R246

VERTICAL

SUB=SUB*_N1453

8
8

VRD2_PWM4A
DRV2_OD

5.1-5%
12

R262

.22uF 25V

C10

20%

50V-10%

21

Input Filtering

+12V

SUB*_P1355

C583

+

2 1

270uF

16V-20%

C820

12

+

560uF

4V-20%

Phase 2

ROOM = VRD2_PHASE2

X03_GT_011804

VRD2_PHASE2B_SENSE

8

.22uF 25V

50V-10%

x03_sd

1000pF

C857

C650

20%

1

BST

2

IN

3

OD

4

VCC

1 2

25V-20%

VRD2_DRV2

ADP3418

C478

.1uF

21

DRVH

PGND
DRVL

NP*

8
7

SW

6
5

R490

1 2

Phase 4

ROOM = VRD2_PHASE4

VRD2_PHASE4B_SENSE

8

50V-10%

x03_sd

1000pF

C859

C649

NP*21

21

21

C475

1 2

.1uF

25V-20%

VRD2_DRV4

1

BST

2

IN

3

OD

4

VCC

C6

1 2

ADP3418

.1uF

50V-20%

DRVH

PGND
DRVL

C7

8
7

SW

6
5

21

R486

21

.1uF

50V-20%

VRD2_LGATE2

R495

4.7K

VRD2_LGATE4

21

R485

4.7K

C23

1 2

SUB*_4053P

4.7K

1 2

4.7K

1uF

25V-10%

Q52

9

4

D

3

2

G

S

1

NC

FDS7096N3

SUB*_N1930

PKG_TYPE=SO8_P9DR_FRCHLD

Q50

9

4

D

3

2

G

S

1

NC

FDS7096N3

SUB*_N1930

PKG_TYPE=SO8_P9DR_FRCHLD

VRD2_UGATE4

Q49

9

4

3

2

G

S

1

FDS7066SN3

SUB*_T1564

PKG_TYPE=SO8_P9DR_FRCHLD

1uF

C22

1 2

SUB*_4053P

5

6

7

8

Q56

9

4

3

2

G

S

1

FDS7066SN3

SUB*_T1564

PKG_TYPE=SO8_P9DR_FRCHLD

5

6

7

8

5

D

6

7

8

NC

25V-10%

.22uF 25V

1 2

20%

5

D

6

7

8

NC

.22uF 25V

20%

16V-10%

4.7uF

C652

16V-10%

4.7uF

C617

1 2

C1710

2 1

25V-20%

.1uF

C1716

2 1

25V-20%

.1uF

25V-20%

2 1

.1uF

C1711

2 1

25V-20%

.1uF

C1717

12

C1712

C1718

12

Q47

9

4

3

2

G

S

1

FDS7096N3

SUB*_N1930

PKG_TYPE=SO8_P9DR_FRCHLD

Q51

9

4

D

3

2

G

S

1

NC

FDS7096N3

SUB*_N1930

PKG_TYPE=SO8_P9DR_FRCHLD

Q48

9

4

D

3

2

G

S

1

NC

FDS7066SN3

SUB*_T1564

PKG_TYPE=SO8_P9DR_FRCHLD

5

D

6

7

8

NC

Q46

9

4

D

3

2

G

S

1

NC

FDS7066SN3

SUB*_T1564

PKG_TYPE=SO8_P9DR_FRCHLD

5

6

7

8

5

6

7

8

TITLE

LINDY PLANAR

DWG NO.

DATE

DC

SUB*_P1355

12

C440

16V-10%

25V-20%

.22uF 25V

20%

4.7uF

C651

2 1

C1713

25V-20%

2 1

.1uF

.1uF

C1714

2 1

C1715

21

5

6

7

8

SUB*_P1355

16V-10%

12

+

C425

560uF

4V-20%

16V-10%

25V-20%

4.7uF

C1719

.22uF 25V

20%

21

2 1

C618

25V-20%

.1uF

12

.1uF

C1720

C1721

12

+CPU_VID2

L18

C284

VID Termination

+CPU_VTT

R79

D1660

1 2
499-1%

R78

1 2
499-1%

R72

1 2
499-1%

R71

1 2
499-1%

R69

1 2
499-1%

R68

1 2
499-1%

H2_VID0

H2_VID1

H2_VID2

H2_VID3

H2_VID4

H2_VID5

COMPUTER
CORPORATION

AUSTIN,TEXAS

SHEET

8 OF 611/13/2004

16V-10%

+

560uF

4V-20%

+CPU_VID2

L16

C285

4.7uF

2 1

C309

1 2

0.6uH, 27Amp

21

3-5%

R178

21

.001UF

REV.

4.7uF

2 1

C333

VERTICAL

1 2

0.6uH, 27Amp

SUB=SUB*_N1453

3-5%

R179

1 2

1 2

.001UF

50V-10%

VERTICAL

SUB=SUB*_N1453

50V-10%

8,12

8,12

8,12

8,12

8,12

8,12

X03

1

2

3

B D

CA

1-23-2004_12:58

1

+12V

R427

1 2
100-1%

100K-5%

T

10K-1%

R104

21

0.1uF 16V
1 2

R90

21

C719

10K-1%

0.1uF 16V

3.32K-1%

1 2

C716

R102

21

R281

1 2

1K-1%

R183

21

.22uF 25V

1 2

20%

C653

5

+

V+
V-

4

-

3

12

U17
LM339

2

10K-1% 25.5K-1%

R140

21

R254

21

9

+

V+
V-

8

-

3

12

U17
LM339

14

+3.3V

8.2K-5%

21

R1704

VRD1_THERMTRIP_N

5,46

2

Locate near hot component in P1 core regulator.

U17
LM339

1

1 2

10K-1% 25.5K-1%

R142

1 2

R253

+3.3V

8.2K-5%
R1705

U17

3

LM339

11

+

V+
V-

10

­12

21

13

VRD2_THERMTRIP_N

5,46

100K-5%

T

1 2

10K-1%

R141

1 2

R89

0.1uF 16V
1 2

C718

10K-1%

0.1uF 16V

3.32K-1%

1 2

C717

21

1 2

R149

R280

1K-1%

R192

21

3

7

+

V+
V-

6

­12

3

1

2

3

Locate near hot component in P2 core regulator.

VRD Over Temperature Detect Circuit

ROOM=VRD_THERM

4 4

COMPUTER
CORPORATION

AUSTIN,TEXAS

REV.

SHEET

X03

subsys done

A B

VRD THERMTRIP

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

TITLE

LINDY PLANAR

DWG NO.

D1660

DATE

1/13/2004 9 OF 61

DC

B D

CA

1-23-2004_12:58

1

2

1

2

3

4 4

COMPUTER
CORPORATION

AUSTIN,TEXAS

REV.

SHEET

X03

A B

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

TITLE

LINDY PLANAR

DWG NO.

DATE

D1660

1/13/2004 10 OF 61

DC

3

B D

ROOM=PROC_1

TO DO - MECHANICAL ADD'S NOT CORRECT

1

Heat Sink Clips

Heat Sink RM

H_A3_N

+CPU_VTT

2

x00_tj_061403

3

Alternate PLL filter circuit recommended by Intel until
on-die version validated.

+1.5V

R1583NP

1 2

2.5V-20%-2STACK

0-5%

1 2

680uF

C1588

+

NP

4 4

+1.5V

R1584NP

0-5%

2.5V-20%-2STACK

680uF

21

+

NP

subsys done

NP

NP

1 2

1 2

4.7uF

C1570

C1371

6.3V-10%

0.1uF 16V

1 2

C1587

NP

NP

4.7uF

C1372

6.3V-10%

NP

21

0.1uF 16V

C1373

21

C1571

A B

R1556

1 2

220

1 2

R1558

1 2

220

1 2

R1562

1 2

220

1 2

R1563

1 2

220

1 2

1 2

R1506

21

51

R1493

21

51

R1497

21

51

R1499

21

51

R1501

21

51

R1503

21

51

NP

1 2

R1494

NP

1 2

51

NP

1 2

R1508

1 2
100-5%

x00_GT_010704

V_1P5_H1_VCCPLL

NP

21

10 - 12 mil traces

C1370

0.1uF 16V

V_1P5_H2_VCCPLL

x00_sd_061703

1 2

0.1uF 16V

R1559

21

H_A20M_N

220

H_SLP_N

R1557

H_NMI

220

H_INTR

R1560

H_SMI_N

220

H_INIT_N

R1561

H_IGNNE_N

220

H_STPCLK_N

R1504

H_FERR_N

51

R1505

H_BREQ0_N

51

H_BREQ1_N

R1496

21

H1_BREQ23_N

51

H1_ODTEN

R1554

21

H_PWRGOOD

301-1%

H1_TESTHI0

R1498

21

H1_TESTHI1

51

H1_TESTHI2

R1500

21

H1_TESTHI3

51

H1_TESTHI4

R1502

21

H1_TESTHI5

51

H1_TESTHI6

R1495

H1_TESTHI7

51

H1_TESTHI8

R1492

H1_BOOTSEL

51

H_RST_N

12

x03b_tj_012004

12

SUB*_X4108

ST1

1

NC_ST1_2

RETENTION SUPPORT, W/CLIP

NC_ST2_2

RETENTION SUPPORT, W/CLIP

GND

2

NC

GROUND, BRACKET

SUB*_X4108

ST2

1

GND

2

NC

GROUND, BRACKET

11,33

11,33

11,33

11,33

11,33

11,33,55

11,33

11,33

11,33

11,17

11,17

11

12

12,33

12

12

12

12

12

12

12

12

12

12

11,15,17

1U Bottom Support Bracket

2U/5U Bottom Support Bracket

Place @ CPU1 Place @ CPU2

11,17

H_A4_N

11,17

H_A5_N

11,17

H_A6_N

11,17

H_A7_N

11,17

H_A8_N

11,17

H_A9_N

11,17

H_A10_N

11,17

H_A11_N

11,17

H_A12_N

11,17

H_A13_N

11,17

H_A14_N

11,17

H_A15_N

11,17

H_A16_N

11,17

H_A17_N

11,17

H_A18_N

11,17

H_A19_N

11,17

H_A20_N

11,17

H_A21_N

11,17

H_A22_N

11,17

H_A23_N

11,17

H_A24_N

11,17

H_A25_N

11,17

H_A26_N

11,17

H_A27_N

11,17

H_A28_N

11,17

H_A29_N

11,17

H_A30_N

11,17

H_A31_N

11,17

H_A32_N

11,17

H_A33_N

11,17

H_A34_N

11,17

H_A35_N

11,17

H_AP0_N

11,17

H_AP1_N

11,17

H_ADS_N

11,17

H_ADSTB0_N

11,17

H_ADSTB1_N

11,17

H_REQ0_N

11,17

H_REQ1_N

11,17

H_REQ2_N

11,17

H_REQ3_N

11,17

H_REQ4_N

11,17

H_BREQ0_N

11,17

H_BREQ1_N

11,17

H1_BREQ23_N

11

H_BNR_N

11,17

H_BPRI_N

11,17

H_LOCK_N

11,17

H_BINIT_N

11,17

H_RS0_N

11,17

H_RS1_N

11,17

H_RS2_N

11,17

H_RSP_N

11,17

H_TRDY_N

11,17

H_HITM_N

11,17

H_HIT_N

11,17

H_DEFER_N

11,17

H_A20M_N

11,33

H_SMI_N

11,33

H_FERR_N

11,33

H_IGNNE_N

11,33

H1_IERR_N

15

H_MCERR_N

11,15,17

H_SLP_N

11,33

H_STPCLK_N

11,33

H_RST_N

11,15,17

H_INIT_N

11,33,55

H_INTR

11,33

H_NMI

11,33

CK_167M_CPU1_P

3

CK_167M_CPU1_N

3

SUB=SUB*_4M319

Retention Screws

proc heatsink RM boat

two of the boats are represented here

PROC_1

A22

A3

A20

A4

B18

A5

C18

A6

A19

A7

C17

A8

D17

A9

A13

A10

B16

A11

B14

A12

B13

A13

A12

A14

C15

A15

C14

A16

D16

A17

D15

A18

F15

A19

A10

A20

B10

A21

B11

A22

C12

A23

E14

A24

D13

A25

A9

A26

B8

A27

E13

A28

D12

A29

C11

A30

B7

A31

A6

A32

A7

A33

C9

A34

C8

A35

E10

AP0

D9

AP1

D19

ADS

F17

ADSTB0

F14

ADSTB1

B19

REQ0

B21

REQ1

C21

REQ2

C20

REQ3

B22

REQ4

D20

BR0

F12

BR1

E11

BR2

D10

BR3

F20

BNR

D23

BPRI

A17

LOCK

F11

BINIT

E21

RS0

D22

RS1

F21

RS2

C6

RSP

E19

TRDY

A23

HITM

E22

HIT

C23

DEFER

F27

A20M

C27

SMI

E27

FERR/PBE

C26

IGNNE

E5

IERR

D7

MCERR

AE6

SLP

D4

STPCLK

Y8

RESET

D6

INIT

B24

LINT0

G23

LINT1

Y4

BCLK0

W5

BCLK1

NOCONA 667MHz / 604 PROCESSOR

REV. 0.5-EMTS, ZIF SKT

HETERO 1 OF 4

ADD1=ADD*_89JJP_RETSCRW1
ADD2=ADD*_89JJP_RETSCRW2
ADD3=ADD*_89JJP_RETSCRW3
ADD4=ADD*_89JJP_RETSCRW4
ADD5=ADD*_89JJP_RETSCRW5
ADD6=ADD*_89JJP_RETSCRW6
ADD7=ADD*_89JJP_RETSCRW7
ADD8=ADD*_89JJP_RETSCRW8

ADD7=ADD02_Y1255_BRKT1
ADD8=ADD02_Y1255_BRKT2

ADD1=ADD13_W1578_BRKT3
ADD2=ADD13_W1578_BRKT4

ADD3=ADD*_X4108_RETMOD1
ADD4=ADD*_X4108_RETMOD2
ADD5=ADD*_X4108_RETMOD3

D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63

DP0
DP1
DP2
DP3

DSTBN0
DSTBN1
DSTBN2
DSTBN3

DSTBP0
DSTBP1
DSTBP2
DSTBP3

DBI0
DBI1
DBI2
DBI3
DBSY
DRDY

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9

Heat Sink RM screws

Y26
AA27
Y24
AA25
AD27
Y23
AA24
AB26
AB25
AB23
AA22
AA21
AB20
AB22
AB19
AA19
AE26
AC26
AD25
AE25
AC24
AD24
AE23
AC23
AA18
AC20
AC21
AE22
AE20
AD21
AD19
AB17
AB16
AA16
AC17
AE13
AD18
AB15
AD13
AD14
AD11
AC12
AE10
AC11
AE9
AD10
AD8
AC9
AA13
AA14
AC14
AB12
AB13
AA11
AA10
AB10
AC8
AD7
AE7
AC6
AC5
AA8
Y9
AB6

AC18
AE19
AC15
AE17

Y21
Y18
Y15
Y12

Y20
Y17
Y14
Y11

AC27
AD22
AE12
AB9
F18
E18

H_D0_N

11,17

H_D1_N

11,17

H_D2_N

11,17

H_D3_N

11,17

H_D4_N

11,17

H_D5_N

11,17

H_D6_N

11,17

H_D7_N

11,17

H_D8_N

11,17

H_D9_N

11,17

H_D10_N

11,17

H_D11_N

11,17

H_D12_N

11,17

H_D13_N

11,17

H_D14_N

11,17

H_D15_N

11,17

H_D16_N

11,17

H_D17_N

11,17

H_D18_N

11,17

H_D19_N

11,17

H_D20_N

11,17

H_D21_N

11,17

H_D22_N

11,17

H_D23_N

11,17

H_D24_N

11,17

H_D25_N

11,17

H_D26_N

11,17

H_D27_N

11,17

H_D28_N

11,17

H_D29_N

11,17

H_D30_N

11,17

H_D31_N

11,17

H_D32_N

11,17

H_D33_N

11,17

H_D34_N

11,17

H_D35_N

11,17

H_D36_N

11,17

H_D37_N

11,17

H_D38_N

11,17

H_D39_N

11,17

H_D40_N

11,17

H_D41_N

11,17

H_D42_N

11,17

H_D43_N

11,17

H_D44_N

11,17

H_D45_N

11,17

H_D46_N

11,17

H_D47_N

11,17

H_D48_N

11,17

H_D49_N

11,17

H_D50_N

11,17

H_D51_N

11,17

H_D52_N

11,17

H_D53_N

11,17

H_D54_N

11,17

H_D55_N

11,17

H_D56_N

11,17

H_D57_N

11,17

H_D58_N

11,17

H_D59_N

11,17

H_D60_N

11,17

H_D61_N

11,17

H_D62_N

11,17

H_D63_N

11,17

H_DP0_N

11,17

H_DP1_N

11,17

H_DP2_N

11,17

H_DP3_N

11,17

H_DSTBN0_N

11,17

H_DSTBN1_N

11,17

H_DSTBN2_N

11,17

H_DSTBN3_N

11,17

H_DSTBP0_N

11,17

H_DSTBP1_N

11,17

H_DSTBP2_N

11,17

H_DSTBP3_N

11,17

H_DBI0_N

11,17

H_DBI1_N

11,17

H_DBI2_N

11,17

H_DBI3_N

11,17

H_DBSY_N

11,17

H_DRDY_N

11,17

ADD1=ADD*_H3668_RMCLIP1
ADD2=ADD*_H3668_RMCLIP2
ADD3=ADD*_H3668_RMCLIP3
ADD4=ADD*_H3668_RMCLIP4

ADD5=ADD*_X4108_RETMOD5
ADD6=ADD*_X4108_RETMOD6
ADD7=ADD*_X4108_RETMOD7

11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17
11,17

11,17
11,17

11,17
11,17
11,17

11,17
11,17
11,17
11,17
11,17

11,17

Swizzled

11,17

11

11,17
11,17
11,17
11,17

11,17
11,17
11,17
11,17
11,17

11,17
11,17
11,17

11,33
11,33
11,33
11,33

15

11,15,17

11,33

11,33
11,15,17
11,33,55

11,33

11,33

3
3

proc heatsink RM clip

x03b_tj_012004

proc heatsink RM boat

x03b_tj_012004

H_A3_N
H_A4_N
H_A5_N
H_A6_N
H_A7_N
H_A8_N
H_A9_N
H_A10_N
H_A11_N
H_A12_N
H_A13_N
H_A14_N
H_A15_N
H_A16_N
H_A17_N
H_A18_N
H_A19_N
H_A20_N
H_A21_N
H_A22_N
H_A23_N
H_A24_N
H_A25_N
H_A26_N
H_A27_N
H_A28_N
H_A29_N
H_A30_N
H_A31_N
H_A32_N
H_A33_N
H_A34_N
H_A35_N

H_AP0_N
H_AP1_N

H_ADS_N
H_ADSTB0_N
H_ADSTB1_N

H_REQ0_N
H_REQ1_N
H_REQ2_N
H_REQ3_N
H_REQ4_N

H_BREQ1_N
H_BREQ0_N
H2_BREQ23_N

H_BNR_N
H_BPRI_N
H_LOCK_N
H_BINIT_N

H_RS0_N
H_RS1_N
H_RS2_N
H_RSP_N
H_TRDY_N

H_HITM_N
H_HIT_N
H_DEFER_N

H_A20M_N
H_SMI_N
H_FERR_N
H_IGNNE_N
H2_IERR_N
H_MCERR_N

H_SLP_N
H_STPCLK_N
H_RST_N
H_INIT_N

H_INTR
H_NMI

CK_167M_CPU2_P
CK_167M_CPU2_N

SUB=SUB*_4M319

PROC_2

A22

A3

A20

A4

B18

A5

C18

A6

A19

A7

C17

A8

D17

A9

A13

A10

B16

A11

B14

A12

B13

A13

A12

A14

C15

A15

C14

A16

D16

A17

D15

A18

F15

A19

A10

A20

B10

A21

B11

A22

C12

A23

E14

A24

D13

A25

A9

A26

B8

A27

E13

A28

D12

A29

C11

A30

B7

A31

A6

A32

A7

A33

C9

A34

C8

A35

E10

AP0

D9

AP1

D19

ADS

F17

ADSTB0

F14

ADSTB1

B19

REQ0

B21

REQ1

C21

REQ2

C20

REQ3

B22

REQ4

D20

BR0

F12

BR1

E11

BR2

D10

BR3

F20

BNR

D23

BPRI

A17

LOCK

F11

BINIT

E21

RS0

D22

RS1

F21

RS2

C6

RSP

E19

TRDY

A23

HITM

E22

HIT

C23

DEFER

F27

A20M

C27

SMI

E27

FERR/PBE

C26

IGNNE

E5

IERR

D7

MCERR

AE6

SLP

D4

STPCLK

Y8

RESET

D6

INIT

B24

LINT0

G23

LINT1

Y4

BCLK0

W5

BCLK1

NOCONA 667MHz / 604 PROCESSOR

REV. 0.5-EMTS, ZIF SKT

HETERO 1 OF 4

D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63

DP0
DP1
DP2
DP3

DSTBN0
DSTBN1
DSTBN2
DSTBN3

DSTBP0
DSTBP1
DSTBP2
DSTBP3

DBI0
DBI1
DBI2
DBI3
DBSY
DRDY

1 2

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9

R1522

51

PROCESSOR 1 & 2

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

Y26
AA27
Y24
AA25
AD27
Y23
AA24
AB26
AB25
AB23
AA22
AA21
AB20
AB22
AB19
AA19
AE26
AC26
AD25
AE25
AC24
AD24
AE23
AC23
AA18
AC20
AC21
AE22
AE20
AD21
AD19
AB17
AB16
AA16
AC17
AE13
AD18
AB15
AD13
AD14
AD11
AC12
AE10
AC11
AE9
AD10
AD8
AC9
AA13
AA14
AC14
AB12
AB13
AA11
AA10
AB10
AC8
AD7
AE7
AC6
AC5
AA8
Y9
AB6

AC18
AE19
AC15
AE17

Y21
Y18
Y15
Y12

Y20
Y17
Y14
Y11

AC27
AD22
AE12
AB9
F18
E18

H_DSTBN0_N
H_DSTBN1_N
H_DSTBN2_N
H_DSTBN3_N

H_DSTBP0_N
H_DSTBP1_N
H_DSTBP2_N
H_DSTBP3_N

H_DBI0_N
H_DBI1_N
H_DBI2_N
H_DBI3_N
H_DBSY_N
H_DRDY_N

H2_ODTEN

CA

ROOM=PROC_2

H_D0_N

11,17

H_D1_N

11,17

H_D2_N

11,17

H_D3_N

11,17

H_D4_N

11,17

H_D5_N

11,17

H_D6_N

11,17

H_D7_N

11,17

H_D8_N

11,17

H_D9_N

11,17

H_D10_N

11,17

H_D11_N

11,17

H_D12_N

11,17

H_D13_N

11,17

H_D14_N

11,17

H_D15_N

11,17

H_D16_N

11,17

H_D17_N

11,17

H_D18_N

11,17

H_D19_N

11,17

H_D20_N

11,17

H_D21_N

11,17

H_D22_N

11,17

H_D23_N

11,17

H_D24_N

11,17

H_D25_N

11,17

H_D26_N

11,17

H_D27_N

11,17

H_D28_N

11,17

H_D29_N

11,17

H_D30_N

11,17

H_D31_N

11,17

H_D32_N

11,17

H_D33_N

11,17

H_D34_N

11,17

H_D35_N

11,17

H_D36_N

11,17

H_D37_N

11,17

H_D38_N

11,17

H_D39_N

11,17

H_D40_N

11,17

H_D41_N

11,17

H_D42_N

11,17

H_D43_N

11,17

H_D44_N

11,17

H_D45_N

11,17

H_D46_N

11,17

H_D47_N

11,17

H_D48_N

11,17

H_D49_N

11,17

H_D50_N

11,17

H_D51_N

11,17

H_D52_N

11,17

H_D53_N

11,17

H_D54_N

11,17

H_D55_N

11,17

H_D56_N

11,17

H_D57_N

11,17

H_D58_N

11,17

H_D59_N

11,17

H_D60_N

11,17

H_D61_N

11,17

H_D62_N

11,17

H_D63_N

11,17

H_DP0_N

11,17

H_DP1_N

11,17

H_DP2_N

11,17

H_DP3_N

11,17

11,17
11,17
11,17
11,17

11,17
11,17
11,17
11,17

11,17
11,17
11,17
11,17
11,17
11,17

12

+CPU_VTT

+CPU_VTT

NP

R1570

1 2

39-5%

R1566

1 2

39-5%

R1569

1 2

39-5%

R1567

1 2

39-5%

R1568

1 2

39-5%

R1518

1 2

51

R1516

1 2

51

R1514

1 2

51

R1512

1 2

51

R1520

51

R1511

51

R1509

51

ECAD: Route trace from L128 to pin AB4

Route trace from L127 to pin AD4

ECAD: Route trace from L125 to pin AB4

Route trace from L126 to pin AD4

C1448

21

50V-5%
C1444

50V-5%

50V-5%

50V-5%

50V-5%

R1521

1 2

R1517

1 2

R1515

1 2

R1513

1 2

R1519

21

R1565

21

21

47pF

1 2

47pF

C1445

2 1

47pF

C1446

47pF

C1447

47pF

51

51

51

51

51

51

12

12

21

21

H_BINIT_N

H_BNR_N

H_HIT_N

H_HITM_N

H_MCERR_N

H2_BREQ23_N

H2_TESTHI0

H2_TESTHI1

H2_TESTHI2

H2_TESTHI3

H2_TESTHI4

H2_TESTHI5

H2_TESTHI6

H2_TESTHI7

H2_TESTHI8

H_FORCEPR_N

H2_BOOTSEL

H_TEST_BUS

11,17

11,17

11,17

11,17

11,15,17

11

12

12

12

12

12

12

12

12

12

5,12

12

12

x02_tj_091903

Dangling 750 ohm resistors are there to help fine-tune
VREF's using a variable powr supply during margin testing

+CPU_VTT

+CPU_VTT

CPU1 GTL VREF

+CPU_VTT

21

ECAD: Route <1.5" trace.
ECAD: Place 220pf caps under CPU

R1592

49.9-1%

NET_PHYSICAL_TYPE=50MIL

754mV

1 2

C1451

R370

1 2

84.5-1%

+CPU_VTT

21

ECAD: Route <1.5" trace.
ECAD: Place 220pf caps under CPU

R1593

49.9-1%

NET_PHYSICAL_TYPE=50MIL

754mV

21

1 2

C1454

R371

84.5-1%

+CPU_VTT

754mV

SUB*_87911

+CPU_VTT

754mV

SUB*_87911

CPU2 GTL VREF

21

ECAD: Route <1.5" trace.
ECAD: Place 220pf caps under CPU

R1594

49.9-1%49.9-1%

NET_PHYSICAL_TYPE=50MIL

R372

1 2

C1453

1 2

84.5-1%84.5-1%

56.2 1%

21

ECAD: Route <1.5" trace.
ECAD: Place 220pf caps under CPU

R1595

NET_PHYSICAL_TYPE=50MIL

21

1 2

C1452

R373

56.2 1%

X02_tj_091603

X03_tj_121503

L136

to pin AD4

L137

to pin AB4

L138

to pin AD4

L139

to pin AB4

1uF

10V-10%

1uF

10V-10%

10V-10%

1uF

10V-10%

21

21

R1824

1 2

0-5%

R1825 NET_PHYSICAL_TYPE=50MIL

1 2

0-5%

R1826

1 2

0-5%

R1827

1 2

0-5%

10uH 165MA

1 2

10uH 165MA

1 2

10uH 165MA

10uH 165MA

1uF

PROCESSORS 1 & 2

TITLE

LINDY PLANAR

DWG NO.

D1660

DATE

DC

1-23-2004_12:58

ROOM=PROC_1

V_VTT_H1_VCCA

cap between AB4 and AA5

1 2

C1492

V_VTT_H1_VSSA

22uF 6.3V22uF 6.3V

V_VTT_H2_VCCA

21

cap between AB4 and AA5

C1491

V_VTT_H2_VSSA

NET_PHYSICAL_TYPE=50MIL

21

220pF

C1581

50V-10%

NC_H1_GTLREF01

NET_PHYSICAL_TYPE=50MIL

21

220pF

C157921C1580

NC_H1_GTLREF23

NET_PHYSICAL_TYPE=50MIL

NET_PHYSICAL_TYPE=50MIL

21

220pF

C157821C1577

NC_H2_GTLREF01

NET_PHYSICAL_TYPE=50MIL

NET_PHYSICAL_TYPE=50MIL

21

220pF

C1583

NC_H2_GTLREF23

NET_PHYSICAL_TYPE=50MIL

12

12

12

12

H1_GTLREF01

21

220pF

C1582

50V-10%

750-1%

H1_GTLREF23

220pF

50V-10%

50V-10%

750-1%

H2_GTLREF01

220pF

50V-10%

50V-10%

H2_GTLREF23

21

220pF

C1584

50V-10%

50V-10%

750-1%

COMPUTER
CORPORATION

AUSTIN,TEXAS

REV.

SHEET

11 OF 611/13/2004

2 1

R323

NP01

R321

12

NP01

750-1%

R319

12

NP01

2 1

R320

NP01

X03

12

12

12

12

1

2

3

B D

CA

1-23-2004_12:58

1

PROC_1

A5

VSS_A5

A11

VSS_A11

A21

VSS_A21

A27

VSS_A27

A29

VSS_A29

A31

VSS_A31

B2

VSS_B2

B9

VSS_B9

B15

VSS_B15

B17

VSS_B17

B23

VSS_B23

B28

VSS_B28

B30

VSS_B30

C7

VSS_C7

C13

VSS_C13

C19

VSS_C19

C25

VSS_C25

C29

VSS_C29

C31

VSS_C31

D2

VSS_D2

D5

VSS_D5

D11

VSS_D11

D21

VSS_D21

D27

VSS_D27

D28

VSS_D28

D30

VSS_D30

E9

VSS_E9

E15

VSS_E15

E17

VSS_E17

E23

VSS_E23

E29

VSS_E29

E31

VSS_E31

2

3

SUB=SUB*_4M319

F2

VSS_F2

F7

VSS_F7

F13

VSS_F13

F19

VSS_F19

F25

VSS_F25

F28

VSS_F28

F30

VSS_F30

G1

VSS_G1

G3

VSS_G3

G5

VSS_G5

G9

VSS_G9

G25

VSS_G25

G27

VSS_G27

G29

VSS_G29

G31

VSS_G31

H2

VSS_H2

H4

VSS_H4

H6

VSS_H6

H8

VSS_H8

H24

VSS_H24

H26

VSS_H26

H28

VSS_H28

H30

VSS_H30

J1

VSS_J1

J3

VSS_J3

J5

VSS_J5

J7

VSS_J7

J9

VSS_J9

J23

VSS_J23

J25

VSS_J25

J27

VSS_J27

J29

VSS_J29

J31

VSS_J31

K2

VSS_K2

K4

VSS_K4

K6

VSS_K6

K8

VSS_K8

K24

VSS_K24

K26

VSS_K26

K28

VSS_K28

K30

VSS_K30

L1

VSS_L1

L3

VSS_L3

L5

VSS_L5

L7

VSS_L7

L9

VSS_L9

L23

VSS_L23

L25

VSS_L25

L27

VSS_L27

L29

VSS_L29

L31

VSS_L31

M2

VSS_M2

M4

VSS_M4

M6

VSS_M6

M8

VSS_M8

M24

VSS_M24

M26

VSS_M26

M28

VSS_M28

M30

VSS_M30

N2

VSS_N2

N4

VSS_N4

NOCONA 667MHz / 604 PROCESSOR

REV. 0.5-EMTS, ZIF SKT

HETERO 4 OF 4

VSS_N6

VSS_N8
VSS_N24
VSS_N26
VSS_N28
VSS_N30

VSS_P1

VSS_P3

VSS_P5

VSS_P7

VSS_P9
VSS_P23
VSS_P25
VSS_P27
VSS_P29
VSS_P31

VSS_R2

VSS_R4

VSS_R6

VSS_R8
VSS_R24
VSS_R26
VSS_R28
VSS_R30

VSS_T1

VSS_T3

VSS_T5

VSS_T7

VSS_T9
VSS_T23
VSS_T25
VSS_T27
VSS_T29
VSS_T31

VSS_U2

VSS_U4

VSS_U6

VSS_U8
VSS_U24
VSS_U26
VSS_U28
VSS_U30

VSS_V1

VSS_V3

VSS_V5

VSS_V7

VSS_V9
VSS_V23
VSS_V25
VSS_V27
VSS_V29
VSS_V31

VSS_W2

VSS_W4
VSS_W24
VSS_W26
VSS_W28
VSS_W30

VSS_Y1

VSS_Y5

VSS_Y7
VSS_Y13
VSS_Y19
VSS_Y25
VSS_Y31
VSS_AA2
VSS_AA9

VSS_AA15
VSS_AA17
VSS_AA23
VSS_AA30

VSS_AB1
VSS_AB5

VSS_AB11
VSS_AB21
VSS_AB27
VSS_AB31

VSS_AC2
VSS_AC7

VSS_AC13
VSS_AC19
VSS_AC25

VSS_AD3
VSS_AD9

VSS_AD15
VSS_AD17
VSS_AD23
VSS_AD31

VSS_AE2

VSS_AE11
VSS_AE21
VSS_AE27

N6
N8
N24
N26
N28
N30
P1
P3
P5
P7
P9
P23
P25
P27
P29
P31
R2
R4
R6
R8
R24
R26
R28
R30
T1
T3
T5
T7
T9
T23
T25
T27
T29
T31
U2
U4
U6
U8
U24
U26
U28
U30
V1
V3
V5
V7
V9
V23
V25
V27
V29
V31
W2
W4
W24
W26
W28
W30
Y1
Y5
Y7
Y13
Y19
Y25
Y31
AA2
AA9
AA15
AA17
AA23
AA30
AB1
AB5
AB11
AB21
AB27
AB31
AC2
AC7
AC13
AC19
AC25
AD3
AD9
AD15
AD17
AD23
AD31
AE2
AE11
AE21
AE27

SUB=SUB*_4M319

PROC_2

A5

VSS_A5

A11

VSS_A11

A21

VSS_A21

A27

VSS_A27

A29

VSS_A29

A31

VSS_A31

B2

VSS_B2

B9

VSS_B9

B15

VSS_B15

B17

VSS_B17

B23

VSS_B23

B28

VSS_B28

B30

VSS_B30

C7

VSS_C7

C13

VSS_C13

C19

VSS_C19

C25

VSS_C25

C29

VSS_C29

C31

VSS_C31

D2

VSS_D2

D5

VSS_D5

D11

VSS_D11

D21

VSS_D21

D27

VSS_D27

D28

VSS_D28

D30

VSS_D30

E9

VSS_E9

E15

VSS_E15

E17

VSS_E17

E23

VSS_E23

E29

VSS_E29

E31

VSS_E31

F2

VSS_F2

F7

VSS_F7

F13

VSS_F13

F19

VSS_F19

F25

VSS_F25

F28

VSS_F28

F30

VSS_F30

G1

VSS_G1

G3

VSS_G3

G5

VSS_G5

G9

VSS_G9

G25

VSS_G25

G27

VSS_G27

G29

VSS_G29

G31

VSS_G31

H2

VSS_H2

H4

VSS_H4

H6

VSS_H6

H8

VSS_H8

H24

VSS_H24

H26

VSS_H26

H28

VSS_H28

H30

VSS_H30

J1

VSS_J1

J3

VSS_J3

J5

VSS_J5

J7

VSS_J7

J9

VSS_J9

J23

VSS_J23

J25

VSS_J25

J27

VSS_J27

J29

VSS_J29

J31

VSS_J31

K2

VSS_K2

K4

VSS_K4

K6

VSS_K6

K8

VSS_K8

K24

VSS_K24

K26

VSS_K26

K28

VSS_K28

K30

VSS_K30

L1

VSS_L1

L3

VSS_L3

L5

VSS_L5

L7

VSS_L7

L9

VSS_L9

L23

VSS_L23

L25

VSS_L25

L27

VSS_L27

L29

VSS_L29

L31

VSS_L31

M2

VSS_M2

M4

VSS_M4

M6

VSS_M6

M8

VSS_M8

M24

VSS_M24

M26

VSS_M26

M28

VSS_M28

M30

VSS_M30

N2

VSS_N2

N4

VSS_N4

NOCONA 667MHz / 604 PROCESSOR

REV. 0.5-EMTS, ZIF SKT

HETERO 4 OF 4

VSS_N6

VSS_N8
VSS_N24
VSS_N26
VSS_N28
VSS_N30

VSS_P1

VSS_P3

VSS_P5

VSS_P7

VSS_P9
VSS_P23
VSS_P25
VSS_P27
VSS_P29
VSS_P31

VSS_R2

VSS_R4

VSS_R6

VSS_R8
VSS_R24
VSS_R26
VSS_R28
VSS_R30

VSS_T1

VSS_T3

VSS_T5

VSS_T7

VSS_T9
VSS_T23
VSS_T25
VSS_T27
VSS_T29
VSS_T31

VSS_U2

VSS_U4

VSS_U6

VSS_U8
VSS_U24
VSS_U26
VSS_U28
VSS_U30

VSS_V1

VSS_V3

VSS_V5

VSS_V7

VSS_V9
VSS_V23
VSS_V25
VSS_V27
VSS_V29
VSS_V31

VSS_W2

VSS_W4
VSS_W24
VSS_W26
VSS_W28
VSS_W30

VSS_Y1

VSS_Y5

VSS_Y7
VSS_Y13
VSS_Y19
VSS_Y25
VSS_Y31
VSS_AA2
VSS_AA9

VSS_AA15
VSS_AA17
VSS_AA23
VSS_AA30

VSS_AB1
VSS_AB5

VSS_AB11
VSS_AB21
VSS_AB27
VSS_AB31

VSS_AC2
VSS_AC7

VSS_AC13
VSS_AC19
VSS_AC25

VSS_AD3
VSS_AD9

VSS_AD15
VSS_AD17
VSS_AD23
VSS_AD31

VSS_AE2

VSS_AE11
VSS_AE21
VSS_AE27

N6
N8
N24
N26
N28
N30
P1
P3
P5
P7
P9
P23
P25
P27
P29
P31
R2
R4
R6
R8
R24
R26
R28
R30
T1
T3
T5
T7
T9
T23
T25
T27
T29
T31
U2
U4
U6
U8
U24
U26
U28
U30
V1
V3
V5
V7
V9
V23
V25
V27
V29
V31
W2
W4
W24
W26
W28
W30
Y1
Y5
Y7
Y13
Y19
Y25
Y31
AA2
AA9
AA15
AA17
AA23
AA30
AB1
AB5
AB11
AB21
AB27
AB31
AC2
AC7
AC13
AC19
AC25
AD3
AD9
AD15
AD17
AD23
AD31
AE2
AE11
AE21
AE27

5,46

5,11,12

12,15
12,15
12,15
12,15
12,15
12,15

12,15

12,15
12,15

H1_ODTEN

11

H1_SLEW_CTRL

12

H1_BOOTSEL

11

H1_OPTIMIZED

12

H1_CPU_PRES_N
H1_BSEL0

15

H1_BSEL1

15

H1_COMP0

12

H1_COMP1

12

H1_COMP2

12

H1_COMP3

12

H1_TESTHI0

11

H1_TESTHI1

11

H1_TESTHI2

11

H1_TESTHI3

11

H1_TESTHI4

11

H1_TESTHI5

11

H1_TESTHI6

11

H1_TESTHI7

11

H1_TESTHI8

11

H1_GTLREF01

11

H1_GTLREF23

11

H1_THRM_AN

45

H1_THRM_CA

45

NC_H1_PKG_ID

H1_PROCHOT_N

15

H_FORCEPR_N
H1_THERMTRIP_N

15

H_BPM0_N
H_BPM1_N
H_BPM2_N
H_BPM3_N
H_BPM4_N
H_BPM5_N

ITP_TCK
ITP_TDI_H1

15

ITP_TDO_H1

15

ITP_TMS
ITP_TRST_N

SUB=SUB*_4M319

+CPU_VTT

1 2

1 2

49.9-1%

+CPU_VTT

301-1%

AC30

AA3
AB3

AD16

E16

AC28

D25

AA7
AD5
AE5
A26
Y29

W23

F23

Y27
Y28
AE4

B25
A15
F26

E24
C24
E25
A25
F24

Place @ CPU1

R1531

21

51

R1526

51

R1527

1 2

51

R1528

21

51

R1529

21

51

R1530

51

R1600

1 2

100-1%

R1601

21

100-1%

R1596

1 2

49.9-1%

R1597

21

R60

21

H_VTT_PWRGOOD

B5

ODTEN
SLEW_CTRL

G7

BOOT_SELECT

C1

OPTIMIZED/COMPAT

A3

SKTOCC
BSEL0
BSEL1

COMP0
COMP1
COMP2
COMP3

W6

TESTHI0

W7

TESTHI1

W8

TESTHI2

Y6

TESTHI3
TESTHI4
TESTHI5
TESTHI6
TESTHI7
TESTHI8

GTLREF0

W9

GTLREF1
GTLREF2

F9 AA28

GTLREF3 NC_AA28

THERMDA
THERMDC
SMB_PRT

PROCHOT
FORCEPR
THRMTRIP

F6

BPM0

F8

BPM1

E7

BPM2

F5

BPM3

E8

BPM4

E4

BPM5

TCK
TDI
TDO
TMS
TRST

NOCONA 667MHz/ 604 PROCESSOR

REV. 0.5-EMTS, ZIF SKT

HETERO 2 OF 4

H_BPM0_N

H_BPM1_N

H_BPM2_N

H_BPM3_N

H_BPM4_N

H_BPM5_N

H1_COMP2

H1_COMP3

H1_COMP0

H1_COMP1

5,12

12,15

12,15

12,15

12,15

12,15

12,15

12

12

12

12

VCCIOPLL

VCCSENSE
VSSSENSE

RSVD_A16

RSVD_AC1
RSVD_AE15
RSVD_AE16
RSVD_AE28
RSVD_AE29

VIDPWRGD

VTT_AA12

VTT_AC10

VTT_AD12

12
12

VID0
VID1
VID2
VID3
VID4
VID5

VCCPLL

VCCA
VSSA

PWRGOOD

RSVD_W3
RSVD_Y3

NC_AA29
NC_AB28
NC_AB29
NC_AC29
NC_AD28
NC_AD29

VTTEN

VTT_A4
VTT_B4

VTT_B12

VTT_C5
VTT_C10
VTT_E12
VTT_F10
VTT_Y10

H1_SLEW_CTRL
H1_OPTIMIZED

F3
E3
D3
C3
B3
A1

AD1
AD4

AB4
AA5

B27
D26

AB7

A16
W3
Y3
AC1
AE15
AE16
AE28
AE29

AA29
AB28
AB29
AC29
AD28
AD29

E1
B1

A4
B4
B12
C5
C10
E12
F10
Y10
AA12
AC10
AD12

PROC_1

H1_VID0
H1_VID1
H1_VID2
H1_VID3
H1_VID4
H1_VID5

V_1P5_H1_VCCPLL

V_VTT_H1_VCCA
V_VTT_H1_VSSA

H1_VCCSENSE
H1_VSSSENSE

H_PWRGOOD

H_TEST_BUS
NC_H1_W3
NC_H1_Y3
NC_H1_AC1
NC_H1_AE15
NC_H1_AE16
NC_H1_AE28
NC_H1_AE29

NC_H1_AA28
NC_H1_AA29
NC_H1_AB28
NC_H1_AB29
NC_H1_AC29
NC_H1_AD28
NC_H1_AD29

H1_VTT_EN
H_VTT_PWRGOOD

+CPU_VTT

+CPU_VTT

NP

NP

21

21

51

R1524

R1523

NP21NP

21

0-5%

R1525

R1585

7
7
7
7
7
7

11

11
11

X00_GT_052203

X00_TJ_061803

7
7

X00_GT_052203

11,12,33

11,12

5
5,12

5151

11
12
11
12

5,46

15
15

12
12
12
12

11
11
11
11
11
11
11
11
11

11

11

45
45

15

5,11,12

15

12,15
12,15
12,15
12,15
12,15
12,15

12,15

15

15
12,15
12,15

+CPU_VTT

H2_ODTEN
H2_SLEW_CTRL
H2_BOOTSEL
H2_OPTIMIZED

H2_CPU_PRES_N
H2_BSEL0
H2_BSEL1

H2_COMP0
H2_COMP1
H2_COMP2
H2_COMP3

H2_TESTHI0
H2_TESTHI1
H2_TESTHI2
H2_TESTHI3
H2_TESTHI4
H2_TESTHI5
H2_TESTHI6
H2_TESTHI7
H2_TESTHI8

H2_GTLREF01

H2_GTLREF23

H2_THRM_AN
H2_THRM_CA
NC_H2_PKG_ID

H2_PROCHOT_N
H_FORCEPR_N
H2_THERMTRIP_N

H_BPM0_N
H_BPM1_N
H_BPM2_N
H_BPM3_N
H_BPM4_N
H_BPM5_N

ITP_TCK
ITP_TDI_H2
ITP_TDO_H2
ITP_TMS
ITP_TRST_N

SUB=SUB*_4M319

Place @ CPU2

R1603

100-1%

R1602

1 2

100-1%

R1598

49.9-1%

R1599

1 2

49.9-1%

B5

PROC_2

ODTEN

AC30

SLEW_CTRL

G7

BOOT_SELECT

C1

OPTIMIZED/COMPAT

A3

SKTOCC

AA3

BSEL0

AB3

BSEL1

AD16

COMP0

E16

COMP1

AC28

COMP2

D25

COMP3

W6

TESTHI0

W7

TESTHI1

W8

TESTHI2

Y6

TESTHI3

AA7

TESTHI4

AD5

TESTHI5

AE5

TESTHI6

A26

TESTHI7

Y29

TESTHI8

W23

GTLREF0

W9

GTLREF1

F23

GTLREF2
GTLREF3 NC_AA28

Y27

THERMDA

Y28

THERMDC

AE4

SMB_PRT

B25

PROCHOT

A15

FORCEPR

F26

THRMTRIP

F6

BPM0

F8

BPM1

E7

BPM2

F5

BPM3

E8

BPM4

E4

BPM5

E24

TCK

C24

TDI

E25

TDO

A25

TMS

F24

TRST

NOCONA 667MHz/ 604 PROCESSOR

REV. 0.5-EMTS, ZIF SKT

HETERO 2 OF 4

21

H2_COMP2

H2_COMP3

21

H2_COMP0

H2_COMP1

12

12

12

12

VID0
VID1
VID2
VID3
VID4
VID5

VCCPLL

VCCIOPLL

VCCA
VSSA

VCCSENSE
VSSSENSE

PWRGOOD

RSVD_A16

RSVD_W3
RSVD_Y3

RSVD_AC1
RSVD_AE15
RSVD_AE16
RSVD_AE28
RSVD_AE29

NC_AA29
NC_AB28
NC_AB29
NC_AC29
NC_AD28
NC_AD29

VTTEN

VIDPWRGD

VTT_A4
VTT_B4

VTT_B12

VTT_C5
VTT_C10
VTT_E12
VTT_F10
VTT_Y10

VTT_AA12
VTT_AC10
VTT_AD12

12
12

F3
E3
D3
C3
B3
A1

AD1
AD4

AB4
AA5

B27
D26

AB7

A16
W3
Y3
AC1
AE15
AE16
AE28
AE29

AA28F9
AA29
AB28
AB29
AC29
AD28
AD29

E1
B1

A4
B4
B12
C5
C10
E12
F10
Y10
AA12
AC10
AD12

H2_SLEW_CTRL
H2_OPTIMIZED

H2_VID0
H2_VID1
H2_VID2
H2_VID3
H2_VID4
H2_VID5

V_1P5_H2_VCCPLL

V_VTT_H2_VCCA
V_VTT_H2_VSSA

H2_VCCSENSE
H2_VSSSENSE

H_PWRGOOD

H_TEST_BUS
NC_H2_W3
NC_H2_Y3
NC_H2_AC1
NC_H2_AE15
NC_H2_AE16
NC_H2_AE28
NC_H2_AE29

NC_H2_AA28
NC_H2_AA29
NC_H2_AB28
NC_H2_AB29
NC_H2_AC29
NC_H2_AD28
NC_H2_AD29

H2_VTT_EN
H_VTT_PWRGOOD

+CPU_VTT

+CPU_VTT

NP

NP

51

R1540

1 2

NP

0-5%

R1586

1 2

8
8
8
8
8
8

11

11
11

X00_GT_052203

X00_TJ_061803

8
8

X00_GT_052203

11,12,33

11,12

5
5,12

R1539

1 2

51 51

R1538

1 2

1

2

3

4 4

COMPUTER
CORPORATION

AUSTIN,TEXAS

REV.

SHEET

X03

subsys done

A B

ECAD: place resistor near processor

PROCESSOR 1 & 2

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

TITLE

LINDY PLANAR

DWG NO.

D1660

DATE

1/13/2004 12 OF 61

DC

1

2

3

+CPU_VID1

SUB=SUB*_4M319

VCC_N1
VCC_N3
VCC_N5
VCC_N7

VCC_N9
VCC_N23
VCC_N25
VCC_N27
VCC_N29
VCC_N31

VCC_P2

VCC_P4

VCC_P6

VCC_P8
VCC_P24
VCC_P26
VCC_P28
VCC_P30

VCC_R1

VCC_R3

VCC_R5

VCC_R7

VCC_R9
VCC_R23
VCC_R25
VCC_R27
VCC_R29
VCC_R31

VCC_T2

VCC_T4

VCC_T6

VCC_T8
VCC_T24
VCC_T26
VCC_T28
VCC_T30

VCC_U1

VCC_U3

VCC_U5

VCC_U7

VCC_U9
VCC_U23
VCC_U25
VCC_U27
VCC_U29
VCC_U31

VCC_V2

VCC_V4

VCC_V6

VCC_V8
VCC_V24
VCC_V26
VCC_V28
VCC_V30

VCC_W1
VCC_W25
VCC_W27
VCC_W29
VCC_W31

VCC_Y2
VCC_Y16
VCC_Y22
VCC_Y30
VCC_AA1
VCC_AA4
VCC_AA6

VCC_AB2
VCC_AB8

VCC_AC3
VCC_AC4

VCC_AD2
VCC_AD6

VCC_AE3
VCC_AE8

+CPU_VID1

N1
N3
N5
N7
N9
N23
N25
N27
N29
N31
P2
P4
P6
P8
P24
P26
P28
P30
R1
R3
R5
R7
R9
R23
R25
R27
R29
R31
T2
T4
T6
T8
T24
T26
T28
T30
U1
U3
U5
U7
U9
U23
U25
U27
U29
U31
V2
V4
V6
V8
V24
V26
V28
V30
W1
W25
W27
W29
W31
Y2
Y16
Y22
Y30
AA1
AA4
AA6
AA20
AA26
AA31
AB2
AB8
AB14
AB18
AB24
AB30
AC3
AC4
AC16
AC22
AC31
AD2
AD6
AD20
AD26
AD30
AE3
AE8
AE14
AE18
AE24

PROC_1

A2

VCC_A2

A8

VCC_A8

A14

VCC_A14

A18

VCC_A18

A24

VCC_A24

A28

VCC_A28

A30

VCC_A30

B6

VCC_B6

B20

VCC_B20

B26

VCC_B26

B29

VCC_B29

B31

VCC_B31

C2

VCC_C2

C4

VCC_C4

C16

VCC_C16

C22

VCC_C22

C28

VCC_C28

C30

VCC_C30

D1

VCC_D1

D8

VCC_D8

D14

VCC_D14

D18

VCC_D18

D24

VCC_D24

D29

VCC_D29

D31

VCC_D31

E2

VCC_E2

E6

VCC_E6

E20

VCC_E20

E26

VCC_E26

E28

VCC_E28

E30

VCC_E30

F1

VCC_F1

F4

VCC_F4

F16

VCC_F16

F22

VCC_F22

F29

VCC_F29

F31

VCC_F31

G2

VCC_G2

G4

VCC_G4

G6

VCC_G6

G8

VCC_G8

G24

VCC_G24

G26

VCC_G26

G28

VCC_G28

G30

VCC_G30

H1

VCC_H1

H3

VCC_H3

H5

VCC_H5

H7

VCC_H7

H9

VCC_H9

H23

VCC_H23

H25

VCC_H25

H27

VCC_H27

H29

VCC_H29

H31

VCC_H31

J2

VCC_J2

J4

VCC_J4

J6

VCC_J6

J8

VCC_J8

J24

VCC_J24

J26

VCC_J26

J28

VCC_J28

J30

VCC_J30

K1

VCC_K1

K3

VCC_K3

K5

VCC_K5

K7

VCC_K7

K9

VCC_K9

K23

VCC_K23

K25

VCC_K25

K27

VCC_K27

K29

VCC_K29

K31

VCC_K31

L2

VCC_L2

L4

VCC_L4

L6

VCC_L6

L8

VCC_L8

L24

VCC_L24

L26

VCC_L26

L28

VCC_L28

L30

VCC_L30

M1

VCC_M1

M3

VCC_M3

M5

VCC_M5

M7

VCC_M7

M9

VCC_M9

M23

VCC_M23

M25

VCC_M25

M27

VCC_M27

M29

VCC_M29

M31

VCC_M31

NOCONA 667MHz / 604 PROCESSOR

REV. 0.5-EMTS, ZIF SKT

VCC_AA20
VCC_AA26
VCC_AA31

VCC_AB14
VCC_AB18
VCC_AB24
VCC_AB30

VCC_AC16
VCC_AC22
VCC_AC31

VCC_AD20
VCC_AD26
VCC_AD30

VCC_AE14
VCC_AE18
VCC_AE24

HETERO 3 OF 4

+CPU_VID2 +CPU_VID2

SUB=SUB*_4M319

PROC_2

A2

VCC_A2

A8

VCC_A8

A14

VCC_A14

A18

VCC_A18

A24

VCC_A24

A28

VCC_A28

A30

VCC_A30

B6

VCC_B6

B20

VCC_B20

B26

VCC_B26

B29

VCC_B29

B31

VCC_B31

C2

VCC_C2

C4

VCC_C4

C16

VCC_C16

C22

VCC_C22

C28

VCC_C28

C30

VCC_C30

D1

VCC_D1

D8

VCC_D8

D14

VCC_D14

D18

VCC_D18

D24

VCC_D24

D29

VCC_D29

D31

VCC_D31

E2

VCC_E2

E6

VCC_E6

E20

VCC_E20

E26

VCC_E26

E28

VCC_E28

E30

VCC_E30

F1

VCC_F1

F4

VCC_F4

F16

VCC_F16

F22

VCC_F22

F29

VCC_F29

F31

VCC_F31

G2

VCC_G2

G4

VCC_G4

G6

VCC_G6

G8

VCC_G8

G24

VCC_G24

G26

VCC_G26

G28

VCC_G28

G30

VCC_G30

H1

VCC_H1

H3

VCC_H3

H5

VCC_H5

H7

VCC_H7

H9

VCC_H9

H23

VCC_H23

H25

VCC_H25

H27

VCC_H27

H29

VCC_H29

H31

VCC_H31

J2

VCC_J2

J4

VCC_J4

J6

VCC_J6

J8

VCC_J8

J24

VCC_J24

J26

VCC_J26

J28

VCC_J28

J30

VCC_J30

K1

VCC_K1

K3

VCC_K3

K5

VCC_K5

K7

VCC_K7

K9

VCC_K9

K23

VCC_K23

K25

VCC_K25

K27

VCC_K27

K29

VCC_K29

K31

VCC_K31

L2

VCC_L2

L4

VCC_L4

L6

VCC_L6

L8

VCC_L8

L24

VCC_L24

L26

VCC_L26

L28

VCC_L28

L30

VCC_L30

M1

VCC_M1

M3

VCC_M3

M5

VCC_M5

M7

VCC_M7

M9

VCC_M9

M23

VCC_M23

M25

VCC_M25

M27

VCC_M27

M29

VCC_M29

M31

VCC_M31

NOCONA 667MHz / 604 PROCESSOR

REV. 0.5-EMTS, ZIF SKT

HETERO 3 OF 4

VCC_N1
VCC_N3
VCC_N5
VCC_N7

VCC_N9
VCC_N23
VCC_N25
VCC_N27
VCC_N29
VCC_N31

VCC_P2

VCC_P4

VCC_P6

VCC_P8
VCC_P24
VCC_P26
VCC_P28
VCC_P30

VCC_R1

VCC_R3

VCC_R5

VCC_R7

VCC_R9
VCC_R23
VCC_R25
VCC_R27
VCC_R29
VCC_R31

VCC_T2

VCC_T4

VCC_T6

VCC_T8
VCC_T24
VCC_T26
VCC_T28
VCC_T30

VCC_U1

VCC_U3

VCC_U5

VCC_U7

VCC_U9
VCC_U23
VCC_U25
VCC_U27
VCC_U29
VCC_U31

VCC_V2

VCC_V4

VCC_V6

VCC_V8
VCC_V24
VCC_V26
VCC_V28
VCC_V30

VCC_W1
VCC_W25
VCC_W27
VCC_W29
VCC_W31

VCC_Y2
VCC_Y16
VCC_Y22
VCC_Y30
VCC_AA1
VCC_AA4
VCC_AA6

VCC_AA20
VCC_AA26
VCC_AA31

VCC_AB2
VCC_AB8

VCC_AB14
VCC_AB18
VCC_AB24
VCC_AB30

VCC_AC3
VCC_AC4

VCC_AC16
VCC_AC22
VCC_AC31

VCC_AD2
VCC_AD6

VCC_AD20
VCC_AD26
VCC_AD30

VCC_AE3
VCC_AE8

VCC_AE14
VCC_AE18
VCC_AE24

X00_GT_052803

N1
N3
N5
N7
N9
N23
N25
N27
N29
N31
P2
P4
P6
P8
P24
P26
P28
P30
R1
R3
R5
R7
R9
R23
R25
R27
R29
R31
T2
T4
T6
T8
T24
T26
T28
T30
U1
U3
U5
U7
U9
U23
U25
U27
U29
U31
V2
V4
V6
V8
V24
V26
V28
V30
W1
W25
W27
W29
W31
Y2
Y16
Y22
Y30
AA1
AA4
AA6
AA20
AA26
AA31
AB2
AB8
AB14
AB18
AB24
AB30
AC3
AC4
AC16
AC22
AC31
AD2
AD6
AD20
AD26
AD30
AE3
AE8
AE14
AE18
AE24

B D

+CPU_VID1

CA

+CPU_VID1

ROOM=PROC_1

4.0V-20%

SUB*_K1098

SUB*_K1098

SUB*_K1098

SUB*_K1098

SUB*_K1098

12

+

C536

560uF

+CPU_VID2

C537

4V-20%

12

+

C538

560uF

4V-20%

12

12

+

+

C540

C539

560uF

560uF

4V-20%

4V-20%

SUB*_K1098

SUB*_K1098

SUB*_K1098

ROOM=PROC_2

SUB*_K1098

SUB*_K1098

SUB*_K1098

SUB*_K1098

12

12

C294

ECAD: Place 7 caps on each side of the each CPU

+CPU_VID1

+CPU_VID2

+CPU_VTT

+

C547

560uF

4V-20%

SUB*_D2341

10uF 6.3V

C1526

21

10uF 6.3V

C1546

1 2

10uF 6.3V

C1539

21

SUB*_D2341

10uF 6.3V

C1510

21

10uF 6.3V

C1540

21

10uF 6.3V

C1545

21

+

C548

560uF

4V-20%

SUB*_D2341

10uF 6.3V

C1520

21

ECAD: Place these 12 caps in CPU socket cavity

10uF 6.3V

C1547

1 2

ECAD: Place on back side of planar

10uF 6.3V

C1538

21

ECAD: Place on back side of planar

SUB*_D2341

10uF 6.3V

C1509

21

ECAD: Place these 12 caps in CPU socket cavity

10uF 6.3V

C1534

21

ECAD: Place on back side of planar

10uF 6.3V

C1516

21

ECAD: Place on back side of planar

12

+

560uF

4V-20%

SUB*_D2341

10uF 6.3V

21

10uF 6.3V

1 2

10uF 6.3V

21

10uF 6.3V

21

10uF 6.3V

10uF 6.3V

12

+

C542

560uF

10uF 6.3V

C1525

10uF 6.3V

C1548

10uF 6.3V

C1528

SUB*_D2341

10uF 6.3V

C1508

10uF 6.3V

C1535

21

10uF 6.3V

C1517

21

4V-20%

SUB*_D2341

C1521

21

C1549

1 2

C1529

21

SUB*_D2341

C1507

21

C1541

21

21

12

12

C543

10uF 6.3V

C1518

+

10uF 6.3V

10uF 6.3V

10uF 6.3V

SUB*_K1098

12

C545

560uF

4V-20%

SUB*_K1098

+

C549

560uF

4V-20%

SUB*_D2341

10uF 6.3V

C1522

21

C1519

21

C1506

21

SUB*_D2341

C1530

21

C1536

21

10uF 6.3V

C1515

1 2

SUB*_K1098

+

C546

560uF

4V-20%

SUB*_K1098

12

+

560uF

4V-20%

SUB*_D2341

10uF 6.3V

C1527

21

10uF 6.3V

C1544

21

10uF 6.3V

C1502

21

SUB*_D2341

10uF 6.3V

C1531

21

10uF 6.3V

C1537

21

10uF 6.3V

C1511

1 2

SUB*_K1098

12

+

560uF

4V-20%

SUB*_K1098

12

+

C544

560uF

SUB*_D2341

10uF 6.3V

21

10uF 6.3V

10uF 6.3V

21

SUB*_D2341

10uF 6.3V

21

10uF 6.3V

21

10uF 6.3V

C550

4V-20%

C1523

C1550

21

C1505

C1532

C1556

C1514

1 2

SUB*_K1098

12

+

560uF

SUB*_K1098

12

+

C541

560uF

SUB*_D2341

10uF 6.3V

21

10uF 6.3V

10uF 6.3V

21

10uF 6.3V

21

10uF 6.3V

21

10uF 6.3V

12

C551

4V-20%

12

C552

4V-20%

10uF 6.3V

C1524

10uF 6.3V

C1551

21

10uF 6.3V

C1542

SUB*_D2341

10uF 6.3V

C1533

10uF 6.3V

C1557

10uF 6.3V

C1512

1 2

X00_GT_052203

SUB*_K1098

+

SUB*_K1098

+

21

12

+

C290

560uF

4V-20%

SUB*_K1098

12

+

C553

560uF

560uF

4V-20%

SUB*_D2341

SUB*_D2341

10uF 6.3V

C732

21

21

10uF 6.3V

C1552

21

X00_GT_052203

10uF 6.3V

C150421C1503

21

SUB*_D2341

SUB*_D2341

10uF 6.3V

C737

21

21

10uF 6.3V

C1558

21

10uF 6.3V

C1513

1 2

SUB*_K1098

12

C292

560uF

4V-20%

SUB*_K1098

12

+

C297

4V-20%

10uF 6.3V

C733

10uF 6.3V

C1553

21

10uF 6.3V

10uF 6.3V

C738

10uF 6.3V

C1559

21

10uF 6.3V

C1543

1 2

12

+

C291

560uF

4V-20%

SUB*_K1098

12

+

C296

560uF

560uF

4V-20%

SUB*_D2341

10uF 6.3V

C734

21

10uF 6.3V

C1554

21

10uF 6.3V

C50021C499

21

SUB*_D2341

SUB*_D2341

10uF 6.3V

C739

21

10uF 6.3V

C1560

21

10uF 6.3V

C511

21

+

C289

560uF

4V-20%

12

C295

4V-20%

SUB*_D2341

C735

21

10uF 6.3V

C1555

21

10uF 6.3V

C736

21

10uF 6.3V

C1561

C507

21

12

+

560uF

4V-20%

SUB*_K1098

+

C298

560uF

4V-20%

C1656

21

C497

21

C1657

21

10uF 6.3V

C508

21

12

+

C293

560uF

SUB*_K1098

12

+

560uF

4V-20%

10uF 6.3V

C498

21

10uF 6.3V

C509

21

4V-20%

10uF 6.3V

21

10uF 6.3V

C496

1 2

C506

10uF 6.3V

C492

21

10uF 6.3V

C502

1 2

10uF 6.3V

C495

21

10uF 6.3V

C505

1 2

10uF 6.3V

C501

21

10uF 6.3V

C503

1 2

10uF 6.3V

C49421C493

21

10uF 6.3V

C504

1 2

+CPU_VID2

4.0V-20%

10uF 6.3V

10uF 6.3V

1 2

330uF

+

330uF

+

C510

1-23-2004_12:58

x00_tj_041003

4.0V-20%
330uF

1 2

C413

+

4.0V-20%
330uF

1 2

C414

21

C415

+

1

4.0V-20%
330uF

C428

21

+

4.0V-20%
330uF

1 2

C516

C517

+

21

2

3

21

4 4

subsys done

A B

1 2

C1496

22uF 6.3V

SUB*_C5127

21

C1495

x03b_tj_011903

1 2

C1494

22uF 6.3V

22uF 6.3V

C1493

21

C286

22uF 6.3V

1 2

C1450

22uF 6.3V

1 2

C1449

1uF 6.3V

21

1 2

C1391

1uF 6.3V

C1374

0.1uF 16V

21

C1785

0.1uF 16V

0.1uF 16V

X00_GT_062003

PROCESSOR 1 & 2

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

TITLE

LINDY PLANAR

DWG NO.

D1660

DATE

DC

COMPUTER
CORPORATION

AUSTIN,TEXAS

REV.

SHEET

13 OF 611/13/2004

X03

B D

CA

1-23-2004_12:58

1

2

1

2

3

4 4

COMPUTER
CORPORATION

AUSTIN,TEXAS

REV.

SHEET

X03

A B

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

TITLE

LINDY PLANAR

DWG NO.

D1660

DATE

1/13/2004 14 OF 61

DC

3

ROOM=ITP

B D

CA

1-23-2004_12:58

ROOMS COMPLETE

+CPU_VTT

x00_GT_010704

1

H_RST_N

11,17

x02_tj_081803

C76

R80

1 2

0-5%

1 2

0.1uF 16V

12
12
12
12
12
12

1uF

C304

1 2

10V-10%

H_BPM0_N
H_BPM1_N
H_BPM2_N
H_BPM3_N
H_BPM4_N
H_BPM5_N
H_RST_ITP_N

R1913

1 2

100-5%

2

21

R568

40.2-0.5%

CK_167M_ITP_P

3

CK_167M_ITP_N

3

x00_tj_051203

R219

R550

1 2

40.2-0.5%

21

R220

40.2-0.5%

21

R221

1 2

40.2-0.5%

SUB=NP01

x00_tj_060403

ITP PORT

R222

1 2

40.2-0.5%

40.2-0.5%

ITP_CONN

1

2
3 4
5 6
7 8

10

9

11 12
13 14
15 16
17 18

(FBO)

19

20

21 22
23
25

K

2MM SMT

KEY 26

ITP_JPR

SUB=NP01

24

26

+CPU_VTT

1
2
3

(BPM5DR#)

21

R218

40.2-0.5%

ITP_PWR

21

R125

R160

680-5%

1 2

x00_tj_051203

R126

150-5%

1 2

ITP_TDI_H2
ITP_TDO_H1
ITP_TDO_H2

x00_tj_060403

R367

27.4-1%

1 2

R4

1 2

1.5K-5%

12
12
12,15

x00_tj_051203

+3.3V_AUX

75-1%

R1756

1 2

+CPU_VTT

21

150-5%

R6001

NC_ITP_26_KEY

x00_tj_091603

150-5%

NC_ITP_DBA_N

ITP_DBR_N

ITP_TDI_H1

ITP_TMS

ITP_TRST_N

ITP_TCK

NC_ITP_FBI

ITP_TDO_H2

12
12
12
12

12,15

FOR JTDO:

Install 1-2 for TWO processor system
Install 2-3 for UNI processor system

(UNI-PROCESSOR IS WITH PROC_1 INSTALLED ONLY!)

PROC_1 PROC_2

5

TDO

ITP_TDO_H1

ITP_TDI_H2

JTDO
1

2
3

TDITDI

TDO

ITP_TD0_H2

ITP ROUTING DRAWING

1

2

ITP_TDI_H1

R554

2.7K-5%

51

R555

1 2

2.7K-5%

x02_tj_092203

+3.3V_AUX

21

R374

Q28

3

3904

1

21

2

x02_tj_092203

+3.3V_AUX

R375

1 2

Q29

3904

1

ROOM=PROC_1

1K-1%
H1_THERMTRIP_3V

1K-1%
H2_THERMTRIP_3V

3

2

5,46

H1_PROCHOT_N

12

ROOM=PROC_2

5,46

H2_PROCHOT_N

12

+CPU_VTT

21

51

R277

H1_THERMTRIP_N

12

3

ECAD: the components within each circuit need to stay clumped

+CPU_VTT

R292

1 2

H2_THERMTRIP_N

12

+CPU_VTT

R308

1 2

+CPU_VTT

51

21

1 2

2.7K-5%

51

R556

2.7K-5%

R1510

R557

3904

21

Q31

3904

Q30

1

1

+3.3V

21

R376

1K-1%

H1_PROCHOT_3V

3

2

+3.3V

R377

1K-1%

1 2

H2_PROCHOT_3V

3

2

+CPU_VTT

R266

51

5

H1_IERR_N

11

5

H2_IERR_N

11

21

+CPU_VTT

R312

1 2

R419

2.7K-5%

51

R420

2.7K-5%

21

3904

21

Q69

3904

Q68

1

1

+3.3V

21

R415

+3.3V

21

R416

3

2

1K-1%

H1_IERR_3V

3

2

1K-1%

H2_IERR_3V

11,17

5,46

NP*

R423

H_MCERR_N

1 2

2.7K-5%

ROOM=PROC_2

5,46

NP*

3904

Q71

+3.3V

NP*

R417

1K-1%

1 2

NC_H_MCERR_3V

3

1

x03b_sd

2

12

12

R586

H1_BSEL0

R588

H2_BSEL0

ROOM = PROC_1

21

R595

1 2

511-1%

R603

2.7K-5%

21

1K-1%
H1_BSEL0_3V_N

Q61

3

3904 3904

1

2

5

12

H1_BSEL1

ROOM = PROC_2

21

R597

Q102

1

1K-1%

H2_BSEL0_3V_N

3

2

5

12

H2_BSEL1

1 2

511-1%

R605

2.7K-5%

21

+CPU_VTT +3.3V+CPU_VTT +3.3V

21

R585

1 2

511-1%

R602

2.7K-5%

R594

1K-1%
H1_BSEL1_3V_N

Q53

3

1

21

2

5

3

+CPU_VTT +3.3V+CPU_VTT +3.3V

21

R587

1 2

511-1%

R604

2.7K-5%

R596

1K-1%
H2_BSEL1_3V_N

Q64

3

39043904

1

21

2

5

INVERTING LEVEL TRANSLATION

4 4

COMPUTER
CORPORATION

AUSTIN,TEXAS

REV.

SHEET

15 OF 611/13/2004

X03

subsys done

A B

ITP & GTL LEVEL TRANSLATION

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

TITLE

LINDY PLANAR

DWG NO.

D1660

DATE

DC

B D

+1.8V

ROOM = DDR_TERM

8

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

RN59

71.5
1%

RN58

71.5
1%

RN57

71.5
1%

RN56

71.5
1%

RN55

71.5
1%

RN54

71.5
1%

RN53

71.5
1%

RN52

71.5
1%

RN51

71.5
1%

RN44

71.5
1%

RN45

71.5
1%

RN46

71.5
1%

RN47

71.5
1%

RN50

71.5
1%

RN49

71.5
1%

RN48

71.5
1%

R397

100-1%

R399

100-1%

R401

100-1%

R403

100-1%

R405

100-1%

R409

100-1%

R411

100-1%

R413

100-1%

7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

21

1 2

21

1 2

21

1 2

21

1 2

21

1 2

21

1 2

21

NP*

1 2

21

NP*

1 2

R398

100-1%

R400

100-1%

R402

100-1%

R404

100-1%

R408

100-1%

R410

100-1%

R412

100-1%

R414

100-1%

DDR2A_CAS_N
DDR2A_CAS_N
DDR2A_CS0_N
DDR2A_CS0_N

DDR2A_WE_N

DDR2A_WE_N
DDR2A_RAS_N
DDR2A_RAS_N

DDR2A_CS3_N
DDR2A_CS3_N
DDR2A_CS2_N
DDR2A_CS2_N

DDR2A_CS7_N
DDR2A_CS7_N

DDR2A_CS6_N
DDR2A_CS6_N

DDR2A_CS1_N
DDR2A_CS1_N

DDR2A_CS5_N
DDR2A_CS5_N
DDR2A_CS4_N
DDR2A_CS4_N

CK_200M_DIMMA3_P

CK_200M_DIMMA3_P

CK_200M_DIMMA3_N

CK_200M_DIMMA3_N

CK_200M_DIMMA1_P

CK_200M_DIMMA1_P

CK_200M_DIMMA1_N

CK_200M_DIMMA1_N

CK_200M_DIMMA2_P

CK_200M_DIMMA2_P

CK_200M_DIMMA2_N

CK_200M_DIMMA2_N

CK_200M_DIMMA0_P

CK_200M_DIMMA0_P

NP*

CK_200M_DIMMA0_N

CK_200M_DIMMA0_N

NP*

DDR2A_A10
DDR2A_A10

DDR2A_A0
DDR2A_A0

DDR2A_A2
DDR2A_A2
DDR2A_A1
DDR2A_A1

DDR2A_A6
DDR2A_A6
DDR2A_A5
DDR2A_A5

DDR2A_A8
DDR2A_A8
DDR2A_A7
DDR2A_A7

DDR2A_A3
DDR2A_A3
DDR2A_A4
DDR2A_A4

DDR2A_A9

DDR2A_A9
DDR2A_A11
DDR2A_A11

DDR2A_A12
DDR2A_A12
DDR2A_BA2
DDR2A_BA2

DDR2A_BA0
DDR2A_BA0
DDR2A_BA1
DDR2A_BA1

DDR2A_A13
DDR2A_A13

DDR2_CKE1
DDR2_CKE1
DDR2_CKE7
DDR2_CKE7

DDR2_CKE5
DDR2_CKE5
DDR2_CKE3
DDR2_CKE3

16,20
16,20
16,20
16,20

16,20
16,20
16,20
16,20

16,20
16,20
16,20
16,20

16,20
16,20
16,20
16,20

16,20
16,20
16,20
16,20

16,20
16,20
16,20
16,20

16,20
16,20
16,20
16,20

16,20
16,20
16,20
16,20

16,20
16,20
16,20
16,20

16,20
16,20
16,20
16,20

16,20
16,20
16,20
16,20

16,20
16,20

16,20
16,20

16,20
16,20

16,20
16,20

16,20
16,20
16,20
16,20

16,21
16,21
16,21
16,21

16,21
16,21
16,21
16,21

16,20

16,20

16,20

16,20

16,20

16,20

16,20

16,20

16,20

16,20

16,20

16,20

16

16

16

16

DDR2B_A10
DDR2B_A10

DDR2B_A11
DDR2B_A11

DDR2B_BA2
DDR2B_BA2
DDR2B_A12
DDR2B_A12

DDR2B_BA1
DDR2B_BA1
DDR2B_BA0
DDR2B_BA0

DDR2B_CS0_N
DDR2B_CS0_N

DDR2B_CAS_N
DDR2B_CAS_N

DDR2B_RAS_N
DDR2B_RAS_N

DDR2B_A13
DDR2B_A13

DDR2B_CS3_N
DDR2B_CS3_N
DDR2B_CS2_N
DDR2B_CS2_N

DDR2B_CS7_N
DDR2B_CS7_N

DDR2B_WE_N
DDR2B_WE_N

DDR2B_CS1_N
DDR2B_CS1_N
DDR2B_CS6_N
DDR2B_CS6_N

DDR2B_CS5_N
DDR2B_CS5_N
DDR2B_CS4_N
DDR2B_CS4_N

DDR2_CKE4
DDR2_CKE4
DDR2_CKE2
DDR2_CKE2

DDR2_CKE6
DDR2_CKE6
DDR2_CKE0
DDR2_CKE0

CK_200M_DIMMB3_P

21

CK_200M_DIMMB3_P

CK_200M_DIMMB3_N

21

CK_200M_DIMMB3_N

CK_200M_DIMMB1_P

21

CK_200M_DIMMB1_P

CK_200M_DIMMB1_N

21

CK_200M_DIMMB1_N

CK_200M_DIMMB2_P

21

CK_200M_DIMMB2_P

CK_200M_DIMMB2_N

21

CK_200M_DIMMB2_N

CK_200M_DIMMB0_P

21

CK_200M_DIMMB0_P

NP*

CK_200M_DIMMB0_N

21

CK_200M_DIMMB0_N

NP*

DDR2B_A0
DDR2B_A0

DDR2B_A1
DDR2B_A1
DDR2B_A2
DDR2B_A2

DDR2B_A5
DDR2B_A5
DDR2B_A6
DDR2B_A6

DDR2B_A7
DDR2B_A7
DDR2B_A8
DDR2B_A8

DDR2B_A4
DDR2B_A4
DDR2B_A3
DDR2B_A3

DDR2B_A9
DDR2B_A9

x00_tj_061903

16,21
16,21
16,21
16,21

16,21
16,21
16,21
16,21

16,21
16,21
16,21
16,21

16,21
16,21
16,21
16,21

16,21
16,21
16,21
16,21

16,21
16,21
16,21
16,21

16,21
16,21
16,21
16,21

16,21
16,21
16,21
16,21

16,21
16,21

16,21
16,21

16,21
16,21
16,21
16,21

16,21
16,21
16,21
16,21

16,21
16,21

16,21
16,21

16,21
16,21
16,21
16,21

16,21
16,21
16,21
16,21

16,20
16,20
16,20
16,20

16,20
16,20
16,20
16,20

x00_tj_051203

16,21

16,21

16,21

16,21

16,21

16,21

16,21

16,21

16,21

16,21

16,21

16,21

16

16

16

16

1

8

RN28

2

7

3

6

71.5

4

5

1

2

x00_tj_051203

x00_tj_051203

3

4 4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1 2

100-1%

1 2

100-1%

1 2

100-1%

1 2

100-1%

1 2

100-1%

1 2

100-1%

1 2

100-1%

1 2

100-1%

1%

RN29

71.5
1%

RN30

71.5
1%

RN31

71.5
1%

RN32

71.5
1%

RN33

71.5
1%

RN36

71.5
1%

RN34

71.5
1%

RN35

71.5
1%

RN39

71.5
1%

RN37

71.5
1%

RN38

71.5
1%

RN43

71.5
1%

RN42

71.5
1%

RN41

71.5
1%

RN40

71.5
1%

R380

R382

R385

R387

R389

R391

R393

R395

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

100-1%

100-1%

100-1%

100-1%

100-1%

100-1%

NP*

100-1%

NP*

100-1%

R381

R383

R386

R388

R390

R392

R394

R396

19

C360

21

.1uF

C358

10V-10%

.1uF

10V-10%

.1uF

10V-10%

.1uF

10V-10%

.1uF

10V-10%

.1uF

10V-10%

.1uF

10V-10%

.1uF

10V-10%

.1uF

10V-10%

.1uF

10V-10%

.1uF

10V-10%

.1uF

10V-10%

.1uF

10V-10%

.1uF

10V-10%

1 2
.1uF

10V-10%

1 2
.1uF

10V-10%

1 2
.1uF

10V-10%

1 2
.1uF

10V-10%

1 2
.1uF

10V-10%

.1uF

10V-10%

C359

C364

C357

C355

C353

C418

C313

C351

C341

C339

C322

C325

C316

C369

C371

C373

C375

C374

C366

21

21

21

21

21

21

21

21

21

21

21

21

21

21

.1uF

10V-10%

C361

.1uF

10V-10%

C362

.1uF

10V-10%

C356

.1uF

10V-10%

C354

.1uF

10V-10%

C352

.1uF

10V-10%

C419

.1uF

10V-10%

C312

.1uF

10V-10%

C342

.1uF

10V-10%

C340

.1uF

10V-10%

C321

.1uF

10V-10%

C363

.1uF

10V-10%

C323

.1uF

10V-10%

C315

.1uF

10V-10%

C370

1 2

.1uF

10V-10%

C372

1 2

.1uF

10V-10%

C314

1 2

.1uF

10V-10%

C368

1 2

.1uF

10V-10%

C365

1 2

.1uF

10V-10%

C367

1 2

.1uF

10V-10%

21

x00_tj_060503

C73

21

1 2

10uF 6.3V

21

C79

21

21

10uF 6.3V

21

21

21

21

21

21

21

21

21

21

CAD Notes:

1) Place one cap near every 2 signals

2) Place 10uF caps at each end of row

DDR2B_DQS0_P

21

DDR2B_DQS0_N

21

DDR2B_DQS1_P

21

DDR2B_DQS1_N

21

DDR2B_DQS2_P

21

DDR2B_DQS2_N

21

DDR2B_DQS3_P

21

DDR2B_DQS3_N

21

DDR2B_DQS4_P

21

DDR2B_DQS4_N

21

DDR2B_DQS5_P

21

DDR2B_DQS5_N

21

DDR2B_DQS6_P

21

DDR2B_DQS6_N

21

DDR2B_DQS7_P

21

DDR2B_DQS7_N

21 DDR2B_SD1_7

DDR2B_DQS8_P

21

DDR2B_DQS8_N

21

DDR2B_DQS9_P

21

DDR2B_DQS9_N

21

DDR2B_DQS10_P

21

DDR2B_DQS10_N

21

DDR2B_DQS11_P

21

DDR2B_DQS11_N

21

DDR2B_DQS12_P

21

DDR2B_DQS12_N

21

DDR2B_DQS13_P

21

DDR2B_DQS13_N

21

DDR2B_DQS14_P

21

DDR2B_DQS14_N

21

DDR2B_DQS15_P

21

DDR2B_DQS15_N

21

DDR2B_DQS16_P

21

DDR2B_DQS16_N

21

DDR2B_DQS17_P

21

DDR2B_DQS17_N

21

DDR2B_A0

16,21

DDR2B_A1

16,21

DDR2B_A2

16,21

DDR2B_A3

16,21

DDR2B_A4

16,21

DDR2B_A5

16,21

DDR2B_A6

16,21

DDR2B_A7

16,21

DDR2B_A8

16,21

DDR2B_A9

16,21

DDR2B_A10

16,21

DDR2B_A11

16,21

DDR2B_A12

16,21

DDR2B_A13

16,21

DDR2B_BA0

16,21

DDR2B_BA1

16,21

DDR2B_BA2

16,21

DDR2B_WE_N

16,21

DDR2B_CAS_N

16,21

DDR2B_RAS_N

16,21

DDR2_CKE4

16,20

DDR2_CKE5

16,21

DDR2_CKE6

16,20

DDR2_CKE7

16,21

DDR2B_CS0_N

16,21

DDR2B_CS1_N

16,21

DDR2B_CS2_N

16,21

DDR2B_CS3_N

16,21

DDR2B_CS4_N

16,21

DDR2B_CS5_N

16,21

DDR2B_CS6_N

16,21

DDR2B_CS7_N

16,21

16
16

23

CK_200M_DIMMB1_P
CK_200M_DIMMB1_N
CK_200M_DIMMB2_P
CK_200M_DIMMB2_N
CK_200M_DIMMB3_P
CK_200M_DIMMB3_N
CK_200M_DIMMB0_P
CK_200M_DIMMB0_N

DDR2B_MCH_VREF

16,21
16,21
16,21
16,21
16,21
16,21

1U Heatsink assembly

AM28

B_DQS0_P

AN29

B_DQS0_N

AM22

B_DQS1_P

AN23

B_DQS1_N

AK17

B_DQS2_P

AL17

B_DQS2_N

AK11

B_DQS3_P

AL11

B_DQS3_N

AG2

B_DQS4_P

AH2

B_DQS4_N

AA3

B_DQS5_P

AB4

B_DQS5_N

P1

B_DQS6_P

R2

B_DQS6_N

H3

B_DQS7_P

H1

B_DQS7_N

AK5

B_DQS8_P

AK6

B_DQS8_N

AK29

B_DQS9_P

AL29

B_DQS9_N

AK23

B_DQS10_P

AL23

B_DQS10_N

AN18

B_DQS11_P

AN17

B_DQS11_N

AN12

B_DQS12_P

AN11

B_DQS12_N

AJ1

B_DQS13_P

AH1

B_DQS13_N

AB2

B_DQS14_P

AB1

B_DQS14_N

T2

B_DQS15_P

R3

B_DQS15_N

J3

B_DQS16_P

J2

B_DQS16_N

AM6

B_DQS17_P

AN6

B_DQS17_N

AF7

B_MA0

AE14

B_MA1

AN14

B_MA2

AK14

B_MA3

AD15

B_MA4

AH16

B_MA5

AG17

B_MA6

AD18

B_MA7

AL20

B_MA8

AJ21

B_MA9

AC4

B_MA10

AH22

B_MA11

AH23

B_MA12

U4

B_MA13

AA8

B_BA0

AE7

B_BA1

AM25

B_BA2

W4

B_WE

W1

B_CAS

Y9

B_RAS

AH26

CKE4

AJ27

CKE5

AJ28

CKE6

AH28

CKE7

V9

B_CS0

V2

B_CS1

T7

B_CS2

P6

B_CS3

N4

B_CS4

M2

B_CS5

M6

B_CS6

L3

B_CS7

AH7

B_CMDCLK0_P

AJ6

B_CMDCLK0_N

AH6

B_CMDCLK1_P

AG6

B_CMDCLK1_N

AG8

B_CMDCLK2_P

AE8

B_CMDCLK2_N

AK9

B_CMDCLK3_P

AL8

B_CMDCLK3_N

AN4

B_VREF

INTEL LINDENHURST MCH V0P21

SUB=SUB*_K4832

HETERO 3 OF 7

x02_tj_041003
x03_tj_121503
x03b_tj_012004

2U/5U Heatsink assembly

CA

MCH

DDR2B_SD0_0

AM30

B_DQ0
B_DQ1
B_DQ2
B_DQ3
B_DQ4
B_DQ5
B_DQ6
B_DQ7

B_DQ8

B_DQ9
B_DQ10
B_DQ11
B_DQ12
B_DQ13
B_DQ14
B_DQ15

B_DQ16
B_DQ17
B_DQ18
B_DQ19
B_DQ20
B_DQ21
B_DQ22
B_DQ23

B_DQ24
B_DQ25
B_DQ26
B_DQ27
B_DQ28
B_DQ29
B_DQ30
B_DQ31

B_DQ32
B_DQ33
B_DQ34
B_DQ35
B_DQ36
B_DQ37
B_DQ38
B_DQ39

B_DQ40
B_DQ41
B_DQ42
B_DQ43
B_DQ44
B_DQ45
B_DQ46
B_DQ47

B_DQ48
B_DQ49
B_DQ50
B_DQ51
B_DQ52
B_DQ53
B_DQ54
B_DQ55

B_DQ56
B_DQ57
B_DQ58
B_DQ59
B_DQ60
B_DQ61
B_DQ62
B_DQ63

B_CB0

B_CB1

B_CB2

B_CB3

B_CB4

B_CB5

B_CB6

B_CB7

ADD=ADD02_W1549_MCHHTSNK1

ADD1=ADD13_X1306_MCHHTSNK2

AN30
AN27
AM27
AK30
AM31
AL28
AK27

AM24
AN24
AN21
AM21
AL25
AK24
AL22
AK21

AK18
AM18
AN15
AM15
AL19
AM19
AM16
AL16

AK12
AM12
AN9
AM9
AL13
AM13
AM10
AL10

AJ3
AJ4
AF1
AF4
AK3
AK2
AG3
AF3

AC3
AC1
Y3
Y4
AD2
AD3
AA2
Y1

T4
T1
N1
N2
U3
U1
P3
P4

K2
K1
F2
E1
L1
K4
G1
G2

AM7
AL7
AM4
AL4
AN8
AK8
AN5
AL5

x00_tj_041003

DDR2B_SD0_1
DDR2B_SD0_2
DDR2B_SD0_3
DDR2B_SD0_4
DDR2B_SD0_5
DDR2B_SD0_6
DDR2B_SD0_7

DDR2B_SD1_0
DDR2B_SD1_1
DDR2B_SD1_2
DDR2B_SD1_3
DDR2B_SD1_4
DDR2B_SD1_5
DDR2B_SD1_6

DDR2B_SD2_0
DDR2B_SD2_1
DDR2B_SD2_2
DDR2B_SD2_3
DDR2B_SD2_4
DDR2B_SD2_5
DDR2B_SD2_6
DDR2B_SD2_7

DDR2B_SD3_0
DDR2B_SD3_1
DDR2B_SD3_2
DDR2B_SD3_3
DDR2B_SD3_4
DDR2B_SD3_5
DDR2B_SD3_6
DDR2B_SD3_7

DDR2B_SD4_0
DDR2B_SD4_1
DDR2B_SD4_2
DDR2B_SD4_3
DDR2B_SD4_4
DDR2B_SD4_5
DDR2B_SD4_6
DDR2B_SD4_7

DDR2B_SD5_0
DDR2B_SD5_1
DDR2B_SD5_2
DDR2B_SD5_3
DDR2B_SD5_4
DDR2B_SD5_5
DDR2B_SD5_6
DDR2B_SD5_7

DDR2B_SD6_0
DDR2B_SD6_1
DDR2B_SD6_2
DDR2B_SD6_3
DDR2B_SD6_4
DDR2B_SD6_5
DDR2B_SD6_6
DDR2B_SD6_7

DDR2B_SD7_0
DDR2B_SD7_1
DDR2B_SD7_2
DDR2B_SD7_3
DDR2B_SD7_4
DDR2B_SD7_5
DDR2B_SD7_6
DDR2B_SD7_7

DDR2B_CB0
DDR2B_CB1
DDR2B_CB2
DDR2B_CB3
DDR2B_CB4
DDR2B_CB5
DDR2B_CB6
DDR2B_CB7

ROOM = MCH

21
21
21
21
21
21
21
21

21
21
21
21
21
21
21
21

21
21
21
21
21
21
21
21

21
21
21
21
21
21
21
21

21
21
21
21
21
21
21
21

21
21
21
21
21
21
21
21

21
21
21
21
21
21
21
21

21
21
21
21
21
21
21
21

21
21
21
21
21
21
21
21

16,20
16,20
16,20
16,20
16,20
16,20

16,20
16,20
16,20
16,20
16,20
16,20
16,20
16,20
16,20
16,20
16,20
16,20
16,20
16,20

16,20
16,20
16,20

16,20
16,20
16,20

16,20
16,21
16,20
16,21

16,20
16,20
16,20
16,20
16,20
16,20
16,20
16,20

16
16

23

DDR2A_DQS0_P

20

DDR2A_DQS0_N

20

DDR2A_DQS1_P

20

DDR2A_DQS1_N

20

DDR2A_DQS2_P

20

DDR2A_DQS2_N

20

DDR2A_DQS3_P

20

DDR2A_DQS3_N

20

DDR2A_DQS4_P

20

DDR2A_DQS4_N

20

DDR2A_DQS5_P

20

DDR2A_DQS5_N

20

DDR2A_DQS6_P

20

DDR2A_DQS6_N

20

DDR2A_DQS7_P

20

DDR2A_DQS7_N

20

DDR2A_DQS8_P

20

DDR2A_DQS8_N

20

DDR2A_DQS9_P

20

DDR2A_DQS9_N

20

DDR2A_DQS10_P

20

DDR2A_DQS10_N

20

DDR2A_DQS11_P

20

DDR2A_DQS11_N

20

DDR2A_DQS12_P

20

DDR2A_DQS12_N

20

DDR2A_DQS13_P

20

DDR2A_DQS13_N

20

DDR2A_DQS14_P

20

DDR2A_DQS14_N

20

DDR2A_DQS15_P

20

DDR2A_DQS15_N

20

DDR2A_DQS16_P

20

DDR2A_DQS16_N

20

DDR2A_DQS17_P

20

DDR2A_DQS17_N

20

DDR2A_A0
DDR2A_A1
DDR2A_A2
DDR2A_A3
DDR2A_A4
DDR2A_A5
DDR2A_A6
DDR2A_A7
DDR2A_A8
DDR2A_A9
DDR2A_A10
DDR2A_A11
DDR2A_A12
DDR2A_A13

DDR2A_BA0
DDR2A_BA1
DDR2A_BA2

DDR2A_WE_N
DDR2A_CAS_N
DDR2A_RAS_N

DDR2_CKE0
DDR2_CKE1
DDR2_CKE2
DDR2_CKE3

DDR2A_CS0_N
DDR2A_CS1_N
DDR2A_CS2_N
DDR2A_CS3_N
DDR2A_CS4_N
DDR2A_CS5_N
DDR2A_CS6_N
DDR2A_CS7_N

CK_200M_DIMMA1_P
CK_200M_DIMMA1_N
CK_200M_DIMMA2_P
CK_200M_DIMMA2_N
CK_200M_DIMMA3_P
CK_200M_DIMMA3_N
CK_200M_DIMMA0_P
CK_200M_DIMMA0_N

DDR2A_MCH_VREF

ROOM=MCH

AJ30

A_DQS0_P

AJ31

A_DQS0_N

AJ24

A_DQS1_P

AJ25

A_DQS1_N

AH19

A_DQS2_P

AH20

A_DQS2_N

AG14

A_DQS3_P

AG15

A_DQS3_N

AC6

A_DQS4_P

AD6

A_DQS4_N

W7

A_DQS5_P

V8

A_DQS5_N

N7

A_DQS6_P

P7

A_DQS6_N

G4

A_DQS7_P

H4

A_DQS7_N

AF9

A_DQS8_P

AG9

A_DQS8_N

AL32

A_DQS9_P

AL31

A_DQS9_N

AF25

A_DQS10_P

AF24

A_DQS10_N

AE20

A_DQS11_P

AE19

A_DQS11_N

AH14

A_DQS12_P

AJ13

A_DQS12_N

AD8

A_DQS13_P

AC7

A_DQS13_N

Y7

A_DQS14_P

Y6

A_DQS14_N

P10

A_DQS15_P

N10

A_DQS15_N

J6

A_DQS16_P

H6

A_DQS16_N

AH8

A_DQS17_P

AJ7

A_DQS17_N

AH5

A_MA0

AD14

A_MA1

AL14

A_MA2

AK15

A_MA3

AJ16

A_MA4

AH17

A_MA5

AF18

A_MA6

AN20

A_MA7

AK20

A_MA8

AJ22

A_MA9

AE4

A_MA10

AF22

A_MA11

AG23

A_MA12

U6

A_MA13

AB5

A_BA0

AF6

A_BA1

AE25

A_BA2

Y10

A_WE

W8

A_CAS

AA6

A_RAS

AE26

CKE0

AN26

CKE1

AL26

CKE2

AK26

CKE3

W2

A_CS0

V3

A_CS1

T8

A_CS2

T10

A_CS3

N5

A_CS4

M5

A_CS5

M3

A_CS6

L4

A_CS7

AF13

A_CMDCLK0_P

AF12

A_CMDCLK0_N

AH11

A_CMDCLK1_P

AJ12

A_CMDCLK1_N

AH13

A_CMDCLK2_P

AG12

A_CMDCLK2_N

AC10

A_CMDCLK3_P

AD9

A_CMDCLK3_N

AM3

A_VREF

INTEL LINDENHURST MCH V0P21

A_DQ0
A_DQ1
A_DQ2
A_DQ3
A_DQ4
A_DQ5
A_DQ6
A_DQ7

A_DQ8

A_DQ9
A_DQ10
A_DQ11
A_DQ12
A_DQ13
A_DQ14
A_DQ15

A_DQ16
A_DQ17
A_DQ18
A_DQ19
A_DQ20
A_DQ21
A_DQ22
A_DQ23

A_DQ24
A_DQ25
A_DQ26
A_DQ27
A_DQ28
A_DQ29
A_DQ30
A_DQ31

A_DQ32
A_DQ33
A_DQ34
A_DQ35
A_DQ36
A_DQ37
A_DQ38
A_DQ39

A_DQ40
A_DQ41
A_DQ42
A_DQ43
A_DQ44
A_DQ45
A_DQ46
A_DQ47

A_DQ48
A_DQ49
A_DQ50
A_DQ51
A_DQ52
A_DQ53
A_DQ54
A_DQ55

A_DQ56
A_DQ57
A_DQ58
A_DQ59
A_DQ60
A_DQ61
A_DQ62
A_DQ63

A_CB0

A_CB1

A_CB2

A_CB3

A_CB4

A_CB5

A_CB6

A_CB7

HETERO 4 OF 7

MCH

AK32
AH31
AH29
AF28
AJ33
AK33
AG30
AG29

AG27
AG26
AD24
AD23
AE28
AF27
AH25
AG24

AF21
AG21
AF19
AG18
AE22
AD21
AJ18
AG20

AF16
AF15
AE13
AD12
AE17
AJ15
AE16
AD17

AH4
AG5
AB8
AB7
AB10
AA9
AE5
AD5

U9
AA5
V6
U7
W10
U10
W5
V5

R6
R5
L7
L6
P9
T5
N8
M9

K5
J5
K8
K10
L9
L10
K7
H7

AJ9
AG11
AE11
AD11
AJ10
AH10
AF10
AE10

DDR2A_SD0_0
DDR2A_SD0_1
DDR2A_SD0_2
DDR2A_SD0_3
DDR2A_SD0_4
DDR2A_SD0_5
DDR2A_SD0_6
DDR2A_SD0_7

DDR2A_SD1_0
DDR2A_SD1_1
DDR2A_SD1_2
DDR2A_SD1_3
DDR2A_SD1_4
DDR2A_SD1_5
DDR2A_SD1_6
DDR2A_SD1_7

DDR2A_SD2_0
DDR2A_SD2_1
DDR2A_SD2_2
DDR2A_SD2_3
DDR2A_SD2_4
DDR2A_SD2_5
DDR2A_SD2_6
DDR2A_SD2_7

DDR2A_SD3_0
DDR2A_SD3_1
DDR2A_SD3_2
DDR2A_SD3_3
DDR2A_SD3_4
DDR2A_SD3_5
DDR2A_SD3_6
DDR2A_SD3_7

DDR2A_SD4_0
DDR2A_SD4_1
DDR2A_SD4_2
DDR2A_SD4_3
DDR2A_SD4_4
DDR2A_SD4_5
DDR2A_SD4_6
DDR2A_SD4_7

DDR2A_SD5_0
DDR2A_SD5_1
DDR2A_SD5_2
DDR2A_SD5_3
DDR2A_SD5_4
DDR2A_SD5_5
DDR2A_SD5_6
DDR2A_SD5_7

DDR2A_SD6_0
DDR2A_SD6_1
DDR2A_SD6_2
DDR2A_SD6_3
DDR2A_SD6_4
DDR2A_SD6_5
DDR2A_SD6_6
DDR2A_SD6_7

DDR2A_SD7_0
DDR2A_SD7_1
DDR2A_SD7_2
DDR2A_SD7_3
DDR2A_SD7_4
DDR2A_SD7_5
DDR2A_SD7_6
DDR2A_SD7_7

DDR2A_CB0
DDR2A_CB1
DDR2A_CB2
DDR2A_CB3
DDR2A_CB4
DDR2A_CB5
DDR2A_CB6
DDR2A_CB7

20
20
20
20
20
20
20
20

20
20
20
20
20
20
20
20

20
20
20
20
20
20
20
20

20
20
20
20
20
20
20
20

20
20
20
20
20
20
20
20

20
20
20
20
20
20
20
20

20
20
20
20
20
20
20
20

20
20
20
20
20
20
20
20

20
20
20
20
20
20
20
20

1

2

3

subsys done

These can be left floating

But BIOS must turn them off

A B

MCH & DDR TERM

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

COMPUTER
CORPORATION

TITLE

AUSTIN,TEXAS

LINDY PLANAR

DWG NO.

D1660

DATE

1/13/2004 16 OF 61

SHEET

DC

REV.

X03

B D

CA

LINDENHURST MCH
MCH REFDES = MCH

1

CK_167M_MCH_N

3

CK_167M_MCH_P

3

H_ADS_N

11

H_A3_N

11

H_A4_N

11

H_A5_N

11

H_A6_N

11

H_A7_N

11

H_A8_N

11

H_A9_N

11

H_A10_N

11

H_A11_N

11

H_A12_N

11

H_A13_N

11

H_A14_N

11

H_A15_N

11

H_A16_N

11

H_A17_N

11

H_A18_N

11

H_A19_N

11

H_A20_N

11

H_A21_N

11

H_A22_N

11

H_A23_N

11

H_A24_N

11

H_A25_N

11

H_A26_N

11

H_A27_N

11

H_A28_N

11

H_A29_N

11

H_A30_N

11

H_A31_N

11

H_A32_N

11,15

17
17
17

MCH_HDACVREF

17

11

H_A33_N

11

H_A34_N

11

H_A35_N

11

H_ADSTB0_N

11

H_ADSTB1_N

11

H_AP0_N

11

H_AP1_N

11

H_BPRI_N

11

H_BINIT_N

11

H_BNR_N

11

H_DRDY_N

11

H_DBSY_N

11

H_DEFER_N

11

H_HIT_N

11

H_HITM_N

11

H_LOCK_N

11

H_RS0_N

11

H_RS1_N

11

H_RS2_N

11

H_RSP_N

11

H_REQ0_N

11

H_REQ1_N

11

H_REQ2_N

11

H_REQ3_N

11

H_REQ4_N

11

H_TRDY_N

11

H_BREQ0_N

11

H_BREQ1_N

11

H_MCERR_N

MCH_HCRES0
MCH_HODTCRES
MCH_HSLWCRES

2

3

ROOM=MCH

J11

BCLKN

K11

BCLKP

B27

ADS

K22

A3

J20

A4

G23

A5

G22

A6

H21

A7

K19

A8

H19

A9

G19

A10

E22

A11

E21

A12

F18

A13

E19

A14

F21

A15

F20

A16

D26

A17

C26

A18

A26

A19

D22

A20

B22

A21

A25

A22

B25

A23

D25

A24

C24

A25

A22

A26

B21

A27

D23

A28

A23

A29

B24

A30

A20

A31

D19

A32

C20

A33

C21

A34

D20

A35

G20

ADSTB0

C23

ADSTB1

G25

AP0

H25

AP1

A28

BPRI

G26

BINIT

B31

BNR

B30

DRDY

H27

DBSY

B28

DEFER

E30

HIT

D28

HITM

C30

LOCK

F29

RS0

D31

RS1

G28

RS2

J26

RSP

K20

HREQ0

J21

HREQ1

J23

HREQ2

H22

HREQ3

K23

HREQ4

A30

TRDY

F24

BREQ0

D29

BREQ1

H24

MCERR

C27

HCRES0

E27

H0DTCRES

F26

HSLWCRES

E13

HDVREF1

D13

HDVREF0

F23

HACVREF

INTEL LINDENHURST MCH V0P21

HETERO 1 OF 7

MCH

D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63

DP0
DP1
DP2
DP3

DBINV0
DBINV1
DBINV2
DBINV3

DSTBN0
DSTBP0
DSTBN1
DSTBP1
DSTBN2
DSTBP2
DSTBN3
DSTBP3

ROOM = MCH

C18

D0

B19

D1

C14

D2

A17

D3

A19

D4

B16

D5

C17

D6

B18

D7

D17

D8

A16

D9

B13
A14
A13
D14
C12
B12
E18
J18
H18
F17
G17
K17
E16
J17
J14
F14
F15
G16
K16
H16
G14
K14
E12
C11
H13
F11
G13
D11
E9
F12
G10
D8
H10
F8
J12
G11
K13
H12
B10
A10
A11
C9
B9
C8
B6
B7
E7
B4
A4
B3
D5
C6
D7
C5

C29
E28
E25
F27

D16
E15
F9
A5

B15
C15
H15
J15
D10
E10
A8
A7

H_D0_N
H_D1_N
H_D2_N
H_D3_N
H_D4_N
H_D5_N
H_D6_N
H_D7_N
H_D8_N

H_D9_N
H_D10_N
H_D11_N
H_D12_N
H_D13_N
H_D14_N
H_D15_N
H_D16_N
H_D17_N
H_D18_N
H_D19_N
H_D20_N
H_D21_N
H_D22_N
H_D23_N
H_D24_N
H_D25_N
H_D26_N
H_D27_N
H_D28_N
H_D29_N
H_D30_N
H_D31_N
H_D32_N
H_D33_N
H_D34_N
H_D35_N
H_D36_N
H_D37_N
H_D38_N
H_D39_N
H_D40_N
H_D41_N
H_D42_N
H_D43_N
H_D44_N
H_D45_N
H_D46_N
H_D47_N
H_D48_N
H_D49_N
H_D50_N
H_D51_N
H_D52_N
H_D53_N
H_D54_N
H_D55_N
H_D56_N
H_D57_N
H_D58_N
H_D59_N
H_D60_N
H_D61_N
H_D62_N
H_D63_N

H_DP0_N
H_DP1_N
H_DP2_N
H_DP3_N

H_DBI0_N
H_DBI1_N
H_DBI2_N
H_DBI3_N

H_DSTBN0_N
H_DSTBP0_N
H_DSTBN1_N
H_DSTBP1_N
H_DSTBN2_N
H_DSTBP2_N
H_DSTBN3_N
H_DSTBP3_N

11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11

11
11
11
11

11
11
11
11

11
11
11
11
11
11
11
11

ITP_TMS_MCH

17

ITP_TDI_MCH

17

ITP_TDO_MCH

17

ITP_TRST_MCH_N

17

ITP_TCK1_MCH

17

+1.5V

R1313

1 2

43.2-1%

PROPAGATION_DELAY=L:S::750

+CPU_VTT

RN7672RN76

1K-5%

1 8

680-5%

1K-5%

RN76

54

x00_tj_052003

21

R180

31
31

31
31

31
31

31
31

31
31

31
31

31
31

31
31

31
31

31
31

31
31

31
31

29
29

29
29

29
29

29
29

31
31

31
31

31
31

31
31

31
31

31
31

31
31

31
31

RN76

1K-5%

3 6

EXP_A_UP_0P
EXP_A_UP_0N

EXP_A_UP_1P
EXP_A_UP_1N

EXP_A_UP_2P
EXP_A_UP_2N

EXP_A_UP_3P
EXP_A_UP_3N

EXP_A_UP_4P
EXP_A_UP_4N

EXP_A_UP_5P
EXP_A_UP_5N

EXP_A_UP_6P
EXP_A_UP_6N

EXP_A_UP_7P
EXP_A_UP_7N

EXP_B_UP_0P
EXP_B_UP_0N

EXP_B_UP_1P
EXP_B_UP_1N

EXP_B_UP_2P
EXP_B_UP_2N

EXP_B_UP_3P
EXP_B_UP_3N

EXP_B_UP_4P
EXP_B_UP_4N

EXP_B_UP_5P
EXP_B_UP_5N

EXP_B_UP_6P
EXP_B_UP_6N

EXP_B_UP_7P
EXP_B_UP_7N

EXP_C_UP_0P
EXP_C_UP_0N

EXP_C_UP_1P
EXP_C_UP_1N

EXP_C_UP_2P
EXP_C_UP_2N

EXP_C_UP_3P
EXP_C_UP_3N

EXP_C_UP_4P
EXP_C_UP_4N

EXP_C_UP_5P
EXP_C_UP_5N

EXP_C_UP_6P
EXP_C_UP_6N

EXP_C_UP_7P
EXP_C_UP_7N

CK_100M_MCH_P

4

CK_100M_MCH_N

4

NC_MCH_TESTIN_N
PCI_RST_MCH_N

5

H_RST_N

11,15

MCH_PME_N

33

MCH_GPE_N

33

HLA_STBS

33

HLA_STBF

33

HLA_MCH_SWING

18

CK_66M_MCH

3

HIRCOMP_MCH

HLA_MCH_VREF

18

SYSTEM_PWRGOOD_CHIPSET

5,33

ICH_SEG0_MCH_SCL

17

ICH_SEG0_MCH_SDA

17

17
17
17
17
17

1K-5%

ITP_TMS_MCH
ITP_TDI_MCH
ITP_TDO_MCH
ITP_TCK1_MCH
ITP_TRST_MCH_N

DDRCRES1

18

DDRCRES2

18

NC_MCH_AF30
NC_MCH_AE23
NC_MCH_AD20
NC_MCH_AJ19
NC_MCH_R10
NC_MCH_R9
NC_MCH_R8
NC_MCH_M8

R33

EXP_A_RXP_0

P33

EXP_A_RXN_0

N28

EXP_A_RXP_1

N29

EXP_A_RXN_1

L31

EXP_A_RXP_2

L30

EXP_A_RXN_2

J33

EXP_A_RXP_3

J32

EXP_A_RXN_3

R26

EXP_A_RXP_4

R27

EXP_A_RXN_4

N25

EXP_A_RXP_5

N26

EXP_A_RXN_5

M27

EXP_A_RXP_6

M26

EXP_A_RXN_6

K29

EXP_A_RXP_7

K28

EXP_A_RXN_7

AG33

EXP_B_RXP_0

AF33

EXP_B_RXN_0

AE32

EXP_B_RXP_1

AD32

EXP_B_RXN_1

AC30

EXP_B_RXP_2

AD30

EXP_B_RXN_2

AC31

EXP_B_RXP_3

AB31

EXP_B_RXN_3

AD29

EXP_B_RXP_4

AE29

EXP_B_RXN_4

AC25

EXP_B_RXP_5

AC24

EXP_B_RXN_5

AB26

EXP_B_RXP_6

AB25

EXP_B_RXN_6

Y25

EXP_B_RXP_7

Y24

EXP_B_RXN_7

Y28

EXP_C_RXP_0

Y27

EXP_C_RXN_0

Y30

EXP_C_RXP_1

Y31

EXP_C_RXN_1

AA30

EXP_C_RXP_2

AA29

EXP_C_RXN_2

V33

EXP_C_RXP_3

V32

EXP_C_RXN_3

T32

EXP_C_RXP_4

T31

EXP_C_RXN_4

R30

EXP_C_RXP_5

R29

EXP_C_RXN_5

V27

EXP_C_RXP_6

V26

EXP_C_RXN_6

V24

EXP_C_RXP_7

U24

EXP_C_RXN_7

T23 U33

EXP_CLK_P EXP_COMP0

R24

EXP_CLK_N

L12

TESTIN

C2

RESET_IN

J24

CPURST

M24

PME

L25

GPE

E31

HI_STBS

D32

HI_STBF

H31

HISWING

L24

HICLK

K25

HIRCOMP

F32

HIVREF

E3

PWRGOOD

C3

SMBCLK

D4

SMBDATA

F3

TMS

G5

TDI

G6

TDO

D2

TCK

J9

TRST

AE2

DDR_RES1

AE1

DDR_RES2

AF30

RESERVED_AF30

AE23

RESERVED_AE23

AD20

RESERVED_AD20

AJ19

RESERVED_AJ19

R10

RESERVED_R10

R9

RESERVED_R9

R8

RESERVED_R8

M8

RESERVED_M8

ROOM=MCH

+CPU_VTT

220pF

50V-10%

x00_tj_051203

21

1uF

C1191

10V-10%

R983

1 2

21

R378

49.9-1%

754mV

84.5-1%

27,31,35

27,31,35

ICH_SEG0_SDA

ICH_SEG0_SCL

R1425

0-5%

R1424

1 2

0-5%

21

ICH_SEG0_MCH_SDA

ICH_SEG0_MCH_SCL

4 4

MCH_HCRES0

17

MCH_HODTCRES

17

MCH_HSLWCRES

17

subsys done

x00_tj_051203

21

R982

MCH_HDACVREF

17

750-1%

21

R1057

1 2

49.9-1%

374-1%

MRGN_MHDAC

1

1
3 4

TSM 2X2
SMT HDR

R1547

12

NP01

C1198

2

2

43

NP*

A B

+3.3V

R1406

1 2

21

R1407

8.2K-5%

NP*

8.2K-5%

NP*

17

17

MCH

EXP_A_TXP_0
EXP_A_TXN_0

EXP_A_TXP_1
EXP_A_TXN_1

EXP_A_TXP_2
EXP_A_TXN_2

EXP_A_TXP_3
EXP_A_TXN_3

EXP_A_TXP_4
EXP_A_TXN_4

EXP_A_TXP_5
EXP_A_TXN_5

EXP_A_TXP_6
EXP_A_TXN_6

EXP_A_TXP_7
EXP_A_TXN_7

EXP_B_TXP_0
EXP_B_TXN_0

EXP_B_TXP_1
EXP_B_TXN_1

EXP_B_TXP_2
EXP_B_TXN_2

EXP_B_TXP_3
EXP_B_TXN_3

EXP_B_TXP_4
EXP_B_TXN_4

EXP_B_TXP_5
EXP_B_TXN_5

EXP_B_TXP_6
EXP_B_TXN_6

EXP_B_TXP_7
EXP_B_TXN_7

EXP_C_TXP_0
EXP_C_TXN_0

EXP_C_TXP_1
EXP_C_TXN_1

EXP_C_TXP_2
EXP_C_TXN_2

EXP_C_TXP_3
EXP_C_TXN_3

EXP_C_TXP_4
EXP_C_TXN_4

EXP_C_TXP_5
EXP_C_TXN_5

EXP_C_TXP_6
EXP_C_TXN_6

EXP_C_TXP_7
EXP_C_TXN_7

EXP_COMP1

EXPHPINTR_N

VCCBGEXP
VSSBGEXP

V3REF

DDRSLWCRES

DDRCRES0

DDRIMPCRES

PLLSEL[1]
PLLSEL[0]

HI11
HI10

3.3V

DEBUG7
DEBUG6
DEBUG5
DEBUG4
DEBUG3
DEBUG2
DEBUG1
DEBUG0

TDIOCATHODE

TDIOANODE

RESERVED_AA24

RESERVED_R32
RESERVED_L33

INTEL LINDENHURST MCH V0P21

HETERO 2 OR 7

HI9
HI8
HI7
HI6
HI5
HI4
HI3
HI2
HI1
HI0

P30
P31

N31
N32

M33
M32

K32
K31

P24
P25

P27
P28

M30
M29

L28
L27

AG32
AH32

AF31
AE31

AC33
AD33

AB32
AA32

AD27
AD26

AC27
AC28

AB29
AB28

AA27
AA26

W26
W25

W28
W29

Y33
AA33

W32
W31

U31
U30

V30
V29

T29
T28

T26
T25

U25
E6
U27
U28

H33
AK1
AC9
AL2
A29
C31

G32
J29
E33
F30
J27
K26
H28
G29
G31
C32
H30
J30

D1
L11
D3
B2
H9
G8
G7
J8

F33
D33
AA24
R32
L33

(MCH_VSSBGEXP)

HLA_11
HLA_10

NC_ITP_MCH_DEBUG7
NC_ITP_MCH_DEBUG6
NC_ITP_MCH_DEBUG5
NC_ITP_MCH_DEBUG4
NC_ITP_MCH_DEBUG3
NC_ITP_MCH_DEBUG2
NC_ITP_MCH_DEBUG1
NC_ITP_MCH_DEBUG0

NC_MCH_TD_CATHODE

NC_MCH_TD_ANODE
NC_MCH_RES_AA24

EXP_A_DN_0P_C
EXP_A_DN_0N_C

EXP_A_DN_1P_C
EXP_A_DN_1N_C

EXP_A_DN_2P_C
EXP_A_DN_2N_C

EXP_A_DN_3P_C
EXP_A_DN_3N_C

EXP_A_DN_4P_C
EXP_A_DN_4N_C

EXP_A_DN_5P_C
EXP_A_DN_5N_C

EXP_A_DN_6P_C
EXP_A_DN_6N_C

EXP_A_DN_7P_C
EXP_A_DN_7N_C

EXP_B_DN_0P_C
EXP_B_DN_0N_C

EXP_B_DN_1P_C
EXP_B_DN_1N_C

EXP_B_DN_2P_C
EXP_B_DN_2N_C

EXP_B_DN_3P_C
EXP_B_DN_3N_C

EXP_B_DN_4P_C
EXP_B_DN_4N_C

EXP_B_DN_5P_C
EXP_B_DN_5N_C

EXP_B_DN_6P_C
EXP_B_DN_6N_C

EXP_B_DN_7P_C
EXP_B_DN_7N_C

EXP_C_DN_0P_C
EXP_C_DN_0N_C

EXP_C_DN_1P_C
EXP_C_DN_1N_C

EXP_C_DN_2P_C
EXP_C_DN_2N_C

EXP_C_DN_3P_C
EXP_C_DN_3N_C

EXP_C_DN_4P_C
EXP_C_DN_4N_C

EXP_C_DN_5P_C
EXP_C_DN_5N_C

EXP_C_DN_6P_C
EXP_C_DN_6N_C

EXP_C_DN_7P_C
EXP_C_DN_7N_C

MCH_EXP_COMP

MCH_VCCBGEXP

DDRSLWCRES

DDRCRES0

DDRIMPCRES
MCH_PLLSTRAP_1
MCH_PLLSTRAP_0

33
33

HLA_9

33

HLA_8

33

HLA_7

33

HLA_6

33

HLA_5

33

HLA_4

33

HLA_3

33

HLA_2

33

HLA_1

33

HLA_0

33

NC_MCH_RES_R32
NC_MCH_RES_L33

17
17

17
17

17
17

17
17

17
17

17
17

17
17

17
17

17
17

17
17

17
17

17
17

17
17

17
17

17
17

17
17

17
17

17
17

17
17

17
17

17
17

17
17

17
17

17
17

17

+1.5V

NP

18

R1605

18

1 2

18

220

21

x02_tj_091903

+1.5V+3.3V

NP

1K-5%

R1606

MCH & PCI EXPRESS CAPS

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

+1.5V

+3.3V

R1604

4.7K

R1001

24.9-1%

1 2

21

MCH_EXPHPINTR_N

21

R1082

220

1K-5%

R1247

1 2

C1738

.1uF

10V-10%

21

+3.3V

R5

2 1

TLV431A

NET_PHYSICAL_TYPE=PWR
PROPAGATION_DELAY=L:S::1200

31

220

21

R12

R181

1 2

1K-1%1K-1%

x00_tj_051203

100K-1%

D33

4

53

EXP_A_DN_0P_C

17

EXP_A_DN_0N_C

17

EXP_A_DN_1P_C

17

EXP_A_DN_1N_C

17

EXP_A_DN_2P_C

17

EXP_A_DN_2N_C

17

EXP_A_DN_3P_C

17

EXP_A_DN_3N_C

17

EXP_A_DN_4P_C

17

EXP_A_DN_4N_C

17

EXP_A_DN_5P_C

17

EXP_A_DN_5N_C

17

EXP_A_DN_6P_C

17

EXP_A_DN_6N_C

17

EXP_A_DN_7P_C

17

EXP_A_DN_7N_C

17

EXP_B_DN_0P_C

17

EXP_B_DN_0N_C

17

EXP_B_DN_1P_C

17

EXP_B_DN_1N_C

17

EXP_B_DN_2P_C

17

EXP_B_DN_2N_C

17

EXP_B_DN_3P_C

17

EXP_B_DN_3N_C

17

EXP_B_DN_4P_C

17

EXP_B_DN_4N_C

17

EXP_B_DN_5P_C

17

EXP_B_DN_5N_C

17

EXP_B_DN_6P_C

17

EXP_B_DN_6N_C

17

EXP_B_DN_7P_C

17

EXP_B_DN_7N_C

17

EXP_C_DN_0P_C

17

EXP_C_DN_0N_C

17

EXP_C_DN_1P_C

17

EXP_C_DN_1N_C

17

EXP_C_DN_2P_C

17

EXP_C_DN_2N_C

17

EXP_C_DN_3P_C

17

EXP_C_DN_3N_C

17

EXP_C_DN_4P_C

17

EXP_C_DN_4N_C

17

EXP_C_DN_5P_C

17

EXP_C_DN_5N_C

17

EXP_C_DN_6P_C

17

EXP_C_DN_6N_C

17

EXP_C_DN_7P_C

17

EXP_C_DN_7N_C

17

NET_PHYSICAL_TYPE=PWR
PROPAGATION_DELAY=L:S::1200

1 2

10uF 6.3V

C1661

1 2

R1833

1-1%

x00_tt_052903

L131

1 2

4.7uH 30mA

SUB*_D2938

X00_TJ_060403

R2

12

2.5V Generation

C1119

21

.1uF

10V-10%

C1121

21

.1uF

10V-10%

C1126

21

.1uF

10V-10%

C1124

21

.1uF

10V-10%

C1134

21

.1uF

10V-10%

C1132

21

.1uF

10V-10%

C1130

21

.1uF

10V-10%

C1128

21

.1uF

10V-10%

C1150

21

.1uF

10V-10%

C1148

21

.1uF

10V-10%

C1146

21

.1uF

10V-10%

C1144

21

.1uF

10V-10%

C1142

21

.1uF

10V-10%

C1140

21

.1uF

10V-10%

C1138

21

.1uF

10V-10%

C1136

21

.1uF

10V-10%

C1151

21

.1uF

10V-10%

C1153

21

.1uF

10V-10%

C1155

21

.1uF

10V-10%

C1157

21

.1uF

10V-10%

C1159

21

.1uF

10V-10%

C1161

21

.1uF

10V-10%

C1163

21

.1uF

10V-10%

C1165

21

.1uF

10V-10%

MCH_VCCBGEXP

10uF 6.3V

0.1uF 16V

C823

21

C1120

21

.1uF

10V-10%

C1122

21

.1uF

10V-10%

C1125

21

.1uF

10V-10%

C1123

21

.1uF

10V-10%

C1133

21

.1uF

10V-10%

C1131

21

.1uF

10V-10%

C1129

21

.1uF

10V-10%

C1127

21

.1uF

10V-10%

C1149

21

.1uF

10V-10%

C1147

21

.1uF

10V-10%

C1145

21

.1uF

10V-10%

C1143

21

.1uF

10V-10%

C1141

21

.1uF

10V-10%

C1139

21

.1uF

10V-10%

C1137

21

.1uF

10V-10%

C1135

21

.1uF

10V-10%

C1152

21

.1uF

10V-10%

C1154

21

.1uF

10V-10%

C1156

21

.1uF

10V-10%

C1158

21

.1uF

10V-10%

C1160

21

.1uF

10V-10%

C1162

21

.1uF

10V-10%

C1164

21

.1uF

10V-10%

C1166

21

.1uF

10V-10%

C195

1 2

TITLE

LINDY PLANAR

DWG NO.

D1660

DATE

DC

EXP_A_DN_0P

EXP_A_DN_0N

EXP_A_DN_1P

EXP_A_DN_1N

EXP_A_DN_2P

EXP_A_DN_2N

EXP_A_DN_3P

EXP_A_DN_3N

EXP_A_DN_4P

EXP_A_DN_4N

EXP_A_DN_5P

EXP_A_DN_5N

EXP_A_DN_6P

EXP_A_DN_6N

EXP_A_DN_7P

EXP_A_DN_7N

EXP_B_DN_0P

EXP_B_DN_0N

EXP_B_DN_1P

EXP_B_DN_1N

EXP_B_DN_2P

EXP_B_DN_2N

EXP_B_DN_3P

EXP_B_DN_3N

EXP_B_DN_4P

EXP_B_DN_4N

EXP_B_DN_5P

EXP_B_DN_5N

EXP_B_DN_6P

EXP_B_DN_6N

EXP_B_DN_7P

EXP_B_DN_7N

EXP_C_DN_0P

EXP_C_DN_0N

EXP_C_DN_1P

EXP_C_DN_1N

EXP_C_DN_2P

EXP_C_DN_2N

EXP_C_DN_3P

EXP_C_DN_3N

EXP_C_DN_4P

EXP_C_DN_4N

EXP_C_DN_5P

EXP_C_DN_5N

EXP_C_DN_6P

EXP_C_DN_6N

EXP_C_DN_7P

EXP_C_DN_7N

17

COMPUTER
CORPORATION

AUSTIN,TEXAS

SHEET

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

27

27

27

27

27

27

27

27

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

REV.

X03

17 OF 611/13/2004

1

2

3

B D

LINDENHURST MCH

C33
G33
H29
K9
K27
L23
M12
M22
N13
N15
N17
N19
N21
N23
P14
P16
P18
P22
R13
R15
R17
R19
R21
T14
T16
T18
T20

U13
U15
U17
U19
U21
V14
V16
V18
V20
W13
W15
W17
W19
W21
Y14
Y16
Y18
Y20
AA13
AA15
AA17
AA19
AA21

A3
A6
A9
A12
A15
A18
A31
D27
D30
E8
E11
E14
E17
E20
E23
H23
H26
J13
J16
J19
L13
L15
L17
L19
L21
M14
M16
M18
M20

F6
E4
U23
P20

+1.5V

+1.5V

+CPU_VTT

MCH_VCCA_VCORE
MCH_VCCA_DDR
MCH_VCCA_EXP
MCH_VCCA_HI

21

C1169

0.1uF 16V

To be placed near hub link on MCH

21

1 2

C401

C636

.01uF 50V

0.1uF 16V

18
18
18
18

MCH POWER

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

MCH REFDES = MCH

GND-A21
GND-A24
GND-A27
GND-B5
GND-B8
GND-B11
GND-B14
GND-B17
GND-B20
GND-B23
GND-B26
GND-B29
GND-C1
GND-C4
GND-C7
GND-C10
GND-C13
GND-C16
GND-C19
GND-C22
GND-C25
GND-C28
GND-B32
GND-D6
GND-D9
GND-D12
GND-D15
GND-D18
GND-D21
GND-D24
GND-E2
GND-E5
GND-E24
GND-E26
GND-E29
GND-E32
GND-F4
GND-F7
GND-F10
GND-F13
GND-F16
GND-F19
GND-F22
GND-F25
GND-F28
GND-F31
GND-G3
GND-G9
GND-G12
GND-G15
GND-G18
GND-G21
GND-G24
GND-G27
GND-G30
GND-H2
GND-H8
GND-H11
GND-H14
GND-H17
GND-H20
GND-H32
GND-J1
GND-J4
GND-J7
GND-J10
GND-J22
GND-J25
GND-J28
GND-J31
GND-K6
GND-K12
GND-K15
GND-K18
GND-K21
GND-K24
GND-L2
GND-L5
GND-L8
GND-L14
GND-L16
GND-L18
GND-L20
GND-L22
GND-L26
GND-L29
GND-L32
GND-M4
GND-M10
GND-M11
GND-M13
GND-M15
GND-M17
GND-M19
GND-M21
GND-M23
GND-M25
GND-M31
GND-N3
GND-N6
GND-N9
GND-N12
GND-N14
GND-N16
GND-N18
GND-N20
GND-N22
GND-N24
GND-N27
GND-N30
GND-P2
GND-P8
GND-P11
GND-P13
GND-P15

ROOM=MCH

MCH

GND-P17
GND-P19
GND-P23
GND-P26
GND-P32

GND-R1
GND-R4

GND-R7
GND-R12
GND-R14
GND-R16
GND-R18
GND-R20
GND-R22
GND-R25
GND-R28
GND-R31

GND-T6
GND-T11
GND-T13
GND-T15
GND-T17
GND-T19
GND-T21
GND-T30

GND-U2

GND-U5

GND-U8
GND-U12
GND-U14
GND-U16
GND-U18
GND-U20
GND-U22
GND-U26
GND-U32

GND-V4
GND-V10
GND-V11
GND-V13
GND-V15
GND-V17
GND-V19
GND-V21
GND-V25
GND-V28
GND-V31

GND-W3

GND-W6

GND-W9
GND-W12
GND-W14
GND-W16
GND-W18
GND-W20
GND-W22
GND-W24
GND-W30

GND-Y2

GND-Y8
GND-Y11
GND-Y13
GND-Y15
GND-Y17
GND-Y19
GND-Y21
GND-Y23
GND-Y26
GND-Y32
GND-AA1
GND-AA4
GND-AA7

GND-AA10
GND-AA12
GND-AA14
GND-AA16
GND-AA18
GND-AA20
GND-AA22
GND-AA25
GND-AA28
GND-AA31

GND-AB6

GND-AB11

GND-AB13
GND-AB15
GND-AB17
GND-AB19
GND-AB21
GND-AB23
GND-AB30

GND-AC2
GND-AC5
GND-AC8

GND-AC12
GND-AC14
GND-AC16
GND-AC18
GND-AC20
GND-AC22
GND-AC26
GND-AC32

GND-AD4

GND-AD10
GND-AD13
GND-AD16
GND-AD19
GND-AD22
GND-AD25
GND-AD28
GND-AD31

GND-AE3
GND-AE6
GND-AE9

VSSA_CORE

VSSA_HI

VSSA_EXP

HETERO 7 OF 7

P17
P19
P23
P26
P32
R1
R4
R7
R12
R14
R16
R18
R20
R22
R25
R28
R31
T6
T11
T13
T15
T17
T19
T21
T30
U2
U5
U8
U12
U14
U16
U18
U20
U22
U26
U32
V4
V10
V11
V13
V15
V17
V19
V21
V25
V28
V31
W3
W6
W9
W12
W14
W16
W18
W20
W22
W24
W30
Y2
Y8
Y11
Y13
Y15
Y17
Y19
Y21
Y23
Y26
Y32
AA1
AA4
AA7
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AA28
AA31
AB6
AB11

AB13
AB15
AB17
AB19
AB21
AB23
AB30
AC2
AC5
AC8
AC12
AC14
AC16
AC18
AC20
AC22
AC26
AC32
AD4
AD10
AD13
AD16
AD19
AD22
AD25
AD28
AD31
AE3
AE6
AE9

MCH_VSSA_SB

F5

MCH_VSSA_HI

P21

MCH_VSSA_EXP

V23

AE15
AE21
AE27

AF2
AF8

AF11

AF14
AF17
AF20
AF23
AF26
AF29
AF32

AG1
AG4

AG7
AG13
AG19
AG25
AG31

AH9
AH12
AH15
AH18
AH21
AH24
AH27
AH30

AJ2

AJ5
AJ11

INTEL LINDENHURST MCH V0P21

18
18
18

GND-AE15
GND-AE21
GND-AE27
GND-AF2
GND-AF8
GND-AF11

GND-AF14
GND-AF17
GND-AF20
GND-AF23
GND-AF26
GND-AF29
GND-AF32
GND-AG1
GND-AG4
GND-AG7
GND-AG13
GND-AG19
GND-AG25
GND-AG31
GND-AH9
GND-AH12
GND-AH15
GND-AH18
GND-AH21
GND-AH24
GND-AH27
GND-AH30
GND-AJ2
GND-AJ5
GND-AJ11

ROOM=MCH

HETERO 6 OF 7

MCH

GND-AJ17
GND-AJ23
GND-AJ29
GND-AJ32

GND-AK4

GND-AK7
GND-AK10
GND-AK13
GND-AK16
GND-AK19
GND-AK22
GND-AK25
GND-AK28
GND-AK31

GND-AL3

GND-AL9
GND-AL15

GND-AL21
GND-AL27
GND-AL33

GND-AM2

GND-AM5

GND-AM8
GND-AM11
GND-AM14
GND-AM17
GND-AM20
GND-AM23
GND-AM26
GND-AM29
GND-AM32

GND-AN7
GND-AN13
GND-AN19
GND-AN25
GND-AN31

AJ17
AJ23
AJ29
AJ32
AK4
AK7
AK10
AK13
AK16
AK19
AK22
AK25
AK28
AK31
AL3
AL9
AL15

AL21
AL27
AL33
AM2
AM5
AM8
AM11
AM14
AM17
AM20
AM23
AM26
AM29
AM32
AN7
AN13
AN19
AN25
AN31

A B

+1.5V

A21
A24

1

2

3

4 4

A27

B11
B14
B17
B20
B23
B26
B29

C10
C13
C16
C19
C22
C25
C28
B32

D12
D15
D18
D21
D24

E24
E26
E29
E32

F10
F13
F16
F19
F22
F25
F28
F31

G12
G15
G18
G21
G24
G27
G30

H11
H14
H17
H20
H32

J10
J22
J25
J28
J31

K12
K15
K18
K21
K24

L14
L16
L18
L20
L22
L26
L29
L32

M10
M11
M13
M15
M17
M19
M21
M23
M25
M31

N12
N14
N16
N18
N20
N22
N24
N27
N30

P11
P13
P15

B5
B8

C1
C4
C7

D6
D9

E2
E5

F4
F7

G3
G9

H2
H8

J1
J4
J7

K6

L2
L5
L8

M4

N3
N6
N9

P2
P8

INTEL LINDENHURST MCH V0P21

subsys done

F1
H5
K3
M1
M7

N11

P5
P12
R11

T3

T9
T12
U11

V1

V7
V12
W11

Y5
Y12

AA11

AB3
AB9

AB12
AB14
AB16
AB18
AB20
AB22
AC11
AC13
AC15
AC17
AC19
AC21
AC23

AD1
AD7

AE12
AE18
AE24

AF5

AG10
AG16
AG22
AG28

AH3
AJ8

AJ14
AJ20
AJ26

AL1
AL6

AL12
AL18
AL24
AL30

AN3

AN10
AN16
AN22
AN28

K30
K33
M28
N33
P29
R23
T22
T24
T27
T33
U29
V22
W23
W27
W33
Y22
Y29

AA23
AB24
AB27
AB33
AC29
AE30
AE33

AH33

INTEL LINDENHURST MCH V0P21

+1.8V

MCH

VDDR_F1
VDDR_H5
VDDR_K3
VDDR_M1
VDDR_M7
VDDR_N11
VDDR_P5
VDDR_P12
VDDR_R11
VDDR_T3
VDDR_T9
VDDR_T12
VDDR_U11
VDDR_V1
VDDR_V7
VDDR_V12
VDDR_W11
VDDR_Y5
VDDR_Y12
VDDR_AA11
VDDR_AB3
VDDR_AB9
VDDR_AB12
VDDR_AB14
VDDR_AB16
VDDR_AB18
VDDR_AB20
VDDR_AB22
VDDR_AC11
VDDR_AC13
VDDR_AC15
VDDR_AC17
VDDR_AC19
VDDR_AC21
VDDR_AC23
VDDR_AD1
VDDR_AD7
VDDR_AE12
VDDR_AE18
VDDR_AE24
VDDR_AF5
VDDR_AG10
VDDR_AG16
VDDR_AG22
VDDR_AG28
VDDR_AH3
VDDR_AJ8
VDDR_AJ14
VDDR_AJ20
VDDR_AJ26
VDDR_AL1
VDDR_AL6
VDDR_AL12
VDDR_AL18
VDDR_AL24
VDDR_AL30
VDDR_AN3
VDDR_AN10
VDDR_AN16
VDDR_AN22
VDDR_AN28

VEXP_K30
VEXP_K33
VEXP_M28
VEXP_N33
VEXP_P29
VEXP_R23
VEXP_T22
VEXP_T24
VEXP_T27
VEXP_T33
VEXP_U29
VEXP_V22
VEXP_W23
VEXP_W27
VEXP_W33
VEXP_Y22
VEXP_Y29
VEXP_AA23
VEXP_AB24
VEXP_AB27
VEXP_AB33
VEXP_AC29
VEXP_AE30
VEXP_AE33
VEXP_AH33

HETERO 5 OF 7

ROOM=MCH

VCORE_C33
VCORE_G33
VCORE_H29

VCORE_K9
VCORE_K27
VCORE_L23
VCORE_M12
VCORE_M22
VCORE_N13
VCORE_N15
VCORE_N17
VCORE_N19
VCORE_N21
VCORE_N23
VCORE_P14
VCORE_P16
VCORE_P18
VCORE_P22
VCORE_R13
VCORE_R15
VCORE_R17
VCORE_R19
VCORE_R21
VCORE_T14
VCORE_T16
VCORE_T18
VCORE_T20

VCORE-U13
VCORE-U15
VCORE_U17
VCORE_U19
VCORE_U21
VCORE_V14
VCORE_V16
VCORE_V18
VCORE_V20
VCORE_W13
VCORE_W15
VCORE_W17
VCORE_W19
VCORE_W21
VCORE_Y14
VCORE_Y16
VCORE_Y18
VCORE_Y20

VCORE_AA13
VCORE_AA15
VCORE_AA17
VCORE_AA19
VCORE_AA21

VTT_A3
VTT_A6

VTT_A9
VTT_A12
VTT_A15
VTT_A18
VTT_A31
VTT_D27
VTT_D30

VTT_E8
VTT_E11
VTT_E14
VTT_E17
VTT_E20
VTT_E23
VTT_H23
VTT_H26
VTT_J13
VTT_J16
VTT_J19
VTT_L13
VTT_L15
VTT_L17
VTT_L19
VTT_L21
VTT_M14
VTT_M16
VTT_M18
VTT_M20

VCCA_CORE

VCCA_DDR
VCCA_EXP

VCCA_HI

1 2

C117021C1171

0.1uF 16V

1 2

C637

C142

0.1uF 16V

MRGN_MHVS

1

1

3 4

3 4

TSM 2X2
SMT HDR

CA

+CPU_VTT

0.1uF 16V

+1.5V

@MCH

1 2

.01uF 50V

2

2

NP*

R234

1 2

43.2-1%49.9-1%

21

R551

2.7K-5%

21

NP01R582

MCH HLA VREF
& VSWING

R276

1 2

NET_PHYSICAL_TYPE=PWR

HLA_MCH_SWING

(804mv)

NET_PHYSICAL_TYPE=PWR

HLA_MCH_VREF

(353mv)

R537

1 2

24.3-1% 78.7-1%

2.7K-5%

MRGN_MHVR

2

1

1

2

43

3 4

NP*

TSM 2X2
SMT HDR

17

1 2

17

R553

NP01

MCH_VCCA_VCORE

18

PROPAGATION_DELAY=L:S::700
NET_PHYSICAL_TYPE=50MIL

MCH_VSSA_SB

18

MCH_VCCA_DDR

18

PROPAGATION_DELAY=L:S::600
NET_PHYSICAL_TYPE=50MIL

MCH_VSSA_SB

18

PROPAGATION_DELAY=L:S::600
NET_PHYSICAL_TYPE=50MIL

MCH_VCCA_EXP

18

PROPAGATION_DELAY=L:S::1200
NET_PHYSICAL_TYPE=50MIL

MCH_VSSA_EXP

18

PROPAGATION_DELAY=L:S::1400
NET_PHYSICAL_TYPE=50MIL

MCH_VCCA_HI

18

PROPAGATION_DELAY=L:S::1500
NET_PHYSICAL_TYPE=50MIL

MCH_VSSA_HI

18

PROPAGATION_DELAY=L:S::1500
NET_PHYSICAL_TYPE=50MIL

PROPAGATION_DELAY=L:S::1000

PROPAGATION_DELAY=L:S::1300

PROPAGATION_DELAY=L:S::1000

PROPAGATION_DELAY=L:S::1000

PROPAGATION_DELAY=L:S::1000

1 2

C1589

17

17

21

C1236

10uF 6.3V

1 2

C1238

10uF 6.3V

21

C1240

10uF 6.3V

10uF 6.3V

x00_tj_042903

1 2

C1242

10uF 6.3V

17

17

17

DDRCRES2

DDRCRES1

1 2

C1226

21

C1225

21

C1227

1 2

C1228

L113

1 2

4.7uH 80mA

X00_TJ_060403
X03b_TJ_011904

MCH_VCCA_VCORE_L

PROPAGATION_DELAY=L:S::200
NET_PHYSICAL_TYPE=50MIL

23.4mA

0.1uF 16V0.1uF 16V

L112

1 2

4.7uH 80mA

X00_TJ_060403
X03b_TJ_011904

4.7uH 80mA

X00_TJ_060403
X03b_TJ_011904

MCH_VCCA_DDR_L

PROPAGATION_DELAY=L:S::200
NET_PHYSICAL_TYPE=50MIL

L111

21

MCH_VCCA_EXP_L

PROPAGATION_DELAY=L:S::200
NET_PHYSICAL_TYPE=50MIL

23.4mA

21.3mA

0.1uF 16V

L110

1 2

4.7uH 80mA

X00_TJ_060403
X03b_TJ_011904

0.1uF 16V

DDRIMPCRES

DDRCRES0

DDRSLWCRES

MCH_VCCA_HI_L

PROPAGATION_DELAY=L:S::200
NET_PHYSICAL_TYPE=50MIL

24.7mA

PN 7H671

ESR = 300mohm
Max current = 80mA
Inductance = 4.7uH

R1031

1 2

287-1%

R1004

1 2

825-1%

+1.8V

R1573

21

40.2-0.5%

C1173

1 2

R1574

1 2

40.2-0.5%

21

C1172

0.1uF 16V 0.1uF 16V

MCH Power & Ground

COMPUTER
CORPORATION

TITLE

LINDY PLANAR

DWG NO.

D1660

DATE

DC

AUSTIN,TEXAS

SHEET

R1173

1 2

1-1%

x00_tj_051203ROOM = MCH

x00_tj_052903
x02_tj_100703

R1174

21

1-1%

x00_tj_052903

R1175

1 2
.499-1%

R1176

1 2

1-1%

x00_tj_052903

REV.

X03

18 OF 611/13/2004

+1.5V

+1.5V

+1.5V

+1.5V

1

2

3

+1.8V

ROOM = MCH

MCH DDR caps (min of 10)

B D

CA

1 2

C1400

0.1uF 16V

0.1uF 16V

21

C1403

0.1uF 16V

0.1uF 16V

100uF

1 2

C762

+

1uF

1uF

1 2

C148621C1485

10V-10%

21

1uF

1uF

C1483

10V-10%

220uF-6.3V

21

C1401

0.1uF 16V0.1uF 16V

1 2

C1402

10V-10%

1 2

C1484

10V-10%

1uF

10V-10%

1uF

10V-10%

ECAD Note:
Place 6 0.1uF beneath BGA

Place 20 0.1uF topside edge of BGA

ECAD Note:
Place 6 0.1uF beneath BGA

Place remaining 18 1uF caps near 1.5V pins on BGA

VTT1.2V

3 560uF Al-Polymer 20% 7mohm 4nh 4V

1.2 6.32X5R22uF Ceramic5

1.8V DDR2
26 .1uF (0603) 200 2
5 100uF (7343) 220 2.3

1.5V EXP
3 .1uF (0603) 200 2

4 1uf (0805) 200

2.3

2 10uF (1206) 200 1.9

1.5V

CORE

TBD TBD TBD TBD

1

2

21

1 2

C1396

0.1uF 16V

0.1uF 16V

21

C1397

C1399

0.1uF 16V

0.1uF 16V

1 2

C1398

21

C1395

1 2

C1394

0.1uF 16V

0.1uF 16V

1 2

C1392

21

C1393

0.1uF 16V

1

1 2

C1410

0.1uF 16V

0.1uF 16V

0.1uF 16V

0.1uF 16V

21

C1419

0.1uF 16V

0.1uF 16V

1uF

1uF

1 2

C1478

10V-10%

21

C1565

10uF 6.3V

10uF 6.3V

21

1 2

C1406

C1407

0.1uF 16V

1 2

C141321C1412

0.1uF 16V

21

1 2

C1423

C1422

0.1uF 16V

1uF

1 2

C147921C1480

10V-10%

10V-10%

1 2

C1404

0.1uF 16V

0.1uF 16V

16V-20%

100uF

+

0.1uF 16V

x00_tj_040803
x02_tj_081803

21

1uF

C1488

0.1uF 16V

1uF

1uF

1 2

C1481

10V-10%

x00_tj_040803

21

C1405

C761

21

1 2

C1487

10V-10%

21

C1482

10V-10%

C763

2 1

16V-20%

+

21

21

1 2

C1408

21

C1417

+1.5V

21

C1421

1 2

2

C1475

21

C1562

C1411

C1409

0.1uF 16V

0.1uF 16V

1 2

1 2

C1416

C141521C1414

0.1uF 16V

0.1uF 16V

MCH EXPRESS caps

1 2

1 2

C1418

C1420

0.1uF 16V

0.1uF 16V

21

21

1uF

1uF10uF 6.3V

C1477

C1476

10V-10%

10V-10%

1 2

1 2

C1563

C1564

10uF 6.3V

21

C766

22uF 6.3V

MCH FSB caps

21

C768

C765

1 2

22uF 6.3V

22uF 6.3V

21

C764

1 2

C760

22uF 6.3V

x00_tj_040803

1 2

C448

1uF 6.3V

1 2

C444

1uF 6.3V

21

C77

0.1uF 16V

0.1uF 16V

+CPU_VTT

C767

1 2

22uF 6.3V

3

4 4

MCH DECOUPLING

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

subsys done

A B

DECOUPLING

TITLE

LINDY PLANAR

DWG NO.

D1660

DATE

DC

COMPUTER
CORPORATION

AUSTIN,TEXAS

REV.

SHEET

X03

19 OF 611/13/2004

3