MSI MS-9575 Schematic 0A

ABC

D

REVISIONS

REV

X00 INITIAL PROTOTYPE BUILD
X01 PROTOTYPE UNIT TEST BUILD

IPMB BUS

X02 PROTOTYPE PRODUCT TEST BUILD

PRODUCT TEST BUILDX03

PRIVATE I2C BUS

1

DESCRIPTIONECO DATE

7/31/03
9/18/03

12/08/03

12/19/03

CORVETTE 1x2/KOBUK DAUGHTER BOARD

APPROVED

7/31/03
9/18/03

12/10/03
12/19/03

1

JTAG

DEBUG PORTS

SMVU
PORTPORT

I2C0
PORT

20MHZ

OSC

MICROCONTROLLER INTERFACE

CLK

I2C1
PORT

FRU

PAGE

TABLE OF CONTENTS

DESCRIPTION

1

BLOCK DIAGRAM

2

STACKUP AND LAYOUT INSTRUCTION

3

BKPLN/DTR MATING CONNECTOR

4

GEM359

5

FLASH

SCSI LVD TERMINATION6

CPLD

7
8

SPARES, DEBUG PORTS, MISC

SCHEMATIC IS CONFIGURED TO USE
THE XLBOM UTILITY:
BUILD0 IS 5U 1X2 DC PROTOTYPE BUILD

2

FLASH

ROM

512KX8

DATA BUS

ADDRESS BUS

QLOGIC GEM359

SCSI ID6

DRIVE PRESENCE

BUILD1 IS 5U 1X2 DC PRODUCTION BUILD
BUILD2 IS 2U SCSI DC PROTOTYPE BUILD
BUILD3 IS 2U SCSI DC PRODUCTION BUILD

2

OUTPUT PORT

3

JTAG

LVD SCSI

3

SCSI BUS

CPLD

LOGIC

DRIVE POWER

TERMINATION

CONTROL

DAUGHTER

A CURRENT ISSUE OF THIS DRAWING MUST
INCLUDE A COPY OF THE FOLLOWING
ECO'S:
ECO

ECO
ECO
ECO
ECO
ECO
ECO

4

THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS
AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS
ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER
CORP., EXCEPT AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN
ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE
REPRODUCED IN WHOLE OR IN PART AND MUST BE RETURNED TO DELL

EXPORT RESTRICTION:

THE EXPORT OF THE INFORMATION, SCHEMATICS AND OTHER TECHNICAL DATA CONTAINED IN THIS DOCUMENT
IS CONTROLLED BY THE U.S. GOVERNMENT. THE EXPORT, DEEMED EXPORT OR OTHER TRANSFER OF THIS DATA
TO CERTAIN COUNTRIES AND INDIVIDUALS IS RESTRICTED. ANY TRANSFER, EXPORT OR REEXPORT, MUST BE
IN COMPLIANCE WITH THE U.S. EXPORT ADMINISTRATION REGULATIONS.

COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION
OF THE PURPOSE OF THE LOAN. NEITHER THIS ITEM NOR THE
INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS
NOT HAVING A NEED FOR SUCH USE OR DISCLOSURE CONSISTENT WITH
THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF
DELL COMPUTER CORPORATION.

PROPRIETARY NOTE

DRAWN

DESIGNED

CHECKED

APPROVED

APPROVED

APPROVED

APPROVED

RELEASED

ECO

TITLE

SCHEM, DTBRD, 1X2, PE2800

DWG NO.

DATE

C1325

12/19/2003

DATE
DATE
DATE
DATE
DATE
DATE
DATE
DATE

COMPUTER
CORPORATION
AUSTIN,TEXAS

REV.

SHEET

1 OF 8

DCBA

12-19-2003_13:41

X03

-02

4

ABC

s

s

%

NOTE ON COMPONENT PLACEMENT:

--> ALL COMPONENTS SHOULD BE PLACED ON THE TOP SIDE IF POSSIBLE

--> REFER TO THE PLACEMENT DIAGRAM FOR MAJOR COMPONENTS PLACEMENT

NOTE ON SCSI ROUTING RULES:

1

--> SCSI SIGNALS ARE NAMED SCSI_D_*. THERE ARE 27 DIFFERENTIAL PAIRS.
THEY HAVE FIRST PRIORITY WHEN ROUTING.

--> AVOID VIAS WHENEVER POSSIBLE. USE THE SAME NUMBER OF VIAS BETWEEN PAIRS IF UNAVOIDABLE.

--> ROUTE SCSI_D_SREQ* AND SCSI_D_SACK* FIRST. ISOLATION FROM OTHER PAIRS IS 1.5X (22MIL) SINCE THEY ARE
MORE SUSCEPTIBLE TO CROSSTALK.

--> TRY TO ROUTE ALL THE ± DIFFERENTIAL SIGNALS ON INNER LAYERS (INNER1 & INNER2) IF POSSIBLE
AS EDGE COUPLED DIFFERENTIAL PAIRS.

--> ALL SCSI SIGNALS SHALL BE LENGTH MATCHED TO WITHIN 100MILS ~17PS WITHIN BUS AND VARIATION

WITHIN PAIR SHALL BE < 5 MILS. RULE FILE WILL BE PROVIDED TO ACHIEVE THIS.

--> CONNECTOR LENGTH WILL BE COMPENSATED ON THE DC TRACE LENGTH. RULE FILE WILL BE PROVIDED TO ACHIEVE THIS.

--> SCSI TRACE WIDTH AND SPACING MUST BE MAINTAINED AS IN THE TABLE. THE ONLY ACCEPTABLE DEVIATION
FROM THE SPACING IS WHERE THE SIGNALS MUST ROUTE THROUGH THE Z-PACK CONNECTOR

--> PLACE AND VERIFY SCSI TERMINATORS AT THE END OF BUS

--> MINIMIZE LENGTH OF STUB (SCSI_D_SD6+/-) & NUMBER OF VIAS TO GEM

GENERAL (NON-SCSI) ROUTING RULES:

--> FOR EXTERNAL LAYERS (TOP AND BOTTOM), USE 6 MIL TRACE, 6MIL SPACING FOR 60 OHM SIGNALS.

--> FOR INTERNAL LAYERS (IN1 AND IN2), USE 6 MIL TRACE, 12MIL SPACING FOR 60 OHM SIGNALS.

2

--> ALL NON-SCSI TRACES SHALL BE ISOLATED FROM LVD SCSI SIGNALS BY 50MILS.

--> CLOCK ROUTING: PLACE SERIAL TERMINATION RESISTORS R3 AND R25 WITHIN 250MIL MAX FROM SOURCE (U8).

--> CLOCK ROUTING: MATCH 20MCLK AND CPLD_CLK IN LENGTH. RULE FILE WILL BE PROVIDED TO ASSIST ACHIEVING THIS.

--> GEM ADDRESS AND DATA BUS (A* AND D*) SHOULD BE ROUTED USING THE FOLLOWING STRING ORDERING:
GEM359(U9) --> CPLD (U6) --> FLASH (U1)

--> I2C SIGNALS SHOULD BE ROUTED SERIALLY. THERE SHOULD NOT BE ANY LONG
STUBS OR BRANCHES.

TRY TO KEEP THESE SIGNALS AWAY FROM SCSI LVD SIGNALS.

STACKUP, ROUTING RULES

Bu
Z Type
Fr eq. ( MHz)
Target Z ( ohms)
Z tol erance

Fi ni shed Dielect Tolerance

Layer Lyr Type Cu Wt Thi ckness

1 Top 1.5 oz 2.1

Prepreg 10.0 +/-2 mil 4.3

2GND1 oz 1.4

Core 7.0 +/-1 mil 4.3

3IN1 1/2 oz 0.7

Pr e p r e g 4 0 . 0 REF 4 . 3

4IN2 1/2 oz 0.7

Core 7.0 +/-1 mil 4.3

5 3.3v 1 oz 1.4

Prepreg 10.0 +/-2 mil 4.3

Er

D

SCSI Clock

Differential

80

120

+/- 10

Trace/ Space / Trace/space_t o_other pair Layer Restrictions

5/9/5/30 (119.5) Ref L2 Allowed

GNDGND

4/10/4/15 (119.3) Ref L2&L5 Allowed

4/10/4/15 (119.3) Ref L2&L5 NOT ALLOWED

VCCVCC

1

2

POWER SIGNALS ROUTING RULES:

--> TRY TO USE ISLANDS FOR ALL POWER SIGNALS WITH NO POWER PLANE.
IF ISLANDS ARE NOT POSSIBLE, USE AT LEAST 30 MIL TRACES, I.E. VCC.

--> USE MULTIPLE VIAS WHERE THE POWER SIGNALS CHANGE LAYERS, I.E. FROM THE POWER SOURCE ON THE TOP/BOTTOM LAYER
TO THE POWER PLANE ON THE INNER LAYER

--> SHORTEN THE PATH FROM THE CAPACITOR PADS TO THE GROUND VIAS (10MIL < L < 20MIL)

AND KEEP THE TRACE AS WIDE AS POSSIBLE TO REDUCE INDUCTANCE.

--> FOR LARGE CERAMIC CAP PACKAGE, I.E. 1210 PACKAGE, USE MULTIPLE VIAS AND MAKE SURE THE TRACE

IS KEPT AS SHORT AS POSSIBLE.

--> LAYER 5 SHALL BE SOLID 3.3V PLANE WITH NO SPLITS AND LAYER 2 SHALL BE SOLID GND PLANE

3

--> DO NOT SHARE POWER OR GROUND VIAS FOR DECOUPLING CAPS.

Total Thickness 82.4 +/- 6mil

6 Bot 1.5 oz 2.1

5/9/5/30 (119.5) Ref L5 NOT ALLOWED

3

TESTABILITY AND TOOLING HOLE:

--> REFER TO SEPERATE TESTABILITY DOCUMENT TEST POINT PLACEMENT REQUIREMENT.

--> AT LEAST THREE TOOLING HOLES MUST BE INCLUDED ON THE BOARD.

DAUGHTER CARD PLACEMENT (NOT to scale)

SILKSCREEN:

--> ALL COMPONENTS SHOULD HAVE PIN 1 LABELED.

--> ON MANY PIN COMPONENTS AND CONNECTORS, THERE SHOULD BE A TICK MARK EVERY 10 PINS.

--> ALL REFERENCE DESIGNATORS SHALL BE VISIBLE WHEN THE PARTS ARE PLACED.

IMPEDANCE COUPON:

--> PLEASE FOLLOW THE SEPERATE IMPEDANCE COUPON DOCUMENT FOR SPECIFIC REQUIREMENT.

SCSIB

GEM359

DTRCONN

TOLERANCES

4

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

LVD SCSI TERMINATION B

SCSI Bus = 100 mils
Differential Pair = 5 mils
Stub Lengths (Bus) = 500 mils
Stub Lengths (Pair) = 100 mils

STACKUP AND ROUTING INFORMATION

COMPUTER
CORPORATION

TITLE

SCHEM, DTBRD, 1X2, PE2800

DWG NO.

DATE

C1325

12/19/2003

AUSTIN,TEXAS

REV.

SHEET

2 OF 8

X03

DCBA

4

ABC

D

+3.3V

+3.3V

+3.3V

4.7K

R4

4.7K

12

A1

J2

A1

B1

B1

C1

C1

A2

A2

B2

B2

C2

C2

A3

A3

B3

B3

C3

C3

A4

A4

B4

B4

C4

C4

A5

A5

B5

B5

C5

C5

A6

A6

B6

B6

C6

C6

A7

A7

B7

B7

C7

C7

A8

A8

B8

B8

C8

C8

A9

A9

B9

B9

C9

C9

A10

A10

B10

B10

C10

C10

A11

A11

B11

B11

C11

C11

A15

A15

B15

B15

C15

C15

A16

A16

B16

B16

C16

C16

A17

A17

B17

B17

C17

C17

A18

A18

B18

B18

C18

C18

A19

A19

B19

B19

C19

C19

A20

A20

B20

B20

C20

C20

A21

A21

B21

B21

C21

C21

A22

A22

B22

B22

C22

C22

A23

A23

B23

B23

C23

C23

A24

A24

B24

B24

C24

C24

A25

A25

B25

B25

C25

C25

RIGHT ANGLE RCPT

HM CONN

E10

D10

E11

D11

E15

D15

E16

D16

E17

D17

E18

D18

E19

D19

E20

D20

E21

D21

E22

D22

E23

D23

E24

D24

E25

D25

R22

4.7K

12

E1

E1

D1

D1

E2

E2

D2

D2

E3

E3

D3

D3

E4

E4

D4

D4

E5

E5

D5

D5

E6

E6

D6

D6

E7

E7

D7

D7

E8

E8

D8

D8

E9

E9

D9

D9

E10
D10

E11
D11

E15
D15

E16
D16

E17
D17

E18
D18

E19
D19

E20
D20

E21
D21

E22
D22

E23
D23

E24
D24

E25
D25

GEM_I2C_ADDR0

LEDFALT4_N
LEDONLN4_N

SCSI_D_SD10-

SCSI_D_SD10+

SCSI_D_SD8­SCSI_D_SD8+

SCSI_D_SREQ­SCSI_D_SREQ+

SCSI_D_SSEL­SCSI_D_SSEL+

SCSI_D_SRST­SCSI_D_SRST+

SCSI_D_SBSY­SCSI_D_SBSY+

HD_PRES3_N
HD_PRES4_N

SCSI_D_SDP0­SCSI_D_SDP0+

SCSI_D_SD6­SCSI_D_SD6+

SCSI_D_SD4­SCSI_D_SD4+

SCSI_D_SD2­SCSI_D_SD2+

SCSI_D_SD0­SCSI_D_SD0+

SCSI_D_SD15­SCSI_D_SD15+

SCSI_D_SD13­SCSI_D_SD13+

HD_PRES1_N

LEDONLN0_N
I2C1_CLK_DC_R

LEDFALT0_N
I2C1_SDA_DC_R

JTAG_TDO
IPMB_RST_N

+5V

4

7
7

6
6

6
6

4,6
4,6

4,6
4,6

4,6
4,6

4,6
4,6

4
4

4,6
4,6

4,6
4,6

4,6
4,6

4,6
4,6

4,6
4,6

6
6

6
6

4

7

7

7
7

R51

NP

12

0-5%

R50

NP

12

0-5%

+3.3V

I2C1_CLK_DC

I2C1_SDA_DC

4,8

4,8

1

2

3

R24

1

3,4

7
7
5
7

4,7

4
4

4,6

6
6

4
6
6

4,6
4,6

4,6
4,6

4,6
4,6

2

3

+3.3V

+5V

4,6
4,6

4,6
4,6

4,6
4,6
4,7

4,6
4,6

3,4

4,6
4,6

4,6
4,6

4,8

4,8

6
6

6
6

6
6

4

7
7

7
7
7
4
4
4
7
7
4

C2_PRES_N

LEDONLN3_N

LEDONLN2_N
DC_PWRGOOD
LEDONLN1_N

CONNB_PRES_N

CONNA_PRES_N
C2_HAS_ID_0_N

SCSI_D_DIFFSENS
SCSI_D_SD11+
SCSI_D_SD11-

GEM_I2C_ADDR1

SCSI_D_SD9+
SCSI_D_SD9-

SCSI_D_SIO+
SCSI_D_SIO-

SCSI_D_SCD+
SCSI_D_SCD-

SCSI_D_SMSG+
SCSI_D_SMSG-

SCSI_D_SACK+
SCSI_D_SACK-

SCSI_D_SATN+
SCSI_D_SATN-

SCSI_D_SD7+
SCSI_D_SD7-

BUS_SPLIT_N

SCSI_D_SD5+
SCSI_D_SD5-

C2_PRES_N
SCSI_D_SD3+
SCSI_D_SD3-

SCSI_D_SD1+

SCSI_D_SD1-

SCSI_D_SDP1+

SCSI_D_SDP1-

SCSI_D_SD14+

SCSI_D_SD14-

SCSI_D_SD12+

SCSI_D_SD12-

HD_PRES0_N

PCI_RESET_N

JTAG_TMS
ISO_IPMB_DATA
ISO_IPMB_CLK

JTAG_TCK

JTAG_TDI

LEDFALT2_N

DC_SERIAL_ID_LATCH

DC_SERIAL_ID_DATA

DC_SERIAL_ID_CLOCK

LEDFALT3_N

LEDFALT1_N

HD_PRES2_N

12

6/12/03: Match Pin Out Ver 2.0

C17

12

22uF 10V

12

C2

12

C5

0.1uF 16V

C18

0.1uF 16V

4

12

C16

22uF 10V

12

0.1uF 16V

BKPLN/DTR MATING CONNECTOR

COMPUTER
CORPORATION

TITLE

AUSTIN,TEXAS

4

SCHEM, DTBRD, 1X2, PE2800

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

DWG NO.

DATE

C1325

12/19/2003

SHEET

REV.

3 OF 8

X03

DCBA