MSI MS-9575 Schematic 0A

ABC

D

REVISIONS

REV

X00 INITIAL PROTOTYPE BUILD
X01 PROTOTYPE UNIT TEST BUILD

IPMB BUS

X02 PROTOTYPE PRODUCT TEST BUILD

PRODUCT TEST BUILDX03

PRIVATE I2C BUS

1

DESCRIPTIONECO DATE

7/31/03
9/18/03

12/08/03

12/19/03

CORVETTE 1x2/KOBUK DAUGHTER BOARD

APPROVED

7/31/03
9/18/03

12/10/03
12/19/03

1

JTAG

DEBUG PORTS

SMVU
PORTPORT

I2C0
PORT

20MHZ

OSC

MICROCONTROLLER INTERFACE

CLK

I2C1
PORT

FRU

PAGE

TABLE OF CONTENTS

DESCRIPTION

1

BLOCK DIAGRAM

2

STACKUP AND LAYOUT INSTRUCTION

3

BKPLN/DTR MATING CONNECTOR

4

GEM359

5

FLASH

SCSI LVD TERMINATION6

CPLD

7
8

SPARES, DEBUG PORTS, MISC

SCHEMATIC IS CONFIGURED TO USE
THE XLBOM UTILITY:
BUILD0 IS 5U 1X2 DC PROTOTYPE BUILD

2

FLASH

ROM

512KX8

DATA BUS

ADDRESS BUS

QLOGIC GEM359

SCSI ID6

DRIVE PRESENCE

BUILD1 IS 5U 1X2 DC PRODUCTION BUILD
BUILD2 IS 2U SCSI DC PROTOTYPE BUILD
BUILD3 IS 2U SCSI DC PRODUCTION BUILD

2

OUTPUT PORT

3

JTAG

LVD SCSI

3

SCSI BUS

CPLD

LOGIC

DRIVE POWER

TERMINATION

CONTROL

DAUGHTER

A CURRENT ISSUE OF THIS DRAWING MUST
INCLUDE A COPY OF THE FOLLOWING
ECO'S:
ECO

ECO
ECO
ECO
ECO
ECO
ECO

4

THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS
AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS
ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER
CORP., EXCEPT AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN
ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE
REPRODUCED IN WHOLE OR IN PART AND MUST BE RETURNED TO DELL

EXPORT RESTRICTION:

THE EXPORT OF THE INFORMATION, SCHEMATICS AND OTHER TECHNICAL DATA CONTAINED IN THIS DOCUMENT
IS CONTROLLED BY THE U.S. GOVERNMENT. THE EXPORT, DEEMED EXPORT OR OTHER TRANSFER OF THIS DATA
TO CERTAIN COUNTRIES AND INDIVIDUALS IS RESTRICTED. ANY TRANSFER, EXPORT OR REEXPORT, MUST BE
IN COMPLIANCE WITH THE U.S. EXPORT ADMINISTRATION REGULATIONS.

COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION
OF THE PURPOSE OF THE LOAN. NEITHER THIS ITEM NOR THE
INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS
NOT HAVING A NEED FOR SUCH USE OR DISCLOSURE CONSISTENT WITH
THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF
DELL COMPUTER CORPORATION.

PROPRIETARY NOTE

DRAWN

DESIGNED

CHECKED

APPROVED

APPROVED

APPROVED

APPROVED

RELEASED

ECO

TITLE

SCHEM, DTBRD, 1X2, PE2800

DWG NO.

DATE

C1325

12/19/2003

DATE
DATE
DATE
DATE
DATE
DATE
DATE
DATE

COMPUTER
CORPORATION
AUSTIN,TEXAS

REV.

SHEET

1 OF 8

DCBA

12-19-2003_13:41

X03

-02

4

ABC

s

s

%

NOTE ON COMPONENT PLACEMENT:

--> ALL COMPONENTS SHOULD BE PLACED ON THE TOP SIDE IF POSSIBLE

--> REFER TO THE PLACEMENT DIAGRAM FOR MAJOR COMPONENTS PLACEMENT

NOTE ON SCSI ROUTING RULES:

1

--> SCSI SIGNALS ARE NAMED SCSI_D_*. THERE ARE 27 DIFFERENTIAL PAIRS.
THEY HAVE FIRST PRIORITY WHEN ROUTING.

--> AVOID VIAS WHENEVER POSSIBLE. USE THE SAME NUMBER OF VIAS BETWEEN PAIRS IF UNAVOIDABLE.

--> ROUTE SCSI_D_SREQ* AND SCSI_D_SACK* FIRST. ISOLATION FROM OTHER PAIRS IS 1.5X (22MIL) SINCE THEY ARE
MORE SUSCEPTIBLE TO CROSSTALK.

--> TRY TO ROUTE ALL THE ± DIFFERENTIAL SIGNALS ON INNER LAYERS (INNER1 & INNER2) IF POSSIBLE
AS EDGE COUPLED DIFFERENTIAL PAIRS.

--> ALL SCSI SIGNALS SHALL BE LENGTH MATCHED TO WITHIN 100MILS ~17PS WITHIN BUS AND VARIATION

WITHIN PAIR SHALL BE < 5 MILS. RULE FILE WILL BE PROVIDED TO ACHIEVE THIS.

--> CONNECTOR LENGTH WILL BE COMPENSATED ON THE DC TRACE LENGTH. RULE FILE WILL BE PROVIDED TO ACHIEVE THIS.

--> SCSI TRACE WIDTH AND SPACING MUST BE MAINTAINED AS IN THE TABLE. THE ONLY ACCEPTABLE DEVIATION
FROM THE SPACING IS WHERE THE SIGNALS MUST ROUTE THROUGH THE Z-PACK CONNECTOR

--> PLACE AND VERIFY SCSI TERMINATORS AT THE END OF BUS

--> MINIMIZE LENGTH OF STUB (SCSI_D_SD6+/-) & NUMBER OF VIAS TO GEM

GENERAL (NON-SCSI) ROUTING RULES:

--> FOR EXTERNAL LAYERS (TOP AND BOTTOM), USE 6 MIL TRACE, 6MIL SPACING FOR 60 OHM SIGNALS.

--> FOR INTERNAL LAYERS (IN1 AND IN2), USE 6 MIL TRACE, 12MIL SPACING FOR 60 OHM SIGNALS.

2

--> ALL NON-SCSI TRACES SHALL BE ISOLATED FROM LVD SCSI SIGNALS BY 50MILS.

--> CLOCK ROUTING: PLACE SERIAL TERMINATION RESISTORS R3 AND R25 WITHIN 250MIL MAX FROM SOURCE (U8).

--> CLOCK ROUTING: MATCH 20MCLK AND CPLD_CLK IN LENGTH. RULE FILE WILL BE PROVIDED TO ASSIST ACHIEVING THIS.

--> GEM ADDRESS AND DATA BUS (A* AND D*) SHOULD BE ROUTED USING THE FOLLOWING STRING ORDERING:
GEM359(U9) --> CPLD (U6) --> FLASH (U1)

--> I2C SIGNALS SHOULD BE ROUTED SERIALLY. THERE SHOULD NOT BE ANY LONG
STUBS OR BRANCHES.

TRY TO KEEP THESE SIGNALS AWAY FROM SCSI LVD SIGNALS.

STACKUP, ROUTING RULES

Bu
Z Type
Fr eq. ( MHz)
Target Z ( ohms)
Z tol erance

Fi ni shed Dielect Tolerance

Layer Lyr Type Cu Wt Thi ckness

1 Top 1.5 oz 2.1

Prepreg 10.0 +/-2 mil 4.3

2GND1 oz 1.4

Core 7.0 +/-1 mil 4.3

3IN1 1/2 oz 0.7

Pr e p r e g 4 0 . 0 REF 4 . 3

4IN2 1/2 oz 0.7

Core 7.0 +/-1 mil 4.3

5 3.3v 1 oz 1.4

Prepreg 10.0 +/-2 mil 4.3

Er

D

SCSI Clock

Differential

80

120

+/- 10

Trace/ Space / Trace/space_t o_other pair Layer Restrictions

5/9/5/30 (119.5) Ref L2 Allowed

GNDGND

4/10/4/15 (119.3) Ref L2&L5 Allowed

4/10/4/15 (119.3) Ref L2&L5 NOT ALLOWED

VCCVCC

1

2

POWER SIGNALS ROUTING RULES:

--> TRY TO USE ISLANDS FOR ALL POWER SIGNALS WITH NO POWER PLANE.
IF ISLANDS ARE NOT POSSIBLE, USE AT LEAST 30 MIL TRACES, I.E. VCC.

--> USE MULTIPLE VIAS WHERE THE POWER SIGNALS CHANGE LAYERS, I.E. FROM THE POWER SOURCE ON THE TOP/BOTTOM LAYER
TO THE POWER PLANE ON THE INNER LAYER

--> SHORTEN THE PATH FROM THE CAPACITOR PADS TO THE GROUND VIAS (10MIL < L < 20MIL)

AND KEEP THE TRACE AS WIDE AS POSSIBLE TO REDUCE INDUCTANCE.

--> FOR LARGE CERAMIC CAP PACKAGE, I.E. 1210 PACKAGE, USE MULTIPLE VIAS AND MAKE SURE THE TRACE

IS KEPT AS SHORT AS POSSIBLE.

--> LAYER 5 SHALL BE SOLID 3.3V PLANE WITH NO SPLITS AND LAYER 2 SHALL BE SOLID GND PLANE

3

--> DO NOT SHARE POWER OR GROUND VIAS FOR DECOUPLING CAPS.

Total Thickness 82.4 +/- 6mil

6 Bot 1.5 oz 2.1

5/9/5/30 (119.5) Ref L5 NOT ALLOWED

3

TESTABILITY AND TOOLING HOLE:

--> REFER TO SEPERATE TESTABILITY DOCUMENT TEST POINT PLACEMENT REQUIREMENT.

--> AT LEAST THREE TOOLING HOLES MUST BE INCLUDED ON THE BOARD.

DAUGHTER CARD PLACEMENT (NOT to scale)

SILKSCREEN:

--> ALL COMPONENTS SHOULD HAVE PIN 1 LABELED.

--> ON MANY PIN COMPONENTS AND CONNECTORS, THERE SHOULD BE A TICK MARK EVERY 10 PINS.

--> ALL REFERENCE DESIGNATORS SHALL BE VISIBLE WHEN THE PARTS ARE PLACED.

IMPEDANCE COUPON:

--> PLEASE FOLLOW THE SEPERATE IMPEDANCE COUPON DOCUMENT FOR SPECIFIC REQUIREMENT.

SCSIB

GEM359

DTRCONN

TOLERANCES

4

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

LVD SCSI TERMINATION B

SCSI Bus = 100 mils
Differential Pair = 5 mils
Stub Lengths (Bus) = 500 mils
Stub Lengths (Pair) = 100 mils

STACKUP AND ROUTING INFORMATION

COMPUTER
CORPORATION

TITLE

SCHEM, DTBRD, 1X2, PE2800

DWG NO.

DATE

C1325

12/19/2003

AUSTIN,TEXAS

REV.

SHEET

2 OF 8

X03

DCBA

4

ABC

D

+3.3V

+3.3V

+3.3V

4.7K

R4

4.7K

12

A1

J2

A1

B1

B1

C1

C1

A2

A2

B2

B2

C2

C2

A3

A3

B3

B3

C3

C3

A4

A4

B4

B4

C4

C4

A5

A5

B5

B5

C5

C5

A6

A6

B6

B6

C6

C6

A7

A7

B7

B7

C7

C7

A8

A8

B8

B8

C8

C8

A9

A9

B9

B9

C9

C9

A10

A10

B10

B10

C10

C10

A11

A11

B11

B11

C11

C11

A15

A15

B15

B15

C15

C15

A16

A16

B16

B16

C16

C16

A17

A17

B17

B17

C17

C17

A18

A18

B18

B18

C18

C18

A19

A19

B19

B19

C19

C19

A20

A20

B20

B20

C20

C20

A21

A21

B21

B21

C21

C21

A22

A22

B22

B22

C22

C22

A23

A23

B23

B23

C23

C23

A24

A24

B24

B24

C24

C24

A25

A25

B25

B25

C25

C25

RIGHT ANGLE RCPT

HM CONN

E10

D10

E11

D11

E15

D15

E16

D16

E17

D17

E18

D18

E19

D19

E20

D20

E21

D21

E22

D22

E23

D23

E24

D24

E25

D25

R22

4.7K

12

E1

E1

D1

D1

E2

E2

D2

D2

E3

E3

D3

D3

E4

E4

D4

D4

E5

E5

D5

D5

E6

E6

D6

D6

E7

E7

D7

D7

E8

E8

D8

D8

E9

E9

D9

D9

E10
D10

E11
D11

E15
D15

E16
D16

E17
D17

E18
D18

E19
D19

E20
D20

E21
D21

E22
D22

E23
D23

E24
D24

E25
D25

GEM_I2C_ADDR0

LEDFALT4_N
LEDONLN4_N

SCSI_D_SD10-

SCSI_D_SD10+

SCSI_D_SD8­SCSI_D_SD8+

SCSI_D_SREQ­SCSI_D_SREQ+

SCSI_D_SSEL­SCSI_D_SSEL+

SCSI_D_SRST­SCSI_D_SRST+

SCSI_D_SBSY­SCSI_D_SBSY+

HD_PRES3_N
HD_PRES4_N

SCSI_D_SDP0­SCSI_D_SDP0+

SCSI_D_SD6­SCSI_D_SD6+

SCSI_D_SD4­SCSI_D_SD4+

SCSI_D_SD2­SCSI_D_SD2+

SCSI_D_SD0­SCSI_D_SD0+

SCSI_D_SD15­SCSI_D_SD15+

SCSI_D_SD13­SCSI_D_SD13+

HD_PRES1_N

LEDONLN0_N
I2C1_CLK_DC_R

LEDFALT0_N
I2C1_SDA_DC_R

JTAG_TDO
IPMB_RST_N

+5V

4

7
7

6
6

6
6

4,6
4,6

4,6
4,6

4,6
4,6

4,6
4,6

4
4

4,6
4,6

4,6
4,6

4,6
4,6

4,6
4,6

4,6
4,6

6
6

6
6

4

7

7

7
7

R51

NP

12

0-5%

R50

NP

12

0-5%

+3.3V

I2C1_CLK_DC

I2C1_SDA_DC

4,8

4,8

1

2

3

R24

1

3,4

7
7
5
7

4,7

4
4

4,6

6
6

4
6
6

4,6
4,6

4,6
4,6

4,6
4,6

2

3

+3.3V

+5V

4,6
4,6

4,6
4,6

4,6
4,6
4,7

4,6
4,6

3,4

4,6
4,6

4,6
4,6

4,8

4,8

6
6

6
6

6
6

4

7
7

7
7
7
4
4
4
7
7
4

C2_PRES_N

LEDONLN3_N

LEDONLN2_N
DC_PWRGOOD
LEDONLN1_N

CONNB_PRES_N

CONNA_PRES_N
C2_HAS_ID_0_N

SCSI_D_DIFFSENS
SCSI_D_SD11+
SCSI_D_SD11-

GEM_I2C_ADDR1

SCSI_D_SD9+
SCSI_D_SD9-

SCSI_D_SIO+
SCSI_D_SIO-

SCSI_D_SCD+
SCSI_D_SCD-

SCSI_D_SMSG+
SCSI_D_SMSG-

SCSI_D_SACK+
SCSI_D_SACK-

SCSI_D_SATN+
SCSI_D_SATN-

SCSI_D_SD7+
SCSI_D_SD7-

BUS_SPLIT_N

SCSI_D_SD5+
SCSI_D_SD5-

C2_PRES_N
SCSI_D_SD3+
SCSI_D_SD3-

SCSI_D_SD1+

SCSI_D_SD1-

SCSI_D_SDP1+

SCSI_D_SDP1-

SCSI_D_SD14+

SCSI_D_SD14-

SCSI_D_SD12+

SCSI_D_SD12-

HD_PRES0_N

PCI_RESET_N

JTAG_TMS
ISO_IPMB_DATA
ISO_IPMB_CLK

JTAG_TCK

JTAG_TDI

LEDFALT2_N

DC_SERIAL_ID_LATCH

DC_SERIAL_ID_DATA

DC_SERIAL_ID_CLOCK

LEDFALT3_N

LEDFALT1_N

HD_PRES2_N

12

6/12/03: Match Pin Out Ver 2.0

C17

12

22uF 10V

12

C2

12

C5

0.1uF 16V

C18

0.1uF 16V

4

12

C16

22uF 10V

12

0.1uF 16V

BKPLN/DTR MATING CONNECTOR

COMPUTER
CORPORATION

TITLE

AUSTIN,TEXAS

4

SCHEM, DTBRD, 1X2, PE2800

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

DWG NO.

DATE

C1325

12/19/2003

SHEET

REV.

3 OF 8

X03

DCBA

ABC

D0 strapping forces boot block only execution

NC_LED_STRB
CPU_STRB_N

7

WRITE_EN_N

7

FLASH_OE_N

5

FLASH_VPP_EN

7

5
5
5
5
5
5
5
5
5
5
5
5

3
3
3
3
3
4
4
4
4
4
4
4

3
3
3
3

3

3
3
4

4

7

3
4

7

4

NC_GEM_PIN_128

NC_GEM_PIN_83

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
GEM_PIN_112

D1

D2
D3
D4
D5
D6
D7

HD_PRES0_N
HD_PRES1_N
HD_PRES2_N
HD_PRES3_N
HD_PRES4_N
HD_PRES5_N
HD_PRES8_N
HD_PRES9_N
HD_PRES10_N
HD_PRES11_N
HD_PRES12_N
HD_PRES13_N

DC_SERIAL_ID_LATCH
DC_SERIAL_ID_DATA
DC_SERIAL_ID_CLOCK

CONNA_PRES_N
CONNB_PRES_N
C2_HAS_ID_0_N

GEM_I2C_ADDR0
GEM_I2C_ADDR1
GEM_I2C_ADDR2
NC_GEM_PIN_126
RSVD_SYS_ID3
BUS_SPLIT_N

EXT_INT_N

NC_GEM_PIN_48
NC_GEM_PIN_41
NC_GEM_PIN_52
NC_GEM_PIN_55
NC_GEM_PIN_58
NC_GEM_PIN_63
NC_GEM_PIN_80
NC_GEM_PIN_76

GEM_SELF_RESET_N
C2_PRES_N
UNIQUE_ID

SLOW_CLK
NC_GEM_PIN_132
NC_GEM_PIN_131

20MCLK

I2C1_CLK_DC
I2C1_SDA_DC

ISO_IPMB_CLK
ISO_IPMB_DATA

1

R37

+3.3V

R6

12

12

+3.3V

NP

4.7K

5,7
5,7
5,7
5,7

2.7K-5%

5,7

D0

5,7
5,7
5,7
5,7
5,7
5,7
5,7

2

3,7

+3.3V

3,7

3

R18

4.7K

12

7

GEM_RESET_N

7

3,8

4.7K

3,8

3,8
3,8

R38

12

135

LED_STRB

136

CPU_STRB

142

PROM_WE

140

PROM_OE

139

PROM_VPPEN

16

A0

17

A1

18

A2

19

A3

64

A4

65

A5

22

A6

66

A7

67

A8

25

A9

26

A10

27

A11

134

A12

74

A13

75

A14

143

A15

112

GPIOB1[4]/A16

28

D0

29

D1

30

D2

31

D3

32

D4

33

D5

137

D6

138

D7

4

DEV_INS0

5

DEV_INS1

6

DEV_INS2

7

DEV_INS3

44

DEV_INS4

45

DEV_INS5

10

DEV_INS6

53

DEV_INS7

54

DEV_INS8

13

DEV_INS9

59

DEV_INS10

60

DEV_INS11

116

GPIOC0[0]

122

GPIOC0[1]/TACH_IN0

117

GPIOC0[2]

123

GPIOC0[3]/TACH_IN1

118

GPIOC0[4]

124

GPIOC0[5]/TACH_IN2

119

GPIOC1[0]

125

GPIOC1[1]

120

GPIOC1[2]

126

GPIOC1[3]/PMW0

121

GPIOC1[4]/TACH_IN3

127

GPIOC1[5]

92

GPIOB1[5]/EXT_INT

128

GPIOB1[6]/PWM1

48

GPIO_A[00]

41

GPIO_A[01]

52

GPIO_A[02]

55

GPIO_A[03]

58

GPIO_A[04]

63

GPIO_A[05]

80

GPIO_A[06]

76

GPIO_A[07]

83

GPIO_A[08]

95

GPIO_A[09]

99

GPIO_A[10]/PWM2

87

GPIO_A[11]

133

GPO[02]/TIMER_PULSE

132

GPO[01]/TRACE_NMI

131

GPO[00]/TRACE_SYNC

35

RESET

2

CLK

43

GPIO[13]/I2C1_SCL

42

GPIO[12]/I2C1_SDA

130

SCL

129

SDA

4

U9

DIFF_SENSE

GPIO_B1[7]/UART_DIN

EMUX/UART_DOUT

GEM359

GEM359

SUB=SUB*_5P116

VDD1
VDD2
VDD3
VDD4

SD0+
SD0­SD1+
SD1­SD2+
SD2­SD3+
SD3­SD4+
SD4­SD5+
SD5­SD6+
SD6­SD7+
SD7-

SPD0+
SPD0-

SATN+
SATN-

SBSY+
SBSY-

SACK+
SACK-

SRST+
SRST-

SMSG+
SMSG-

SSEL+
SSEL-

SCD+
SCD-

SREQ+
SREQ-

SIO+
SIO-

ID_ON0+
ID_ON0­ID_ON1+
ID_ON1-

RBIAS

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8

GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19

1
36
73
108

105
106
101
102
97
98
93
94
89
90
85
86
81
82
77
78

69
70

23
24

61
62

20
21

14
15

56
57

11
12

50
51

46
47

39
40

8
9
103
104

111
113

115
141

3
34
37
38
49
68
71
72
79
84
88
91
96
100
107
109
110
114
144

SCSI_D_SD0+
SCSI_D_SD0­SCSI_D_SD1+
SCSI_D_SD1­SCSI_D_SD2+
SCSI_D_SD2­SCSI_D_SD3+
SCSI_D_SD3­SCSI_D_SD4+
SCSI_D_SD4­SCSI_D_SD5+
SCSI_D_SD5­SCSI_D_SD6+
SCSI_D_SD6­SCSI_D_SD7+
SCSI_D_SD7-

SCSI_D_SDP0+
SCSI_D_SDP0-

SCSI_D_SATN+
SCSI_D_SATN-

SCSI_D_SBSY+
SCSI_D_SBSY-

SCSI_D_SACK+
SCSI_D_SACK-

SCSI_D_SRST+
SCSI_D_SRST-

SCSI_D_SMSG+
SCSI_D_SMSG-

SCSI_D_SSEL+
SCSI_D_SSEL-

SCSI_D_SCD+
SCSI_D_SCD-

SCSI_D_SREQ+
SCSI_D_SREQ-

SCSI_D_SIO+
SCSI_D_SIO-

GEM_IDON0+
GEM_IDON0-

GEM_IDON1+
GEM_IDON1-

SCSI_D_DIFFSENS
RBIAS-

UART_DIN

UART_DOUT

+3.3V

3,6
3,6
3,6
3,6
3,6
3,6
3,6
3,6
3,6
3,6
3,6
3,6
3,4,6
3,4,6
3,6
3,6

3,6
3,6

3,6
3,6

3,6
3,6

3,6
3,6

3,6
3,6

3,6
3,6

3,6
3,6

3,6
3,6

3,6
3,6

3,6
3,6

R66

12

1K-5%

3,6

C35

12

22uF 10V

R67

12

1K-5%

4
4

12

C4

0.1uF 16V

SCSI_D_SD6+
SCSI_D_SD6-

12

C7

R32

12

3.01K-1%

12

C3

0.1uF 16V

+3.3V

R47

3,4,6
3,4,6

12

C1

4.7K

0.1uF 16V

21

220

0.1uF 16V

12

+5V

21

220

R23

R5

P2

NP

34

SHROUDED

SUB1=SUB*_T1199

21

220

R58

21

GEM_I2C_ADDR2

RSVD_SYS_ID3

UART header

+5V

R31

12

8.2K-5%

UART_DOUT

UART_DIN

4

4

+3.3V

ROOM=GEM359

L1

21

FERRITE

1206

0.1uF 16V

2

C95

1

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

0.1uF 16V

2

C96

1

FIL20_VCC

NP

R48

12

8.2K-5%

RFIL20

U8

20.0000MHz

4

3.3V

VDD

1

ED

GND

2

OUT

3

R20MHZ

33-5%

33-5%

R3

R25

D

+3.3V

1

R62

R59

12

HD_PRES5_N

4

HD_PRES8_N

4

HD_PRES9_N

4

HD_PRES10_N

4

HD_PRES11_N

4

HD_PRES12_N

4

HD_PRES13_N

4

4
4

4.7K

4.7K
12

12

R61

R60

4.7K

4.7K
12

4.7K
12

12

ADD1=ADD*_C1324_PWB

4.7K

4.7K
12

2

R65

R64

R63

ADD2=ADD*_C1325_SCHEM
ADD3=ADD01_C1326_ASSY_DWG

ADD4=ADD23_F2805_ASSY_DWG
ADD5=ADD*_42753_REV
ADD6=ADD*_42610_BAR

Mechanical parts for 2U SCSI DC:

ADD7=ADD*_U4214_CAM

ADD8=ADD*_9908Y_SCR

3

64bit Unique ID

+3.3V

VR1

DS2401Z

NP

DATA

GND

41

21

CPLD_CLK

20MCLK

21

7

4

GEM359

TITLE

SCHEM, DTBRD, 1X2, PE2800

DWG NO.

DATE

C1325

12/19/2003

R57

4.7K

12

2

COMPUTER
CORPORATION
AUSTIN,TEXAS

SHEET

UNIQUE_ID

4 OF 8

REV.

4

4

X03

DCBA

ABC

D

1

4Mb Flash 512Kx8

1

+3.3V

+3.3V

16V-10%

4.7uF

21

C36

C8

R40

R41

4.7K

12

12

4.7K

12

0.1uF 16V

U1

VCC

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8A2

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14

VSS1
VSS2

NC1

NC2

NC3

NC4

NC5

37

29
31
33
35
38
40
42
44
3023
32
34
36
39
41
43
45

27
46

9
10
13
14
16

FLASH_PD_30

NC_29LV400_9
NC_29LV400_10
NC_29LV400_11
NC_29LV400_12
NC_29LV400_16

D0
D1
D2
D3
D4
D5
D6
D7

R8

220

21

4,7
4,7
4,7
4,7
4,7
4,7
4,7
4,7

+3.3V

A0

4,7

DC_PWRGOOD

3

1410U7

DC_PWRGOOD_BUF11

VHC14

+3.3V

U7

9148

VHC14

3.3V_PWRGOOD = FLASH RESET

RESET DELAY CIRCUIT

FLASH_RESET_N

16V-10%

4.7K

1000pF

5

12

R27

RESET_RC

12

C32

Rise time delay = R27 * C32

5146

+3.3V

U7

RESET_DC_BUF

+3.3V

3144

VHC14 VHC14

GEM_RESET_N = GEM, CPLD, SMVU RESET

= 4.7kohm * 1000pF
= 4.7 us

U7

CPLD_RESET_N

7

2

3

+3.3V

+3.3V

FLASH_RESET_N

4
4
4
4

FLASH_CE_N

FLASH_OE_N

A1

A2
A3
A4
A5
A6
A7
A8
A9
A10
A11

A12

A13

A14

A15

R15

21

FLASH_WE_N

FLASH_BYTE_N

BANK_SWITCH

FLASH_PU48

220

7
4
7

5

2

+3.3V

R19

NP

4,7
4,7
4,7

4.7K

12

R7

220

12

4
4
4
4
4
4
4
4

PU_RY_BY

26

CE

28

OE

11

WE

47

BYTE

12

RESET

15

RY/BY

25

A0

24

A1

22

A3

21

A4

20

A5

19

A6

18

A7

8

A8

48
17

7
6
5
4
3

2

1

A9
A10
A11
A12
A13
A14
A15
A16
A17

DQ15/A-1

29LV400

SUB=SUB*_C3126

3

U7

BLANK P/N FOR 3.3V DEVICE = J1202

SOCKET P/N = 8M346

PROG. P/N = C3126

DSK/PROG P/N = C3128

7414_IN

21

220

R1

131412

VHC14

U7

1142

VHC14

NC_7414_12

NC_7414_8

C19

12

0.1uF 16V

FLASH & RESET

4

TITLE

COMPUTER
CORPORATION

AUSTIN,TEXAS

4

SCHEM, DTBRD, 1X2, PE2800

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

DWG NO.

DATE

C1325

12/19/2003

SHEET

REV.

5 OF 8

X03

DCBA

ABC

D

+3.3V

ROOM=TERMB

22uF 10V

12

1

C27

SCSI TERMINATION

1

0.1uF 16V

U3

3,4
3,4
3,4
3,4

3,4
3,4
3,4
3,4
3,4
3,4

3
3
3
3
3
3
3
3

SCSI_D_SSEL+
SCSI_D_SSEL­SCSI_D_SRST+
SCSI_D_SRST­SCSI_D_SD8+
SCSI_D_SD8­SCSI_D_SD10+
SCSI_D_SD10­SCSI_D_SD11+
SCSI_D_SD11­SCSI_D_SD9+
SCSI_D_SD9­SCSI_D_SIO+
SCSI_D_SIO­SCSI_D_SACK+
SCSI_D_SACK­SCSI_D_SATN+

SCSI_D_SATN-

2

L1+

3

L1-

4

L2+

5

L2-

6

L3+

7

L3-

8

L4+

9

L4-

14

L5+

15

L5-

16

L6+

17

L6-

18

L7+

19

L7-

20

L8+

21

L8-

22

L9+

23

L9-

SUB=SUB*_D1913

DISCNCT

DIFFSENSE

UCC5640PW

TRMPWR

DIFF_B

REG

GND

24

SCSITERM_DISCNCT

13

11

10

SCSI_D_DIFFSENS

B_DIFF_B

1

12

B_REG_0

2

3,4
3,4
3,4
3,4
3,4
3,4
3,4
3,4
3,4
3,4
3,4
3,4
3,4
3,4
3,4
3,4
3,4
3,4

SCSI_D_SD6+
SCSI_D_SD6­SCSI_D_SD7+
SCSI_D_SD7­SCSI_D_SMSG+
SCSI_D_SMSG­SCSI_D_SCD+
SCSI_D_SCD­SCSI_D_SREQ+
SCSI_D_SREQ­SCSI_D_SBSY+
SCSI_D_SBSY­SCSI_D_SDP0+
SCSI_D_SDP0­SCSI_D_SD5+
SCSI_D_SD5­SCSI_D_SD4+
SCSI_D_SD4-

14
15
16
17
18
19
20
21
22
23

2

U4

L1+

3

L1-

4

L2+

5

L2-

6

L3+

7

L3-

8

L4+

9

L4­L5+
L5­L6+
L6­L7+
L7­L8+
L8­L9+
L9-

DISCNCT

DIFFSENSE

TRMPWR

DIFF_B

REG

GND

24

13

11

10

1

12

B_REG_1

16V-10%

4.7uF

12

C30

C9

12

16V-10%

4.7uF

12

0.1uF 16V
21

NC_B_DS_1

C29

C10

51K-5%

R16

21

1

16V-10%

4.7uF

2

3,4

C28

2

UCC5640PW

SUB=SUB*_D1913

3

0.1uF 16V
21

C11

3

U5

TRMPWR

DIFF_B

REG

GND

24

13

11

10

1

12

B_REG_2

R2

220

21

NC_B_DS_2

16V-10%

4.7uF

12

C31

3,4
3,4
3,4
3,4
3,4
3,4
3,4
3,4

3
3
3
3
3
3
3
3

3
3

SCSI_D_SD12+
SCSI_D_SD12­SCSI_D_SD14+
SCSI_D_SD14­SCSI_D_SD15+
SCSI_D_SD15­SCSI_D_SDP1+
SCSI_D_SDP1­SCSI_D_SD0+
SCSI_D_SD0­SCSI_D_SD1+
SCSI_D_SD1­SCSI_D_SD2+
SCSI_D_SD2­SCSI_D_SD3+
SCSI_D_SD3­SCSI_D_SD13+
SCSI_D_SD13-

14
15
16
17
18
19
20
21
22
23

2

L1+

3

L1-

4

L2+

5

L2-

6

L3+

7

L3-

8

L4+

9

L4­L5+
L5­L6+
L6­L7+
L7­L8+
L8­L9+
L9-

DISCNCT

DIFFSENSE

UCC5640PW

SUB=SUB*_D1913

SCSI LVD TERMINATION

4

TITLE

COMPUTER
CORPORATION

AUSTIN,TEXAS

4

SCHEM, DTBRD, 1X2, PE2800

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

DWG NO.

DATE

C1325

12/19/2003

SHEET

REV.

6 OF 8

X03

DCBA

ABC

D

+3.3V

+3.3V

1

+3.3V

+3.3V

1

U6

5

VCCINT1

57

VCCINT2

98

VCCINT3

LEDONLN4_N

3

GEM_RESET_N

4

NC_LEDONLN5_N
NC_LEDFALT5_N
PCI_RESET_N

3

IPMB_RST_N

3

NC_CPLD_PIN25
LEDFALT4_N

3

CPLD_CLK

4

SERIAL_ID_DC_LATCH

7

NC_SHIFTY_BCKPLN_CLK
NC_LEDONLN9_N
SERIAL_ID_DC_DATA

7

SLOW_CLK

4

NC_LEDFALT8_N
NC_BP_REV_1
NC_LEDONLN8_N
SERIAL_ID_DC_CLOCK

7

2

3,4

4,5
4,5

3

3

3

3

3
5

3
3
3
3

NC_BP_REV_0
LEDFALT0_N
NC_BUS_SPLIT
LEDONLN0_N
NC_CPLD_PIN95
LEDONLN1_N
CONNB_PRES_N
LEDFALT1_N
CPLD_RESET_N
NC_CPLD_PIN1
LEDONLN2_N
LEDFALT2_N
LEDONLN3_N
LEDFALT3_N
A0
A1
NC_BP_REV_2
NC_CPLD_PIN92

NC_CPLDPIN2
NC_CPLDPIN7
NC_CPLDPIN19
NC_CPLDPIN24
NC_CPLDPIN34
NC_CPLDPIN43
NC_CPLDPIN46
NC_CPLDPIN73
NC_CPLDPIN80

16

IO1/FB1

13

IO2/FB1

18

IO3/FB1

20

IO4/FB1

14

IO5/FB1

15

IO6/FB1

25

IO7/FB1

17

IO8/FB1

22

IO9/GCK1

28

IO10/FB1

23

IO11/GCK2

33

IO12/FB1

36

IO13/FB1

27

IO14/GCK3

29

IO15/FB1

39

IO16/FB1

30

IO17/FB1

40

IO18/FB1

87

IO1/FB2

94

IO2/FB2

91

IO3/FB2

93

IO4/FB2

95

IO5/FB2

96

IO6/FB2

3

IO7/GTS1

97

IO8/FB2

99

IO9/GSR

1

IO10/FB2

4

IO11/GTS2

6

IO12/FB2

8

IO13/FB2

9

IO14/FB2

11

IO15/FB2

10

IO16/FB2

12

IO17/FB2

92

IO18/FB2

2

NC1

7

NC2

19

NC3

24

NC4

34

NC5

43

NC6

46

NC7

73

NC8

80

NC9

XC9572XL-TQ

IO1/FB3
IO2/FB3
IO3/FB3
IO4/FB3
IO5/FB3
IO6/FB3
IO7/FB3
IO8/FB3

IO9/FB3
IO10/FB3
IO11/FB3
IO12/FB3
IO13/FB3
IO14/FB3
IO15/FB3
IO16/FB3
IO17/FB3
IO18/FB3

IO1/FB4

IO2/FB4

IO3/FB4

IO4/FB4

IO5/FB4

IO6/FB4

IO7/FB4

IO8/FB4

IO9/FB4
IO10/FB4
IO11/FB4
IO12/FB4
IO13/FB4
IO14/FB4
IO15/FB4
IO16/FB4
IO17/FB4
IO18/FB4

SUB=SUB*_X2203

BLANK P/N for 3.3V 9572XL 7278P

Programmed part number: X2203

DSK/PROG P/N: U2930

VCCIO1
VCCIO2
VCCIO3
VCCIO4

TCK
TDI
TDO
TMS

26
38
51
88

41
32
49
50
35
53
54
37
42
60
52
61
63
55
56
64
58
59

65
67
71
72
68
76
77
70
66
81
74
82
85
78
89
86
90
79

48
45
83
47

NC_FIO_PRES_N

NC_SYS_ID2
FLASH_WE_N
NC_SMVU_WRITE_N
NC_LEDFALT9_N
SERIAL_ID_BP_LATCH
FLASH_VPP_EN
NC_SYS_ID3

NC_CTRLPNL_PRES_N

CPU_STRB_N
NC_CD_PRES_N
WRITE_EN_N
FLASH_CE_N
NC_FLP_PRES_N

NC_TOWER_CFG_N

GEM_SELF_RESET_N
SERIAL_ID_BP_DATA
SERIAL_ID_BP_CLOCK

BUS_SPLIT_N
A3
D2
D3
D0
NC_CPLD_PIN76
NC_SYS_ID1

D1
A2
D7
NC_SYS_ID0
D6
NC_SHIFTY_BCKPLN_DATA_UP
D4
EXT_INT_N
NC_SHIFTY_BCKPLN_LTCH
NC_SHIFTY_DATA_DN

D5

CPLD_TCK
CPLD_TDI
CPLD_TDO
CPLD_TMS

R20

4.7K

12

5

7
4

4

4
5

4
7
7

3,4
4,5
4,5
4,5
4,5

4,5
4,5
4,5

4,5

4,5
4

4,5

7
7
7
7

7

7

7

SERIAL_ID_DC_LATCH

SERIAL_ID_DC_DATA

SERIAL_ID_DC_CLOCK

R29

12

4.7K

R39

12

4.7K

R42

4.7K

12

+3.3V

7

7

7

SERIAL_ID_BP_LATCH

SERIAL_ID_BP_DATA

SERIAL_ID_BP_CLOCK

R49

12

4.7K

R46

12

12

12

R28

JTAG_TDI

3

JTAG_TMS

3

12

0-5%

R34

12

0-5%

R26

12

CPLD_TCK

7

CPLD_TDO

7

CPLD_TDI

7

CPLD_TMS

7

R35

0-5%

R36

0-5%

+3.3V

4.7K

4.7K

NP

R43

4.7K

12

JTAG_TDO

J1

1
2
3
4
5
6

JTAG_TCK

2

3

3

3

+3.3V

4

C26

12

C25

12

0.1uF 16V

C24

12

0.1uF 16V

C23

12

0.1uF 16V

C14

0.1uF 16V

12

0.1uF 16V

C13

12

C15

12

0.1uF 16V

0.1uF 16V

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

TITLE

SCHEM, DTBRD, 1X2, PE2800

DWG NO.

DATE

C1325

12/19/2003

COMPUTER
CORPORATION

AUSTIN,TEXAS

REV.

SHEET

7 OF 8

4

X03

DCBA

ABC

D

SCHEMATICS REV CHANGE TRACKER

X00-01 Initial ECAD schematics release
X00-02 Page 8, remove debug header J3 because no space on the board on 5/19/03

X00-03 Page 3 and 5, change 1x2_RESET_N to DC_PWRGOOD on 5/19/03

Power Connections per SI request (VOLTAGE = XX)

1

+3.3V

VOLTAGE=3.3

VOLTAGE=0

2

+5V

VOLTAGE=5

3,4,8

3,4,8

I2C1_SDA_DC

I2C1_CLK_DC
NC_KEY_I2C1

P1

1
2
3
4

2.5mm

SHROUDED

NP13

X00-04 Page 4, changed UART header to TH shrouded header and added p.u. on UART_DIN on 5/20/03
X00-05 Page 6, changed SCSI terminators DPN to D1913 on 5/21/03
X00-06 Page 4, removed 3.3V LDO on 5/22/03

X00-07, changes based on CDR on 5/27/03

X00-08, page 6 pin swap on SCSI terminators to make routing easier on 6/3/03

On page 4, change unique ID chip pull up to 3.3V on 6/3/03
On page 5, added decoupling cap for U7 on 6/3/03
On page 8, Removed SMVU since space on DC is very tight on 6/3/03
On page 4, Removed R34 since it is not needed on 6/3/03

X00-09, On page 3,4, changed DC_PRES_N to C2_PRES_N on 6/18/03

X00-10, On page 3, Added 0ohm isolation resistors on private I2C bus on 7/9/03

X00-11, On page 3, No-poped 0ohm isolation resistors on private I2C bus on 7/10/03

X00-12, On page 4, Changed screw part number from 16WPR to 9908Y on 7/28/03

9/4/03: X01-01 changes, see R:\Schematic_Projects\PowerEdge\Uniplanar\Backplanes\MB-1x2_DC\doc\1x2DC-SCH-CHANGE-TRACKING.xls

12/3/03: X02-01 changes, see R:\Schematic_Projects\PowerEdge\Uniplanar\Backplanes\MB-1x2_DC\doc\1x2DC-SCH-CHANGE-TRACKING.xls

12/17/03: X03-01 changes, see R:\Schematic_Projects\PowerEdge\Uniplanar\Backplanes\MB-1x2_DC\doc\1x2DC-SCH-CHANGE-TRACKING.xls

On Page 7, removed CONNA_PRES_N from U6.1 (CPLD) on 6/18/03

On page 4, Changed GEM pull up resistor R6 to pin 112 on 7/9/03
General, Changed 8.2K pull up resistors to 4.7K on 7/9/03

On page 6, Removed L2 for TERMPWR to connect directly to 3.3V on 7/10/03
On page 4, Removed C6 on 7/10/03
On page 8, Added IPMB debug header on IPMB bus on 7/11/03

On page 4, No install UART header P2 on 7/28/03 since it created mechanical interference.

On page 4, No install JTAG header J1 on 7/28/03 since it created mechanical interference.
On page 8, Removed mounting hole per mechanical request on 7/29/03

On page 5, removed socket from the BOM on 7/29/03 since it interfere with mechanical parts.

1

2

+3.3V

+3.3V

3

+3.3V

+3.3V

LYR3

1

RX

3

RY

NP*

ZDI4PINS2R

COUPON TEST

LYR4

1

RX

3

RY

NP*

ZDI4PINS2R

COUPON TEST

120D_L3+

2

+

120D_L3-

4

-

2

120D_L4+

+

120D_L4-

4

-

4

ZEP3_P
1

1

NP*

ZEP

COUPON TEST

ZEP3_N
1

1

NP*

ZEP

COUPON TEST

ZEP4_P

1

1

NP*

ZEP

COUPON TEST

ZEP4_N
1

1

NP*

ZEP

COUPON TEST

NP

R13

4.7K

12

NP

R9

220

21

R11

R12

4.7K
12

12

FRU_ADDR0

FRU_ADDR1

FRU_ADDR2

NP

220

R14

R10

21

21

4.7K

220

ADDRESS = 1010101X =AAh

U2

81

VCCA0

27

A1 WC

36

A2 SCL

4

GND

SUB*_9K205

24C02

SDA

5

R17

21

220

C34

12

0.1uF 16V

3,4,8

3,4,8

I2C1_CLK_DC
I2C1_SDA_DC

I2C1_SDA_DC

I2C1_CLK_DC

3,4,8
3,4,8

+3.3V

R44

4.7K

12

R45

4.7K

12

3,4

3,4

ISO_IPMB_CLK

ISO_IPMB_DATA

+3.3V

NP

R30

4.7K

12

NP

R33

4.7K

12

SPARES, DEBUG PORTS, MISC

COMPUTER
CORPORATION

TITLE

AUSTIN,TEXAS

3

4

SCHEM, DTBRD, 1X2, PE2800

PROPRIETARY NOTE: THIS ITEM IS THE PROPERTY OF DELL COMPUTER CORP. AUSTIN, TEXAS AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS ITEM MAY NOT BE TRANSFERRED FROM THE CUSTODY OF DELL COMPUTER CORP. EXCEPT
AS AUTHORIZED BY DELL COMPUTER CORP., AND THEN ONLY BY WAY OF LOAN FOR LIMITED PURPOSES. IT MUST NOT BE REPRODUCED IN WHOLE
OR IN PART AND MUST BE RETURNED TO DELL COMPUTER CORP. UPON REQUEST AND IN ALL EVENTS UPON COMPLETION OF THE PURPOSE OF THE
LOAN. NEITHER THIS ITEM OR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO PERSONS NOT HAVING A NEED FOR SUCH
USE OR DISCLOSURE CONSISTENT WITH THE PURPOSE OF THE LOAN WITHOUT THE PRIOR WRITTEN CONSENT OF DELL COMPUTER CORPORATION.

DWG NO.

DATE

C1325

12/19/2003

SHEET

REV.

8 OF 8

X03

DCBA