PAGE11.Remove 1'st TMDS & Hotplug
PAGE11.Net name change from 5v_ENBL* to EN_FBVDD*
PAGE13.Remove feature connector
3
PAGE13.Change input power from MIOA_2V5 to A3V3
3
PAGE15.Add Scart TV chip CX25874/5
PAGE15.Add Scart TV connector
PAGE16.Remove EXT 12pin PVA connector
PAGE17.Add 0 ohm to OPT GPIO 8 or 7 to control EXTENSE
pin
4
PAGE20.Change all power(NVVDD,FBVDD/Q,A3V3,5V & ADD EXT PWR)
ALL NVIDIA DESIGN SPECIFICAT IONS, R EFERENC E SPECIFIC ATION S, REFER ENCE BOAR DS, FILES, DRAWING S, DIAG NOST ICS, LIST S AND O THER DO CUMEN TS OR I NFO RMATIO N (T OGET HER AND SEPAR ATELY, 'MAT ERIALS') ARE BEING PROVIDED 'AS IS'. TH E MA T ER IA L S MA Y
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTI ES, EXPRESSED, IM PLIED, STAT UTO RY OR O THER WISE WITH R ESPECT TO THE MAT ERIALS O R O T H ER W ISE, AN D EXPRESSLY DISCLAIM S ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FRO M A COU RSE OF DEALING , TRADE U SAGE, T RADE PRACT ICE, O R INDUSTRY STANDARDS.
ABDFH
CON_PCI_EXPRESS
SMCLK
SMDAT
PERST
REFCLK
REFCLK
PERP0
PERN0
PETP0
PETN0
PERP1
PERN1
PETP1
PETN1
PERP2
PERN2
PETP2
PETN2
PERP3
PERN3
PETP3
PETN3
PERP4
PERN4
PETP4
PETN4
PERP5
PERN5
PETP5
PETN5
PERP6
PERN6
PETP6
PETN6
PERP7
PERN7
PETP7
PETN7
PERP8
PERN8
PETP8
PETN8
PERP9
PERN9
PETP9
PETN9
PERP10
PERN10
PETP10
PETN10
PERP11
PERN11
PETP11
PETN11
PERP12
PERN12
PETP12
PETN12
PERP13
PERN13
PETP13
PETN13
PERP14
PERN14
PETP14
PETN14
PERP15
PERN15
PETP15
PETN15
{NAME}
C915
C950
.01UF
?
?
?
0402
COMMON
NTP_JTAG_TRST*
B9
NTP_JTAG_TCLK
A5
JTAG_TDI_TDO
A6
JTAG_TDI_TDO
A7
NTP_JTAG_TMS
A8
NTP_PEX_SMCLK
B5
NTP_PEX_SMDAT
B6
NTP_PEX_WAKE*
B11
WAKE
PEX_PWRGD*
A11
A13
A14
PEX_TXX0
A16
PEX_TXX0*
A17
PEX_RX0
B14
PEX_RX0*
B15
PEX_TXX1
A21
PEX_TXX1*
A22
PEX_RX1
B19
PEX_RX1*
B20
PEX_TXX2
A25
PEX_TXX2*
A26
PEX_RX2
B23
PEX_RX2*
B24
PEX_TXX3
A29
PEX_TXX3*
A30
PEX_RX3
B27
PEX_RX3*
B28
PEX_TXX4
A35
PEX_TXX4*
A36
PEX_RX4
B33
PEX_RX4*
B34
PEX_TXX5
A39
PEX_TXX5*
A40
PEX_RX5
B37
PEX_RX5*
B38
PEX_TXX6
A43
PEX_TXX6*
A44
PEX_RX6
B41
PEX_RX6*
B42
PEX_TXX7
A47
PEX_TXX7*
A48
PEX_RX7
B45
PEX_RX7*
B46
PEX_TXX8
A52
PEX_TXX8*
A53
PEX_RX8
B50
PEX_RX8*
B51
PEX_TXX9
A56
PEX_TXX9*
A57
PEX_RX9
B54
PEX_RX9*
B55
PEX_TXX10
A60
PEX_TXX10*
A61
PEX_RX10
B58
PEX_RX10*
B59
PEX_TXX11
A64
PEX_TXX11*
A65
PEX_RX11
B62
PEX_RX11*
B63
PEX_TXX12
A68
PEX_TXX12*
A69
PEX_RX12
B66
PEX_RX12*
B67
PEX_TXX13
A72
PEX_TXX13*
A73
PEX_RX13
B70
PEX_RX13*
B71
PEX_TXX14
A76
PEX_TXX14*
A77
PEX_RX14
B74
PEX_RX14*
B75
PEX_TXX15
A80
PEX_TXX15*
A81
PEX_RX15
B78
PEX_RX15*
B79
C93
10UF
.1UF
?
?
?
?
?
?
0603
1206
COMMON
COMMON
{NAME}
{NAME}
5
3.5MIL
1
2
PEX_REFCLK
PEX_REFCLK*
C930
C928
C926
C924
C922
C920
C918
3
U_AND_2IN
{NAME}
C948
C946
C944
C942
C940
C938
C936
C934
C932
COMMON
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
U819
R2075
R2076
0402
?
R2072
0402 COMMON
R2073
0402 COMMON
C947
C945
C943
C941
C939
C937
C935
C933
C931
C929
C927
C925
C923
C921
C919
C917
0402
?
200
NS
PEX_TEST_PLLCLK_OUT
PEX_TEST_PLLCLK_OUT_N
0
0
?
?
.1UF
.1UF
???0402
.1UF
???0402
.1UF
???0402
.1UF
???0402
.1UF
???0402
.1UF
???0402
.1UF
???0402
.1UF
???0402
.1UF
???0402
.1UF
???0402
.1UF
???0402
.1UF
???0402
.1UF
???0402
.1UF
???0402
.1UF
???0402
100
COMMON
TP_PEXCAPD_VDDQ
TP_PEXCALPD_GND
R102
0402
3.5MIL
3.5MIL
???0402
3.5MIL
3.5MIL
3.5MIL
3.5MIL
3.5MIL
3.5MIL
3.5MIL
3.5MIL
3.5MIL
3.5MIL
3.5MIL
3.5MIL
3.5MIL
3.5MIL
3.5MIL
3.5MIL
3.5MIL
3.5MIL
3.5MIL
3.5MIL
3.5MIL
3.5MIL
3.5MIL
3.5MIL
3.5MIL
3.5MIL
3.5MIL
3.5MIL
3.5MIL
3.5MIL
?
NV43CLK_REF
NV43CLK_REF*
PEX_TX0
PEX_TX0*
COMMON
PEX_TX1
PEX_TX1*
COMMON
PEX_TX2
PEX_TX2*
COMMON
PEX_TX3
PEX_TX3*
COMMON
PEX_TX4
PEX_TX4*
COMMON
PEX_TX5
PEX_TX5*
COMMON
PEX_TX6
PEX_TX6*
COMMON
PEX_TX7
PEX_TX7*
COMMON
PEX_TX8
PEX_TX8*
COMMON
PEX_TX9
PEX_TX9*
COMMON
PEX_TX10
PEX_TX10*
COMMON
PEX_TX11
PEX_TX11*
COMMON
PEX_TX12
PEX_TX12*
COMMON
PEX_TX13
PEX_TX13*
COMMON
PEX_TX14
PEX_TX14*
COMMON
PEX_TX15
PEX_TX15*
COMMON
4
SC70-5
???0402
???0402
???0402
???0402
???0402
???0402
???0402
???0402
???0402
???0402
???0402
???0402
???0402
???0402
???0402
???0402
C2042
1UF
?
?
?
0402
COMMON
3.5MIL
3.5MIL
3.5MIL
3.5MIL
COMMON
3.5MIL
3.5MIL
3.5MIL
3.5MIL
COMMON
3.5MIL
3.5MIL
3.5MIL
3.5MIL
COMMON
3.5MIL
3.5MIL
3.5MIL
3.5MIL
COMMON
3.5MIL
3.5MIL
3.5MIL
3.5MIL
COMMON
3.5MIL
3.5MIL
3.5MIL
3.5MIL
COMMON
3.5MIL
3.5MIL
3.5MIL
3.5MIL
COMMON
3.5MIL
3.5MIL
3.5MIL
3.5MIL
COMMON
3.5MIL
3.5MIL
3.5MIL
3.5MIL
COMMON
3.5MIL
3.5MIL
3.5MIL
3.5MIL
COMMON
3.5MIL
3.5MIL
3.5MIL
3.5MIL
COMMON
3.5MIL
3.5MIL
3.5MIL
3.5MIL
COMMON
3.5MIL
3.5MIL
3.5MIL
3.5MIL
COMMON
3.5MIL
3.5MIL
3.5MIL
3.5MIL
COMMON
3.5MIL
3.5MIL
3.5MIL
3.5MIL
COMMON
3.5MIL
3.5MIL
3.5MIL
3.5MIL
COMMON
3.5MIL
3.5MIL
R2074
10K
0402
COMMON
?
{NAME}
AH15
AG12
AH13
200
NS
AM12
AM11
AH14
AJ14
AJ15
AK15
AK13
AK14
AH16
AG16
AM14
AM15
AG17
AH17
AL15
AL16
AG18
AH18
AK16
AK17
AK18
AJ18
AL17
AL18
AJ19
AH19
AM18
AM19
AG20
AH20
AK19
AK20
AG21
AH21
AL20
AL21
AK21
AJ21
AM21
AM22
AJ22
AH22
AK22
AK23
AG23
AH23
AL23
AL24
AK24
AJ24
AM24
AM25
AJ25
AH25
AK25
AK26
AH26
AG26
AL26
AL27
AK27
AJ27
AM27
AM28
AJ28
AH27
AL28
AL29
U11A
BGA820_P10_33X33MM
COMMON
1/14 PCI_EXPRESS
PEX_RST
RFU
RFU
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT
PEX_REFC LK
PEX_REFC LK
PEX_TX0
PEX_TX0
PEX_RX0
PEX_RX0
PEX_TX1
PEX_TX1
PEX_RX1
PEX_RX1
PEX_TX2
PEX_TX2
PEX_RX2
PEX_RX2
PEX_TX3
PEX_TX3
PEX_RX3
PEX_RX3
PEX_TX4
PEX_TX4
PEX_RX4
PEX_RX4
PEX_TX5
PEX_TX5
PEX_RX5
PEX_RX5
PEX_TX6
PEX_TX6
PEX_RX6
PEX_RX6
PEX_TX7
PEX_TX7
PEX_RX7
PEX_RX7
PEX_TX8
PEX_TX8
PEX_RX8
PEX_RX8
PEX_TX9
PEX_TX9
PEX_RX9
PEX_RX9
PEX_TX10
PEX_TX10
PEX_RX10
PEX_RX10
PEX_TX11
PEX_TX11
PEX_RX11
PEX_RX11
PEX_TX12
PEX_TX12
PEX_RX12
PEX_RX12
PEX_TX13
PEX_TX13
PEX_RX13
PEX_RX13
PEX_TX14
PEX_TX14
PEX_RX14
PEX_RX14
PEX_TX15
PEX_TX15
PEX_RX15
PEX_RX15
U_GPU_G3
ASSEMBLY
PAGE DETAI L
VALUES TBD
Place near balls
600mA
PEX_IO_VDD
C846
C845
.022UF
.022UF
?
AD23
PEX_IOVD D
AF23
PEX_IOVD D
AF24
PEX_IOVD D
AF25
PEX_IOVD D
AG24
PEX_IOVD D
AG25
PEX_IOVD D
AC16
PEX_IOVDD Q
AC17
PEX_IOVDD Q
AC21
PEX_IOVDD Q
AC22
PEX_IOVDD Q
AE18
PEX_IOVDD Q
AE21
PEX_IOVDD Q
AE22
PEX_IOVDD Q
AF12
PEX_IOVDD Q
AF18
PEX_IOVDD Q
AF21
PEX_IOVDD Q
AF22
PEX_IOVDD Q
K16
VDD
K17
VDD
N13
VDD
N14
VDD
N16
VDD
N17
VDD
N19
VDD
P13
VDD
P14
VDD
P16
VDD
P17
VDD
P19
VDD
R16
VDD
R17
VDD
T13
VDD
T14
VDD
T15
VDD
T18
VDD
T19
VDD
U13
VDD
U14
VDD
U15
VDD
U18
VDD
U19
VDD
V16
VDD
V17
VDD
W13
VDD
W14
VDD
W16
VDD
W17
VDD
W19
VDD
Y13
VDD
Y14
VDD
Y16
VDD
Y17
VDD
Y19
VDD
Y20
VDD
P20
VDD_LP
T20
VDD_LP
T23
VDD_LP
U20
VDD_LP
U23
VDD_LP
W20
VDD_LP
NVVDD_SENSE
N20
VDD_SENSE
GND_SENSE
M21
GND_SENSE
AC11
VDD33
AC12
VDD33
AC24
VDD33
AD24
VDD33
AE11
VDD33
AE12
VDD33
H7
VDD33
J7
VDD33
K7
VDD33
L10
VDD33
L7
VDD33
L8
VDD33
M10
VDD33
AF15
PEX_PLLAVDD
AE15
PEX_PLLDV D D
AE16
PEX_PLLGND
{NAME}
NTP_GPU_AM10_NC
AM8
NC
NTP_GPU_AM8_NC
AM9
NC
NTP_GPU_AM9_NC
B32
NC
NTP_GPU_B32_NC
J6
NC
BASE LEVEL GENERIC SCHEMATIC ONLY, COMMO N & NO _STUFF ASSEMBLY NO TES AN D BO M N O T F I N AL
PCI EXPRESS 16X, NVVDD DECOUPLING CAPS,PEX_IO VD D /Q DE C O UP LI N G C A PS
?
?
0402
COMMON
2A
PEX_IO_VDDQ
C849
.022UF
?
?
?
0402
COMMON
C747
0.47UF
?
?
?
0402
COMMON
C675
.1UF
?
?
?
0402
COMMON
C804
0.47UF
?
?
?
0402
COMMON
C773
0.47UF
?
?
?
0402
COMMON
VALUES TBD
R629
0402 COMMON
?
VDD33
PEX_PLL_VDD
0
?
?
?
0402
COMMON
VALUES TBD
Place near balls
C857
.022UF
?
?
?
0402
COMMON
C780
.1UF
?
?
?
0402
COMMON
C781
.1UF
?
?
?
0402
COMMON
C756
.1UF
?
?
?
0402
COMMON
C796
.1UF
?
?
?
0402
COMMON
C751
.001UF
?
?
?
0402
{NAME}
180mA
Place near balls
20mA
C842
4700PF
?
?
0402
COMMON
COMMON
Place near balls
C833
.1UF
?
0402
COMMON
EGC
C847
.01UF
?
?
?
0402
COMMON
Place near balls
OUT
Place near balls
C826
.1UF
?
?
?
0402
COMMON
C853
.1UF
?
?
?
0402
COMMON
??
?
Place Close to GPU
C848
.01UF
?
?
?
0402
COMMON
C786
0.47UF
?
?
?
0402
COMMON
C801
0.47UF
?
?
?
0402
COMMON
C798
.1UF
?
?
?
0402
COMMON
C762
.1UF
?
?
?
0402
COMMON
2.5G<> 22.2G<
C738
4700PF
?
?
?
0402
COMMON
C745
4700PF
?
?
?
0402
COMMON
C825
.01UF
?
?
?
0402
COMMON
C831
470PF
?
?
?
0402
COMMON
HGFEDCBA
?
COMMON0805
220R@100MHz
LB9
0805?COMMON
C2043
4.7UF
C96
?
?
4.7UF
?
?
C0805_67
?
COMMON
C0805_67
COMMON
C790
.1UF
?
?
?
0402
COMMON
C721
.022UF
?
?
?
0402
COMMON
C843
.022UF
?
?
?
0402
COMMON
Place Near BGA
150-220R@100MHz
LB524
C828
4.7UF
??
?
C0805_67
COMMON
?
?
C757
.1UF
?
?
?
0402
COMMON
C784
10UF
?
?
?
0805
COMMON
C742
10UF
?
?
?
0805
COMMON
LB532
120R@100MHz
COMMON
0603
{NAME}
{NAME}
C894
4.7UF
?
?
C0805_67
COMMON
C797
0.47UF
?
?
?
0402
COMMON
{NAME}
{NAME}
{NAME}
C734
1UF
?
?
?
0603
COMMON
?
00A
220
1
2
3
4
5
{NAME}
{NAME}
C908
2.2C> 21.3B<
10UF
?
?
?
0805
2.2C< 21.3G>
COMMON
{NAME}
C783
10UF
?
?
?
0805
COMMON
C659
.1UF
{NAME}
?
?
?
0402
COMMON
C769
.1UF
{NAME}
?
?
?
0402
COMMON
{NAME}
{NAME}
{NAME}
COMMON0603
{NAME}
C812
4.7UF
?
?
?
C0805_67
COMMON
2.3F> 22.2G<
{NAME}
NET
PEX_REFCLK
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
I think it can't cost down so much.I prefer not to change and it is safe.
PLACE close to G P U
{NAME}
4.1G<
4
4.2A<
R596
4.1G<
4.2D<
R599
4
100
100
?
?
0402
0402
COMMON
COMMON
FBA_REFCLK*
R593
R601
100
100
?
?
0402
0402
COMMON
COMMON
{NAME}
PLACE close to b a l l s
C689
.01UF
?
?
?
0402
COMMON
C710
.01UF
?
?
?
0402
COMMON
C692
.1UF
?
?
?
0402
COMMON
C685
.1UF
?
?
?
0402
COMMON
FB_DLLVDD
ON NV3x version's of G3
FB_DL LVDD will be routed on FB_PLLVDD
150-220R@100MHz
LB507
150-220R@100MHz
LB509
COMMON0603
COMMON0603
{NAME}
C674
1UF
?
?
?
0402
COMMON
C672
1UF
?
?
?
0402
COMMON
{NAME}
C662
4.7UF
?
?
?
C0805_67
COMMON
C654
4.7UF
?
?
?
C0805_67
COMMON
{NAME}
C740
10UF
?
?
?
0805
COMMON
PLACE MIDWAY BETWEEN GPU AND MEMORY
{NAME}
{NAME}
C597
10UF
?
?
?
0805
COMMON
MIN_LINE_WIDTHNET
4MIL10MIL
NET_SPACING_R U LE
10MIL
10MIL
10MIL4MIL
1
2
FBA_PLLVDD
FBA_PLLAVDD
C594
10UF
?
?
?
0805
COMMON
DIFFPAIR
FBA_REFCLK
IN
FBA_REFCLK*
IN
IN
IN
C856
10UF
?
?
?
0805
COMMON
{NAME}
PLACE NEAR GPU
{NAME}
R638
10K
?
0402
R640
COMMON
NS
3
10K
?
0402
FBA_CMD11
{NAME}
CKE St uff options for DDR3 configation for
on-die terminations at the memor y
IMPORTANT FOR POWER ON INITIALIZATION OF DDR3 MEMS
DDR3: DETERMINES THE ODT VALUE FOR ADDR AND CONTROL PINS
CKE = 0 --> ODT = ZQ/2
CKE = 1 --> ODT = ZQ
4
FBA_AVDD is TBD. This may not be hooked up on the Package.
U_GPU_G3
5
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ABDFH
Micro-Star Interna t i o nal Co. , L TD.
MS-8979 base on P216 Modify
Size Document NumberRev
Custom
Monday, August 23, 2004
EGC
Date:
Sheetof
00A
320
5 FrameBuffer: Partition A 8Mx32 BGA144 DDR3
A-CS0-LOW-32bit
U8E
BGA_DIAMOND144_P08_DDR_13MM_B2
{NAME}
FBAD[63..0]
FBADQM[7..0]
FBADQS_RN[7..0]
FBADQS_WP[7..0]
BGA144
COMMON
M5
RAS
N6
CAS
N9
WE
M10
CS
N2
A0
N3
A1
M3
A2
L3
A3
L12
A4
M12
A5
N12
A6
N13
A7
N11
A8
M11
A9
M4
A10
N4
A11
L9
NC/A<12>
N5
BA<0>
N10
BA<1>
L6
NC/BA<2>
M7
CKE
N7
CLK
N8
CLK
NC/RFU
E3
NC/RFU
E12
NC/RFU
M8
RESET
M6
M9
ZQ
F6
THERM
F7
THERM
F8
THERM
F9
THERM
G6
THERM
G7
THERM
G8
THERM
G9
THERM
H6
THERM
H7
THERM
H8
THERM
H9
THERM
J6
THERM
J7
THERM
J8
THERM
J9
THERM
U_MEM_ SD_DDR3_X32#3
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
1
2
3
4
5
ZQ = 6x desired output
DDR3:
impedence of DQ driver s
Impedence = 240 / 6 = 40 ohm