MSI MS-8832 Schematic 100

NV11, 1/2/4MX32 DDR, RGB, INTERNAL DVI-I, TV, AGP.

PCI DEVICE ID 0X0=0X112 FOR NV11.

4 4

01. List of Schematic sheets

02. HOST INTERFACE_NEW

03. FB(MEMORY)/NVXX DECOUPLING

04. NVXX BOOT STRAPS

05. DAC and MEDIA PORT

06. LOWER SDRAM FBI

07. BT & CH TV ENCODER

08. DFP/DVI/CLK_DVR

09. DC-DC CONVTR

3 3

STRAPS: AGP4X, SIDEBAND DIS, FAST WRITE ENA, ADP BIOS, NORMAL PCIAD, 14.318MHZ STRAP_RAM_TYPE [5:2]=1011-1MX32 DDR SDRAM

5) E00:

- Implemented ECO change list "P41_D00_ECOs-X02.doc" in current working directory: \\nvcorp\applied\designs\working\nv11\XXX-P0041-0000-E00

- Sync'd up netlist with Layout.

- Connect the S0 input of the IMISM530 to 3.3VRUN instead of CLK_VDD

6) E02:

- Added 1000pf cap (C535) in parallel to R535 for EMI supression.

- Changed mem termination from +3.3VRUN to +3.3VSUS. Affects R183-R186, C416

6a) E02-X01: Change C279 to no stuff per Dell request.

7) E03: Added SMD0603 foot print to the backside of board, C536 to DVI, DFP page.

HISTORY REV. :

1) Based on P39-A00

2) Schematic changes; role rev to B00

-remove BT device

-strap resistor changes

-add/remove resistors and caps

-remove high dropout reg (u514)

- R502 changed from 20K to 10K

3) C00:

- Swapped LVDS signals back to "Rev A connections".

- Hi Freq. cap arrays Decoupled to GND:

1) SMB_CLK

2) SMB_DAT

3) PID2_I2C_CLK (aka I2CSCL)

4) PID3_I2C_DAT (aka I2CSDA)

5) PID3_I2CDAT (aka PID3)

6) PID2_I2CCLK (aka PID2)

2 2

7) PID1

8) PID0

- Added 10K, NO STUFF, from AGP_BUSY# to +3.3VSUS.

- Connected C279 to +5VSUS.

4) D00:

A) Power U513 from +3.3vsus instead of +3.3vrun. B) Changed R68 to 10K. Change R69 to 9.09K (to decrease static current draw in +2.5v regulator circuit) C) (layout change) Moved MVREF divider & caps (R172, R175, C424, C426) next to the RAMs D) Added 0-Ohm STUFF OPTION resistors for memory core FBVDD to go from either +3.3VSUS or +2.5V. E) Moved C836, C837, C247, C248, C270 to FBVDD F) Removed R166 & R126 (DFPCLK is unused) G) Moved pin 1 of R501 from +5vsus to +5vrun H) (layout change) Split 5vsus bus into +5vrun and +5vsus I) Added a NOSTUFF zero ohm resistor from DFP3.3V to +3.3VRUN (adds option to remove dfp regulator J) Added a .022uF cap in parallel with R550 (Increase power sequencing delay) K) Changed C57 to 330uF, d-size case L) Changed C828 is 330uF, d-size case M) (layout change) Moved IMI530 part (designator u1) to fix shorting problem N) (layout change) Connected J1 connector shield to ground O) (layout change) Connected mounting holes to ground. Don't plate inside of hole to allow for pimnut Q) Route VDDEN (GPIO3) to pin 166 on connector J10 (FPVCC) P) Added 2 Standoffs (1 metal, 1 plastic) and thermal pad per Dell's request. R) Connected pin 24 of J10 (ZV_PCLK) to pin B4 (VIPPCLK) on U29 (NV11) S) Created +5VRUN net, connect to pin 168 on J10 (+5VRUN)

1 1

T) R155 = 357ohm, R150 is no-stuff U) Removed R152. Connected CHTVPIO_1 to CHTVPIO_0. V) Adjusted PCB form factor W) Changed R548 from 400K 5% to standard 390K 5% X) Changed R550 from 600K 5% to standard 620K 5% Y) Configured memory to 2Mx32-1001b (R524=NO STUFF, R523= STUFF Z) Changed R154, R156 to 10K.

Micro-Star International Co., L TD .

MS8832,1/2/4MX32-DDR,TV

{Item}\t{Quantity}\t{Reference}\t{USR DFINE}\t{PN}\t{Assembly}\t{Value} {Assembly}{Source Package} {Value}{PN}{AVL1}{AVL2}{AVL3}{AVL4}{AVL5}

Size Document Number Rev

Date:

Tuesday, April 30, 2002

List of schematic sheets

Sheet of

100

www.vinafix.vn

U902

D_C

AVdd

STOP

DVdd

SSON

Fout

REFout

D D

OVdd

OSCin

OVss

OSCout

AVss DVss

IMISM530ATB

C C

B B

U900

11 17 16

8 13

IMISM530ATB

D_C STOP SSON

S0 S1

S2 S3 R0 R1

OSCin OSCout

REFout

AVdd

DVdd

Fout

OVdd

OVss

AVss

DVss

4 5

6 9

14 11 17 16

1 2

U901

D_C STOP SSON

S0 S1

S2 S3 R0 R1

OSCin OSCout

IMISM530ATB

REFout

AVdd

DVdd

Fout

OVdd

OVss

AVss

DVss

A A

Title

<Title>

Size Document Number Rev

Date: Sheet

11Tuesday, April 30, 2002

www.vinafix.vn

+12V8

C141

+5VALW8

1uF

C94

4 4

10uF

+3.3VSUS

C79 10uF

In all cases each capacitor should be low ESR/ESL and placed as close as possible to the respective rail connector pin(s).

3 3

2 2

1 1

C85

C84

0.01UF

C82

C81

0.022uF

ZV_UV[7:0]5 ZV_VSYNC5

ZV_Y[7:0]5 ZV_HREF5

+5VSUS

+3.3VRUN

C92

C87

0.01UF

0.022uF

C83

0.022uF

SMB_CLK8 SMB_DAT8

DDC_CLK5 DDC_DAT5

+5VRUN

+5VALW

VDDQ

C93

0.01UF

C80

0.1uF

VDDEN8

PWR_SRC8

VSYNCR5 HSYNCR5

RED5

GREEN5

BLUE5 TVY7

TVC7 CVBS7

ZV_UV0 ZV_UV1 ZV_UV2 ZV_UV3 ZV_UV4 ZV_UV5 ZV_UV6 ZV_UV7

ZV_PCLK5 ZV_Y0 ZV_Y1 ZV_Y2 ZV_Y3 ZV_Y4 ZV_Y5 ZV_Y6 ZV_Y7

164 168

172

28 49 93

128 161

163 165

169 171 173

177 170 166 176

178 125

129 133 137 141

145 149 153

158 156 154 152

148 146

19 24 18

8 16 10 12

6 14

4 20

2 21 22 25 26 32 35 41 42 51 52 61 62 67 68 73 74 81 82 89 90 99

100 107 108 113 114 119 120 123 127 130 131 135 139 140 143 147 150 151 155 159 160 167 174 179 180

J10

+12V +5VRUN

+5VALW VDDQ0

VDDQ1 VDDQ2 VDDQ3

+5VSUS0 +5VSUS1 +5VSUS2

3.3VSUS0

3.3VSUS1

3.3VSUS2

3.3VSUS4 +3VRUN FPVCC PWR_SRC0

PWR_SRC1 VSYNC

HSYNC VGA_RED VGA_GRN BGA_BLU

TV_Y TV_C TV_CVBS

PWR_OK TYPE_DET# SMB_CLK SMB_DAT

CLK_DDC2 DAT_DDC2

ZV_UV0 ZV_UV1 ZV_UV2 ZV_UV3 ZV_UV4 ZV_UV5 ZV_UV6 ZV_UV7 ZV_VSYNC

ZV_PCLK ZV_Y0

ZV_Y1 ZV_Y2 ZV_Y3 ZV_Y4 ZV_Y5 ZV_Y6 ZV_Y7 ZV_HREF

GND0 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18 GND19 GND20 GND21 GND22 GND23 GND24 GND25 GND26 GND27 GND28 GND29 GND30 GND31 GND32 GND33 GND34 GND35 GND36 GND37 GND38 GND39 GND40 GND41 GND42 GND43 GND44 GND45 GND46 GND47

QT01NNNA-*120

GC_SUSPEND#

C/BE0# C/BE1# C/BE2# C/BE3#

CLK66_AGP

FRAME#

TRDY#

DEVSEL#

STOP#

SBSTB

SBSTB#

ADSTB1

ADSTB1#

VREFGC VREFCG

ADSTB0

ADSTB0#

STP_AGP#

GC_STNDBY#

M_ID2#

M_SEN#

AGP_BUSY#

CLKRUN#

+3.3VSUS

118

AD0

121

AD1

116

AD2

117

AD3

112

AD4

115

AD5

110

AD6

105

AD7

106

AD8

103

AD9

104

AD10

101

AD11

102

AD12

AD13

AD14

AD15

86175

AD163.3VSUS3

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AD27

AD28

AD29

AD30

AD31

122 96 79 59

23 48

RST#

126

GNT#

REQ#

58 53

IRDY#

55 46 57 124

PAR

PME#

INTA#

INTB#

RBF#

WBF#

PIPE#

ST0

ST1

ST2

SBA0

SBA1

SBA2

SBA3

SBA4

SBA5

SBA6

SBA7

37 39

71 69

92 91

111 109

136 134

132 142

144 94

138

157

NC0

162

NC1

R553

1 2

10K

NO STUFF

R_AGPST0P_L

AGP_BUSY_L

R502

1 2

10K

C834 56pF

PCICLK_RC

PCIINTAJ AGPRBFJ AGPWBFJ AGPPIPEJ

R507 300

U16 FDC6301N

413 5 6

R_3.3VSUS

PCIAD0 PCIAD1 PCIAD2 PCIAD3 PCIAD4 PCIAD5 PCIAD6 PCIAD7 PCIAD8 PCIAD9 PCIAD10 PCIAD11 PCIAD12 PCIAD13 PCIAD14 PCIAD15 PCIAD16 PCIAD17 PCIAD18 PCIAD19 PCIAD20 PCIAD21 PCIAD22 PCIAD23 PCIAD24 PCIAD25 PCIAD26 PCIAD27 PCIAD28 PCIAD29 PCIAD30 PCIAD31

PCICBE0J PCICBE1J PCICBE2J PCICBE3J

PCICLK PCIRSTJ

PCIGNTJ PCIREQJ

R545 75

PCIFRAMEJ PCIIRDYJ PCITRDYJ PCIDEVSELJ PCISTOPJ PCIPAR

AGPST0 AGPST1 AGPST2

AGPADSTB1 AGPADSTB1J AGPADSTB0 AGPADSTB0J

AGPBUSY_L

AGPST0P_L

AGPVREFCG

AGPVREFGC

U29A

AJ28

PCIAD0

AH27

PCIAD1

AK26

PCIAD2

AJ27

PCIAD3

AG24

PCIAD4

AH26

PCIAD5

AK24

PCIAD6

AK27

PCIAD7

AH24

PCIAD8

AK23

PCIAD9

AK25

PCIAD10

AH23

PCIAD11

AG23

PCIAD12

AK22

PCIAD13

AH22

PCIAD14

AJ22

PCIAD15

AG19

PCIAD16

AH19

PCIAD17

AJ19

PCIAD18

AG18

PCIAD19

AJ18

PCIAD20

AK19

PCIAD21

AH18

PCIAD22

AJ16

PCIAD23

AK17

PCIAD24

AK16

PCIAD25

AH15

PCIAD26

AJ15

PCIAD27

AH14

PCIAD28

AG15

PCIAD29

AG14

PCIAD30

AK14

PCIAD31

AJ24

PCICBE#0

AG22

PCICBE#1

AK21

PCICBE#2

AK18

PCICBE#3

AG16

PCICLK

AK15

PCIRST#

AH11

PCIGNT#

AK11

PCIREQ#

AH20

PCIFRAME#

AG20

PCIIRDY#

AK20

PCITRDY#

AG21

PCIDEVSEL#

AH21

PCISTOP#

AJ21

PCIPAR

AH16

PCIINTA#

AH12

AGPRBF#

AH13

AGPWBF#

AG13

AGPPIPE#

AG12

AGPST0

AJ12

AGPST1

AK12

AGPST2

AG17

AGPADSTB1

AH17

AGPADSTB1#

AH25

AGPADSTB0

AJ25

AGPADSTB0#

AK13

AGPBUSY#

AJ13

AGPSTOP#

AK28

AGPVREF

A01

VDDQ

R78 301K

R77 221K

AE24

VDDQ

AF11

VDDQ

AF13

VDDQ

AF18

VDDQ

AF20

VDDQ

AF24

VDDQ

AG25

VDDQ

AA26

VDD

AF10

VDD

AF12

VDD

AF19

VDD

AF21

VDD

AF23

VDD

E10

VDD

E11

VDD

E12

VDD

E13

VDD

E18

VDD

E19

VDD

E20

VDD

E21

VDD

K26

VDD

L26

VDD

M26

VDD

N26

VDD

V26

VDD

W26

VDD

Y26

VDD

AA5

VD50CLAMP

AB5

VD50CLAMP

AF8

VD50CLAMP

+3.3VSUS

AD5

VDD33

AD6

VDD33

AE4

VDD33

AE5

VDD33

AE7

VDD33

AF4

VDD33

AF6

VDD33

AF7

VDD33

AG5

VDD33

AG6

VDD33

GND

P29

GND

U29

GND

Y29

GND

AK2

TESTMODE0

AK29

TESTMODE1

C145

0.1uF

NO STUFF

VDDQ

R157

1.5K

R159

1.5K

NVVDD

+5VSUS

TEST0 TEST1

C320

470pF

AGPVREF1

R158 75

R160 75

AGPVREF2

C321

470pF

C423

0.1uF

C17 10uF

R65 10K

PCB1000

VDDQ

+3.3VSUS

1 2

R171 10K

C127

0.1uF

R112

C324

0.1uF

(PER FAB DWG)

C128

0.1uF

REG5V

C325

CMP

1 2

TOFF

470pF

R168 180K

1 2

C130

C131

0.1uF

IN_1

IN_2

VCC

FBSEL

SHDN

COMP

TOFF

MAX1644EAE

THERMAL

INTERFACE PAD FOR P41

NVXX HOST INTERFACE

NVVDD_L

LX_1

LX_2

LX_3

ADJ

PGND_1

PGND_2

GND

REF

C326

0.01UF

STANDOFF

METAL FOR P41

Micro-Star International Co., L TD .

MS8832,1/2/4MX32-DDR,TV

Size Document Number Rev

Tuesday, April 30, 2002

Date:

Note: R11 18.2K = 1.5V R11 36.5K = 1.9V

L29 6.8uH

1 2

R11

18.2K

49.9K

C327

1uF

HOST INTERFACE_NEW

NVVDD

STANDOFF

PLASTIC FOR P41

Sheet of

C57

330uF R040

100

www.vinafix.vn

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MSI MS-8832 Schematic 100

Specifications and Main Features

Frequently Asked Questions

User Manual