MSI MS-6761 Schematics

5

Title Page

Cover Sheet 1

D D

C C

B B

Block Diagram

PCI Routing & CK 4

Clock Synthesizer & MS1 8
System Memory

DDR Terminations R & C
DDR Damping R & Bypass Cap.
NB VIA K8T400M/VER:0.4 (HT)
K8 Vcore
AGP SLOT 8X
VT8235
PCI Connectors * 6
AD1981b
Serial ATA Controller PDC20375
IDE ATA 66/100 Connectors * 2
1394 Controller NEC72874
INTEL 82540EM G-bit
USB Port
LPC I/O
LPT/COM Port
ACPI Power & Power-Good Circuit
Power OK Sequence (GAL) & Front Panel
Decoupling Cap.

DDR DIMM 1 & 2 9

4

2
3GPIO SPEC

5,6,7AMD K8 -> 754 PGA Socket

10
11
12,13,14
15
16
17,18,19
20,21,22
23
24
25
26
27
28
29
30
31
32
33

3

2

Stella II

MS-6761n1 VER:0A ATX

*AMD PGA 754 K8-Processor (DDR 333)
*VIA K8T400M / VT8235 Chipset

(AGP 8X / VLink 8X)
*Winbond 83697HF-VF LPC I/O
*NEC 72874 1394a Controller
*I82540 Giga/100/10 Bit LAN Support
*PDC20375 Serial ATA Controller
*USB 2.0 support (integrated into VT8235)

*AD1981B S/W Audio

*DDR DIMM * 3

*AGP SLOT * 1 ( 8X )

*PCI SLOT * 5

1

A A

Title

Special design for NEC

5

4

3

2

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

Micro Star Restricted Secret

Cover Sheet

MS-6761N1

Last Revision Date:

Thursday, January 09, 2003

Sheet

1 36

of

1

Rev

0A

5

Block Diagram

4

3

2

1

AMD K8 Socket 754

D D

DDR333

DDR * 2 (DIMM2 )

A
G

AGP 8X /Fast Write

C C

PCI SLOT-3

PCI SLOT-4

PCI SLOT-5

PCI - Slot4

PCI - Slot5

Modem

MS-1

PCI SLOT-1

PCI SLOT-2

W-LAN

TV-Out card

P

S
L
O
T

PCI-33

B B

1394
Front-Port *2 ,
Back-Port *1

1394 Host
Controller
NEC72874

AC97 => S/W Audio
ALC650 / 6 channel

VIA
K8T400M

VT8235

Dual ATA
100/133

IDE Slot
==>ATA66,100,133 *2

SUPER I/O
W83697HF

Serial ATA & IDE
RAID Controller
PDC20375

A A

Serial Port *2

IDE Port *1

5

Giga Bit LAN
Intel-82540

4

Dual USB 1.1 OHCI
/2.0 EHCI 6 Ports
==> Front-Port *4 ,
Back-Port *2

3

Support *1 Blue-Tooth
Connector ( Share
with USB-Port *1 )

2

ROM

Micro Star Restricted Secret

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

Block Diagram

MS-6761N1

Last Revision Date:

Sheet

1

Thursday, January 09, 2003

2 36

of

Rev

0A

5

4

3

2

1

GPIO FUNCTION

VT8233 GPIO Function Define

PIN NAME

D D

GPO0 (VSUS33)

GPO1/SUSA#(VSUS33)

GPO2/SUSB#(VSUS33)

GPO3/SUSST1#(VSUS33)

GPO4/SUSCLK(VSUS33)

GPO5/CPUSTP#

GPO6/PCISTP#

GPO7/SLP#

GPO8/GPI8/IPBIN0

GPO9/GPI9/IPBIN1

C C

GPO10/GPI10/IPBRDFR

GPO11/GPI11/IPBRDCK

GPO12/GPI12/IPBOUT0

GPO13/GPI13/IPBOUT1

GPO14/GPI14/IPBTDFR

GPO15/GPI15/IPBTDCK

GPO16/SA16/STRAP

GPO17/SA17/STRAP

GPO18/SA18/STRAP

GPO19/SA19/STRAP

B B

GPO20/GPI20
/ACSDIN2/PCS0#/EI

GPO21/GPI21/ACSDIN3
/PCS1#/SLPBTN#

GPO22/GPI22/IOR#

GPO23/GPI23/IOW#

GPO24/GPI24/GPIOA

GPO25/GPI25/GPIOC
GPO26/GPI26/SMBDT2

(VSUS33)
GPO27/GPI27/SMBCK2

(VSUS33)
GPO28/GPI28/

APICD0/APICCS#
GPO29/GPI29/

A A

APICD1/APICACK#

GPO30/GPI30/GPIOD

GPO31/GPI31/GPIOE

5

SBGPO0 ( GLAN_EN )

SUSLED ( Power LED )

SUSB#

SUSST#

CTL_PLED1# ( Power LED )

NA (Exteranl Pull up to VCC3)

SBGPO6 ( 1394_EN )

GNT#5

SBGPO8 ->Vcore Setting ( Hi=CPU
Default , Low=Manual )

NA

SVID0

( Vcore Adjusting )

SVID1 ( Vcore Adjusting )

ROMLOCK

SVID2 ( Vcore Adjusting )

SVID3 ( Vcore Adjusting )

SVID4 ( Vcore Adjusting )

LDT Freq Strapping Bit0

LDT Freq Strapping Bit1

LDT Width (Low=8 Bit)

Fast Command (Low=Disable)

NA

(Exteranl Pull down to GND)

NA

(Exteranl Pull down to GND)

NA

NA

DLED1

DLED2

SMBDATA2/Slave SMBUS

SMBCLK2/Slave SMBUS

NA

NA

DLED3

DLED4

PIN NAME Function defineFunction define

GPI0

GPI1

GPI2/EXTSMI#

GPI3/RING#

GPI4/LID#

GPI5/BATLOW#

GPI6/PME#

GPI7/REQ#5

GPI16/INTRUDER#

GPI17/CPUMISS

GPI18/AOLGP1/THRM#

GPI19/IORDY

4

(Exteranl Pull up to VBAT)NA

ATADET0=>Detect IDE1 ATA100/66

EXTSMI#

RING#

ATADET1=>Detect IDE2 ATA100/66

(Exteranl Pull up to 3VDUAL)

NA

PCI_PME#

(Exteranl Pull up to 3VDUAL)

NA

(Exteranl Pull up to VBAT)

NA

(Exteranl Pull up to 3VDUAL)

NA

THRM#

(Exteranl Pull up to VCC3)NA

3

PCI Routing

DEVICES

PCI SLOT 1

PCI SLOT 2

PCI SLOT 3

PCI SLOT 4

PCI SLOT 5

Giga-Bit
LAN

1394 INT#D AD25

SETIAL ATA INT#B AD24

MS1

INT#

INT#A

INT#B
INT#C
INT#D

INT#B

INT#C
INT#D
INT#A

INT#C

INT#D
INT#A
INT#B

INT#D

INT#A
INT#B
INT#C

INT#B

INT#C
INT#D
INT#A

INT#C AD26

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

2

Output From MS1 -> Red Color

IDSEL

AD16

AD17

AD18

AD19

AD21

REQ#/GNT#

PREQ#4
PGNT#4

PREQ#5
PGNT#5

PREQ#6
PGNT#6

PREQ#7
PGNT#7

PREQ#8
PGNT#8

PREQ#1
PGNT#1

PREQ#3
PGNT#3

PREQ#2
PGNT#2

PREQ#0
PGNT#0

CLOCK

Pin 13

Pin 14

PCICLK6

PCICLK7

PCICLK8

Pin 22

Pin 17

Pin 18

Pin 21

Micro Star Restricted Secret

GPIO Spec.

MS-6761N1

Last Revision Date:

Thursday, January 09, 2003

Sheet

3 36

of

1

Rev

0A

5

4

3

2

1

D D

PCI Routing

6

PREQ#6 & PGNT#6

PCI-3

7

PREQ#0 & PGNT#0

0

PREQ#1 & PGNT#1

1

PREQ#2 & PGNT#2

2

SB

PREQ#3 & PGNT#3

3

4

PREQ#4 & PGNT#4

PREQ#5 & PGNT#5

C C

5

Giga-Bit LAN

SATA

1394

PCI-1

MS-1
#1

PREQ#7 & PGNT#7

PREQ#8 & PGNT#8

8

PCI-4

PCI-5

PCI-2

PCI Clock

B B

0

Pin-13

Pin-14

1

Pin-17

2

Pin-18

3

CK

Pin-21

4

Pin-22

5

Pin-23

F

Pin-12

A A

5

10

R_PCICLK4 PCICLK4

R_PCICLK5

R_PCICLK3 PCICLK4

R_PCICLK4

R_PCICLK5

R_PCICLKF

R_SIOPCLK SIOPCLK

22

PCICLK5

22

PCICLK3R_PCICLK2

22

22

22

PCICLK5

22

PCICLKF

22

4

PCI-4

PCI-5

1394

SATA

MS1_PCLK

LAN

SB

SIO

MS-1
#1

R_PCICLK1

7
8
9
10

X

11

X

3

R_PCICLK2

R_PCICLK3

22

22

22

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

2

PCICLK1

PCICLK2

PCICLK3

PCI1

PCI2

PCI3

Micro Star Restricted Secret

PCI & MS-1

MS-6761N1

Last Revision Date:

Thursday, January 09, 2003

Sheet

4 36

of

1

Rev

0A

5

4

3

2

1

VREF routed as 40~50 mils trace wide ,
Space>25 mils

C52

104P/25V/Y5V

VREF_DDR_CLAW

D D

VDD_25_SUS

Place near CPU in 1" ,
Routed => 5:10/Trace:Space ,
Same Length

MD[63..0]11

The MEMZN and MEMZP
pins separately
control the NMOS and
PMOS I/O driver
strength. If the
resistance is
increased, the buffer
becomes weaker.

C C

B B

-MDQS[8..0]11

A A

R104 20RST
R108 20RST

MD[63..0]

DM[8..0]11

-MDQS[8..0]

102P

MEMZN
MEMZP

MD63
MD62
MD61
MD60
MD59
MD58
MD57
MD56
MD55
MD54
MD53
MD52
MD51
MD50
MD49
MD48
MD47
MD46
MD45
MD44
MD43
MD42
MD41
MD40
MD39
MD38
MD37
MD36
MD35
MD34
MD33
MD32
MD31
MD30
MD29
MD28
MD27
MD26
MD25
MD24
MD23
MD22
MD21
MD20
MD19
MD18
MD17
MD16
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0

DM8
DM7
DM6
DM5
DM4
DM3
DM2
DM1
DM0

-MDQS8

-MDQS7

-MDQS6

-MDQS5

-MDQS4

-MDQS3

-MDQS2

-MDQS1

-MDQS0

5

AE13

AG12

AJ10

AH11

AJ11

AH15

AJ15

AG11

AJ12
AJ14
AJ16

AH13

AJ13

D14
C14

A16
B15
A12
B11
A17
A15
C13
A11
A10

C11

AC1
AC3

AC2
AD1
AE1
AE3
AG3
AJ4
AE2
AF1
AH3
AJ3
AJ5
AJ6
AJ7
AH9
AG5
AH5
AJ9

A13

AA1
AG1
AH7

A14

AB1
AJ2
AJ8

B9
C7
A6

A9
A5
B5
C5
A4
E2
E1
A3
B3
E3

F1
G2
G1

L3

L1
G3

J2

L2
M1
W1
W3

W2

Y1

R1

A7

C2

H1

T1

A8

D1

J1

VTT_SENSE 31

U8B

N12-7540010-A10

VTT_SENSE

MEMVREF1
MEMZN

MEMZP

MEMDATA63
MEMDATA62
MEMDATA61
MEMDATA60
MEMDATA59
MEMDATA58
MEMDATA57
MEMDATA56
MEMDATA55
MEMDATA54
MEMDATA53
MEMDATA52
MEMDATA51
MEMDATA50
MEMDATA49
MEMDATA48
MEMDATA47
MEMDATA46
MEMDATA45
MEMDATA44
MEMDATA43
MEMDATA42
MEMDATA41
MEMDATA40
MEMDATA39
MEMDATA38
MEMDATA37
MEMDATA36
MEMDATA35
MEMDATA34
MEMDATA33
MEMDATA32
MEMDATA31
MEMDATA30
MEMDATA29
MEMDATA28
MEMDATA27
MEMDATA26
MEMDATA25
MEMDATA24
MEMDATA23
MEMDATA22
MEMDATA21
MEMDATA20
MEMDATA19
MEMDATA18
MEMDATA17
MEMDATA16
MEMDATA15
MEMDATA14
MEMDATA13
MEMDATA12
MEMDATA11
MEMDATA10
MEMDATA9
MEMDATA8
MEMDATA7
MEMDATA6
MEMDATA5
MEMDATA4
MEMDATA3
MEMDATA2
MEMDATA1
MEMDATA0

MEMDQS17
MEMDQS16
MEMDQS15
MEMDQS14
MEMDQS13
MEMDQS12
MEMDQS11
MEMDQS10
MEMDQS9
MEMDQS8
MEMDQS7
MEMDQS6
MEMDQS5
MEMDQS4
MEMDQS3
MEMDQS2
MEMDQS1
MEMDQS0

MEMORY INTERFACE

VTT_A4
VTT_A1
VTT_A2
VTT_A3
VTT_B1
VTT_B2
VTT_B3
VTT_B4

MEMRESET_L

MEMCKEA
MEMCKEB

MEMCLK_H7

MEMCLK_L7

MEMCLK_H6

MEMCLK_L6

MEMCLK_H5

MEMCLK_L5

MEMCLK_H4

MEMCLK_L4

MEMCLK_H3

MEMCLK_L3

MEMCLK_H2

MEMCLK_L2

MEMCLK_H1

MEMCLK_L1

MEMCLK_H0

MEMCLK_L0

MEMCS_L7
MEMCS_L6
MEMCS_L5
MEMCS_L4
MEMCS_L3
MEMCS_L2
MEMCS_L1
MEMCS_L0

MEMRASA_L
MEMCASA_L

MEMWEA_L

MEMBANKA1
MEMBANKA0

RSVD_MEMADDA15
RSVD_MEMADDA14

MEMADDA13
MEMADDA12
MEMADDA11
MEMADDA10

MEMADDA9
MEMADDA8
MEMADDA7
MEMADDA6
MEMADDA5
MEMADDA4
MEMADDA3
MEMADDA2
MEMADDA1
MEMADDA0

MEMRASB_L
MEMCASB_L

MEMWEB_L

MEMBANKB1
MEMBANKB0

RSVD_MEMADDB15
RSVD_MEMADDB14

MEMADDB13
MEMADDB12
MEMADDB11
MEMADDB10

MEMADDB9
MEMADDB8
MEMADDB7
MEMADDB6
MEMADDB5
MEMADDB4
MEMADDB3
MEMADDB2
MEMADDB1
MEMADDB0

MEMCHECK7
MEMCHECK6
MEMCHECK5
MEMCHECK4
MEMCHECK3
MEMCHECK2
MEMCHECK1
MEMCHECK0

4

D17
A18
B17
C17
AF16
AG16
AH16
AJ17

AG10
AE8

AE7
D10

C10
E12
E11
AF8
AG8
AF10
AE10
V3
V4
K5
K4
R5
P5
P3
P4

D8
C8
E8
E7
D6
E6
C4
E5

H5
D4
G5

K3
H3

E13
C12
E10
AE6
AF3
M5
AE5
AB5
AD3
Y5
AB4
Y3
V5
T5
T3
N5

H4
F5
F4

L5
J5

E14
D12
E9
AF6
AF4
M4
AD5
AC5
AD4
AA5
AB3
Y4
W5
U5
T4
M3

N3
N1
U3
V1
N2
P1
U1
U2

VTT_DDR_SUS

MCKE0
MCKE1

MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
MEMCLK_L6
MEMCLK_H5
MEMCLK_L5
MEMCLK_H4
MEMCLK_L4

MEMCLK_H1
MEMCLK_L1
MEMCLK_H0
MEMCLK_L0

-MCS3

-MCS2

-MCS1

-MCS0

-MSRASA

-MSCASA

MAA13
MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0

MAB13
MAB12
MAB11
MAB10
MAB9
MAB8
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0

MEMCHECK7
MEMCHECK6
MEMCHECK5
MEMCHECK4
MEMCHECK3
MEMCHECK2
MEMCHECK1
MEMCHECK0

MCKE0 9,10
MCKE1 9,10

MEMCLK_H7 9,10

MEMCLK_L7 9,10

MEMCLK_H6 9,10

MEMCLK_L6 9,10

MEMCLK_H5 9,10

MEMCLK_L5 9,10

MEMCLK_H4 9,10

MEMCLK_L4 9,10

MEMCLK_H1 9,10

MEMCLK_L1 9,10

MEMCLK_H0 9,10

MEMCLK_L0 9,10

-MCS3 9,10

-MCS2 9,10

-MCS1 9,10

-MCS0 9,10

-MSRASA 9,10

-MSCASA 9,10

-MSWEA 9,10
MEMBANKA1 9,10

MEMBANKA0 9,10

-MSRASB 9,10

-MSCASB 9,10

-MSWEB 9,10
MEMBAKB1 9,10

MEMBAKB0 9,10

MAB[13..0]

MEMCHECK[7..0]

MAA[13..0]

MAA[13..0] 9,10

CLKIP112

CLKIN112

CLKIP012

CLKIN012

VLDT0

CTLIP012
CTLIN012

All signals are point to point except for the unused CTLIN1 pins.
These inputs must be terminated to a logic 1 (true is pulled high and
its complement low with 50ohm1% resistors) for correct operation.

MAB[13..0] 9,10

MEMCHECK[7..0] 11

3

VDD_12_A

CADIP[0..15]12

CADIN[0..15]12

VDD_12_A

R63 49.9RST
R60 49.9RST

C161
X_0.22u

CADIP15

CADIN15

CADIP14

CADIN14

CADIP13

CADIN13

CADIP12

CADIN12

CADIP11

CADIN11

CADIP10

CADIN10

CADIP9

CADIN9

CADIP8

CADIN8

CADIP7

CADIN7

CADIP6

CADIN6

CADIP5

CADIN5

CADIP4

CADIN4

CADIP3

CADIN3
CADIN2

CADIP1

CADIN1

CADIP0

CADIN0

C148

0.22uC53

CADIP[0..15]
CADIN[0..15]

CTLIP1
CTLIN1

C199

C150

0.22u

U8A

N12-7540010-A10

D29

VLDT0_A6

D27

VLDT0_A5

D25

VLDT0_A4

C28

VLDT0_A3

C26

VLDT0_A2

B29

VLDT0_A1

B27

VLDT0_A0

T25

L0_CADIN_H15

R25

L0_CADIN_L15

U27

L0_CADIN_H14

U26

L0_CADIN_L14

V25

L0_CADIN_H13

U25

L0_CADIN_L13

W27

L0_CADIN_H12

W26

L0_CADIN_L12

AA27

L0_CADIN_H11

AA26

L0_CADIN_L11

AB25

L0_CADIN_H10

AA25

L0_CADIN_L10

AC27

L0_CADIN_H9

AC26

L0_CADIN_L9

AD25

L0_CADIN_H8

AC25

L0_CADIN_L8

T27

L0_CADIN_H7

T28

L0_CADIN_L7

V29

L0_CADIN_H6

U29

L0_CADIN_L6

V27

L0_CADIN_H5

V28

L0_CADIN_L5

Y29

L0_CADIN_H4

W29

L0_CADIN_L4

AB29

L0_CADIN_H3

AA29

L0_CADIN_L3

AB27

L0_CADIN_H2

AB28

L0_CADIN_L2

AD29

L0_CADIN_H1

AC29

L0_CADIN_L1

AD27

L0_CADIN_H0

AD28

L0_CADIN_L0

Y25

L0_CLKIN_H1

W25

L0_CLKIN_L1

Y27

L0_CLKIN_H0

Y28

L0_CLKIN_L0

R27

L0_CTLIN_H1

R26

L0_CTLIN_L1

T29

L0_CTLIN_H0

R29

L0_CTLIN_L0

Close to CPU

VDD_25_SUS

R37

X_1KRST

R40

X_1KRST

Title

C208

0.22u

0.22u

HYPER TRANSPORT - LINK0

VREF routed as 40~50 mils trace wide ,
Space>25 mils

C55
X_104P

C37
X_104P

C38

X_105P/0805

Micro Star Restricted Secret

K8 DDR & HT

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

2

C216

0.22u

VLDT0_B6
VLDT0_B5
VLDT0_B4
VLDT0_B3
VLDT0_B2
VLDT0_B1
VLDT0_B0

L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10

L0_CADOUT_H9

L0_CADOUT_L9

L0_CADOUT_H8

L0_CADOUT_L8

L0_CADOUT_H7

L0_CADOUT_L7

L0_CADOUT_H6

L0_CADOUT_L6

L0_CADOUT_H5

L0_CADOUT_L5

L0_CADOUT_H4

L0_CADOUT_L4

L0_CADOUT_H3

L0_CADOUT_L3

L0_CADOUT_H2

L0_CADOUT_L2

L0_CADOUT_H1

L0_CADOUT_L1

L0_CADOUT_H0

L0_CADOUT_L0
L0_CLKOUT_H1

L0_CLKOUT_L1

L0_CLKOUT_H0

L0_CLKOUT_L0

L0_CTLOUT_H1

L0_CTLOUT_L1

L0_CTLOUT_H0

L0_CTLOUT_L0

R57 0

VREF_DDR_CLAW

C54
X_104P

C149

0.22u

AH29
AH27
AG28
AG26
AF29
AE28
AF25

CADOP15

N26

CADON15

N27

CADOP14

L25

CADON14

M25

CADOP13

L26

CADON13

L27

CADOP12

J25

CADON12

K25

CADOP11

G25

CADON11

H25

CADOP10

G26

CADON10

G27

CADOP9

E25

CADON9

F25

CADOP8

E26

CADON8

E27

CADOP7

N29

CADON7

P29

CADOP6

M28

CADON6

M27

CADOP5

L29

CADON5

M29

CADOP4

K28

CADON4

K27

CADOP3

H28

CADON3

H27

CADOP2CADIP2

G29

CADON2

H29

CADOP1

F28

CADON1

F27

CADOP0

E29

CADON0

F29

CLKOP1

J26

CLKON1

J27

CLKOP0

J29

CLKON0

K29
N25

P25

CTLOP0

P28

CTLON0

P27

MEM_VREF 9

MS-6761N1

Last Revision Date:

Sheet

C200

C158

X_0.22u

X_0.22u

CADOP[0..15]
CADON[0..15]

VLDT0

CLKOP1 12
CLKON1 12
CLKOP0 12
CLKON0 12

CTLOP0 12
CTLON0 12

CADOP[0..15] 12
CADON[0..15] 12

VLDT0 6

C64

4.7u/0805

Wednesday, January 15, 2003

5 36

of

1

Rev

0A

5

4

3

VCCA_PLL trace length from the VR1 to the
PGA must be 0.75".

2

1

Place al filters close to the PGA.

Keep all power and signal trce away from
the VR1.

AMD CPU Thermal Protection Circuit

D D

The COREFB_H and
COREFB_L signals are
routed differentially
to a device such as a
unity gain
differential op-amp
that will shift the
voltage difference to

C C

correspond with the
ground of the digital
to analog converter.
When these two values
have a common ground,
a comparison can be
made that drives the
control logic of the
power supply. This
strategy compensates
for voltage drops
across both the power
and ground planes.

TMP_SPK32

PS_IN#32 PS_OUT# 32

VTIN229

R24 X_0

THERMDA_CPU

R18 0 C7

U1

1

SIREN#

2

GND

3

PS_OUT#

PS_IN#

4 5

TMP-D+ TMP-D-

X_ATTP1

C5

D0F-ATTP103-A64

X_104P

R1 X_4.32KST

PWROK is a processor
input signal used to
indicate when the
processor can attempt
to lock the internal
PLL

CPU_GD32

5VSB

8

5VSB

7

VREF

6

C9
X_104P

VLDT05

Place near CPU in 1" ,
Routed => 5:10/Trace:Space ,
Same Length

C1
X_104P

VLDT0

R13

X_16.2KST

X_104P

R39 0

R64 44.2RST
R61 44.2RST

LAYOUT: Route VDDA trace approx. 50 mils wide (use 2x25 mil
traces to exit ball field) and 500 mils long.

VDDA_25

C70
102P

C36
X_102P

FB1

180nH/1210

VCC2_5

102P

C71

CPU_VDDA_25

C42

X_10u/1206

-CPURST32

-LDTSTOP12,17

COREFB_H15

COREFB_L15

Differential , "10:10:5:10:10" .

CPUCLK0_H8

Near CPU in 0.5" .

CPUCLK0_L8

C50
X_0.22u

L0_REF1
L0_REF0

VDDIO_SENSE31

C69 3900P/X7R

C72 3900P/X7R

VTT_DDR_SUS

C67

4.7u/0805

CPU_PWROK

VDDIO_SENSE

R62

R56 820
R45 820

HDT Test Port Signal .

VCC2_5

R109

R110

R119

1K

1K

R115

R50

1K

1K

5

1K

R107
1K

R114
1K

R102
1K

R38
1K

R101
1K

R51
1K

Reserved for test

R117
1K

Under normal
operation this
signal should be
pulled up to
VDDIO_RUN through a
680-. resistor.
When entering S3-S5
Sleep states, the
HyperTransport
links must be
deactivated by
driving LDTSTOP_L
signal down to VSS.

-LDTSTOP

PS_ON#A32

4

PS_ON#A

VCC2_5

R113 1K
R106 1K

R34

R55

1K

1K

VCC2_5

R47

470

Q9
2N7002S

3

DBREQ_L
DBRDY
TCK
TMS
TDI
TRST_L
TDO

NC_AG18
NC_AH18
NC_AG17
NC_AJ18
NC_D18
NC_B19
NC_C19
NC_D20
NC_C21

VDD_25_SUS

R127
1K

R58
1K

B B

A A

Place a cut in the GND plane around the
VCCA_PLL regulator circuit.

C65

C66
3300p

0.22u

U8C

N12-7540010-A10

AH25

VDDA1

AJ25

VDDA2

AF20

RESET_L

AE18

PWROK

AJ27

LDTSTOP_L

AF27

L0_REF1

AE26

L0_REF0

A23

COREFB_H

A24

COREFB_L

B23

CORE_SENSE

AE12

VDDIOFB_H

AF12

VDDIOFB_L

AE11

169RST

R41
1KR36 X

NC_AJ23
NC_AH23

DBRDY

TMS
TCK
TRST_L
TDI

NC_C18

NC_A19

NC_AE23
NC_AF23
NC_AF22
NC_AF21

R49
1K

CLKIN_H

CLKIN_L

AJ21

AH21

AJ23

AH23

AE24
AF24

AG15
AH17

AJ28

AE23
AF23
AF22
AF21

AG2
AH1

AE21

C20
AG4

AG6
AE9
AG9

C16

C15
E20

E17
B21
A21

C18
A19
A28

C1

J3

R3

AA2

D3

B18

C6

VDDIO_SENSE
CLKIN_H

CLKIN_L

NC_AJ23
NC_AH23

NC_AE24
NC_AF24

VTT_A5
VTT_B5

DBRDY
NC_C15
TMS

TCK
TRST_L
TDI

NC_C18
NC_A19
KEY1

KEY0
NC_AE23

NC_AF23
NC_AF22
NC_AF21

FREE29
FREE31
FREE33
FREE35
FREE1
FREE37
FREE4
FREE38
FREE41
FREE7
FREE11
FREE12
FREE13
FREE14
FREE40

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

2

VCC2_5

Near SB/VT8235

Q22

VID4
VID3
VID2
VID1
VID0

TDO

2N3904S

THERMTRIP_CPU_L

A20

THERMDA_CPU

A26

THERMDC_CPU

A27

VID4

AG13

VID3

AF14

VID2

AG14

VID1

AF15

VID0

AE15
AG18

AH18
AG17
AJ18

AH19
AJ19

AE19
D20

C21
D18
C19
B19

A22

AF18

D22
C22

B13
B7
C3
K1
R2
AA3
F3
C23
AG7
AE22
C24
A25
C9

R140 X_0

R142

4.7K

NC_AG18
NC_AH18
NC_AG17
NC_AJ18

FBCLKOUT_H

R65

80.6RST

FBCLKOUT_L

Zdiff = 80 ohm

DBREQ_L
NC_D20

NC_C21
NC_D18
NC_C19
NC_B19

TDO

VCC2_5

LAYOUT: Route
FBCLKOUT_H/L differentially
with 20/8/5/8/20 spacing and
trace width. ( In CPU
breakout => routed 5:5:5 )

The Hammer family
processors provide a
hardware enforced
thermal protection
mechanism. When
the processor.s die
temperature exceeds a
specified
temperature, the
processor is designed
to protect
itself from over
temperature
conditions by
stopping its internal
clocks and asserting
the
THERMTRIP_L output.

R148

1K

THERMTRIP_L

THERMDA
THERMDC

NC_AG18
NC_AH18
NC_AG17

NC_AJ18

G_FBCLKOUT_H

G_FBCLKOUT_L

DBREQ_L

NC_D20
NC_C21
NC_D18
NC_C19
NC_B19

NC_AF18

RSVD_SCL
RSVD_SDA

FREE26
FREE28
FREE30
FREE32
FREE34
FREE36
FREE10
FREE18
FREE19
FREE42
FREE24
FREE25
FREE27

Micro Star Restricted Secret

K8 HDT & MISC

MS-6761N1

Last Revision Date:

Wednesday, January 15, 2003

Sheet

THRMTRIP_EN# 32
THRM# 18,29

This pin is a thermal
alarm output that
will be used to power
down the system and
prevent processor
damage due to
overheating.

VID[4..0] 15

6 36

1

CP20X_COPPER

of

Rev

0A

5

4

3

2

1

U8E

B2

VSS1

AH20

VSS3

AB21

VSS4

W22

VSS5

M23

VSS6

L24

VSS7

AG25

VSS8

AG27

AA10

AE16

W20
AA20
AC20
AE20
AG20

AJ20

AD21
AG21

AG29
AA22
AC22
AG22
AH22

AJ22

AB23
AD23
AG23

W24
AA24
AC24
AG24

AJ24

AD26
AF26
AH26

AB17
AD17

AA18
AC18

AB19
AD19
AF19

VSS9

D2

VSS10

AF2

VSS11

W6

VSS12

Y7

VSS13

AA8

VSS14

AB9

VSS15
VSS16

J12

VSS17

B14

VSS18

Y15

VSS19
VSS20

J18

VSS21

G20

VSS22

R20

VSS23

U20

VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30

D21

VSS31

F21

VSS32

H21

VSS33

K21

VSS34

M21

VSS35

P21

VSS36

T21

VSS37

V21

VSS38

Y21

VSS39
VSS40
VSS41

B22

VSS42

E22

VSS43

G22

VSS44

J22

VSS45

L22

VSS46

N22

VSS47

R22

VSS48

U22

VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55

D23

VSS56

F23

VSS57

H23

VSS58

K23

VSS59

P23

VSS60

T23

VSS61

V23

VSS62

Y23

VSS63
VSS64
VSS65
VSS66

E24

VSS67

G24

VSS68

J24

VSS69

N24

VSS70

R24

VSS71

U24

VSS72
VSS73
VSS74
VSS75
VSS76
VSS77

B25

VSS78

C25

VSS79

B26

VSS80

D26

VSS81

H26

VSS82

M26

VSS83

T26

VSS84

Y26

VSS85
VSS86
VSS87
VSS88

C27

VSS89

B28

VSS90

D28

VSS91

G28

VSS92

F15

VSS187

H15

VSS188
VSS206
VSS207

B16

VSS208

G18

VSS209
VSS210
VSS211

D19

VSS212

F19

VSS213

H19

VSS214

K19

VSS215

Y19

VSS216
VSS217
VSS218
VSS219

J20

VSS220

L20

VSS221

N20

VSS222

GROUND

5

D D

C C

B B

A A

VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS189
VSS190
VSS191
VSS192
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS223
VSS201
VSS202
VSS203
VSS204
VSS205

L28
R28
W28
AC28
AF28
AH28
C29
F2
H2
K2
M2
P2
T2
V2
Y2
AB2
AD2
AH2
B4
AH4
B6
G6
J6
L6
N6
R6
U6
AA6
AC6
AH6
F7
H7
K7
M7
P7
T7
V7
AB7
AD7
B8
G8
J8
L8
N8
R8
U8
W8
AC8
AH8
F9
H9
K9
M9
P9
T9
V9
Y9
AD9
B10
G10
J10
L10
N10
R10
U10
W10
AC10
AH10
F11
H11
K11
Y11
AB11
AD11
B12
G12
AA12
AC12
AH12
F13
H13
K13
Y13
AB13
AD13
AF17
G14
J14
AA14
AC14
AE14
D16
E15
K15
AB15
AD15
AH14
E16
G16
J16
AA16
AC16
AE29
AJ26
E18
F17
H17
K17
Y17

N12-7540010-A10

GNDGND

VCORE

AC15

AB14

AA15

AB16

AA17
AC17
AE17

AB18
AD18
AG19

AC19
AA19

AB20
AD20

W21
AA21
AC21

AB22
AD22

W23
AA23
AC23

AB24
AD24
AH24
AE25

LAYOUT: Place 1 capacitor every 1-1.5"

VCORE

along VDD_CORE perimiter.

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO7
VDDIO8

VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27
VDDIO28
VDDIO29
VDDIO30
VDDIO31
VDDIO32
VDDIO33
VDDIO34
VDDIO35
VDDIO36
VDDIO37
VDDIO38
VDDIO39
VDDIO40
VDDIO41
VDDIO42
VDDIO43
VDDIO44
VDDIO45
VDDIO46
VDDIO47
VDDIO48
VDDIO49
VDDIO50

VDDIO6

VDD96
VDD97
VDD98

VDD99
VDD100
VDD101
VDD102
VDD103
VDD104
VDD105
VDD106
VDD107
VDD108
VDD109
VDD110
VDD111
VDD112
VDD113
VDD114
VDD115
VDD116
VDD117
VDD118
VDD119
VDD120
VDD121
VDD122
VDD123
VDD124
VDD125
VDD126
VDD127
VDD128
VDD129
VDD130
VDD131
VDD132
VDD133

VDD93

VDD94

VDD95

VDD_25_SUS

E4
G4
J4
L4
N4
U4
W4
AA4
AC4
AE4
D5
AF5
F6
H6
K6
M6
P6
T6
V6
Y6
AB6
AD6
D7
G7
J7
AA7
AC7
AF7
F8
H8
AB8
AD8
D9
G9
AC9
AF9
F10
AD10
D11
AF11
F12
AD12
D13
AF13
F14
AD14
F16
AD16
D15
R4

N28
U28
AA28
AE27
R7
U7
W7
K8
M8
P8
T8
V8
Y8
J9
N9
R9
U9
W9
AA9
H10
K10
M10
P10
T10
Y10
AB10
G11
J11
AA11
AC11
H12
K12
Y12
AB12
J13
AA13
AC13
H14
AB26
E28
J28

N12-7540010-A10

4

VCORE

X_6.8pF C68

GND

LAYOUT: Place 6 EMI caps along bottom right side of Clawhammer,
2 in middle of HT link, and 12 along bottom left side of Claw-hammer.

VCORE VCORE

X_6.8pF/BACK C530

C102

104P/25V/Y5V

{nopop}

X_4.7u/0805 C103

X_6.8pF/BACK C523

C166

104P/25V/Y5V

X_4.7u/0805 C138

VCORE

X_6.8pF/BACK C515

X_6.8pF/BACK C520

C224

104P/25V/Y5V

X_6.8pF/BACK C513

C263

104P/25V/Y5V

GND

LAYOUT: Place beside processor.

{nopop}

X_0.22u C157

X_0.22u C171

In CPU.

C115

C110

224P

224P

C124

C111

224P

224P

3

X_6.8pF/BACK C529

Place between DIMN1 & 2

VDD_25_SUS

C80

104P/25V/Y5V

VDD_25_SUS

X_0.22u C79

U8D

L7

VDD1
VDD2

H18

VDD3

B20

VDD4

E21

VDD5

H22

VDD6

J23

VDD7

H24

VDD8

F26

VDD9

N7

VDD10

L9

VDD11

V10

VDD12

G13

VDD13

K14

VDD14

Y14

VDD15
VDD16

G15

VDD17

J15

VDD18
VDD19

H16

VDD20

K16

VDD21

Y16

VDD22
VDD23

G17

VDD24

J17

VDD25
VDD26
VDD27
VDD28

F18

VDD29

K18

VDD30

Y18

VDD31
VDD32
VDD33
VDD34

E19

VDD35

G19

VDD36
VDD39
VDD38

J19

VDD37

F20

VDD40

H20

VDD41

K20

VDD42

M20

VDD43

P20

VDD44

T20

VDD45

V20

VDD46

Y20

VDD47
VDD48
VDD49

G21

VDD50

J21

VDD51

L21

VDD52

N21

VDD53

R21

VDD54

U21

VDD55
VDD56
VDD57
VDD58

F22

VDD59

K22

VDD60

M22

VDD61

P22

VDD62

T22

VDD63

V22

VDD64

Y22

VDD65
VDD66
VDD67

E23

VDD68

G23

VDD69

L23

VDD70

N23

VDD71

R23

VDD72

U23

VDD73
VDD74
VDD75
VDD76

B24

VDD77

D24

VDD78

F24

VDD79

K24

VDD80

M24

VDD81

P24

VDD82

T24

VDD83

V24

VDD84

Y24

VDD85
VDD86
VDD87
VDD88
VDD89

K26

VDD90

P26

VDD91

V26

VDD92

POWER

EMI

{nopop}

X_6.8pF/BACK C531

C48

X_0.22u

{nopop}

C260

X_0.22u

{nopop}

{nopop}

X_6.8pF/BACK C528

Title

{nopop}

C120
224P

C118
224P

X_6.8pF/BACK C519

X_6.8pF/BACK C521

0.22u C96

4.7u/0805 C114

C123
224P

C121
224P

X_6.8pF/BACK C517

X_6.8pF/BACK C525

GND GND

4.7u/0805 C141

4.7u/0805 C152

C130

C113

224P

224P

C125

C129

224P

224P

X_6.8pF/BACK C533

VDD_25_SUS VTT_DDR_SUS

0.22u C164
X_0.22u C162

0.22u C156

GND

X_6.8pF/BACK C527

X_6.8pF/BACK C524

X_0.22u C87

X_4.7u/0805 C213

C117
224P

C116
224P

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

2

{nopop}

{nopop}

X_6.8pF/BACK C522

X_6.8pF/BACK C518

{nopop}

X_6.8pF/BACKC516

Micro Star Restricted Secret

K8 POWER & GND

MS-6761N1

Last Revision Date:

Sheet

Rev

Wednesday, January 15, 2003

7 36

of

1

0A

5

VCC3_MS1_D

FRAME#

FRAME#17,20,21,22,24,26,27

STOP#

STOP#17,20,21,22,24,26,27

PREQ#0

PREQ#017

PGNT#0

PGNT#017

PREQ#6

PREQ#621

PGNT#6

PGNT#621

PREQ#7

PREQ#721

D D

VCC3

VCC3

FB5

X_120S/0805

CP17
X_COPPER

C C

PGNT#721
PREQ#822
PGNT#822

FB4

X_120S/0805

CP16
X_COPPER

PGNT#7
PREQ#8

PGNT#8

VCC3_MS1_D

VCC3_MS1_A

MSI PCI-Clock delay about 150pS from
PCI clock-input to PCI clock-output
.

U26

1

FRAME#

2

STOP#

3

SYSREQ#

4

SYSGNT#

5

PCIREQ1#

6

VSS

7

PCIGNT1#

8

PCIREQ2#

9

VCC

10

PCIGNT2#

11

PCIREQ3#

12

PCIGNT3#

13

VC3A

14 15

VC5A VC5B

MS1

B07-00MS102-E18

C450

C462

X_104P

X_104P

C451

104P/25V/Y5V

PGNT#8
PREQ#8
PGNT#6
PREQ#6

PGNT#7
PREQ#7

AVCC
PCICLKI
RESET#

AVSS

VSS

PCLCLK0

PCICLK1

VCC
PCICLK2
PCICLK3
PCICLK4

VSS

VC3B

R419 4.7K
R405 4.7K

PCICLK1
PCICLK2
PCICLK3

28
27
26
25
24
23
22
21
20
19
18
17
16

RN111

8P4R-4.7K

1 2
3 4
5 6
7 8

1 2
3 4
5 6
7 8

CN22

X_8P4C-10P

ICS950403

Strapping CPU

FS0FS2FS3

0 0 0 0

FS1

B B

0 0 0
0 0 0
0 0
0 0 0
0 0
0 0

0

***

1
1 1
1 1
1 1 1
1 1
1 1 1

1

1 1
1
1 1
1 1

1 1 1

0 0 0
0 0
0 0
0

0 0

0

1 1 1
1 1 1 1

A A

ModeA ModeB

***

0 0

0 1

1 0
1 1

100.90

1

133.90

168.00

202.00

100.20

133.50

166.70

200.40

150.00

180.00

210.00

240.00

270.00

233.33

0

266.67

300.00

Pin7 Pin8 Pin11

HTTCLK1 HTTCLK2 PCICLK10

HTTCLK1 HTTCLK2 HTTCLK3

PCICLK8 PCICLK9 PCICLK10
PCICLK8 PCICLK9 PCICLK10

5

MHz

HTT

PCI

MHz

67.27 33.63

66.95

67.20

67.33

66.80

66.75

66.68

66.80

60.00

60.00

70.00

60.00

67.50

66.67

66.67

75.00

MHz

33.48

33.60

33.67

33.40

33.38

33.34

33.40

33.00

33.00

35.00

30.00

33.75

33.33

33.33

37.50

4

VCC3_MS1_A

MS1_PCLK
PCIRST2#

R_PCICLK1

R389 33

R_PCICLK2

R390 33

VCC3_MS1_D

R391 33
R387 X_10K
R388 10K

VCC3

For EMI

VCC3

C389 X_104P

VCC3 VCC

C476 X_104P

FB2

X_120S/0805

CP6
X_COPPER

VCC3

C385

C316

104P/25V/Y5V

104P/25V/Y5V

4

PCIRST2# 17,20,21,22

C332

4.7u/0805

FB3 X_120S/0805

CP9

X_COPPER

PCICLK1
PCICLK2

PCICLK3R_PCICLK3

CLKVDDA

PCICLK1 20
PCICLK2 20

PCICLK3 21

C380

4.7u/0805

C377
X_104P

3

Clock Synthesizer

U18
ICS950403
I11-9504002-I02

CLKVCC3

CLKVCC3

CLKVCC3

CLKVCC3

CLKVCC3

CLKVCC3

CLKVCC3

CLKVCC3

CLKVCC3

CLKVDDA

C372

104P/25V/Y5V

C320 104P/25V/Y5V

C336 104P/25V/Y5V

C350 104P/25V/Y5V

C359 104P/25V/Y5V

C313 104P/25V/Y5V

C335 104P/25V/Y5V

C354 104P/25V/Y5V

C330 104P/25V/Y5V

C373
X_104P

3

46

VDD_46

47

VSS_47

2

VDD_2

5

VSS_5

32

VDDF

33

VSSF

9

VDD_9

10

VSS_10

16

VDD_16

15

VSS_15

19

VDD_19

20

VSS_20

29

VDD_29

30

VSS_30

27

VSS_27

38

VDD_38

39

VSS_39

35

VDD_35

34

VSS_34

43

VDDA

42

VSSA

Only support in ICS950402

CLK_RESET#32

R_GLAN_PCLK GLAN_PCLK

CLKVCC3

C371
104P/25V/Y5V

ModeB/PCICLK7/HTTCLK

PCICLK8/HTTCLK2
PCICLK9/HTTCLK3

24_48MHZ/SEL

ModeA/HTTCLK0

R280 X_10K

R284 33

FS0/REF0
FS1/REF1
FS2/REF2

XOUT

48MHZ/FS3

PCI33_0
PCI33_1
PCI33_2
PCI33_3

PCI33_F

PCI33_4
PCI33_5

SDATA

SCLK

CPUT_0

CPUC_0

CPUT_1

CPUC_1

PCICLK6

Reset#PCICLK10

"24_48MHZ/SEL" Freq.-Out select pin
=> Low->48MHz , Hi->24MHz .
( Internal pull-up via 100K ohm )

"FS0~FS3" are all internal
pull-up via 100K ohm ..

FS1

48

FS2

45

CLKX1

3

XIN

CLKX2

4

31

HT_66_0

7

HT_66_1

8

HT_66_2

11

R_PCICLK4

13

R_PCICLK5

14

R_1394_PCLK

17

R_SATAPCLK

18

R_PCICLKF

23

R_MS1_PCLK

21
22

SEL_48

28

SMBDATA1

26

SMBCLK1

25
41

40

R_CPU_CLK

37

-R_CPU_CLK

36

-SEL_66

6
24

Mode A ( ICS950403 )

4412

Mode B ( Set Pin 7,8,11 output
clock -> 33 or 66 MHz )

HT_66_0

SEL_48

R327 10K

FS0
FS2
FS1

FS3

R267 10K
R273 10K
R270 10K

R300 C_10K

FS0

1

2

R262 22
R263 22
R278 22

R303 33

7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2

RN81 8P4R-22

R326 22
R314 22
R320 M_22

R321 33

R269 10K

R271 C_10K

GLAN_PCLK 27

CLKVCC3

SB_OSC14
AC_14
APICCLK

C314 10P/X7R

X1 14.318MHZ

C315 10P/X7R

RN78
8P4R-22

SBPCLK
MS1_PCLK

SIOPCLKR_SIOPCLK

R287 15RST
R297 15RST

CLKVCC3

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

2

1

SB_OSC14 18
AC_14 23
APICCLK 17,19

USBCLK_SBFS3

VCLK
GCLK_NB
GCLK_SLOT

PCICLK4
PCICLK5
1394_PCLK
SATAPCLK

SIO48M

"-SEL_66" Freq.-Out select pin =>
Low->66MHz , Hi->33MHz .
( Internal pull-up via 100K ohm )

USBCLK_SB 19

VCLK 17
GCLK_NB 13
GCLK_SLOT 16

PCICLK4 21
PCICLK5 22
1394_PCLK 26
SATAPCLK 24

SBPCLK 17
SIOPCLK 29
SIO48M 29

SMBDATA1 9,18,27
SMBCLK1 9,18,27

CPUCLK0_H 6
CPUCLK0_L 6

VCLK
GCLK_NB
GCLK_SLOT

GLAN_PCLK

USBCLK_SB
SIO48M
SB_OSC14
APICCLK
AC_14

PCICLK4
PCICLK5
1394_PCLK
SATAPCLK

SBPCLK

MS1_PCLK

SIOPCLK

CPUCLK0_H
CPUCLK0_L

VCC3

Decoupling Cap for CPU Clock

Micro Star Restricted Secret

Clock Synthesizer

MS-6761N1

Last Revision Date:

Wednesday, January 15, 2003

Sheet

8 36

1

CN20

7 8
5 6
3 4
1 2

X_8P4C-10P

C352 X_10P

C364 X_10P
C310 X_10P
C325 X_10P
C307 X_10P

CN21

7 8
5 6
3 4
1 2

X_8P4C-10P

C374 X_10P

C363 X_10P

C365 X_10P

Near CK-Gen in 0.5" .

C342 X_5P/X7R
C347 X_5P/X7R

C212 104P/25V/Y5V

Rev

of

0A

5

-MSWEA5,10

104P/25V/Y5V

C29

DR_MD[63..0]

DR_MD0
DR_MD1
DR_MD2
DR_MD3
DR_MD4
DR_MD5
DR_MD6
DR_MD7
DR_MD8
DR_MD9
DR_MD10
DR_MD11
DR_MD12
DR_MD13
DR_MD14
DR_MD15
DR_MD16
DR_MD17
DR_MD18
DR_MD19
DR_MD20
DR_MD21
DR_MD22
DR_MD23
DR_MD24
DR_MD25
DR_MD26
DR_MD27
DR_MD28
DR_MD29
DR_MD30
DR_MD31
DR_MD32
DR_MD33
DR_MD34
DR_MD35
DR_MD36
DR_MD37
DR_MD38
DR_MD39
DR_MD40
DR_MD41
DR_MD42
DR_MD43
DR_MD44
DR_MD45
DR_MD46
DR_MD47
DR_MD48
DR_MD49
DR_MD50
DR_MD51
DR_MD52
DR_MD53
DR_MD54
DR_MD55
DR_MD56
DR_MD57
DR_MD58
DR_MD59
DR_MD60
DR_MD61
DR_MD62
DR_MD63

WP1

-MSWEA

C27
X_104P

2
4
6

8
94
95
98
99
12
13
19
20

105
106
109
110

23
24
28
31

114
117
121
123

33
35
39
40

126
127
131
133

53
55
57
60

146
147
150
151

61
64
68
69

153
155
161
162

72
73
79
80

165
166
170
171

83
84
87
88

174
175
178
179

90
63

1

9

101
102

DR_MD[63..0]10,11

D D

C C

B B

VDD_25_SUS

R195 4.7K

DDR_VREF

VREF routed as 40~50
mils trace wide ,
Space>25 mils

Place 104p and 1000p Cap. near the DIMM

Place near the DIMM

VDD_25_SUS

R52
1KRST

A A

R46
1KRST

C32
104P/25V/Y5V

C35
105P/0805/16V

VREF routed as 40~50 mils trace wide ,
Space>25 mils

C14 X_102P

R59 0

DDR_VREF

C24

C23

X_102P

X_104P

5

VDD_25_SUS

738467085

108

VDD0

VDD1

VDD2

VDD3

VDD4

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

WP(NC)
WE#

VREF
NC2

NC3
NC4

VSS0

VSS1

3111826344250586674818993

MEM_VREF 5

120

148

168223054627796

VDD5

VDD6

VDD7

VSS2

VSS3

VSS4

VDD8

VSS5

VDDQ0

VDDQ1

VSS6

VSS7

4

SYSTEM MEMORY

104

112

128

136

143

156

164

172

1801582

184

VDDQ2

VDDQ3

VDDQ4

VDDQ5

VDDQ6

VDDQ7

VDDQ8

VDDQ9

VDDQ10

184

DDR DIMM

SOCKET

VSS8

VSS9

VSS10

VSS11

VSS12

VSS13

VSS14

VSS15

VSS16

100

116

124

132

DIMM1 SLAVE ADDRESS
= (1010000X)B = A0

4

VDDQ11

VDDQ12

PIN

VSS17

VSS18

139

145

VDDQ13

VDDQ14

VSS19

VSS20

152

160

VDDID

VDDQ15

CS0#
CS1#
CS2#
CS3#

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8

FETEN

A10_AP

SDA

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

CK0(DU)
CK0#(DU)
CK1(CK0)

CK1#(CK0#)

CK2(DU)
CK2#(DU)

NC5

NC(RESET#)

CKE0
CKE1
CAS#
RAS#

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8

VSS21

DDR1

176

DDRDIMM_184

N13-1840021-F02

VDDSPD

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

A11
A12
A13

BA0
BA1
BA2
SCL

SA0
SA1
SA2

3

-MCS0

157
158
71
163

5
14
25
36
56
67
78
86
47

103

MAA0

48

MAA1

43

MAA2

41

MAA3

130

MAA4

37

MAA5

32

MAA6

125

MAA7

29

MAA8

122

MAA9

27

MAA10

141

MAA11

118

MAA12 MAB12

115

MAA13

167
59

52
113

SMBCLK1

92

SMBDATA1

91
181
182
183

DR_CHECK0

44

DR_CHECK1

45

DR_CHECK2

49

DR_CHECK3

51

DR_CHECK4

134

DR_CHECK5

135

DR_CHECK6

142

DR_CHECK7

144

MEMCLK_H5

16

MEMCLK_L5

17

MEMCLK_H0

137

MEMCLK_L0

138

MEMCLK_H7

76

MEMCLK_L7

75
173

10

MCKE0

21

MCKE1

111

-MSCASA

65

-MSRASA

154

DR_DM0

97

DR_DM1

107

DR_DM2

119

DR_DM3

129

DR_DM4

149

DR_DM5

159

DR_DM6

169

DR_DM7

177

DR_DM8

140

-MCS1

-DR_MDQS0

-DR_MDQS1

-DR_MDQS2

-DR_MDQS3

-DR_MDQS4

-DR_MDQS5

-DR_MDQS6

-DR_MDQS7

-DR_MDQS8

-MCS0 5,10

-MCS1 5,10

-DR_MDQS0 10,11

-DR_MDQS1 10,11

-DR_MDQS2 10,11

-DR_MDQS3 10,11

-DR_MDQS4 10,11

-DR_MDQS5 10,11

-DR_MDQS6 10,11

-DR_MDQS7 10,11

-DR_MDQS8 10,11

MAA[13..0]

MEMBANKA0 5,10
MEMBANKA1 5,10

SMBCLK1 8,18,27
SMBDATA1 8,18,27

DR_CHECK[7..0]

MEMCLK_H5 5,10
MEMCLK_L5 5,10
MEMCLK_H0 5,10
MEMCLK_L0 5,10
MEMCLK_H7 5,10
MEMCLK_L7 5,10

MCKE0 5,10
MCKE1 5,10

-MSCASA 5,10

-MSRASA 5,10

MAA[13..0] 5,10

DR_CHECK[7..0] 10,11

VDD_25_SUS

DDR_VREF

VREF routed as 40~50
mils trace wide ,
Space>25 mils

-MSWEB5,10

C43
104P/25V/Y5V

R193 4.7K

DR_MD0
DR_MD1
DR_MD2
DR_MD3
DR_MD4
DR_MD5
DR_MD6
DR_MD7
DR_MD8
DR_MD9
DR_MD10
DR_MD11
DR_MD12
DR_MD13
DR_MD14
DR_MD15
DR_MD16
DR_MD17
DR_MD18
DR_MD19
DR_MD20
DR_MD21
DR_MD22
DR_MD23
DR_MD24
DR_MD25
DR_MD26
DR_MD27
DR_MD28
DR_MD29
DR_MD30
DR_MD31
DR_MD32
DR_MD33
DR_MD34
DR_MD35
DR_MD36
DR_MD37
DR_MD38
DR_MD39
DR_MD40
DR_MD41
DR_MD42
DR_MD43
DR_MD44
DR_MD45
DR_MD46
DR_MD47
DR_MD48
DR_MD49
DR_MD50
DR_MD51
DR_MD52
DR_MD53
DR_MD54
DR_MD55
DR_MD56
DR_MD57
DR_MD58
DR_MD59
DR_MD60
DR_MD61
DR_MD62
DR_MD63

C30
X_102P

WP2

-MSWEB

2

DQ0

4

DQ1

6

DQ2

8

DQ3

94

DQ4

95

DQ5

98

DQ6

99

DQ7

12

DQ8

13

DQ9

19

DQ10

20

DQ11

105

DQ12

106

DQ13

109

DQ14

110

DQ15

23

DQ16

24

DQ17

28

DQ18

31

DQ19

114

DQ20

117

DQ21

121

DQ22

123

DQ23

33

DQ24

35

DQ25

39

DQ26

40

DQ27

126

DQ28

127

DQ29

131

DQ30

133

DQ31

53

DQ32

55

DQ33

57

DQ34

60

DQ35

146

DQ36

147

DQ37

150

DQ38

151

DQ39

61

DQ40

64

DQ41

68

DQ42

69

DQ43

153

DQ44

155

DQ45

161

DQ46

162

DQ47

72

DQ48

73

DQ49

79

DQ50

80

DQ51

165

DQ52

166

DQ53

170

DQ54

171

DQ55

83

DQ56

84

DQ57

87

DQ58

88

DQ59

174

DQ60

175

DQ61

178

DQ62

179

DQ63

90

WP(NC)

63

WE#

1

VREF

9

NC2

101

NC3

102

NC4

Place 104p and 1000p Cap. near the DIMM

DR_DM[8..0]

DR_DM[8..0] 10,11

3

2

VDD_25_SUS

738467085

108

120

148

168223054627796

VDD0

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

VDD7

VSS0

VSS1

VSS2

VSS3

VSS4

3111826344250586674818993

DIMM2 SLAVE ADDRESS
= (1010001X)B = A2

Title

104

112

VDD8

VDDQ0

VDDQ1

VDDQ2

VDDQ3

VDDQ4

VDDQ5

VDDQ6

DDR DIMM

SOCKET

VSS5

VSS6

VSS7

VSS8

VSS9

VSS10

VSS11

VSS12

100

Micro Star Restricted Secret

System Memory : DDR DIMM 1

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

2

128

136

VDDQ7

VDDQ8

VDDQ9

184

VSS13

VSS14

VSS15

116

124

143

156

VDDQ10

VDDQ11

VSS16

VSS17

132

139

164

172

VDDQ12

PIN

VSS18

145

152

1801582

VDDQ13

VDDQ14

VDDQ15

CK1#(CK0#)

NC(RESET#)

VSS19

VSS20

VSS21

160

176

184

VDDID

CS0#
CS1#
CS2#
CS3#

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8

FETEN

A10_AP

A11
A12
A13

BA0
BA1

BA2
SCL
SDA

SA0

SA1

SA2
CB0

CB1
CB2
CB3
CB4
CB5
CB6
CB7

CK0(DU)
CK0#(DU)
CK1(CK0)

CK2(DU)
CK2#(DU)

NC5

CKE0
CKE1
CAS#
RAS#

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8

MS-6761N1

1

VDDSPD

-MCS2

157

-MCS3

158
71
163

-DR_MDQS0

5

-DR_MDQS1

14

-DR_MDQS2

25

-DR_MDQS3

36

-DR_MDQS4

56

-DR_MDQS5

67

-DR_MDQS6

78

-DR_MDQS7

86

-DR_MDQS8

47

MAB[13..0]

103

MAB0

48

A0

MAB1

43

A1

MAB2

41

A2

MAB3

130

A3

MAB4

37

A4

MAB5

32

A5

MAB6

125

A6

MAB7

29

A7

MAB8

122

A8

MAB9

27

A9

MAB10

141

MAB11

118
115

MAB13

167

MEMBAKB0

59

MEMBAKB1

52
113

SMBCLK1

92

SMBDATA1

91
181
182
183

DR_CHECK0

44

DR_CHECK1

45

DR_CHECK2

49

DR_CHECK3

51

DR_CHECK4

134

DR_CHECK5

135

DR_CHECK6

142

DR_CHECK7

144

MEMCLK_H4

16

MEMCLK_L4

17

MEMCLK_H1

137

MEMCLK_L1

138

MEMCLK_H6

76

MEMCLK_L6

75
173

10

MCKE0

21

MCKE1

111

-MSCASB

65

-MSRASB

154

DR_DM0

97

DR_DM1

107

DR_DM2

119

DR_DM3

129

DR_DM4

149

DR_DM5

159

DR_DM6

169

DR_DM7

177

DR_DM8

140

DDR2
DDRDIMM_184

N13-1840021-F02

MEMCLK_H5

Last Revision Date:

Wednesday, January 15, 2003

Sheet

9 36

1

-MCS2 5,10

-MCS3 5,10

MAB[13..0] 5,10

MEMBAKB0 5,10
MEMBAKB1 5,10

VDD_25_SUS

MEMCLK_H4 5,10
MEMCLK_L4 5,10
MEMCLK_H1 5,10
MEMCLK_L1 5,10
MEMCLK_H6 5,10
MEMCLK_L6 5,10

-MSCASB 5,10

-MSRASB 5,10

MEMCLK_H5 5,10

of

Rev

0A

5

4

3

2

1

DDR Terminations

VTT_DDR_SUS VTT_DDR_SUS

DR_MD40
DR_MD39
DR_MD35

D D

DR_MD59
DR_MD63
DR_MD58
DR_MD62

-DR_MDQS7
DR_DM7
DR_MD57
DR_MD61

DR_MD56
DR_MD60
DR_MD51
DR_MD55

C C

B B

MEMBANKA05,9

MEMBAKB05,9

MEMBANKA15,9

DR_MD50
DR_MD54

-DR_MDQS6
DR_DM6

MAA13
MAB13
DR_MD53
DR_MD52

DR_MD49
DR_MD48
DR_MD47
DR_MD46

DR_MD43
DR_MD42
DR_DM5

-DR_MDQS5

-MCS1

-MCS15,9

-MCS0

-MCS05,9

-MSCASA

-MSCASA5,9
DR_MD41

-MSWEB

-MSWEB5,9
DR_MD45

-MSRASB

-MSRASB5,9
DR_MD44

-MSRASA

-MSRASA5,9

RN76 8P4R-47

7 8
5 6
3 4
1 2

RN75 8P4R-47

7 8
5 6
3 4
1 2

RN74 8P4R-47

7 8
5 6
3 4
1 2

RN72 8P4R-47

7 8
5 6
3 4
1 2

RN70 8P4R-47

7 8
5 6
3 4
1 2

RN68 8P4R-47

7 8
5 6
3 4
1 2

RN66 8P4R-47

7 8
5 6
3 4
1 2

RN65 8P4R-47

7 8
5 6
3 4
1 2

RN62 8P4R-47

7 8
5 6
3 4
1 2

RN57 8P4R-47

7 8
5 6
3 4
1 2

MEMBAKB15,9

DR_MD38

DR_MD34
DR_DM4

-DR_MDQS4
DR_MD37

DR_MD33
DR_MD36
DR_MD32

DR_CHECK7
DR_CHECK3
DR_CHECK6
DR_CHECK2

DR_DM8

-DR_MDQS8
DR_CHECK1
DR_CHECK0

DR_CHECK5
DR_CHECK4
DR_MD31
DR_MD27

MAA1
MAB1
MAA2
MAB2

MAA3
MAA4
MAB4
MAA6

DR_MD30
MAB3
DR_MD26
DR_DM3

-DR_MDQS3
DR_MD25
DR_MD29
DR_MD28

MAB6
MAB5
MAA5
MAA8

VTT_DDR_SUS

RN54 8P4R-47

7 8
5 6
3 4
1 2

RN46 8P4R-47

7 8
5 6
3 4
1 2

RN45 8P4R-47

7 8
5 6
3 4
1 2

RN44 8P4R-47

7 8
5 6
3 4
1 2

RN41 8P4R-47

7 8
5 6
3 4
1 2

RN37 8P4R-47

7 8
5 6
3 4
1 2

RN31 8P4R-47

7 8
5 6
3 4
1 2

RN27 8P4R-47

7 8
5 6
3 4
1 2

RN30 8P4R-47

7 8
5 6
3 4
1 2

RN29 8P4R-47

7 8
5 6
3 4
1 2

RN24 8P4R-47

7 8
5 6
3 4
1 2

DR_MD24
DR_MD19
DR_MD23
MAA7

DR_DM2
MAA9
MAA11
MAA12

MAB8
DR_MD22
MAB7
DR_MD18

MAB9
MAB11
DR_MD21

-DR_MDQS2

DR_MD17
MAB12
DR_MD16
DR_MD20

DR_MD11
DR_MD10
DR_MD15
DR_MD14

DR_DM1
DR_MD13

-DR_MDQS1
DR_MD12

DR_MD9
DR_MD8
DR_MD3
DR_MD7

DR_MD6
DR_MD2
DR_DM0

-DR_MDQS0

DR_MD1
DR_MD5
DR_MD4
DR_MD0

MAB10
MAB0
MAA10
MAA0

RN22 8P4R-47

7 8
5 6
3 4
1 2

RN20 8P4R-47

7 8
5 6
3 4
1 2

RN18 8P4R-47

7 8
5 6
3 4
1 2

RN15 8P4R-47

7 8
5 6
3 4
1 2

RN13 8P4R-47

7 8
5 6
3 4
1 2

RN9 8P4R-47

7 8
5 6
3 4
1 2

RN7 8P4R-47

7 8
5 6
3 4
1 2

RN5 8P4R-47

7 8
5 6
3 4
1 2

RN4 8P4R-47

7 8
5 6
3 4
1 2

RN2 8P4R-47

7 8
5 6
3 4
1 2

RN39 8P4R-47

7 8
5 6
3 4
1 2

-MCS2

-MCS25,9

-MCS3

-MCS35,9
MAB13

MAA13

VTT_DDR_SUS

MCKE05,9
MCKE15,9

-MCS3

-MCS35,9

-MCS2

-MCS25,9

-MSCASB

-MSCASB5,9

-MSWEA

-MSWEA5,9

DR_DM[8..0]9,11

-DR_MDQS[8..0]9,11

DR_MD[63..0]9,11

MAB[13..0]5,9
MAA[13..0]5,9

DR_CHECK[7..0]9,11

R72 47
R68 47

RN63 8P4R-47

7 8
5 6
3 4
1 2

DR_DM[8..0]

-DR_MDQS[8..0]

DR_MD[63..0]
MAB[13..0]
MAA[13..0]

DR_CHECK[7..0]

MEMBAKB15,9

MEMBANKA15,9

MEMBAKB05,9

MEMBANKA05,9

MAB12
MAA12
MAB11
MAA11

MAB1
MAA1

MAB3
MAA3
MAB2
MAA2

MAB6

MAA6
MAB4
MAA4

MAB8
MAA8
MAA5
MAB5

MAA0

MAA10

MAB0
MAB10

-MSCASB

-MSCASB5,9

-MCS0

-MCS05,9

-MSCASA

-MSCASA5,9

-MCS1

-MCS15,9

MAA9
MAB9
MAB7
MAA7

-MSRASB

-MSRASB5,9

-MSRASA

-MSRASA5,9

-MSWEA

-MSWEA5,9

-MSWEB

-MSWEB5,9

MCKE15,9

MCKE05,9

CN19

8P4C-22P
CN6

8P4C-22P
CN14

8P4C-22P
CN12

8P4C-22P
CN11

8P4C-22P
CN10

8P4C-22P
CN15

8P4C-22P
CN18

8P4C-22P
CN8

8P4C-22P
CN17

8P4C-22P
CN16

8P4C-22P
CN5

8P4C-22P

12
34
56
78

12
34
56
78

12
34
56
78

12
34
56
78

12
34
56
78

12
34
56
78

12
34
56
78

12
34
56
78

12
34
56
78

12
34
56
78

12
34
56
78

12
34
56
78

MEMCLK_H55,9

A A

MEMCLK_H05,9

MEMCLK_H65,9 MEMCLK_L6 5,9
MEMCLK_H15,9

MEMCLK_H5

MEMCLK_H0

MEMCLK_H4
MEMCLK_H6
MEMCLK_H1

5

R74 120RST
R103 120RST
R95 120RST

R73 120RST
R105 120RST
R93 120RST

MEMCLK_L5

MEMCLK_L7MEMCLK_H7
MEMCLK_L0

MEMCLK_L4
MEMCLK_L6
MEMCLK_L1

MEMCLK_L5 5,9
MEMCLK_L7 5,9MEMCLK_H75,9
MEMCLK_L0 5,9

MEMCLK_L4 5,9MEMCLK_H45,9

MEMCLK_L1 5,9

Title
Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

4

3

http://www.msi.com.tw

2

Micro Star Restricted Secret

DDR Terminations Bank 0

MS-6761N1

Last Revision Date:

Tuesday, January 14, 2003

Sheet

10 36

of

1

Rev

0A

5

4

3

2

1

LAYOUT: Place on backside,

MD38

R126 10

RN43 8P4R-10

MEMCHECK7 DR_CHECK7

DDR Terminations

-MDQS0 -DR_MDQS0

D D

C C

B B

R66 10

RN6 8P4R-10

MD0

1 2

MD4

3 4

MD5

5 6

MD1

7 8

RN8 8P4R-10

DM0

1 2
3 4

MD6 DR_MD6

5 6

MD7 DR_MD7

7 8

RN10 8P4R-10

1 2

MD8 DR_MD8

3 4

MD9 DR_MD9

5 6
7 8

MD15

R76 10

RN12 8P4R-10

-MDQS1

1 2

MD13 DR_MD13
DM1
MD14 DR_MD14

3 4
5 6
7 8

RN19 8P4R-10

1 2

MD17

3 4

MD21 DR_MD21

5 6

DM2

7 8

MD18

R89 10

RN16 8P4R-10

MD10

1 2
3 4

MD20 DR_MD20

5 6

MD16 DR_MD16

7 8

RN23 8P4R-10

1 2

MD23 DR_MD23

3 4
5 6

MD24

7 8

RN26 8P4R-10

1 2

MD29

3 4
5 6

-MDQS3

7 8

RN32 8P4R-10

MD26

1 2
3 4

MD27

5 6

MD31 DR_MD31

7 8

DR_MD0
DR_MD4
DR_MD5
DR_MD1

DR_DM0
DR_MD2MD2

DR_MD3MD3

DR_MD12MD12

DR_MD15

-DR_MDQS1
DR_DM1

-DR_MDQS2-MDQS2
DR_MD17

DR_DM2

DR_MD18

DR_MD10
DR_MD11MD11

DR_MD22MD22
DR_MD19MD19

DR_MD24

DR_MD28MD28
DR_MD29
DR_MD25MD25

-DR_MDQS3

DR_MD26
DR_MD30MD30
DR_MD27

-MDQS7

MD63

MEMCHECK5
MEMCHECK0
MEMCHECK1

-MDQS8

1 2
3 4
5 6
7 8

RN47 8P4R-10

1 2

-MDQS4 -DR_MDQS4

3 4

DM4

5 6

MD34 DR_MD34

7 8

MD42

R133 10
RN56 8P4R-10

MD35 DR_MD35

1 2

MD39 DR_MD39

3 4
5 6

MD44 DR_MD44

7 8

RN60 8P4R-10

1 2

MD41 DR_MD41

3 4

-MDQS5 -DR_MDQS5

5 6

DM5 DR_DM5

7 8

RN64 8P4R-10

MD43

1 2

MD46 DR_MD46

3 4

MD47 DR_MD47

5 6
7 8

RN67 8P4R-10

1 2
3 4

MD53 DR_MD53

5 6
7 8

MD51

R169 10

RN69 8P4R-10

1 2
3 4

MD50

5 6

MD55

7 8

RN71 8P4R-10

1 2

MD56

3 4

MD61 DR_MD61

5 6

MD57 DR_MD57

7 8

RN73 8P4R-10

DM7

1 2
3 4

MD62 DR_MD62

5 6

MD58

7 8

R191 10

R189 10

RN38

1 2
3 4
5 6
7 8

8P4R-10

DM8

MEMCHECK2 DR_CHECK2

-MDQS[8..0]5

-DR_MDQS[8..0]9,10
DR_MD[63..0]9,10

MD[63..0]5

A A

MEMCHECK[7..0]5

DR_CHECK[7..0]9,10

DR_DM[8..0]9,10

DM[8..0]5

-MDQS[8..0]

-DR_MDQS[8..0]
DR_MD[63..0]

MD[63..0]

MEMCHECK[7..0]

DR_CHECK[7..0]

DR_DM[8..0]

DM[8..0]

5

MEMCHECK6
MEMCHECK3

MEMCHECK4

DM3

RN40

1 2
3 4
5 6
7 8

8P4R-10

R100 10

R94 10

DR_MD38

DR_MD32MD32
DR_MD36MD36
DR_MD33MD33

DR_MD37MD37
DR_DM4

DR_MD42

DR_MD40MD40

DR_MD45MD45

DR_MD43

DR_MD48MD48

DR_MD49MD49
DR_MD52MD52

DR_DM6DM6

DR_MD51

-DR_MDQS6-MDQS6
DR_MD54MD54
DR_MD50
DR_MD55

DR_MD60MD60
DR_MD56

DR_DM7

-DR_MDQS7
DR_MD58

DR_MD59MD59

VDD_25_SUS VDD_25_SUS VDD_25_SUS VDD_25_SUS VDD_25_SUS

VTT_DDR_SUS

VTT_DDR_SUS

evenly spaced around VTT fill.

VDD_25_SUS VDD_25_SUS

VTT_DDR_SUS VTT_DDR_SUS

C186

X_0.22u

{nopop}

C247

X_0.22u

{nopop}

C262

X_0.22u

{nopop}

C267

X_0.22u

{nopop}

C47

104P/25V/Y5V
C62

104P/25V/Y5V

C75

104P/25V/Y5V
C78

104P/25V/Y5V

C85

104P/25V/Y5V

C91

104P/25V/Y5V
C98

104P/25V/Y5V

LAYOUT: Place alternating caps to GND and VDD_2.5_SUS in a single line along VTT island.

C60

C73

104P/25V/Y5V

C76

104P/25V/Y5V

C81

104P/25V/Y5V

104P/25V/Y5V

C101

104P/25V/Y5V
C109

104P/25V/Y5V

C119

104P/25V/Y5V
C126

104P/25V/Y5V

C132

104P/25V/Y5V

C134

104P/25V/Y5V

C137

104P/25V/Y5V

C88

104P/25V/Y5V

C95

C12

X_0.22u

{nopop}

C56

X_0.22u

{nopop}

C28

X_0.22u

{nopop}

C11

X_0.22u

{nopop}

C58

X_0.22u

{nopop}

104P/25V/Y5V

C99

C105

104P/25V/Y5V

C143

104P/25V/Y5V
C145

104P/25V/Y5V
C147

104P/25V/Y5V

C160

104P/25V/Y5V

C165

104P/25V/Y5V

C169

104P/25V/Y5V

C176

104P/25V/Y5V

C112

104P/25V/Y5V

C122

104P/25V/Y5V

C131

104P/25V/Y5V

C182

104P/25V/Y5V

C188

104P/25V/Y5V

C191

104P/25V/Y5V

C195

104P/25V/Y5V

C202

104P/25V/Y5V

C209

104P/25V/Y5V

C218

104P/25V/Y5V

C133

104P/25V/Y5V

C136

104P/25V/Y5V

C140

104P/25V/Y5V

C144

104P/25V/Y5V

LAYOUT: Locate close
to Clawhammer
socket.

VTT_DDR_SUS

+

EC17

1000U/6.3V

VTT_DDR_SUSVTT_DDR_SUSVTT_DDR_SUSVTT_DDR_SUSVTT_DDR_SUS

C226

104P/25V/Y5V

C232

104P/25V/Y5V

C240

104P/25V/Y5V

C245

104P/25V/Y5V

C250

104P/25V/Y5V

C257

104P/25V/Y5V

C153

C146

104P/25V/Y5V

GND

104P/25V/Y5V

104P/25V/Y5V

GND

+

EC5
1000U/6.3V

DR_MD63

C215

DR_CHECK5
DR_CHECK0
DR_CHECK1

-DR_MDQS8

DR_DM8

DR_CHECK6
DR_CHECK3

DR_CHECK4

C163

104P/25V/Y5V

VTT_DDR_SUS

0.22uC74

C51

VTT_DDR_SUS

C167

4.7u/0805

C173

104P/25V/Y5V

C59

X_0.22uC57

10u/1206

C190

C185

C179

104P/25V/Y5V

104P/25V/Y5V

104P/25V/Y5V

LAYOUT: Locate close to
Clawhammer socket.

102PC25

C17

X_4.7u/0805

X_100PC18

C194

104P/25V/Y5V

X_102PC16

X_0.22uC10

C198

104P/25V/Y5V

X_100PC15

GND

C205

104P/25V/Y5V

DR_DM3

102PC172

X_100PC271

X_102PC273

4

C272

X_4.7u/0805

3

X_100PC270

C253

X_4.7u/0805

X_0.22uC243

C187

4.7u/0805

0.22uC151

C178

10u/1206

GND

104P/25V/Y5V

C220

104P/25V/Y5V

Title

C228

104P/25V/Y5V

C242

C235

104P/25V/Y5V

104P/25V/Y5V

Micro Star Restricted Secret

DDR Terminations Bank 1

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

2

C248

104P/25V/Y5V

C254

104P/25V/Y5V

MS-6761N1

104P/25V/Y5V

C266

104P/25V/Y5V

GND

Last Revision Date:

Wednesday, January 15, 2003

Sheet

11 36

of

1

Rev

0A