MSI MS-10581 BLOCK DIAGRAM
5
4
3
2
1
AMD S1 PROCESSOR
EXTERNAL CLOCK GENERATOR
D D
ICS951462
16
HyperTransport
638-Pin uFCPGA 638
LINK0
OUT
5,6,7,8
16x16
IN
DDR II 400/533/667
UNBUFFERED
DDR2 NEAR
SODIMM
9,10
200-PIN DDR2 SODIMM
UNBUFFERED
DDR2 FAR
LVDS CON
15
LVDS
ATI NB - RSRS485M
SODIMM
200-PIN DDR2 SODIMM
9,10
HyperTransport LINK0 CPU I/F
BOOTSTRAPS
ROM(DNI)
13
I2C I/F
INTEGRATED GRAPHICS
LVDS/TVOUT/TMDS
1 X16 PCIE VIDEO/SDVO I/F
CRT
VGA CON
15
1 X4 PCIE I/F WITH SB
2(4) X1 PCIE I/F
X1 PCIE INTERFACE
C C
NEW CARD
23
RTL8111B
PCIE ETHERNET
X1
25
11,12,13,14
PCIE
X2
ATI SB - SB460
USB#3
23
B B
MiniPCINewCard
USB#4
USBPORT USBPORT USBPORT
28
USB#1USB#2
2828
USB#6USB#7 USB#5
BOOTSTRAPS
ROM (SB)
SECONDARY PCI BUS
USB 2.0USB#0
28
DNIDNIDNI
USB 2.0 (8 PORTS)
SATA (4 PORTS)
AZALIA HD AUDIO
HD AUDIO I/F
AZALIA CODEC
26
AZALIA
CONNECTOR
27
AC97 2.3
ATA 66/100/133
SPI I/F
LPC I/F
IDE CONNECTORATA 66/100/133 I/F
29
ACPI 2.0
OZ128
1394 &
CARDREADER
22
21
I2C I/F
INT RTC
HW MONITOR
PCI
PCI/PCI BDGE
17, 18, 19, 20, 21
MINIPCI SLOT
LPC BUS
30
BATTERY CHAGER
41
SYSTEM MAIN POWER
37
A A
SB460 & PCIE POWER
CPU CORE POWER
CPU&RS485 HT
VLDT POWER
35
36
CPU MEMORY POWER
RS485 CORE
POWER
38
39
KBC ENE3910
KBD
MOUSE
31 34
BIOS
31
ISA I/FPS2
DISCHARGE CIRCUIT
52
RESET,FAN,SPKR
& ENABLES
42
39
MICRO-STAR INT'L CO.,LTD.
Title
BLOCK DIAGRAM
Size Document Number Rev
Custom
5
4
3
2
Date: Sheet of
MS-10581
1
1 44Tuesday, January 10, 2006
A
5
4
3
2
1
TABLE OF CONTENTS
P01: BLOCK DIAGRAM
P02: TABLE OF CONTENTS
P03: POWER DELIVERY CHART
P04: CLOCK DISTRIBUTION
P05: Socket S1 HT I/F
D D
C C
P06: Socket S1 DDRII MEMORY I/F
P07: Socket S1 CTRL
P08: Socket S1 PWR & GND
P09: DDR2 SODIMMS: A/B CHANNEL
P10: DDR2 SODIMMS TERMINATIONS
P11: RS485-HT LINK0 I/F
P12: RS485-PCIE LINK I/F
P13: RS485-SYSTEM I/F & CLKGEN
P14: RS485-POWER
P15: LVDS & INVERTER
P16: CLOCK GENERATOR(ICS951462)
P17: SB460-PCIE/PCI/CPU/LPC
P18: SB460-ACPI/GPIO/USB/AUDIO
P19: SB460-SATA/IDE/HWM/SPI
P20: SB460-POWER & DECOUPLING
P21: SB460-STRAPS
P22: PCI/1394/FLASH CARD(OZ128)
P23: NEWCARD & MDC CONN
P24: DVI
P25: PCIE GIGALAN(RTL8111B)
P26: Audio(ALC882)
P27: AMP(FAN7031)HP & Mic
P28: USB2.0 CON x 3 / Camera
P29: HDD & CDROM CONN.
P30: MiniPCI/BlueTooth(6855B)
P31: KBC (ENE3910) & ISA BIOS
P32: LED & LAUNCH Key
P33: POWER GOOD
P34: SYSTEM & CPU FAN
P35: M_1.2V VDDA 2.5V VLDT
P36: VCORE
P37: SYSTEM POWER 3/5VSUS
P38: DDR2 1.8V VTT 0.9V
P39: VCC_NB 1.2V 1.8V 1.5VRUN
P40: M_Battery select
P41: M_Battery Charger
P43: PCB IMPEDANCE JUMP
P43: CPU CORE PWR
POWER RAIL
+12V_ATX +12V
-12V_ATX -12V
+5VALW_ATX +5V
+3.3VALW_ATX
+5VDUAL_ATX
+3.3VDUAL_ATX
+5V_ATX
+3.3V_ATX
+VDC
+VIN +12V
+5VALW_NTB
+3.3VALW_NTB
+5VSUS_NTB
+3.3VSUS_NTB +3.3V
+5V_NTB
+3.3V_NTB
+5VALW
+3.3VALW
+1.2VALW +1.2V
+5VSUS
+3.3VSUS
+5V OFFOFF
+3.3V
CPU_VDD_RUN
VLDT_RUN
CPU_VCCA_RUN
+3.3V
+5V
+3.3V
+5V
+3.3V
+12V
+5V
+3.3V
+5V OFFOFF OFF OFF OFF
+5V
+3.3V
+5V
+3.3V
+5V
+3.3V
+5V
+3.3V
VID[5:0]
+1.05V
+1.5V
DESKTOP MODE LAPTOP MODE
S0 S1 S3 S4
ON ON OFF
ON ON
ON ONON ON ON
ON ONON
ON ON ON
OFF OFF
ON ONONON ON
ON
ON
OFF OFF
OFF
ON OFFOFFON
OFF OFFONON OFF
OFF
ON
ONON ON
ONONON
ON OFFONON OFF
ON OFFON
S5
OFFOFFOFF
ONON ONON ON
ON ON
ON ON
OFFOFFOFFOFF OFF
OFFOFF OFF OFF OFF
OFFOFFOFFOFF OFF
OFFOFF
OFFOFF OFF
OFFOFF OFF OFF
ON
ON
OFFOFF
OFF
OFFON ON
OFFOFFOFFONON
OFFOFFOFFONON OFF OFF OFFON ON
S0 S1 S3 S4 S5
OFF OFFOFF OFF OFF
OFF OFFOFF OFF OFF
OFF OFFOFF OFF OFF
OFF OFFOFF OFF OFF
OFF OFFOFF OFF OFF
OFF OFFOFF OFF OFF
OFF OFFOFF OFF OFF
OFF OFFOFF OFF OFF
ON
ON ON ON
ON
ON ON
ON OFF
ON
ONON ON
ON
ON ON ON
ON ON
ON OFFOFFOFFONOFF OFF OFFON ON
OFF OFFON
ON
ON
OFF OFFON OFFON
OFF OFF OFF
ONON ONON ONOFFOFFOFF
OFFOFFOFFONONOFFON ON OFF OFF
ONON
ONON
ONON ONON
ON
OFFOFF
OFFOFF
OFFON ON OFFOFF
ONON
ON
ONONON
ON
ONON ON ON
OFF OFF
OFFOFFOFFONONOFF OFF OFFON ON
POWER RAIL
VCC_NB
VDDA_1V2
VDDA18
VDD18
VDDR3
VDDR +1.8V OFFOFFOFFONON
CPU_VDDIO_SUS
CPU_M_VREF_SUS ONON OFFOFFON
MEM_M_VREF_SUS
CPU_VTT_SUS
+VIN_MEM +12V/+5V OFF OFFON ON ON ON OFF OFFON ON
A_VBAT
VCC_SB
PCIE_VDDR
AVDD_USB
+3.3V_AVDDC
PLLVDD_ATA
XTLVDD_ATA
AVDD_HWM
AVDDCK_3.3V
AVDDCK_1.2
+1.2V_USB_PHY +1.2V ONONONONON ON ONON ON ON
VCC_AUDIO +5V
+3.3V_NC
+1.5V_NC
+3.3VSUS_NC
+1.2V
+1.2V
+1.8V
+1.8V
+3.3V
+1.8V
+0.9V
+0.9V
+0.9V
+3.0V
+1.2V
+1.2V
+3.3V
+3.3V
+1.2V
+3.3V
+3.3V
+3.3V
+1.2V
+3.3V
+1.5V
+3.3V OFFOFFONON ON ONON ON OFF OFF
DESKTOP MODE
S0 S4S3S1 S5 S0 S5S1 S3 S4
OFFOFFOFFONON OFF OFFON ON OFF
OFFOFFOFFONON OFF OFF OFFON ON
OFFOFFOFFONON
ON OFF OFF OFFON
OFFOFFOFFONON
OFF OFFON ON ON
ON ON
ON ON OFF OFF OFF
ON
ON
ON OFFOFFOFFON
ON OFFON OFF OFF
OFFON OFFON OFFON OFF
ON OFFON OFF OFF
OFFOFFONON ON ON OFF OFF
ONONONON ON
OFFOFFOFFONON
OFFOFFONON
OFFON ON OFF
OFFOFFOFFONON
OFFON ON OFF OFF
OFFON OFFOFFON
OFFON OFF
OFFOFFON OFFON
LAPTOP MODE
ON OFF OFF OFFON
ON OFFOFFOFFON
ON OFF OFF OFFON
ON ON OFF OFF OFF
ON OFFOFFONON OFF OFFON ON ON
ONON OFFOFFON
ON OFF OFFON ON
ONON ON ON ON
ON ON OFF OFF OFF
OFFOFFOFFONON
ON ON OFF
ON
ON
ON ON OFF OFF
ON OFF
ON OFF OFF
OFF
OFF
OFFONON
OFF
OFFOFFON
OFFON
OFFON OFFOFFON
OFFON OFFOFFON
OFFOFFON OFFON
OFFON OFFON OFF
BOWFIN POWER ON/OFF SEQUENCE (ACPI_S3=LOW)
ENE ASIC8M
t1=1uS
t2=50uS
SIO_PSON#
ATX_PSON#
ATX_PWRGD
B B
VDIMM_DUAL_EN
VDDA_EN_OD
VCORE_EN_OD
VCORE_GD
VLDT_EN_OD
CPU_PWRGD_OD
VRM_PWRGD
VDRAM_PWRGD
NB_PWRGD
SB_PWRGD
ALL_POWERGOOD
PCI_RST#
RESET_CPU_L
EXT CLKx
A A
AMD CPU POWER
VDDA_2.5V_RUN
VDD_CORE_RUN
VDDHT
NB RS690/485 POWER
VDDR3,VDDR,VDDA18
AVDD,AVDDQ
VDDA12,VCC_NB,HTPVDD
SB SB600/460 POWER
+3.3V_SB,+1.8V_SB
AVDD_CK
+3.3VALW_SB
t1=50uS
wait PSON#
t3=50uS+t_vdda_gd
5
t4=50uS
t5=5mS+t_vldt_gd
t=50mS
t6=50uS
t7=10mS
t8=10mS
t9=10mS
t10=50mS
4
DEFAULT JUMPER SETTING FOR POWER ON PCI DEVICES IRQ TABLE
JUMPER DEF. FUNCTION
JU600 1-2
JU601
JU602
JU603
SW600
SW601
SW1100
SW1101
SW2700
SW2800
SW2801
SW3100
SW3101
SW3102
2-3 SELECT SB600 DEBUG BUS STRAPS OR IGNORE THEM
1-2
2-3
OPEN SELECT SATA IS[1:0]: CLOSED HIGH; OPEN LOW
OPEN
OPEN
OPEN
1-2
OPEN
OPEN
1-2
OPEN
OPEN
CMOS NORMAL MODE OR CLEAR CMOS
SELECT SB600 BIOS FLASH TYPE
SELECT SB600 STRAPS FOR PCIE
SELECT SATA IS[3:2]: CLOSED HIGH; OPEN LOW
SELECT LCD PANEL ID LCD_ID[1:0]: CLOSED LOW; OPEN HIGH
SELECT LCD PANEL ID LCD_ID[3:2]: CLOSED LOW; OPEN HIGH
SELECT CPU MODE: 1-2 PERFORMANCE MODE; 2-3 BATTERY MODE
SELECT CPU VID[5:2]: CLOSED LOW; OPEN HIGH
SELECT CPU VID[1:0]: CLOSED LOW; OPEN HIGH
SELECT LAPTOP/DESKTOP MODE: 1-2 DESKTOP MODE; 2-3 LAPTOP MODE
RESET BUTTON
POWER-ON BUTTON
3
DEVICE
NB VGA
SB
ATA100
AC97/AZALIA
USB
PCI SLOT2
PCI SLOT1
PCI SLOT0
MINI PCI SLOT
SMBUS TABLE
SOURCE SIGNAL NAME LINKED DEVICES
NB
SB
what's
that?
2
IDSEL# REQ/GNT# PCI INT CLOCK
N/A
AD31(INT)
AD31
AD31
AD30
AD23
AD22
AD21
AD20
DAC_SCL/DAC_SDAT CRT/LVDS
I2C_CLK/I2C_DATA LVDS/TMDS
I2C_CLK/DDC_DATA GFX X16
SCLK0/SDATA0
SCLK1/SDATA1
Title
TABLE OF CONTENTS
Size Document Number Rev
Custom
Date: Sheet of
MS-10581
N/A
A
N/AN/A
N/A
N/A
N/A
2
1
0
3
A
B
D
G
F
E
E,F
SO-DIMMs/CLK_GEN/CNR CON
/LPC SLOT/BAT CHG/THERM_SENSOR
GB ETH/GPP X1/NEW CARD
/PCI SLOTs
INT
INT
INT
PCI_CLK7
PCI_CLK1
PCI_CLK0
PCI_CLK2
MICRO-STAR INT'L CO.,LTD.
1
2 44Tuesday, January 10, 2006
A
5
4
3
2
1
SB SB460
+3.3VALW_NTB
+3.3VSUS_NTB
+VDC
BATTERY
D D
CPU
PWR
12V
12V
5VSB
5V
+/-5%
+/-5%
+/-5%
+/-5%
BATTERY
CHARGER
SWITCH
ATX POWER SUPPLY
C C
3.3V
+/-5%
MAIN PWR SW
REGULATOR
+3.3VALW LDO
REGULATOR
SW
+5VALW_NTB
+5VSUS_NTB
+VIN_MEM
+5VSUS
SW
SW
+5VALW_ATX
+5VDUAL_ATX
+5V_ATX
+3.3VALW_ATX
+3.3VDUAL_ATX
+3.3V_ATX
+3.3V_NTB
+5V_NTB
SWITCH
+3.3VALW
+3.3VSUS
+3.3V
POWER SWITCH
+5VALW
+5VSUS
+5V
+5V
+VIN
+5V
+VIN
+5V
+VIN
+5V
+VIN
+5V
+5V
+3.3V
+VIN
+5VSUS
1.5V SW
REGULATOR
SW REGULATOR
VLDT 1.2V SW
REGULATOR
NB CORE SW
REGULATOR
PCIE&SB SW
REGULATOR
1.8V SW
REGULATOR
1.8V VDD&VTT
SW REGULATOR
CPU_VDDA_RUN (S0, S1)
CPU_VDD_RUN (S0, S1)
VLDT_RUN (S0, S1)
VCC_NB (S0, S1)
VDDA_1V2(S0, S1)
+1.8V(S0, S1)
AVDD (S0, S1)
CPU_VDDIO_SUS (S0, S1, S3)
CPU_VTT_SUS (S0, S1)
AMD CPU
VCCA 2.5V
VDDCORE
0.375-1.500V 30A
VLDT 1.2V 3A
DDRII SODIMMX2
VDD MEM 4A
VTT_MEM 0.5A
NB RS485
HT VLDT 1.2V 1A
NB CORE 10A
PCI-E CORE
&PCI-E IO 3.5A
HTPLL (1.8V) 200mA
PLL & DAC-Q(1.8V)
200mA
TRANSFORMER
400mA
DAC 300mA
-12V
+/-5%
VCC_SB (S0, S1)
CONTROL SIGNAL:
MOBILE: BATTERY
DESKTOP: ATX
+3.3VALW
+3.3V
+3.3VALW
1.2V LDO
REGULATOR
+1.2VALW
+5V
MINI PCI SLOT
+3.3V
B B
+5V
+3.3VALW
3.3V(S0, S1)1.5A
5V (S0, S1) 0.1A
3.3V(S3, S5) 0.2A
+VIN
+3.3V
X4 PCI-E 0.8A
ATA I/O 0.2A
ATA PLL 0.01A
PCI-E PVDD 80mA
SB CORE 0.6A
1.2V S5 PW 0.22A
3.3V I/O 0.45A
3.3V S5 PW 0.01A
USB CORE I/O 0.2A
GBIT ENTHENET
3.3V 0.5A
(S0, S1, S3, S4, S5)
PCI-E CARD
1.5V (S0, S1) 0.7A
3.3V (S3, S5) 0.3A
3.3V (S0, S1) 1.3A
+5V
PCI Slot (per slot)
5V
3.3V
12V
3.3Vaux
-12V
A A
5.0A
7.6A
0.5A
0.375A
0.1A
3.3V
3.3Vaux
0.5A
0.1A
X16 PCIEX1 PCIE per
3.3V
12V12V
3.0A3.0A
5.5A
CNR CONNECTOR
5V
3.3V
12V
3.3Vaux
-12V
5VDual
1.0A
1.0A
0.5A
1.0A
0.1A
0.5A
+5VALW
USB X7 FR
VDD
5VDual
VDD
5VDual
1.0A3.5A
2XPS/2USB X2 RL
5VDual
1.0A
SUPER I/O
+3.3VDUAL (S3) 0.01A
+3.3V (S0, S1) 0.01A
+5V (S0, S1) 0.1A
HD CODEC
3.3V CORE 0.3A
5V ANALOG 0.1A
MICRO-STAR INT'L CO.,LTD.
Title
POWER DELIVERY CHART
Size Document Number Rev
Custom
5
4
3
2
Date: Sheet of
MS-10581
1
3 44Tuesday, January 10, 2006
A
5
D D
4
3
2
1
PCI CLK0
33MHZ
PCI CLK1
33MHZ
HTREFCLK
66MHZ
NB-OSC
C C
B B
NEAR SO-DIMM REV SO-DIMM
2 PAIR MEM CLK
ATHLON64 S1 CPU
2 PAIR MEM CLK
1 PAIR CPU CLK
LGA638 PACKAGE
EXTERNAL
CLK GEN.
200MHZ
14.318MHZ
NB PCIE CLK
100MHZ
SB PCIE CLK
100MHZ
SB-OSCIN
14.318MHZ
PCIE CLK
100MHZ
PCIE CLK
100MHZ
PCIE CLK
100MHZ
PCIE CLK
100MHZ
PCIE CLK
100MHZ
SUPER IO CLK
48MHZ
ATI NB - RS485M
TVCLKIN
TVCLKIN
PCIE GFX SLOT - 16 LANES
PCIE GPP SLOT 1 - 1 LANE
PCIE GPP SLOT 2 - 1 LANE
PCI EXPRESS CARD - 1 LANE
GIGABIT ETHERNET - 1 LANE
SB-OSCIN
14.318MHZ
ATI SB
SB460
SUPER IO CLK
SB-OSCIN
14.318MHZ
AZALIA_BITCLK
25MHZ OSC INPUT
PCIE CLK
100MHZ
USB CLK
48MHZ
PCI CLK2
33MHZ
PCI CLK3
33MHZ
48MHZ
PCI CLK4
33MHZ
PCI CLK5
33MHZ
PCI CLK6
33MHZ
PCI CLK7
33MHZ
25M Hz
PCI SLOT0
PCI SLOT1
MINI PCI SLOT
SUPER IO
IT8712F
LPC SLOT
LPC BIOS
DEBUG POST
PCI SLOT2
AZALIA CODEC
KB_CLK
MS_CLK
KEYBOARD
MOUSE
32.768K Hz
14.31818MHz
A A
MICRO-STAR INT'L CO.,LTD.
Title
CLOCK DISTRIBUTION
Size Document Number Rev
Custom
5
4
3
2
Date: Sheet of
MS-10581
1
4 44Tuesday, January 10, 2006
A
5
4
3
2
1
PROCESSOR HYPERTRANSPORT INTERFACE
VLDT_Ax AND VLDT_Bx ARE CONNECTED TO THE LDT_RUN POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
D D
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE
+VLDT
0922 by
harry
D4
D3
D2
D1
VLDT_A3
VLDT_A2
VLDT_A1
VLDT_A0
U1A
VLDT_B3
VLDT_B2
VLDT_B1
VLDT_B0
AE5
AE4
AE3
AE2
4.7u_0805
C1
HT_CADIN15_P11
HT_CADIN15_N11
HT_CADIN14_P11
HT_CADIN14_N11
HT_CADIN13_P11
C C
B B
HT_CADIN13_N11
HT_CADIN12_P11
HT_CADIN12_N11
HT_CADIN11_P11
HT_CADIN11_N11
HT_CADIN10_P11
HT_CADIN10_N11
HT_CADIN9_P11
HT_CADIN9_N11
HT_CADIN8_P11
HT_CADIN8_N11
HT_CADIN7_P11
HT_CADIN7_N11
HT_CADIN6_P11
HT_CADIN6_N11
HT_CADIN5_P11
HT_CADIN5_N11
HT_CADIN4_P11
HT_CADIN4_N11
HT_CADIN3_P11
HT_CADIN3_N11
HT_CADIN2_P11
HT_CADIN2_N11
HT_CADIN1_P11
HT_CADIN1_N11
HT_CADIN0_P11
HT_CADIN0_N11
N5
L0_CADIN_H15
P5
L0_CADIN_L15
M3
L0_CADIN_H14
M4
L0_CADIN_L14
L5
L0_CADIN_H13
M5
L0_CADIN_L13
K3
L0_CADIN_H12
K4
L0_CADIN_L12
H3
L0_CADIN_H11
H4
L0_CADIN_L11
G5
L0_CADIN_H10
H5
L0_CADIN_L10
F3
L0_CADIN_H9
F4
L0_CADIN_L9
E5
L0_CADIN_H8
F5
L0_CADIN_L8
N3
L0_CADIN_H7
N2
L0_CADIN_L7
L1
L0_CADIN_H6
M1
L0_CADIN_L6
L3
L0_CADIN_H5
L2
L0_CADIN_L5
J1
L0_CADIN_H4
K1
L0_CADIN_L4
G1
L0_CADIN_H3
H1
L0_CADIN_L3
G3
L0_CADIN_H2
G2
L0_CADIN_L2
E1
L0_CADIN_H1
F1
L0_CADIN_L1
E3
L0_CADIN_H0
E2
L0_CADIN_L0
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0
T4
T3
V5
U5
V4
V3
Y5
W5
AB5
AA5
AB4
AB3
AD5
AC5
AD4
AD3
T1
R1
U2
U3
V1
U1
W2
W3
AA2
AA3
AB1
AA1
AC2
AC3
AD1
AC1
HT_CADOUT15_P 11
HT_CADOUT15_N 11
HT_CADOUT14_P 11
HT_CADOUT14_N 11
HT_CADOUT13_P 11
HT_CADOUT13_N 11
HT_CADOUT12_P 11
HT_CADOUT12_N 11
HT_CADOUT11_P 11
HT_CADOUT11_N 11
HT_CADOUT10_P 11
HT_CADOUT10_N 11
HT_CADOUT9_P 11
HT_CADOUT9_N 11
HT_CADOUT8_P 11
HT_CADOUT8_N 11
HT_CADOUT7_P 11
HT_CADOUT7_N 11
HT_CADOUT6_P 11
HT_CADOUT6_N 11
HT_CADOUT5_P 11
HT_CADOUT5_N 11
HT_CADOUT4_P 11
HT_CADOUT4_N 11
HT_CADOUT3_P 11
HT_CADOUT3_N 11
HT_CADOUT2_P 11
HT_CADOUT2_N 11
HT_CADOUT1_P 11
HT_CADOUT1_N 11
HT_CADOUT0_P 11
HT_CADOUT0_N 11
+VLDT
4.7u_0805
C2
C3
4.7u_0805
0.22u_0603
C4
C5
0.22u_0603
0.01u_0402
C6
C7
0.01u_0402
LAYOUT: Place bypass cap on topside of board
NEAR HT POWER PINS THAT ARE NOT CONNECTED DIRECTLY
TO DOWNSTREAM HT DEVICE, BUT CONNECTED INTERNALLY
TO OTHER HT POWER PINS
PLACE CLOSE TO VLDT0 POWER PINS
HT_CLKIN1_P11
HT_CLKIN1_N11
+VLDT
A A
HT_CLKIN0_P11
HT_CLKIN0_N11
R1 51_0402
R2 51_0402
HT_CTLIN0_P11
HT_CTLIN0_N11
HT_CTLIN1_P
HT_CTLIN1_N
J5
L0_CLKIN_H1
K5
L0_CLKIN_L1
J3
L0_CLKIN_H0
J2
L0_CLKIN_L0
P3
L0_CTLIN_H1
P4
L0_CTLIN_L1
N1
L0_CTLIN_H0
P1
L0_CTLIN_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
Y4
Y3
Y1
W1
HT_CPU_CTLOUT1_P
T5
HT_CPU_CTLOUT1_N
R5
R2
R3
HT_CLKOUT1_P 11
HT_CLKOUT1_N 11
HT_CLKOUT0_P 11
HT_CLKOUT0_N 11
TP1
TP2
HT_CTLOUT0_P 11
HT_CTLOUT0_N 11
MICRO-STAR INT'L CO.,LTD.
Title
SOCKET S1 HT I/F
Athlon 64 S1
Processor
Socket
5
4
3
Size Document Number Rev
Custom
MS-10581
Date: Sheet of
2
5 44Tuesday, January 10, 2006
1
A
A
B
C
D
E
VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER
Processor DDR2 Memory Interface
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE
4 4
3 3
2 2
CPU_VDDIO_SUS
R3
39.2_0402 1%
R4
39.2_0402 1%
PLACE THEM CLOSE TO
CPU WITHIN 1"
CPU_VTT_SUS
CPU_M_VREF_SUS
1000p_0603 (DNI)
C8
MEM_MA0_CS#39,10
MEM_MA0_CS#29,10
MEM_MA0_CS#19,10
MEM_MA0_CS#09,10
MEM_MB0_CS#39,10
MEM_MB0_CS#29,10
MEM_MB0_CS#19,10
MEM_MB0_CS#09,10
MEM_MB_CKE19,10
MEM_MB_CKE09,10
MEM_MA_CKE19,10
MEM_MA_CKE09,10
MEM_MA_BANK29,10
MEM_MA_BANK19,10
MEM_MA_BANK09,10
MEM_MA_RAS#9,10
MEM_MA_CAS#9,10
MEM_MA_WE#9,10
SNS_+0.9VTT
M_ZN
M_ZP
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0
W17
Y10
AE10
AF10
V19
J22
V22
T19
Y26
J24
W24
U23
H26
J23
J20
J21
K19
K20
V24
K24
L20
R19
L19
L22
L21
M19
M20
M24
M22
N22
N21
R21
K22
R20
T22
T20
U20
U21
MEMVREF
VTT_SENSE
MEMZN
MEMZP
MA0_CS_L3
MA0_CS_L2
MA0_CS_L1
MA0_CS_L0
MB0_CS_L3
MB0_CS_L2
MB0_CS_L1
MB0_CS_L0
MB_CKE1
MB_CKE0
MA_CKE1
MA_CKE0
MA_ADD15
MA_ADD14
MA_ADD13
MA_ADD12
MA_ADD11
MA_ADD10
MA_ADD9
MA_ADD8
MA_ADD7
MA_ADD6
MA_ADD5
MA_ADD4
MA_ADD3
MA_ADD2
MA_ADD1
MA_ADD0
MA_BANK2
MA_BANK1
MA_BANK0
MA_RAS_L
MA_CAS_L
MA_WE_L
U1B
MA0_CLK_H2
MA0_CLK_L2
MA0_CLK_H1
MA0_CLK_L1
MB0_CLK_H2
MB0_CLK_L2
MB0_CLK_H1
MB0_CLK_L1
MB0_ODT1
MB0_ODT0
MA0_ODT1
MA0_ODT0
MB_ADD15
MB_ADD14
MB_ADD13
MB_ADD12
MB_ADD11
MB_ADD10
MB_ADD9
MB_ADD8
MB_ADD7
MB_ADD6
MB_ADD5
MB_ADD4
MB_ADD3
MB_ADD2
MB_ADD1
MB_ADD0
MB_BANK2
MB_BANK1
MB_BANK0
MB_RAS_L
MB_CAS_L
MB_WE_L
DDR II: CMD/CTRL/CLK
Athlon 64 S1
Processor Socket
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
CPU_VTT_SUS
D10
C10
B10
AD10
W10
AC10
AB10
AA10
A10
Y16
AA16
E16
F16
AF18
AF17
A17
A18
W23
W26
V20
U19
MEM_MB_ADD15
J25
MEM_MB_ADD14
J26
MEM_MB_ADD13
W25
MEM_MB_ADD12
L23
MEM_MB_ADD11
L25
MEM_MB_ADD10
U25
MEM_MB_ADD9
L24
MEM_MB_ADD8
M26
MEM_MB_ADD7
L26
MEM_MB_ADD6
N23
MEM_MB_ADD5
N24
MEM_MB_ADD4
N25
MEM_MB_ADD3
N26
MEM_MB_ADD2
P24
MEM_MB_ADD1
P26
MEM_MB_ADD0
T24
K26
T26
U26
U24
V26
U22
C9
0.1u_0402
MEM_MA0_CLK2_P 9
MEM_MA0_CLK2_N 9
MEM_MA0_CLK1_P 9
MEM_MA0_CLK1_N 9
MEM_MB0_CLK2_P 9
MEM_MB0_CLK2_N 9
MEM_MB0_CLK1_P 9
MEM_MB0_CLK1_N 9
MEM_MB0_ODT1 9,10
MEM_MB0_ODT0 9,10
MEM_MA0_ODT1 9,10
MEM_MA0_ODT0 9,10
MEM_MB_ADD[15..0] 9,10MEM_MA_ADD[15..0]9,10
MEM_MB_BANK2 9,10
MEM_MB_BANK1 9,10
MEM_MB_BANK0 9,10
MEM_MB_RAS# 9,10
MEM_MB_CAS# 9,10
MEM_MB_WE# 9,10
CI10
0.1u_0402
EMI
CI11
0.1u_0402
CI12
0.1u_0402
MEM_MB_DATA[63..0]9
MEM_MB_DM[7..0]9
MEM_MB_DQS7_P9
MEM_MB_DQS7_N9
MEM_MB_DQS6_P9
MEM_MB_DQS6_N9
MEM_MB_DQS5_P9
MEM_MB_DQS5_N9
MEM_MB_DQS4_P9
MEM_MB_DQS4_N9
MEM_MB_DQS3_P9
MEM_MB_DQS3_N9
MEM_MB_DQS2_P9
MEM_MB_DQS2_N9
MEM_MB_DQS1_P9
MEM_MB_DQS1_N9
MEM_MB_DQS0_P9
MEM_MB_DQS0_N9
MEM_MB_DATA63
MEM_MB_DATA62
MEM_MB_DATA61
MEM_MB_DATA60
MEM_MB_DATA59
MEM_MB_DATA58
MEM_MB_DATA57
MEM_MB_DATA56
MEM_MB_DATA55
MEM_MB_DATA54
MEM_MB_DATA53
MEM_MB_DATA52
MEM_MB_DATA51
MEM_MB_DATA50
MEM_MB_DATA49
MEM_MB_DATA48
MEM_MB_DATA47
MEM_MB_DATA46
MEM_MB_DATA45
MEM_MB_DATA44
MEM_MB_DATA43
MEM_MB_DATA42
MEM_MB_DATA41
MEM_MB_DATA40
MEM_MB_DATA39
MEM_MB_DATA38
MEM_MB_DATA37
MEM_MB_DATA36
MEM_MB_DATA35
MEM_MB_DATA34
MEM_MB_DATA33
MEM_MB_DATA32
MEM_MB_DATA31
MEM_MB_DATA30
MEM_MB_DATA29
MEM_MB_DATA28
MEM_MB_DATA27
MEM_MB_DATA26
MEM_MB_DATA25
MEM_MB_DATA24
MEM_MB_DATA23
MEM_MB_DATA22
MEM_MB_DATA21
MEM_MB_DATA20
MEM_MB_DATA19
MEM_MB_DATA18
MEM_MB_DATA17
MEM_MB_DATA16
MEM_MB_DATA15
MEM_MB_DATA14
MEM_MB_DATA13
MEM_MB_DATA12
MEM_MB_DATA11
MEM_MB_DATA10
MEM_MB_DATA9
MEM_MB_DATA8
MEM_MB_DATA7
MEM_MB_DATA6
MEM_MB_DATA5
MEM_MB_DATA4
MEM_MB_DATA3
MEM_MB_DATA2
MEM_MB_DATA1
MEM_MB_DATA0
MEM_MB_DM7
MEM_MB_DM6
MEM_MB_DM5
MEM_MB_DM4
MEM_MB_DM3
MEM_MB_DM2
MEM_MB_DM1
MEM_MB_DM0
AD11
AF11
AF14
AE14
Y11
AB11
AC12
AF13
AF15
AF16
AC18
AF19
AD14
AC14
AE18
AD18
AD20
AC20
AF23
AF24
AF20
AE20
AD22
AC22
AE25
AD26
AA25
AA26
AE24
AD24
AA23
AA24
G24
G23
D26
C26
G26
G25
E24
E23
C24
B24
C20
B20
C25
D24
A21
D20
D18
C18
D14
C14
A20
A19
A16
A15
A13
D12
E11
G11
B14
A14
A11
C11
AD12
AC16
AE22
AB26
E25
A22
B16
A12
AF12
AE12
AE16
AD16
AF21
AF22
AC25
AC26
F26
E26
A24
A23
D16
C16
C12
B12
MB_DATA63
MB_DATA62
MB_DATA61
MB_DATA60
MB_DATA59
MB_DATA58
MB_DATA57
MB_DATA56
MB_DATA55
MB_DATA54
MB_DATA53
MB_DATA52
MB_DATA51
MB_DATA50
MB_DATA49
MB_DATA48
MB_DATA47
MB_DATA46
MB_DATA45
MB_DATA44
MB_DATA43
MB_DATA42
MB_DATA41
MB_DATA40
MB_DATA39
MB_DATA38
MB_DATA37
MB_DATA36
MB_DATA35
MB_DATA34
MB_DATA33
MB_DATA32
MB_DATA31
MB_DATA30
MB_DATA29
MB_DATA28
MB_DATA27
MB_DATA26
MB_DATA25
MB_DATA24
MB_DATA23
MB_DATA22
MB_DATA21
MB_DATA20
MB_DATA19
MB_DATA18
MB_DATA17
MB_DATA16
MB_DATA15
MB_DATA14
MB_DATA13
MB_DATA12
MB_DATA11
MB_DATA10
MB_DATA9
MB_DATA8
MB_DATA7
MB_DATA6
MB_DATA5
MB_DATA4
MB_DATA3
MB_DATA2
MB_DATA1
MB_DATA0
MB_DM7
MB_DM6
MB_DM5
MB_DM4
MB_DM3
MB_DM2
MB_DM1
MB_DM0
MB_DQS_H7
MB_DQS_L7
MB_DQS_H6
MB_DQS_L6
MB_DQS_H5
MB_DQS_L5
MB_DQS_H4
MB_DQS_L4
MB_DQS_H3
MB_DQS_L3
MB_DQS_H2
MB_DQS_L2
MB_DQS_H1
MB_DQS_L1
MB_DQS_H0
MB_DQS_L0
VDD_VREF_SUS_CPU
CPU_VDDIO_SUS
CPU_M_VREF_SUS
U1C
DDR: DATA
Athlon 64 S1
Processor Socket
MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54
MA_DATA53
MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
MA_DATA15
MA_DATA14
MA_DATA13
MA_DATA12
MA_DATA11
MA_DATA10
MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0
MA_DM7
MA_DM6
MA_DM5
MA_DM4
MA_DM3
MA_DM2
MA_DM1
MA_DM0
MA_DQS_H7
MA_DQS_L7
MA_DQS_H6
MA_DQS_L6
MA_DQS_H5
MA_DQS_L5
MA_DQS_H4
MA_DQS_L4
MA_DQS_H3
MA_DQS_L3
MA_DQS_H2
MA_DQS_L2
MA_DQS_H1
MA_DQS_L1
MA_DQS_H0
MA_DQS_L0
AA12
AB12
AA14
AB14
W11
Y12
AD13
AB13
AD15
AB15
AB17
Y17
Y14
W14
W16
AD17
Y18
AD19
AD21
AB21
AB18
AA18
AA20
Y20
AA22
Y22
W21
W22
AA21
AB22
AB24
Y24
H22
H20
E22
E21
J19
H24
F22
F20
C23
B22
F18
E18
E20
D22
C19
G18
G17
C17
F14
E14
H17
E17
E15
H15
E13
C13
H12
H11
G14
H14
F12
G12
Y13
AB16
Y19
AC24
F24
E19
C15
E12
W12
W13
Y15
W15
AB19
AB20
AD23
AC23
G22
G21
C22
C21
G16
G15
G13
H13
MEM_MA_DATA63
MEM_MA_DATA62
MEM_MA_DATA61
MEM_MA_DATA60
MEM_MA_DATA59
MEM_MA_DATA58
MEM_MA_DATA57
MEM_MA_DATA56
MEM_MA_DATA55
MEM_MA_DATA54
MEM_MA_DATA53
MEM_MA_DATA52
MEM_MA_DATA51
MEM_MA_DATA50
MEM_MA_DATA49
MEM_MA_DATA48
MEM_MA_DATA47
MEM_MA_DATA46
MEM_MA_DATA45
MEM_MA_DATA44
MEM_MA_DATA43
MEM_MA_DATA42
MEM_MA_DATA41
MEM_MA_DATA40
MEM_MA_DATA39
MEM_MA_DATA38
MEM_MA_DATA37
MEM_MA_DATA36
MEM_MA_DATA35
MEM_MA_DATA34
MEM_MA_DATA33
MEM_MA_DATA32
MEM_MA_DATA31
MEM_MA_DATA30
MEM_MA_DATA29
MEM_MA_DATA28
MEM_MA_DATA27
MEM_MA_DATA26
MEM_MA_DATA25
MEM_MA_DATA24
MEM_MA_DATA23
MEM_MA_DATA22
MEM_MA_DATA21
MEM_MA_DATA20
MEM_MA_DATA19
MEM_MA_DATA18
MEM_MA_DATA17
MEM_MA_DATA16
MEM_MA_DATA15
MEM_MA_DATA14
MEM_MA_DATA13
MEM_MA_DATA12
MEM_MA_DATA11
MEM_MA_DATA10
MEM_MA_DATA9
MEM_MA_DATA8
MEM_MA_DATA7
MEM_MA_DATA6
MEM_MA_DATA5
MEM_MA_DATA4
MEM_MA_DATA3
MEM_MA_DATA2
MEM_MA_DATA1
MEM_MA_DATA0
MEM_MA_DM7
MEM_MA_DM6
MEM_MA_DM5
MEM_MA_DM4
MEM_MA_DM3
MEM_MA_DM2
MEM_MA_DM1
MEM_MA_DM0
MEM_MA_DATA[63..0] 9
MEM_MA_DM[7..0] 9
MEM_MA_DQS7_P 9
MEM_MA_DQS7_N 9
MEM_MA_DQS6_P 9
MEM_MA_DQS6_N 9
MEM_MA_DQS5_P 9
MEM_MA_DQS5_N 9
MEM_MA_DQS4_P 9
MEM_MA_DQS4_N 9
MEM_MA_DQS3_P 9
MEM_MA_DQS3_N 9
MEM_MA_DQS2_P 9
MEM_MA_DQS2_N 9
MEM_MA_DQS1_P 9
MEM_MA_DQS1_N 9
MEM_MA_DQS0_P 9
MEM_MA_DQS0_N 9
R5
1K_0402 1%
R6
1K_0402 1%
C14
1n_0402
0922 by
harry
1n_0402
C15
MEM_MB0_CLK2_P9
C13
MEM_MB0_CLK2_N9
MEM_MB0_CLK1_P9
MEM_MB0_CLK1_N9
1.5p_0402
PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH
C19
1.5p_0402
A1
A26
Athlon 64 S1g1
uPGA638
E
Top View
A
6 44Tuesday, January 10, 2006
1 1
A
LAYOUT:PLACE CLOSE TO CPU
B
MEM_MA0_CLK2_P9
C20
MEM_MA0_CLK2_N9
MEM_MA0_CLK1_P9
MEM_MA0_CLK1_N9
1.5p_0402
PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH
C21
1.5p_0402
Title
SOCKET S1 DDR2 MEMORY I/F
Size Document Number Rev
C
C
D
Date: Sheet of
AF1
MICRO-STAR INT'L CO.,LTD.
MS-10581
5
LAYOUT: ROUTE VDDA TRACE APPROX.
50 mils WIDE (USE 2x25 mil TRACES TO
+1.8VRUN
R18
300_0402
D D
C C
B B
+3VSUS
SB_CPUPWRGD18
+1.8VRUN
LDT_STOP#13,18
+1.8VRUN
LDT_RST#17
VDD_PG33,36
RN1 8P4R-10K_RN0402
R27 0R_0402
1
3
5
7
+3VRUN
R19
R23
300_0402
R25
300_0402
T_CRIT_CPU#
2
CPU_THRM_ALERT-
4
SMB_THRMCPU_DATA
6
SMB_THRMCPU_CLK
8
Cap close to
thermal
sensor
CPU_TEST4_THERMDA
2200p_0402
A A
CPU_TEST5_THERMDC
T_CRIT_CPU#33
C30
R32 0_0603
CPU_VDDIO_SUS
4.7K_0603 (DNI)
DNI
2
1
CPU_VDDIO_SUS
2
1
CPU_VDDIO_SUS
2
1
1029 connect to SUS power
+3VSUS
C31
0.1u_0402
3 5
3 5
3 5
1110 Albert
C25 0.1u_0402 R8
NC7SZ08M5X
C28 0.1u_0402
NC7SZ08M5X
C29 0.1u_0402
NC7SZ08M5X
2
3
4
Close to CPU socket
0R_0402
R21
4
U2
0R_0402
R24
4
U3
0R_0402
R26
4
U4
U5
D+
DÂT_CRIT_A#
LM86CIMMXNOPB_MSOP8-RH
EXIT BALL FIELD) AND 500 mils LONG.
CPU_VDDA_2.5_RUN
CPU_ALL_PWROK
CPU_LDTSTOP#
CPU_HT_RESET#
CPU_PROCHOT#_1.8
SMB_THRMCPU_CLK
GND
81
SMB_THRMCPU_DATA
7
6
5
SMBCLKVDD
SMBDATA
ALERT#
4
+VDDA
L1
CPU_VDDIO_SUS
300L600m
1027 Harry
R12 300_0603 (DNI)
R14 300_0402
+VLDT
C22
4.7u_0805
R15 44.2_0603 1%
R16 44.2_0603 1%
place them to CPU within 1"
CPUCLK16
CPUCLK#16
CPU_VDDIO_SUS
C26 3.9n_0602
C27 3.9n_0602
R38
10K_0603
CPU_PH_G
B
E C
Q3
SMBT3904
SMB_THRMCPU_CLK 31
SMB_THRMCPU_DATA 31
CPU_THRM_ALERT- 31
+3VRUN
R42
4.7K_0603
R20
169_0402 1%
CPU_CLKIN_SC_P
CPU_CLKIN_SC_N
CPU_TEST5_THERMDC
CPU_TEST4_THERMDA
SB_TALERT# 18
3
ATHLON Control and Debug
C23
TP7
TP9
TP11
TP13
TP14
TP16
TP18
TP21
TP22
TP23
TP25
TP27
TP28
TP36
TP38
TP40
TP42
0.2u_0603
CPU_HTREF1
CPU_HTREF0
3300p_0603
CPU_HT_RESET#
R13
300_0402
CPU_VDD_RUN_FB_H36
CPU_VDD_RUN_FB_L36
TP3
TP4
TP5
CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1
CPU_ALL_PWROK
CPU_LDTSTOP#
CPU_SIC_R
CPU_SID_R
CPU_VDDIO_SUS_FB_H
CPU_VDDIO_SUS_FB_L
CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI
C24
F8
VDDA2
F9
VDDA1
B7
RESET_L
A7
PWROK
F10
LDTSTOP_L
AF4
SIC
AF5
SID
P6
HT_REF1
R6
HT_REF0
F6
VDD_FB_H
E6
VDD_FB_L
W9
VDDIO_FB_H
Y9
VDDIO_FB_L
A9
CLKIN_H
A8
CLKIN_L
G10
DBRDY
AA9
TMS
AC9
TCK
AD9
TRST_L
AF9
TDI
E9 C9
TEST25_H TEST29_H
E8
TEST25_L
G9
TEST19
H10
TEST18
AA7
TEST13
C2
TEST9
D7
TEST17
E7
TEST16
F7
TEST15
C7
TEST14
AC8
TEST12
C3
TEST7
AA6
TEST6
W7
THERMDC
W8
THERMDA
Y6
TEST3
AB6
TEST2
P20
RSVD0
P19
RSVD1
N20
RSVD2
N19
RSVD3
R26
RSVD4
R25
RSVD5
P22
RSVD6
R22
RSVD7
U1D
THERMTRIP_L
PROCHOT_L
CPU_PRESENT_L
DBREQ_L
JTAC
TEST29_L
TEST24
TEST23
TEST22
TEST21
TEST20
TEST28_H
TEST28_L
TEST27
TEST26
TEST10
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
MISC
AMD NPT S1 SOCKET
Processor Socket
VID5
VID4
VID3
VID2
VID1
VID0
PSI_L
TDO
TEST8
RSVD8
RSVD9
2
CPU_VDDIO_SUS
CPU_THERMTRIP#_R
AF6
CPU_PROCHOT#_1.8
AC7
A5
C6
A6
A4
C5
B5
AC6
A3
E10
AE9
CPU_TEST29_H_FBCLKOUT_P
CPU_TEST29_L_FBCLKOUT_N
C8
AE7
AD7
AE8
AB8
AF7
J7
H8
AF8
AE6
K8
C4
H16
B18
B3
C1
H6
G6
D5
R24
W18
R23
AA8
H18
H19
220_0402
CPU_VID5
CPU_VID4
CPU_VID3
CPU_VID2
CPU_VID1
CPU_VID0
CPU_PRESENT#
CPU_PSI#
CPU_DBREQ#
CPU_TDO
TP8
TP10
TP12
TP15
TP17
TP19
TP20
TP24
TP26
TP29
TP30
TP31 R35 1K_0402
TP32
TP33
TP34
TP35
TP37
TP39
TP41
TP43
CPU_VDDIO_SUS
R10
R9
220_0402
CPU_TEST21_SCANEN
CPU_TEST26_BURNIN#
CPU_DBREQ#
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI
CPU_TEST26_BURNIN#
CPU_PRESENT#
CPU_TEST25_H_BYPASSCLK_H
CPU_TEST21_SCANEN
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1
300_0402
CPU_PSI# 36
CPU_PROCHOT#_1.8
TP6
R22 80.6_0603 1%
1
+3VSUS
R7
10K_0603
B
E C
Q1
SMBT3904
CPU_VDDIO_SUS
E C
ROUTE AS 80 Ohm DIFFERENTIAL PAIR
PLACE IT CLOSE TO CPU WITHIN 1"
R11
4.7K_0603
CPU_THERMTRIP# 18
CPU_VID5 36
CPU_VID4 36
CPU_VID3 36
CPU_VID2 36
CPU_VID1 36
CPU_VID0 36
R17
10K_0603
B
Q2
SMBT3904
CPU_VDDIO_SUS
R28 510_0402
R29 510_0402
R30 510_0402
R31 510_0402
R33 510_0402
R34 300_0402
R36 510_0402
R37 300_0402
R39 510_0402
R40 300_0402
R41 300_0402
CPU_PROCHOT# 36
MICRO-STAR INT'L CO.,LTD.
Title
SOCKET S1 CTRL
Size Document Number Rev
B
5
4
3
2
Date: Sheet of
MS-10581
1
7 44Tuesday, January 10, 2006
A
5
AA4
VSS1
AA11
VSS2
AA13
VSS3
AA15
VSS4
AA17
CPU_VDD_RUN CPU_VDD_RUN
AC4
VDD1
AD2
VDD2
G4
D D
C C
H2
J11
J13
K6
K10
K12
K14
L4
L7
L9
L11
L13
M2
M6
M8
M10
N7
N9
N11
P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
V6
V8
V10
VDD3
VDD4
J9
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34
VDD35
VDD36
VDD37
VDD38
VDD39
VDD40
VDD41
VDD42
A1
B B
U1E
POWER
Athlon 64 S1
Processor
Socket
VDD43
VDD44
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51
VDD52
VDD53
VDD54
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27
V12
V14
W4
Y2
J15
K16
L15
M16
P16
T16
U15
V16
H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
P18
P21
P23
P25
R17
T18
T21
T23
T25
U17
V18
V21
V23
V25
Y25
A26
CPU_VDDIO_SUS
Athlon 64 S1g1
uPGA638
AA19
AB2
AB7
AB9
AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21
AD6
AD8
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23
B4
B6
B8
B9
B11
B13
B15
B17
B19
B21
B23
B25
D6
D8
D9
D11
D13
D15
D17
D19
D21
D23
D25
E4
F2
F11
F13
F15
F17
F19
F21
F23
F25
H7
H9
H21
H23
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
J4
VSS65
Top View
AF1
CPU_VDD_RUN
4
U1F
GROUND
Athlon 64 S1
Processor
Socket
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
M11
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6
3
2
BOTTOMSIDE DECOUPLING
CPU_VDD_RUN
22u_0805
C32
CPU_VDD_RUN
0.22u_0603
C41
CPU_VDDIO_SUS
C45
22u_0805
22u_0805
C33
22u_0805
0.01u_0402
C42
0.22u_0603
C46
22u_0805
C34
C43
0.22u_0603
C47
22u_0805
C35
22u_0805
C44
0.01u_0402
C48
0.22u_0603
C36
C37
22u_0805
22u_0805
C38
C39
22u_0805
22u_0805
C40
DECOUPLING BETWEEN PROCESSOR AND DIMMs
PLACE CLOSE TO PROCESSOR AS POSSIBLE
CPU_VDDIO_SUS
C49
4.7u_0805
CPU_VTT_SUS
C61
4.7u_0805
4.7u_0805
C50
4.7u_0805
C62
4.7u_0805
C51
4.7u_0805
4.7u_0805
C63
0.22u_0603
C52
C64
4.7u_0805
C53
0.22u_0603
0.22u_0603
C65
0.22u_0603
C54
C66
0.22u_0603
C55
0.22u_0603
0.22u_0603
C67
C56
C68
0.22u_0603
0.01u_0402
C57
0.01u_0402
1n_0402
C69
C58
0.01u_0402
C70
1n_0402
C59
1n_0402
C71
0.01u_0402
C60
C72
1n_0402
0.01u_0402
C73
0.01u_0402
C74
0.01u_0402
1
C75
C76
0.01u_0402
A A
CI77
0.1u_0402
CI78
0.1u_0402
CI79
0.1u_0402
CI80
0.1u_0402
CI81
0.1u_0402
CI82
0.1u_0402
CI83
0.1u_0402
CI84
0.01u_0402
CI85
0.01u_0402
CI86
0.01u_0402
CI87
0.01u_0402
MICRO-STAR INT'L CO.,LTD.
EMI
PROCESSOR POWER AND GROUND
5
4
3
2
Title
SOCKET S1 PWR & GND
Size Document Number Rev
B
Date: Sheet of
MS-10581
1
8 44Tuesday, January 10, 2006
A
5
CPU_VDDIO_SUS
MEM_MA_ADD[15..0]6,10
D D
MEM_MA_BANK[2..0]6,10
MEM_MA_DM[7..0]6
MEM_MA_DQS0_P6
MEM_MA_DQS1_P6
MEM_MA_DQS2_P6
MEM_MA_DQS3_P6
C804
MEM_MA_DQS4_P6
MEM_MA_DQS5_P6
MEM_MA_DQS6_P6
MEM_MA_DQS7_P6
MEM_MA_DQS0_N6
MEM_MA_DQS1_N6
MEM_MA_DQS2_N6
MEM_MA_DQS3_N6
MEM_MA_DQS4_N6
MEM_MA_DQS5_N6
MEM_MA_DQS6_N6
MEM_MA_DQS7_N6
MEM_MA0_CLK1_P6
MEM_MA0_CLK1_N6
MEM_MA0_CLK2_P6
MEM_MA0_CLK2_N6
CPU_VDDIO_SUS
MEM_MA0_CS#06,10
MEM_MA0_CS#16,10
C805
C C
B B
47UF_1210
A A
MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13
MEM_MA_ADD14
MEM_MA_ADD15
MEM_MA_BANK0
MEM_MA_BANK1
MEM_MA_BANK2
MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7
MEM_MA_CKE06,10
MEM_MA_CKE16,10
MEM_MA_RAS#6,10
MEM_MA_CAS#6,10
MEM_MA_WE#6,10
MEM_MA0_ODT06,10
MEM_MA0_ODT16,10
SDATA016,18,23
SCLK016,18,23
+3VRUN
MEM_M_VREF_SUS
47UF_1210
102
101
100
105
116
107
106
130
147
170
185
131
148
169
188
129
146
167
186
164
166
108
113
109
110
115
114
119
198
200
195
197
199
99
98
97
94
92
93
91
90
89
86
84
85
10
26
52
67
13
31
51
70
11
29
49
68
30
32
79
80
1
2
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14/NC
A15/NC
BA0
BA1
BA2
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
CK0
CK0
CK1
CK1
CKE0
CKE1
RAS
CAS
WE
S0
S1
ODT0
ODT1
SA0
SA1
SDA
SCL
VDDspd
VREF
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
818287889596103
VDD0
VDD1
VSS22
VSS21
104
VDD2
VDD3
VDD4
VDD5
VDD6
SO-DIMM
(RVS)
VSS27
VSS26
VSS25
VSS24
VSS23
787772
7166656059
111
VDD8
VDD7
VSS29
VSS28
121
112
117
VDD9
VSS30
127
122
4
118
VDD10
VDD11
NC/TEST
VSS32
VSS31
132
128
J2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
NC1
NC2
NC3
NC4
VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
MEM_MA_DATA0
5
MEM_MA_DATA1
7
MEM_MA_DATA2
17
MEM_MA_DATA3
19
MEM_MA_DATA4
4
MEM_MA_DATA5
6
MEM_MA_DATA6
14
MEM_MA_DATA7
16
MEM_MA_DATA8MEM_MA_ADD8
23
MEM_MA_DATA9
25
MEM_MA_DATA10
35
MEM_MA_DATA11
37
MEM_MA_DATA12
20
MEM_MA_DATA13
22
MEM_MA_DATA14
36
MEM_MA_DATA15
38
MEM_MA_DATA16
43
MEM_MA_DATA17
45
MEM_MA_DATA18
55
MEM_MA_DATA19
57
MEM_MA_DATA20
44
MEM_MA_DATA21
46
MEM_MA_DATA22
56
MEM_MA_DATA23
58
MEM_MA_DATA24
61
MEM_MA_DATA25
63
MEM_MA_DATA26
73
MEM_MA_DATA27
75
MEM_MA_DATA28
62
MEM_MA_DATA29
64
MEM_MA_DATA30
74
MEM_MA_DATA31
76
MEM_MA_DATA32
123
MEM_MA_DATA33
125
MEM_MA_DATA34
135
MEM_MA_DATA35
137
MEM_MA_DATA36
124
MEM_MA_DATA37
126
MEM_MA_DATA38
134
MEM_MA_DATA39
136
MEM_MA_DATA40
141
MEM_MA_DATA41
143
MEM_MA_DATA42
151
MEM_MA_DATA43
153
MEM_MA_DATA44
140
MEM_MA_DATA45
142
MEM_MA_DATA46
152
MEM_MA_DATA47
154
MEM_MA_DATA48
157
MEM_MA_DATA49
159
MEM_MA_DATA50
173
MEM_MA_DATA51
175
MEM_MA_DATA52
158
MEM_MA_DATA53
160
MEM_MA_DATA54
174
MEM_MA_DATA55
176
MEM_MA_DATA56
179
MEM_MA_DATA57
181
MEM_MA_DATA58
189
MEM_MA_DATA59
191
MEM_MA_DATA60
180
MEM_MA_DATA61
182
MEM_MA_DATA62
192
MEM_MA_DATA63
194
50
69
83
120
163
196
193
190
187
184
183
178
177
172
171
168
165
162
161
156
155
150
149
145
144
139
138
133
MEM_MA0_CS#2 6,10
MEM_MA0_CS#3 6,10
1% 0922 by
harry
MEM_MA_DATA[63..0] 6
CPU_VDDIO_SUS
C781 0.1u_0402
C783 0.1u_0402
C785 0.1u_0402
C787 0.1u_0402
C789 0.1u_0402
C791 0.1u_0402
C793 0.1u_0402
C795 0.1u_0402
C797 0.1u_0402
C799 0.1u_0402
C800 0.1u_0402
C801 0.1u_0402
CPU_VDDIO_SUS
R44
1K_0402 1%
R45
1K_0402 1%
3
MEM_MB_ADD[15..0]6,10
MEM_MB_BANK[2..0]6,10
MEM_MB_DM[7..0]6
MEM_VREF_SUS
1n_0402
C88
1n_0402
C89
C90
0.1u_0402
MEM_MB_DQS0_P6
MEM_MB_DQS1_P6
MEM_MB_DQS2_P6
MEM_MB_DQS3_P6
MEM_MB_DQS4_P6
MEM_MB_DQS5_P6
MEM_MB_DQS6_P6
MEM_MB_DQS7_P6
MEM_MB_DQS0_N6
MEM_MB_DQS1_N6
MEM_MB_DQS2_N6
MEM_MB_DQS3_N6
MEM_MB_DQS4_N6
MEM_MB_DQS5_N6
MEM_MB_DQS6_N6
MEM_MB_DQS7_N6
MEM_MB0_CLK1_P6
MEM_MB0_CLK1_N6
MEM_MB0_CLK2_P6
MEM_MB0_CLK2_N6
MEM_MB0_CS#06,10
MEM_MB0_CS#16,10
+3VRUN
MEM_M_VREF_SUS
1n_0402
C91
C92
1n_0402
MEM_MB_ADD0
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MB_ADD3
MEM_MB_ADD4
MEM_MB_ADD5
MEM_MB_ADD6
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD9
MEM_MB_ADD10
MEM_MB_ADD11
MEM_MB_ADD12
MEM_MB_ADD13
MEM_MB_ADD14
MEM_MB_ADD15
MEM_MB_BANK0
MEM_MB_BANK1
MEM_MB_BANK2
MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7
MEM_MB_CKE06,10
MEM_MB_CKE16,10
MEM_MB_RAS#6,10
MEM_MB_CAS#6,10
MEM_MB_WE#6,10
MEM_MB0_ODT06,10
MEM_MB0_ODT16,10
R43 4.7K_0603
SDATA016,18,23
SCLK016,18,23
+3VRUN
MEM_M_VREF_SUS
CPU_VDDIO_SUS
102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
107
106
85
10
26
52
67
130
147
170
185
13
31
51
70
131
148
169
188
11
29
49
68
129
146
167
186
30
32
164
166
79
80
108
113
109
110
115
114
119
198
200
195
197
199
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
2
1
2
3
8
9
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14/NC
A15/NC
BA0
BA1
BA2
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
CK0
CK0
CK1
CK1
CKE0
CKE1
RAS
CAS
WE
S0
S1
ODT0
ODT1
SA0
SA1
SDA
SCL
VDDspd
VREF
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
818287889596103
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VSS26
VSS25
VSS24
VSS23
VSS22
VSS21
59
111
104
112
117
118
J1
DQ0
VDD6
VDD8
VDD7
SO-DIMM(RVS)
VSS29
VSS28
VSS27
122
121
78777271666560
DQ1
VDD9
DQ2
VDD10
VDD11
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
NC1
NC2
NC3
NC4
NC/TEST
VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
DDR2_SODIMM_RVS_H=9.2mm
132
128
127
MEM_MB_DATA0
5
MEM_MB_DATA1
7
MEM_MB_DATA2
17
MEM_MB_DATA3
19
MEM_MB_DATA4
4
MEM_MB_DATA5
6
MEM_MB_DATA6
14
MEM_MB_DATA7
16
MEM_MB_DATA8
23
MEM_MB_DATA9
25
MEM_MB_DATA10
35
MEM_MB_DATA11
37
MEM_MB_DATA12
20
MEM_MB_DATA13
22
MEM_MB_DATA14
36
MEM_MB_DATA15
38
MEM_MB_DATA16
43
MEM_MB_DATA17
45
MEM_MB_DATA18
55
MEM_MB_DATA19
57
MEM_MB_DATA20
44
MEM_MB_DATA21
46
MEM_MB_DATA22
56
MEM_MB_DATA23
58
MEM_MB_DATA24
61
MEM_MB_DATA25
63
MEM_MB_DATA26
73
MEM_MB_DATA27
75
MEM_MB_DATA28
62
MEM_MB_DATA29
64
MEM_MB_DATA30
74
MEM_MB_DATA31
76
MEM_MB_DATA32
123
MEM_MB_DATA33
125
MEM_MB_DATA34
135
MEM_MB_DATA35
137
MEM_MB_DATA36
124
MEM_MB_DATA37
126
MEM_MB_DATA38
134
MEM_MB_DATA39
136
MEM_MB_DATA40
141
MEM_MB_DATA41
143
MEM_MB_DATA42
151
MEM_MB_DATA43
153
MEM_MB_DATA44
140
MEM_MB_DATA45
142
MEM_MB_DATA46
152
MEM_MB_DATA47
154
MEM_MB_DATA48
157
MEM_MB_DATA49
159
MEM_MB_DATA50
173
MEM_MB_DATA51
175
MEM_MB_DATA52
158
MEM_MB_DATA53
160
MEM_MB_DATA54
174
MEM_MB_DATA55
176
MEM_MB_DATA56
179
MEM_MB_DATA57
181
MEM_MB_DATA58
189
MEM_MB_DATA59
191
MEM_MB_DATA60
180
MEM_MB_DATA61
182
MEM_MB_DATA62
192
MEM_MB_DATA63
194
50
69
83
120
163
196
193
190
187
184
183
178
177
172
171
168
165
162
161
156
155
150
149
145
144
139
138
133
47UF_1210
1
C778 0.1u_0402
C779 0.1u_0402
C780 0.1u_0402
C782 0.1u_0402
C784 0.1u_0402
C786 0.1u_0402
C788 0.1u_0402
C790 0.1u_0402
C792 0.1u_0402
C794 0.1u_0402
C796 0.1u_0402
C798 0.1u_0402
MEM_MB0_CS#2 6,10
MEM_MB0_CS#3 6,10
CPU_VDDIO_SUS
C802
MEM_MB_DATA[63..0] 6
CPU_VDDIO_SUS
C803
47UF_1210
MICRO-STAR INT'L CO.,LTD.
DDR2_SODIMM_RVS_H=5.2mm
5
4
LAYOUT: PLACE CLOSE TO DIMMs
3
2
Title
DDR2 SODIMMS A/B CHANNEL
Size Document Number Rev
Custom
Date: Sheet of
MS-10581
1
9 44Tuesday, January 10, 2006
A
5
MEM_MA_ADD[15..0]6,9
D D
MEM_MA_BANK[2..0]6,9
C C
MEM_MB_ADD[15..0]6,9
B B
MEM_MB_BANK[2..0]6,9
A A
MEM_MA_ADD[15..0]
MEM_MA_BANK[2..0]
MEM_MA_CAS#6,9
MEM_MA_WE#6,9
MEM_MA_RAS#6,9
MEM_MA0_CS#06,9
MEM_MA0_CS#16,9
MEM_MA0_CS#26,9
MEM_MA0_CS#36,9
MEM_MA0_ODT06,9
MEM_MA0_ODT16,9
MEM_MA_CKE16,9
MEM_MA_CKE06,9
MEM_MB_ADD[15..0]
MEM_MB_BANK[2..0]
MEM_MB_CAS#6,9
MEM_MB_WE#6,9
MEM_MB_RAS#6,9
MEM_MB0_CS#06,9
MEM_MB0_CS#16,9
MEM_MB0_CS#26,9
MEM_MB0_CS#36,9
MEM_MB0_ODT06,9
MEM_MB0_ODT16,9
MEM_MB_CKE16,9
MEM_MB_CKE06,9
5
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0
MEM_MA_BANK2
MEM_MA_BANK1
MEM_MA_BANK0
MEM_MA_CAS#
MEM_MA_WE#
MEM_MA_RAS#
MEM_MA0_CS#0
MEM_MA0_CS#1
MEM_MA0_CS#2
MEM_MA0_CS#3
MEM_MA0_ODT0
MEM_MA0_ODT1
MEM_MA_CKE1
MEM_MA_CKE0
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0
MEM_MB_BANK2
MEM_MB_BANK1
MEM_MB_BANK0 MEM_MB_ADD15
MEM_MB_CAS#
MEM_MB_WE#
MEM_MB_RAS#
MEM_MB0_CS#0
MEM_MB0_CS#1
MEM_MB0_CS#2
MEM_MB0_CS#3
MEM_MB0_ODT0
MEM_MB0_ODT1
MEM_MB_CKE1
MEM_MB_CKE0
4
MEM_MA_CKE0
MEM_MA_ADD12
MEM_MA_BANK2
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD3
MEM_MA_ADD5
MEM_MA_ADD2
MEM_MA_BANK0
MEM_MA_ADD10
MEM_MA_WE#
MEM_MA_CAS#
MEM_MA_ADD13
MEM_MA0_CS#3
MEM_MA0_ODT1
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_CKE1
MEM_MA0_CS#2
MEM_MA_ADD6
MEM_MA_ADD4
MEM_MA_ADD11
MEM_MA_ADD7
MEM_MA_RAS#
MEM_MA_BANK1
MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA0_ODT0
MEM_MA0_CS#1
MEM_MA0_CS#0
MEM_MB_CKE0
MEM_MB_BANK2
MEM_MB0_CS#2
MEM_MB_ADD12
MEM_MB_ADD9
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD3
MEM_MB_ADD5
MEM_MB_ADD1
MEM_MB_ADD10
MEM_MB_WE#
MEM_MB_CAS#
MEM_MB0_CS#1
MEM_MB_ADD13
MEM_MB_ADD11
MEM_MB_ADD14
MEM_MB_CKE1
MEM_MB_ADD0
MEM_MB_ADD2
MEM_MB_ADD6
MEM_MB_ADD4
MEM_MB0_CS#0
MEM_MB_RAS#
MEM_MB_BANK1
MEM_MB_BANK0
MEM_MB0_CS#3
MEM_MB0_ODT0
MEM_MB0_ODT1
4
8P4R-47_RN0402
8P4R-47_RN0402
8P4R-47_RN0402
8P4R-47_RN0402
8P4R-47_RN0402
8P4R-47_RN0402
8P4R-47_RN0402
8P4R-47_RN0402
8P4R-47_RN0402
8P4R-47_RN0402
8P4R-47_RN0402
8P4R-47_RN0402
8P4R-47_RN0402
8P4R-47_RN0402
8P4R-47_RN0402
8P4R-47_RN0402
3
2
1
EMI
CPU_VTT_SUS
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
RN2
2
4
6
8
RN3
2
4
6
8
RN4
2
4
6
8
RN5
2
4
6
8
RN6
2
4
6
8
RN7
2
4
6
8
RN8
2
4
6
8
RN9
2
4
6
8
CPU_VTT_SUS
RN11
2
4
6
8
RN12
2
4
6
8
RN13
2
4
6
8
RN14
2
4
6
8
RN15
2
4
6
8
RN16
2
4
6
8
RN17
2
4
6
8
RN18
2
4
6
8
C93 0.1u_0402
C94 0.1u_0402
C95 0.1u_0402
C96 0.1u_0402
C97 0.1u_0402
C98 0.1u_0402
C106 0.1u_0402
C107 0.1u_0402
C108 0.1u_0402
C116 0.1u_0402
C117 0.1u_0402
C118 0.1u_0402
C119 0.1u_0402
C127 0.1u_0402
C128 0.1u_0402
C129 0.1u_0402
C144 0.1u_0402
C145 0.1u_0402
C153 0.1u_0402
C154 0.1u_0402
C155 0.1u_0402
C163 0.1u_0402
C164 0.1u_0402
C165 0.1u_0402 CI177
C173 0.1u_0402
C174 0.1u_0402
C175 0.1u_0402
C176 0.1u_0402
C181 0.1u_0402
C182 0.1u_0402
C183 0.1u_0402
C184 0.1u_0402
CPU_VDDIO_SUS
CPU_VDDIO_SUS
CPU_VDDIO_SUS
CPU_VDDIO_SUS
CPU_VDDIO_SUS
CPU_VDDIO_SUS
CPU_VDDIO_SUS
CPU_VDDIO_SUS
CPU_VDDIO_SUS
CPU_VDDIO_SUS
CPU_VDDIO_SUS
CPU_VDDIO_SUS
CPU_VDDIO_SUS
CPU_VDDIO_SUS
CPU_VDDIO_SUS
CPU_VDDIO_SUS
MEM_MA_ADD0
CI99
0.01u_0402
MEM_MA_ADD7 MEM_MA_ADD9
CI109
0.01u_0402
CI120
0.01u_0402
MEM_MB_ADD5
CI130
0.01u_0402
MEM_MB_ADD12
CI137
0.01u_0402
MEM_MB_BANK0
CI146
0.01u_0402
MEM_MA_CAS# MEM_MB_CAS#
CI156
0.01u_0402
MEM_MA0_CS#1 MEM_MB0_CS#0
CI166
0.01u_0402
MEM_MA0_ODT0
0.01u_0402
MEM_MA_ADD1
CI100
0.01u_0402
MEM_MA_ADD8
CI110
0.01u_0402
CI121
0.01u_0402
MEM_MB_ADD6
CI131
0.01u_0402
MEM_MB_ADD13
CI138
0.01u_0402
MEM_MB_BANK1
CI147
0.01u_0402
MEM_MA_WE#
CI157
0.01u_0402
MEM_MA0_CS#2
CI167
0.01u_0402
MEM_MA0_ODT1
CI178
0.01u_0402
MEM_MA_ADD2
CI101
0.01u_0402
CI111
0.01u_0402
CI122
0.01u_0402
MEM_MB_ADD7
CI132
0.01u_0402
MEM_MB_ADD14
CI139
0.01u_0402
MEM_MB_BANK2
CI148
0.01u_0402
MEM_MA_RAS#
CI158
0.01u_0402
MEM_MA0_CS#3 MEM_MB0_CS#3
CI168
0.01u_0402
MEM_MB0_ODT0
CI179
0.01u_0402
CI102
0.01u_0402
MEM_MA_ADD10
CI112
0.01u_0402
MEM_MB_ADD1MEM_MA_ADD14
CI123
0.01u_0402
MEM_MB_ADD8
CI133
0.01u_0402
MEM_MB_ADD15
CI140
0.01u_0402
MEM_MA_CKE0
CI149
0.01u_0402
CI159
0.01u_0402
CI169
0.01u_0402
MEM_MB0_ODT1
CI180
0.01u_0402
Title
MEM_MA_ADD4MEM_MA_ADD3
CI103
0.01u_0402
MEM_MA_ADD11
CI113
0.01u_0402
MEM_MB_ADD2MEM_MA_ADD15
CI124
0.01u_0402
MEM_MB_ADD9
CI134
0.01u_0402
MEM_MA_BANK0
CI141
0.01u_0402
MEM_MA_CKE1
CI150
0.01u_0402
MEM_MB_WE#
CI160
0.01u_0402
MEM_MB0_CS#1
CI170
0.01u_0402
MEM_MA_ADD5
CI104
0.01u_0402
CI114
0.01u_0402
MEM_MB_ADD3MEM_MB_ADD0
CI125
0.01u_0402
MEM_MB_ADD10
CI135
0.01u_0402
MEM_MA_BANK1
CI142
0.01u_0402
MEM_MB_CKE0
CI151
0.01u_0402
MEM_MB_RAS#
CI161
0.01u_0402
MEM_MB0_CS#2
CI171
0.01u_0402
MICRO-STAR INT'L CO.,LTD.
DDR2 SODIMMS TERMINATIONS
Size Document Number Rev
Custom
3
2
Date: Sheet of
MS-10581
1
MEM_MA_ADD6
CI105
0.01u_0402
MEM_MA_ADD13MEM_MA_ADD12
CI115
0.01u_0402
MEM_MB_ADD4
CI126
0.01u_0402
MEM_MB_ADD11
CI136
0.01u_0402
MEM_MA_BANK2
CI143
0.01u_0402
MEM_MB_CKE1
CI152
0.01u_0402
MEM_MA0_CS#0
CI162
0.01u_0402
CI172
0.01u_0402
A
10 44Tuesday, January 10, 2006
5
4
U6A
3
2
1
HT_CADOUT15_P5
D D
C C
HT_CADOUT15_N5
HT_CADOUT14_P5
HT_CADOUT14_N5
HT_CADOUT13_P5
HT_CADOUT13_N5
HT_CADOUT12_P5
HT_CADOUT12_N5
HT_CADOUT11_P5
HT_CADOUT11_N5
HT_CADOUT10_P5
HT_CADOUT10_N5
HT_CADOUT9_P5
HT_CADOUT9_N5
HT_CADOUT8_P5
HT_CADOUT8_N5
HT_CADOUT7_P5
HT_CADOUT7_N5
HT_CADOUT6_P5
HT_CADOUT6_N5
HT_CADOUT5_P5
HT_CADOUT5_N5
HT_CADOUT4_P5
HT_CADOUT4_N5
HT_CADOUT3_P5
HT_CADOUT3_N5
HT_CADOUT2_P5
HT_CADOUT2_N5
HT_CADOUT1_P5
HT_CADOUT1_N5
HT_CADOUT0_P5
HT_CADOUT0_N5
R19
R18
R21
R22
U22
U21
U18
U19
W19
W20
AC21
AB22
AB20
AA20
AA19
Y19
T24
R25
U25
U24
V23
U23
V24
V25
AA25
AA24
AB23
AA23
AB24
AB25
AC24
AC25
HT_RXCAD15P
HT_RXCAD15N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD7P
HT_RXCAD7N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD0P
HT_RXCAD0N
PART 1 OF 5
HT_TXCAD15P
HT_TXCAD15N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD0P
HT_TXCAD0N
P21
P22
P18
P19
M22
M21
M18
M19
L18
L19
G22
G21
J20
J21
F21
F22
N24
N25
L25
M24
K25
K24
J23
K23
G25
H24
F25
F24
E23
F23
E24
E25
HT_CADIN15_P 5
HT_CADIN15_N 5
HT_CADIN14_P 5
HT_CADIN14_N 5
HT_CADIN13_P 5
HT_CADIN13_N 5
HT_CADIN12_P 5
HT_CADIN12_N 5
HT_CADIN11_P 5
HT_CADIN11_N 5
HT_CADIN10_P 5
HT_CADIN10_N 5
HT_CADIN9_P 5
HT_CADIN9_N 5
HT_CADIN8_P 5
HT_CADIN8_N 5
HT_CADIN7_P 5
HT_CADIN7_N 5
HT_CADIN6_P 5
HT_CADIN6_N 5
HT_CADIN5_P 5
HT_CADIN5_N 5
HT_CADIN4_P 5
HT_CADIN4_N 5
HT_CADIN3_P 5
HT_CADIN3_N 5
HT_CADIN2_P 5
HT_CADIN2_N 5
HT_CADIN1_P 5
HT_CADIN1_N 5
HT_CADIN0_P 5
HT_CADIN0_N 5
HT_CLKOUT1_P5
HT_CLKOUT1_N5
B B
HT_CLKOUT0_P5
HT_CLKOUT0_N5
HT_CTLOUT0_P5
HT_CTLOUT0_N5
R48 49.9_0402
+1.2VRUN
harry
1025
A A
HT_RXCALP
HT_RXCALN
W21
W22
Y24
W25
P24
P25
A24
C24
HT_RXCLK1P
HT_RXCLK1N
HT_RXCLK0P
HT_RXCLK0N
HT_RXCTLP
HT_RXCTLN
HT_RXCALP
HT_RXCALN
RS485M_A12
HT_TXCLK1P
HT_TXCLK1N
HT_TXCLK0P
HYPER TRANSPORT CPU
I/F
HT_TXCLK0N
HT_TXCTLP
HT_TXCTLN
HT_TXCALP
HT_TXCALN
Title
L21
L22
J24
J25
N23
P23
C25
D24
HT_TXCALP
HT_TXCALN
MICRO-STAR INT'L CO.,LTD.
HT_CLKIN1_P 5
HT_CLKIN1_N 5
HT_CLKIN0_P 5
HT_CLKIN0_N 5
HT_CTLIN0_P 5
HT_CTLIN0_N 5
R47 100_0402R46 49.9_0402
RS485M HT LINK I/F
Size Document Number Rev
A
A
MS-10581
Date: Sheet of
5
4
3
2
11 44Tuesday, January 10, 2006
1
5
U6B
4
3
2
1
G5
GFX_RX0P
G4
GFX_RX0N
J8
GFX_RX1P
J7
GFX_RX1N
J4
GFX_RX2P
D D
C C
GPP_RX0P_R
GPP_RX0N_R
GPP_RX1P_R
GPP_RX1N_R
J5
L8
L7
L4
L5
M8
M7
M4
M5
P8
P7
P4
P5
R4
R5
R7
R8
U4
U5
W4
W5
Y4
Y5
V9
W9
AB7
AB6
W11
W12
AA11
AB11
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N
GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
PART 2 OF 5
PCIE I/F
GFX
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
PCIE I/F GPP
GPP_RX2P23
B B
GPP_RX2N23
GPP_RX3P25
GPP_RX3N25
A_RX0P17
A_RX0N17
A_RX1P17
A_RX1N17
R49 10K_0402 1%
R51 8.25K_0402 1%
1 2
1 2
Y7
AA7
AB9
AA9
W14
W15
AB12
AA12
AA14
AB14
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
PCE_ISET
PCE_TXISET
PCIE I/F SB
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
PCE_PCAL
PCE_NCAL
J1
H2
K2
K1
K3
L3
L1
L2
N2
N1
P2
P1
P3
R3
R1
R2
T2
U1
V2
V1
V3
W3
W1
W2
Y2
AA1
AA2
AB2
AB1
AC1
AE3
AE4
AD8
AE8
AD7
AE7
AD4
AE5
AD5
AD6
AE9
AD10
AC8
AD9
AD11
AE11
A_RX2P17
A_RX2N17
A_RX3P17
A_RX3N17
A_TX2P17
A_TX2N17
A_TX3P17
A_TX3N17
GPP_TX0P_C
GPP_TX0N_C
GPP_TX1P_C
GPP_TX1N_C
GPP_TX2P_C
GPP_TX2N_C
GPP_TX3P_C
GPP_TX3N_C
A_TX0P_C
A_TX0N_C
A_TX1P_C
A_TX1N_C
R50 150_0402 1%
R52 100_1%_0402
R53 0R_0402 (DNI)
R54 0R_0402 (DNI)
R55 0R_0402 (DNI)
R56 0R_0402 (DNI)
C193 0.01u_0402 (DNI)
C194 0.01u_0402 (DNI)
C195 0.01u_0402 (DNI)
C196 0.01u_0402 (DNI)
GPP_RX0P_R
GPP_RX0N_R
GPP_RX1P_R
GPP_RX1N_R
NOTE: RS485 4-LANE ALINK CONFIGURATION
Change them to
10nF ==>ATI
C185 0.1u_0402
C186 0.1u_0402
C187 0.1u_0402
C188 0.1u_0402
C189 0.01u_0402
C190 0.01u_0402
C191 0.01u_0402
C192 0.01u_0402
+1.2VRUN
Change them to
10nF ==>ATI
GPP_TX2P 23
GPP_TX2N 23
GPP_TX3P 25
GPP_TX3N 25
A_TX0P 17
A_TX0N 17
A_TX1P 17
A_TX1N 17
GPP_TX0P_C
GPP_TX0N_C
GPP_TX1P_C
GPP_TX1N_C
RS485M_A12
A A
Title
100 1%
MICRO-STAR INT'L CO.,LTD.
RS485M PCI-E LINK I/F
Size Document Number Rev
A
A
MS-10581
Date: Sheet of
5
4
3
2
12 44Tuesday, January 10, 2006
1
5
GR B
4
3
2
1
CI197
0.01u_0402
D D
C C
B B
+1.8VRUN
1 2
1 2
+1.8VRUN
1 2
300L300m
L3
300L300m
L4
300L300m
L7
AVDDQ
PLLVDD
HTPVDD
+3VRUN
4.7K_0603
R72
C201
10u_0805
C204
10u_0805
C208
10u_0805
R73
4.7K_0603
C202
2.2u_0805
C205
4.7u_0805
C209
4.7u_0805 R62
LDT_STOP#7,18
I2C_CLK
I2C_DATA
+3VRUN
CI198
0.01u_0402
R15
G15
B15
150_0402 1%
CI199
0.01u_0402
PLEASE CLOSE TO NB
R57
R58
150_0402 1%
+1.8VRUN
+3VRUN
R61
10K_0603
B
E C
Q4
SMBT3904
EMI
R59
150_0402 1%
1K_0402
+3VRUN
L2
300L600m
+1.8VRUN
AVDDQ
WD_PWRGD/GPIO718
NB_PWRGD27,31,33
HTREFCLK16
NB_OSC16
SB_OSCIN16,18
NBSRC_CLKP16
NBSRC_CLKN16
SBLINK_CLKP16
SBLINK_CLKN16
R63 0R_0402 (DNI)
R64 0R_0402
LOAD_ROM#
AVDD
PLLVDD
HTPVDD
LDT_STOP#_NB
R68 2.7K_0402
R69 2.7K_0402
R70 2.7K_0402
R71 2.7K_0402
R74 2.7K_0402
BMREQ#17
I2C_CLK15
I2C_DATA15
R75
4.7K_0603
C200
4.7u_0805
C203
2.2u_0805
VSYNC#15
HSYNC#15
DAC_SCL15
DAC_SDAT15
R65 10K_0603
R66 10K_0603
R67 22_0603 (DNI)
ALLOW_LDTSTOP17
R60 715_0402
NB_RST#17
DFT_GPIO0
DFT_GPIO2
DFT_GPIO3
DFT_GPIO4
DFT_GPIO5
TP45
TP46
STRP_DATA
1%
B22
C22
G17
H17
A20
B20
A21
A22
C21
C20
D19
E19
F19
G19
B21
A10
B10
B24
B25
C10
C11
C23
B23
B11
A11
AA15
AB15
C14
C6
A5
B6
A6
C5
B5
C2
F2
E1
G1
G2
D6
D7
C8
C7
B8
A8
B2
A2
B4
B3
C3
A3
U6C
RS485M_A12
AVDD1
AVDD2
AVSSN1
AVSSN2
AVDDDI
AVSSDI
AVDDQ
AVSSQ
C_R
Y_G
COMP_B
RED
GREEN
BLUE
DACVSYNC
DACHSYNC
RSET
DACSCL
DACSDA
PLLVDD
PLLVSS
HTPVDD
HTPVSS
SYSRESET#
POWERGOOD
LDTSTOP#
ALLOW_LDTSTOP
HTTSTCLK
HTREFCLK
TVCLKIN
OSCIN
OSCOUT
GFX_CLKP
GFX_CLKN
SB_CLKP
SB_CLKN
DFT_GPIO0
DFT_GPIO1
DFT_GPIO2
DFT_GPIO3
DFT_GPIO4
DFT_GPIO5
BMREQ#
I2C_CLK
I2C_DATA
THERMALDIODE_P
THERMALDIODE_N
TMDS_HPD
DDC_DATA
TESTMODE
STRP_DATA
PART 3 OF 5
CRT/TVOUT
LVDS
PLL
PWR
PM
CLOCKs
DVO
MIS.
TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N
TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N
TXCLK_LP
TXCLK_LN
TXCLK_UP
TXCLK_UN
LPVDD
LPVSS
LVDDR18D_1
LVDDR18D_2
LVDDR18A_1
LVDDR18A_2
LVSSR1
LVSSR3
LVSSR5
LVSSR6
LVSSR7
LVSSR8
LVSSR12
LVSSR13
LVDS_DIGON
LVDS_BLON
LVDS_BLEN
DVO_D0
DVO_D1
DVO_D2
DVO_D3
DVO_D4
DVO_D5
DVO_D6
DVO_D7
DVO_D8
DVO_D9
DVO_D10
DVO_D11
DVO_VSYNC
DVO_DE
DVO_HSYNC
DVO_IDCKP
DVO_IDCKN
B14
B15
B13
A13
H14
G14
D17
E17
A15
B16
C17
C18
B17
A17
A18
B18
E15
D15
H15
G15
D14
E14
A12
B12
C12
C13
A16
A14
D12
C19
C15
C16
F14
F15
E12
G12
F12
AD14
AD15
AE15
AD16
AE16
AC17
AD18
AE19
AD19
AE20
AD20
AE21
AD13
AC13
AE13
AE17
AD17
TP44
LVDS_TXL0P 15
LVDS_TXL0N 15
LVDS_TXL1P 15
LVDS_TXL1N 15
LVDS_TXL2P 15
LVDS_TXL2N 15
LVDS_TXLCKP 15
LVDS_TXLCKN 15
C206
0.1u_0402
C210
4.7u_0805
LVDS_DIGON 15
LVDS_BLON 15
C207
4.7u_0805
C211
0.1u_0402
L5
1 2
300L300m
L8
1 2
300L300m
+1.8VRUN
+1.8VRUN
C212
0.1u_0402
+1.8VRUN
300L300m
1 2
C213
4.7u_0805
L6
R76
2K_0603
U7
1
A0
2
A1
3
+3VRUN
A A
R77
10K_0603 (DNI)
A2
7
WP
AT24C04N-10SU-2.7-RH (DNI)
SDA
SCL
VCC
GND
5
I2C_CLK
6
8
4
+3VRUN
C214
0.1u_0603 (DNI)
NOTE: ACCESS TO STRAP_DATA and I2C_CLK PINS
IS MANDATORY.
5
STRP_DATA
R78
2K_0603 (DNI)
LOAD_ROM#: LOAD ROM STRAP ENABLE
High, LOAD ROM STRAP DISABLE
Low, LOAD ROM STRAP ENABLE
LOAD_ROM#
4
R79 3K_0603 (DNI)
MICRO-STAR INT'L CO.,LTD.
Title
RS485M SYSTEM I/F&CLK
Size Document Number Rev
Custom
3
2
Date: Sheet of
MS-10581
1
13 44Tuesday, January 10, 2006
A
5
VDDA12
10u_0805
VSSA8
VSSA9
C222
1u_0603
C235
AE10
VSSA10
VSSA11
VSSA12
C220
10u_0805
D D
+1.8VRUN VDD18
+1.8VRUN VDDA18
C C
B B
L10
300L600m
L11
220L3A
+3VRUN VDDR3
L12
+1.8VRUN
VDDA12
V12
M3
VSSA2
VSSA1
10u_0805
1 2
300L300m
L13
220L3A
V11
V14F3V15A1H1G3J2H3J6F1L6M2M6J3P6T1N3R6U2T3U3U6Y1W6AC2Y3Y9
VSSA3
VSSA4
VSSA5
VSSA6
VSSA7
C227
2.2u_0805
C236
10u_0805
C245
4.7u_0805
C246
1u_0603
C263
4.7u_0805
AE6
VSSA13
VSSA15
VSSA14
C223
1u_0603
C228
2.2u_0805
VDDR
VSSA16
VSSA17
1u_0603
C237
C247
1u_0603
C264
1u_0603
VSSA18
VSSA19
VSSA20
C224
1u_0603
P9
VSSA21
VSSA22
VSSA23
C238
1u_0603
C248
1u_0603
VSSA24
VSSA25
VSSA26
C225
1u_0603
C239
1u_0603
AC4
VSSA27
VSSA28
VSSA29
C240
1u_0603
Y15
VSSA30
VSSA32
VSSA31
C226
1u_0603
VDDA12
VDDA12
VSSA33
VSSA34
VSSA35
C241
1u_0603
+1.2VRUN
Y11R9AD1
VSSA36
GROUND
PAR 5 OF 5
AC5
VSSA37
VSSA38
VSSA39
4
AC6
AC7
AD3
VSSA40
VSSA41
VDDA12
AC9
AC10
VSSA42
VSSA43
VSSA44
C255
10u_0805
G6
Y12
Y14
VSSA45
VSSA46
AE24
AD24
AD22
AB17
AE23
Y17
W17
AC18
AD21
AC19
AC20
AB19
AD23
AA17
AE25
J14
J15
AE2
AB3
AB4
AC3
AD2
AE1
E11
D11
AC12
AD12
AE12
D22
AC11
AA3
VSSA47
VSSA48
U6D
VDD_HT1
VDD_HT2
VDD_HT3
VDD_HT4
VDD_HT5
VDD_HT6
VDD_HT7
VDD_HT8
VDD_HT9
VDD_HT10
VDD_HT11
VDD_HT12
VDD_HT13
VDD_HT14
VDD_HT15
VDD18_1
VDD18_2
VDDA18_1
VDDA18_2
U7
VDDA18_3
W7
VDDA18_4
VDDA18_5
VDDA18_6
VDDA18_7
VDDA18_8
VDDR3_1
VDDR3_2
VDD_DVO1
VDD_DVO2
VDD_DVO3
E7
VDDA12_13
F7
VDDA12_14
F9
VSSA49
G9
VSSA50
VDDHT_PKG
M1
VDDA12_PKG1
VDDA12_PKG2
RS485M_A12
PART 4 OF 5
U6E
RS485M_A12
3
VDDA12_1
VDDA12_2
VDDA12_3
VDDA12_4
VDDA12_5
VDDA12_6
VDDA12_7
VDDA12_8
VDDA12_9
VDDA12_10
VDDA12_11
VDDA12_12
VDDC_1
VDDC_2
VDDC_3
POWER
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23
VDDC_24
VDDC_25
VDDC_26
VDDC_27
VDDC_28
VDDC_29
VDDC_30
VDDC_31
VDDC_32
D1
G7
E2
C1
E3
D2
M9
F4
B1
D3
L9
E6
L11
L13
L15
M12
R15
M14
N11
N13
N15
J11
H11
P12
P14
R11
R13
A19
B19
U11
U14
P17
L17
J19
D20
G20
A9
B9
C9
D9
A7
A4
U12
U15
VDDA12
+1.8VRUN
+3VRUN
VCC_NB
+1.2VRUN
VDDA12
CI249
0.1u_0402
CI256
0.1u_0402
CI265
0.1u_0402
CI269
0.1u_0402
CI275
0.1u_0402
C215
1u_0603
EMI
CI250
0.1u_0402
CI257
0.1u_0402
CI266
0.1u_0402
CI270
0.1u_0402
CI276
0.1u_0402
C216
1u_0603
C229
10u_0805
CI251
0.1u_0402
CI258
0.1u_0402
CI267
0.1u_0402
CI271
0.1u_0402
CI277
0.1u_0402
C217
1u_0603C221
C230
10u_0805
CI252
0.1u_0402
CI259
0.1u_0402
CI268
0.1u_0402
CI272
0.1u_0402
CI278
0.1u_0402
2
CI253
0.1u_0402
CI260
0.1u_0402
CI273
0.1u_0402
C231
1u_0603
C242
1u_0603
CI254
0.1u_0402
CI261
0.1u_0402
CI274
0.1u_0402
C218
10u_0805
C232
1u_0603
C243
1u_0603
CI262
0.1u_0402
1
L9
C219
10u_0805
VCC_NB
C233
1u_0603
C244
1u_0603
+1.2VRUN
80L6_30_0805
C234
1u_0603
NB RS485 POWER STATES
S1
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
S3
OFF
OFF
OFF
OFF
OFF
OFF
OFFAVDD
OFF
OFF
OFF
OFF
OFF
OFF
S4/S5
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
Power Signal
VDDHT
VDDR
VDD18
VDDC
VDDA18
VDDA12
S0
ON
ON
ON
ON
ON
ON
ON
AVDDDI
PLLVDD
HTPVDD
VDDR3
LPVDD
LVDDR18D
ON
ON
ON
ON
ON
ON
LVDDR18A OFFON ON OFF OFF
G3
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
A A
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS52
VSS54
VSS56
VSS57
VSS59
VSS55
F17D4M13
AC15
VSS58
AC16
A25
F11
D23E9G11
Y23
P11
R24
AE18
M15
J22
G23
J12
L12
L14
L20
L23
M11
M20
M23
M25
N12
N14
VSS24
L24
B7
P13
P20
P15
R12
R14
R20
W23
Y25
AD25
U20
H25
W24
Y22
AC23
D25
G24
AC14
H12
VSS43
AC22
R23C4AE22
T23
T25
AE14
R17
VSS51
H23
M17
VSS53
A23
VDDA18
CI279
0.1u_0402
CI280
0.1u_0402
CI281
0.1u_0402
CI282
0.1u_0402
C2I83
0.1u_0402
MICRO-STAR INT'L CO.,LTD.
Title
RS485M POWER & GND
Size Document Number Rev
B
5
4
3
2
Date: Sheet of
MS-10581
1
14 44Tuesday, January 10, 2006
A
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