5
www.schematic-x.blogspot.com
4
3
2
1
MSI
MS-1013 Ver:0C
D D
DDR 333/400
AMD K8 Socket 754
2~5
HT
C C
LCD
25
CRT
25
LVDS
RGB
North Bridge
ATI RS480M
8~12
Clock Generator
Mini PCI
Socket
20 29
USB 2.0 x3
B B
27
HDD
24
CD-ROM
24
USB
PIDE
SIDE
South Bridge
ATI SB400
LPC
6,7
DDR SODIMM * 2
14
PCI
KBC
ENE3910
28
LAN
Realtec
8101L
X-BUS
R5C593
CARDBUS
CARDREADER
1394
BIOS
22
23
21
MDC
A A
5
30
4
AC Link
AC'97 CODEC
ALC655
26
Keyboard
3
28
Audio Amp
TPA0202
26
Touch
PAD
28
Speaker/HP
26
Title
Cover Sheet & Block Diagram
Size Document Number Rev
Custom
2
Date: Sheet of
MSI CORPORATION
MS1013
1
14 1 Tuesday, January 25, 2005
0C
5
4
3
2
1
LAYOUT: Place HT bypass caps on topside
near unconnected Clawhammer HT Link
4 4
Clawhammer HT Interface
VLDT Power Decoupling
VLDT Plane Rout with 250 mil trace or a plane
VLDT plane In CPU pins rout >100 mil
for emi
1 2
C131
330u-2.5V
3 3
2 2
+
0.22U_0603X7R
HT_CADIN_H[15:0] 8
HT_CADIN_L[15:0] 8
C143
0.22U_0603X7R
+1.2VRUN
C134
0.22U_0603X7R
HT_CTLIN_H0 8
HT_CTLIN_L0 8
C144
0.22U_0603X7R
HT_CLKIN_H1 8
HT_CLKIN_L1 8
HT_CLKIN_H0 8
HT_CLKIN_L0 8
49.9R1%_0603 R115
C127
+1.2VRUN +1.2VRUN
U7A
C132
4.7u_0805
HT_CADIN_H15
HT_CADIN_L15
HT_CADIN_H14
HT_CADIN_L14
HT_CADIN_H13
HT_CADIN_L13
HT_CADIN_H12
HT_CADIN_L12
HT_CADIN_H11
HT_CADIN_L11
HT_CADIN_H10
HT_CADIN_L10
HT_CADIN_H9
HT_CADIN_L9
HT_CADIN_H8
HT_CADIN_L8
HT_CADIN_H7
HT_CADIN_L7
HT_CADIN_H6
HT_CADIN_L6
HT_CADIN_H5
HT_CADIN_L5
HT_CADIN_H4
HT_CADIN_L4
HT_CADIN_H3
HT_CADIN_L3
HT_CADIN_H2
HT_CADIN_L2
HT_CADIN_H1
HT_CADIN_L1
HT_CADIN_H0
HT_CADIN_L0
HT_CTLIN_H1
R116
49.9R1%_0603
D29
D27
D25
C28
C26
R25
U27
U26
U25
W27
W26
AA27
AA26
AB25
AA25
AC27
AC26
AD25
AC25
U29
W29
AB29
AA29
AB27
AB28
AD29
AC29
AD27
AD28
W25
R27
R26
R29
B29
B27
T25
V25
T27
T28
V29
V27
V28
Y29
Y25
Y27
Y28
T29
VLDT_A6
VLDT_A5
VLDT_A4
VLDT_A3
VLDT_A2
VLDT_A1
VLDT_A0
L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKIN_H0
L0_CLKIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLIN_H0
L0_CTLIN_L0
ZIF_SOCKET754
VLDT0_B6
VLDT0_B5
VLDT0_B4
VLDT0_B3
VLDT0_B2
VLDT0_B1
VLDT0_B0
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
AH29
AH27
AG28
AG26
AF29
AE28
AF25
N26
N27
L25
M25
L26
L27
J25
K25
G25
H25
G26
G27
E25
F25
E26
E27
N29
P29
M28
M27
L29
M29
K28
K27
H28
H27
G29
H29
F28
F27
E29
F29
J26
J27
J29
K29
N25
P25
P28
P27
0.22U_0603X7R
HT_CADOUT_H15
HT_CADOUT_L15
HT_CADOUT_H14
HT_CADOUT_L14
HT_CADOUT_H13
HT_CADOUT_L13
HT_CADOUT_H12
HT_CADOUT_L12
HT_CADOUT_H11
HT_CADOUT_L11
HT_CADOUT_H10
HT_CADOUT_L10
HT_CADOUT_H9
HT_CADOUT_L9
HT_CADOUT_H8
HT_CADOUT_L8
HT_CADOUT_H7
HT_CADOUT_L7
HT_CADOUT_H6
HT_CADOUT_L6
HT_CADOUT_H5
HT_CADOUT_L5
HT_CADOUT_H4
HT_CADOUT_L4
HT_CADOUT_H3
HT_CADOUT_L3
HT_CADOUT_H2
HT_CADOUT_L2
HT_CADOUT_H1
HT_CADOUT_L1
HT_CADOUT_H0
HT_CADOUT_L0
HT_CTLOUT_H1
HT_CTLOUT_L1 HT_CTLIN_L1
C145
0.22U_0603X7R
TP58
TP57
C146
C135
0.22U_0603X7R
0.22U_0603X7R
HT_CLKOUT_H1 8
HT_CLKOUT_L1 8
HT_CLKOUT_H0 8
HT_CLKOUT_L0 8
HT_CTLOUT_H0 8
HT_CTLOUT_L0 8
C136
C128
4.7u_0805
HT_CADOUT_H[15:0] 8
HT_CADOUT_L[15:0] 8
1 2
+
C133
330u-2.5V
1 1
Title
CPU SocketA (Host)
Size Document Number Rev
Custom
5
4
3
2
Date: Sheet
MSI CORPORATION
MS1013
1
24 1 Tuesday, January 25, 2005
0A
of
5
4
3
2
1
U7B
SNS_+1.25VTT 34
4 4
MD[63:0] 7
3 3
2 2
DM[7:0] 7
DQS[7:0] 7
1 1
SNS_+1.25VTT
VREF_DDR_MEM
5
DM8
DM7
DM6
DM5
DM4
DM3
DM2
DM1
DM0
DQS8
DQS7
DQS6
DQS5
DQS4
DQS3
DQS2
DQS1
DQS0
MEMZN
MEMZP
MD63
MD62
MD61
MD60
MD59
MD58
MD57
MD56
MD55
MD54
MD53
MD52
MD51
MD50
MD49
MD48
MD47
MD46
MD45
MD44
MD43
MD42
MD41
MD40
MD39
MD38
MD37
MD36
MD35
MD34
MD33
MD32
MD31
MD30
MD29
MD28
MD27
MD26
MD25
MD24
MD23
MD22
MD21
MD20
MD19
MD18
MD17
MD16
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
AE13
AG12
D14
C14
A16
B15
A12
B11
A17
A15
C13
A11
A10
C11
AC1
AC3
AC2
AD1
AE1
AE3
AG3
AJ4
AE2
AF1
AH3
AJ3
AJ5
AJ6
AJ7
AH9
AG5
AH5
AJ9
AJ10
AH11
AJ11
AH15
AJ15
AG11
AJ12
AJ14
AJ16
A13
AA1
AG1
AH7
AH13
A14
AB1
AJ2
AJ8
AJ13
B9
C7
A6
A9
A5
B5
C5
A4
E2
E1
A3
B3
E3
F1
G2
G1
L3
L1
G3
J2
L2
M1
W1
W3
W2
Y1
R1
A7
C2
H1
T1
A8
D1
J1
VTT_SENSE
MEMVREF1
MEMZN
MEMZP
MEMDATA63
MEMDATA62
MEMDATA61
MEMDATA60
MEMDATA59
MEMDATA58
MEMDATA57
MEMDATA56
MEMDATA55
MEMDATA54
MEMDATA53
MEMDATA52
MEMDATA51
MEMDATA50
MEMDATA49
MEMDATA48
MEMDATA47
MEMDATA46
MEMDATA45
MEMDATA44
MEMDATA43
MEMDATA42
MEMDATA41
MEMDATA40
MEMDATA39
MEMDATA38
MEMDATA37
MEMDATA36
MEMDATA35
MEMDATA34
MEMDATA33
MEMDATA32
MEMDATA31
MEMDATA30
MEMDATA29
MEMDATA28
MEMDATA27
MEMDATA26
MEMDATA25
MEMDATA24
MEMDATA23
MEMDATA22
MEMDATA21
MEMDATA20
MEMDATA19
MEMDATA18
MEMDATA17
MEMDATA16
MEMDATA15
MEMDATA14
MEMDATA13
MEMDATA12
MEMDATA11
MEMDATA10
MEMDATA9
MEMDATA8
MEMDATA7
MEMDATA6
MEMDATA5
MEMDATA4
MEMDATA3
MEMDATA2
MEMDATA1
MEMDATA0
MEMDQS17
MEMDQS16
MEMDQS15
MEMDQS14
MEMDQS13
MEMDQS12
MEMDQS11
MEMDQS10
MEMDQS9
MEMDQS8
MEMDQS7
MEMDQS6
MEMDQS5
MEMDQS4
MEMDQS3
MEMDQS2
MEMDQS1
MEMDQS0
ZIF_SOCKET754
VTT_A4
VTT_A1
VTT_A2
VTT_A3
VTT_B1
VTT_B2
VTT_B3
VTT_B4
MEMRESET_L
MEMCKEA
MEMCKEB
MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
MEMCLK_L6
MEMCLK_H5
MEMCLK_L5
MEMCLK_H4
MEMCLK_L4
MEMCLK_H3
MEMCLK_L3
MEMCLK_H2
MEMCLK_L2
MEMCLK_H1
MEMCLK_L1
MEMCLK_H0
MEMCLK_L0
MEMCS_L7
MEMCS_L6
MEMCS_L5
MEMCS_L4
MEMCS_L3
MEMCS_L2
MEMCS_L1
MEMCS_L0
MEMRASA_L
MEMCASA_L
MEMWEA_L
MEMBANKA1
MEMBANKA0
RSVD_MEMADDA15
RSVD_MEMADDA14
MEMADDA13
MEMADDA12
MEMADDA11
MEMADDA10
MEMADDA9
MEMADDA8
MEMADDA7
MEMADDA6
MEMADDA5
MEMADDA4
MEMADDA3
MEMADDA2
MEMADDA1
MEMADDA0
MEMRASB_L
MEMCASB_L
MEMWEB_L
MEMBANKB1
MEMBANKB0
RSVD_MEMADDB_B15
RSVD_MEMADDB_B14
MEMADDB_B13
MEMADDB_B12
MEMADDB_B11
MEMADDB_B10
MEMADDB_B9
MEMADDB_B8
MEMADDB_B7
MEMADDB_B6
MEMADDB_B5
MEMADDB_B4
MEMADDB_B3
MEMADDB_B2
MEMADDB_B1
MEMADDB_B0
MEMCHECK7
MEMCHECK6
MEMCHECK5
MEMCHECK4
MEMCHECK3
MEMCHECK2
MEMCHECK1
MEMCHECK0
4
D17
A18
B17
C17
AF16
AG16
AH16
AJ17
AG10
AE8
AE7
D10
C10
E12
E11
AF8
AG8
AF10
AE10
V3
V4
K5
K4
R5
P5
P3
P4
D8
C8
E8
E7
D6
E6
C4
E5
H5
D4
G5
K3
H3
E13
C12
E10
AE6
AF3
M5
AE5
AB5
AD3
Y5
AB4
Y3
V5
T5
T3
N5
H4
F5
F4
L5
J5
E14
D12
E9
AF6
AF4
M4
AD5
AC5
AD4
AA5
AB3
Y4
W5
U5
T4
M3
N3
N1
U3
V1
N2
P1
U1
U2
+V1.25_VTT
MEMRST#
DCLK7+
DCLK7ÂDCLK6+
DCLK6ÂDCLK5+
DCLK5ÂDCLK4+
DCLK4ÂDCLK3+
DCLK3ÂDCLK2+
DCLK2ÂDCLK1+
DCLK1ÂDCLK0+
DCLK0-
CS#7
CS#6
CS#5
CS#4
CS#3
CS#2
CS#1
CS#0
MA15
MA14
MA13
MA12
MA11
MA10
MA9
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA0
MB15
MB14
MB13
MB12
MB11
MB10
MB9
MB8
MB7
MB6
MB5
MB4
MB3
MB2
MB1
MB0
C79
0.1u_0402
TP96
CKE0 6,7
CKE1 6,7
DCLK7+ 6,7
DCLK7- 6,7
DCLK6+ 6,7
DCLK6- 6,7
DCLK5+ 6,7
DCLK5- 6,7
DCLK4+ 6,7
DCLK4- 6,7
TP6
TP5
TP7
TP8
TP99
TP98
TP97
TP100
SRASA# 6,7
SCASA# 6,7
SWEA# 6,7
MEMBAA1 6,7
MEMBAA0 6,7
TP89
TP93
SRASB# 6,7
SCASB# 6,7
SWEB# 6,7
MEMBAB1 6,7
MEMBAB0 6,7
TP88
TP92
C318
0.1u_0402
CS#[3:0] 6,7
MA[13:0] 6,7
MB[13:0] 6,7
C319
0.1u_0402
C320
0.1u_0402
3
Clawhammer DDR Interface
+2.5VSUS
R141
1KR1%_0603
R139
1KR1%_0603
C228
0.01u_0603X7R
C233
0.01u_0603X7R
Routing
in the top layer
MEMDATA[63:0] with 5/15
MEMDQS[8:0] with 5/20
in the bottom layer
MEMADDA[13:0] with 5/15
MA COMMAND with 5/15
MEMCLK_H/L are routed
20/5/5/5/20 trace
width/spacing., 20 mil
spacing
Rout DDR nets 50 mil
sapcing to their own
net
MEMZN
MEMZP
MEMZN,MEMZP with
5/10,<1000 mils
DCLK1-
DCLK0-
DCLK1+
DCLK0+
for emi
C234
1000p_0603X7R
R140 34.8R1%_0603
R137 34.8R1%_0603
R45 10KR_0603
R43 10KR_0603
R46 10KR_0603
R44 10KR_0603
DM8
DQS8
+2.5VSUS
+2.5VSUS
2
VREF_DDR_MEM
C219
0.1u_0603
TP102
TP101
DDRVREF with
40~50 mil, 25
mil clearance
or shielded by
GND
0.1 UF, 0603, X7R
1000 PF, 0603, X7R
Near Socket
Title
CPU SocketA (DDR Interface)
Size Document Number Rev
Custom
Date: Sheet
MSI CORPORATION
MS1013
1
34 1 Tuesday, January 25, 2005
of
0A
5
VDDA
4 4
Place near CPU in 1" , Routed =>
5:10/Trace:Space , Same Length
CPUCLK0_H 14
3 3
2 2
CPUCLK0_L 14
C190 3900p_0603X7R
C182 3900p_0603X7R
Max current
105 mA
L3 0.18U450m_1210
+1.2VRUN
R126
169R1%_0603
Rout 5/5/5 mil, Long:<500 mils
and 20 mils spacing
Width:50mil and
Long:500~750mil
C20
4.7u_0805
R119 44.2R1%_0603
R121 44.2R1%_0603
1000p_0402X7R
CPUCK+
Near CPU in 0.5" .
CPUCK-
V_CORE
TP64
C155
X_1000p_0603X7R
C13
4
Width:50mil and Long:500mil
C26
3300p_0603X7R
C154
1000p_0402X7R
+2.5VSUS
+V1.25_VTT
CORE_SENSE
CPURST#
+2.5VRUN
SNS_+2.5VDIMM 34
1 2
3 4
5 6
C24
0.22U_0603X7R
COREFB+ 33
COREFB- 33
TP95
TP91
820R_0603 R23
820R_0603 R24
TP59
TP56
TP78
TP81
TP69
TP76
TP63
TP67
680R_0402 R16
680R_0402 R13
NC_AE23
NC_AF23
NC_AF22
NC_AF21
RN40
X_8P4R-680_0603
7 8
CPURST#
CPU_PWRGD
HTSTOP#
COREFB+
COREFB-
CORE_SENSE
VDDIOFB+
VDDIOFB-
SNS_+2.5VDIMM
CPUCK+
CPUCK-
BPSCLK+
BPSCLK-
PLLCHRZ+
PLLCHRZ-
DBRDY
DCLKTWO
TMS
TCK
TRST#
TDI
NC_C18
NC_A19
AH25
AJ25
AF20
AE18
AJ27
AF27
AE26
AE12
AF12
AE11
AJ21
AH21
AJ23
AH23
AE24
AF24
AG15
AH17
AJ28
AE23
AF23
AF22
AF21
AG2
AH1
AE21
AG4
AG6
AE9
AG9
A23
A24
B23
C16
C15
E20
E17
B21
A21
C18
A19
A28
C1
R3
AA2
D3
B18
C20
C6
U7C
VDDA1
VDDA2
RESET_L
PWROK
LDTSTOP_L
L0_REF1
L0_REF0
COREFB_H
COREFB_L
CORE_SENSE
VDDIOFB_H
VDDIOFB_L
VDDIO_SENSE
CLKIN_H
CLKIN_L
NC
NC
NC
NC
VTT_A5
VTT_B5
DBRDY
NC
TMS
TCK
TRST_L
TDI
NC
NC
KEY1
KEY0
NC
NC
NC
NC
FREE29
J3
FREE31
FREE33
FREE35
FREE1
FREE37
FREE4
FREE38
FREE41
FREE7
FREE11
FREE12
FREE13
FREE14
FREE40
3
2
1
Clawhammer Control and Debug
+2.5VRUN
+2.5VRUN +3VSUS
R113
1KR_0402
THERMTRIP#
LAYOUT: Route FBCLKOUT_H/L
differentially with 20/8/5/8/20
spacing and trace width. ( In CPU
breakout => routed 5:5:5 )
E C
Q4
N-MMBT3904
Zdiff = 80 ohm
NC_AJ18
NC_B19
NC_AG17
NC_D18
NC_C19
NC_D20
NC_C21
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
R114
1KR_0402
B
R110
10KR_0603
RN41
8P4R-680_0603
RN39
8P4R-680_0603
H_THERMTRIP# 16
THERMTRIP_L
THERMDA
THERMDC
VID4
VID3
VID2
VID1
VID0
G_FBCLKOUT_H
G_FBCLKOUT_L
DBREQ_L
TDO
RSVD_SCL
RSVD_SDA
FREE26
FREE28
FREE30
FREE32
FREE34
FREE36
FREE10
FREE18
FREE19
FREE42
FREE24
FREE25
FREE27
THERMTRIP#
A20
A26
A27
VID4
AG13
VID3
AF14
VID2
AG14
VID1
AF15
VID0
AE15
NC_AG18
AG18
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
AH18
AG17
AJ18
AH19
AJ19
AE19
D20
C21
D18
C19
B19
A22
AF18
D22
C22
B13
B7
C3
K1
R2
AA3
F3
C23
AG7
AE22
C24
A25
C9
NC_AH18
NC_AG17
NC_AJ18
FBCLKOUT+
FBCLKOUT-
DBREQ#
NC_D20
NC_C21
NC_D18
NC_C19
NC_B19
TDO
CPU_THERMDA 30
CPU_THERMDC 30
VID4 33
VID3 33
VID2 33
VID1 33
VID0 33
TP70
TP62
TP86
TP82
80.6R1%_0603 R130
+2.5VSUS
vcc=2.0~3.6V
Vo=0~Vcc
Vi=0~5V
VRM_GD
3,16,33
LDT_RST# 15
1 1
VRM_GD
3,16,33
SB_CPUPWRGD 15
+2.5VRUN +2.5VRUN
U17A
14 7
+2.5VRUN
14 7
X_LCX08_SOIC14
3
0R_0603 R180
U17C
X_LCX08_SOIC14
8
0R_0603 R176
CPURST#
CPU_PWRGD
VRM_GD 13,16,33
LDTSTOP# 11,15
LDT_RST# 15
NB_RST# 15
4
1
2
9
10
5
U17B
14 7
+3VSUS
14 7
X_LCX08_SOIC14
6
0R_0603 R181
U16D
LCX08_SOIC14
11
X_0R_0603 R175
HTSTOP#
4
5
12
13
ZIF_SOCKET754
RS480M_RST# 11
3
Title
CPU SocketA (Control and Debug)
Size Document Number Rev
Custom
2
Date: Sheet
MSI CORPORATION
MS1013
1
44 1 Tuesday, January 25, 2005
0A
of
5
V_CORE +2.5VSUS
D D
C C
B B
A A
AC15
AB14
AA15
AB16
AA17
AC17
AE17
AB18
AD18
AG19
AC19
AA19
M20
AB20
AD20
W21
AA21
AC21
M22
AB22
AD22
W23
AA23
AC23
M24
AB24
AD24
AH24
AE25
L7
H18
B20
E21
H22
J23
H24
F26
N7
L9
V10
G13
K14
Y14
G15
J15
H16
K16
Y16
G17
J17
F18
K18
Y18
E19
G19
J19
F20
H20
K20
P20
T20
V20
Y20
G21
J21
L21
N21
R21
U21
F22
K22
P22
T22
V22
Y22
E23
G23
L23
N23
R23
U23
B24
D24
F24
K24
P24
T24
V24
Y24
K26
P26
V26
U7D
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34
VDD35
VDD36
VDD37
VDD38
VDD39
VDD40
VDD41
VDD42
VDD43
VDD44
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51
VDD52
VDD53
VDD54
VDD55
VDD56
VDD57
VDD58
VDD59
VDD60
VDD61
VDD62
VDD63
VDD64
VDD65
VDD66
VDD67
VDD68
VDD69
VDD70
VDD71
VDD72
VDD73
VDD74
VDD75
VDD76
VDD77
VDD78
VDD79
VDD80
VDD81
VDD82
VDD83
VDD84
VDD85
VDD86
VDD87
VDD88
VDD89
VDD90
VDD91
VDD92
ZIF_SOCKET754
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27
VDDIO28
VDDIO29
VDDIO30
VDDIO31
VDDIO32
VDDIO33
VDDIO34
VDDIO35
VDDIO36
VDDIO37
VDDIO38
VDDIO39
VDDIO40
VDDIO41
VDDIO42
VDDIO43
VDDIO44
VDDIO45
VDDIO46
VDDIO47
VDDIO48
VDDIO49
VDDIO50
VDDIO6
VDD96
VDD97
VDD98
VDD99
VDD100
VDD101
VDD102
VDD103
VDD104
VDD105
VDD106
VDD107
VDD108
VDD109
VDD110
VDD111
VDD112
VDD113
VDD114
VDD115
VDD116
VDD117
VDD118
VDD119
VDD120
VDD121
VDD122
VDD123
VDD124
VDD125
VDD126
VDD127
VDD128
VDD129
VDD130
VDD131
VDD132
VDD133
VDD93
VDD94
VDD95
5
E4
G4
J4
L4
N4
U4
W4
AA4
AC4
AE4
D5
AF5
F6
H6
K6
M6
P6
T6
V6
Y6
AB6
AD6
D7
G7
J7
AA7
AC7
AF7
F8
H8
AB8
AD8
D9
G9
AC9
AF9
F10
AD10
D11
AF11
F12
AD12
D13
AF13
F14
AD14
F16
AD16
D15
R4
N28
U28
AA28
AE27
R7
U7
W7
K8
M8
P8
T8
V8
Y8
J9
N9
R9
U9
W9
AA9
H10
K10
M10
P10
T10
Y10
AB10
G11
J11
AA11
AC11
H12
K12
Y12
AB12
J13
AA13
AC13
H14
AB26
E28
J28
V_CORE
AH20
AB21
W22
M23
AG25
AG27
AA10
AE16
W20
AA20
AC20
AE20
AG20
AJ20
M21
AD21
AG21
AG29
AA22
AC22
AG22
AH22
AJ22
AB23
AD23
AG23
W24
AA24
AC24
AG24
AJ24
M26
AD26
AF26
AH26
AB17
AD17
AA18
AC18
AB19
AD19
AF19
B2
L24
D2
AF2
W6
Y7
AA8
AB9
J12
B14
Y15
J18
G20
R20
U20
D21
F21
H21
K21
P21
T21
V21
Y21
B22
E22
G22
J22
L22
N22
R22
U22
D23
F23
H23
K23
P23
T23
V23
Y23
E24
G24
J24
N24
R24
U24
B25
C25
B26
D26
H26
T26
Y26
C27
B28
D28
G28
F15
H15
B16
G18
D19
F19
H19
K19
Y19
J20
L20
N20
U7E
VSS1
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS187
VSS188
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
ZIF_SOCKET754
4
4
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS189
VSS190
VSS191
VSS192
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS223
VSS201
VSS202
VSS203
VSS204
VSS205
L28
R28
W28
AC28
AF28
AH28
C29
F2
H2
K2
M2
P2
T2
V2
Y2
AB2
AD2
AH2
B4
AH4
B6
G6
J6
L6
N6
R6
U6
AA6
AC6
AH6
F7
H7
K7
M7
P7
T7
V7
AB7
AD7
B8
G8
J8
L8
N8
R8
U8
W8
AC8
AH8
F9
H9
K9
M9
P9
T9
V9
Y9
AD9
B10
G10
J10
L10
N10
R10
U10
W10
AC10
AH10
F11
H11
K11
Y11
AB11
AD11
B12
G12
AA12
AC12
AH12
F13
H13
K13
Y13
AB13
AD13
AF17
G14
J14
AA14
AC14
AE14
D16
E15
K15
AB15
AD15
AH14
E16
G16
J16
AA16
AC16
AE29
AJ26
E18
F17
H17
K17
Y17
3
2
Clawhammer Power and Ground Connections
EMI
V_CORE V_CORE
C138 0.1u_0402
C184 0.1u_0402
C137 0.1u_0402
C165 0.1u_0402
C202 0.1u_0402
C141 0.1u_0402
C167 1000p_0402X7R
C166 1000p_0402X7R
C169 1000p_0402X7R
C179 1000p_0402X7R
backside
V_CORE V_CORE
C205 0.22U_0603X7R
C204 0.22U_0603X7R
C207 0.22U_0603X7R
C193 0.22U_0603X7R
C186 0.22U_0603X7R
C177 10u_1206X5R
+2.5VSUS
C240 0.22U_0603X7R
C241 0.22U_0603X7R
C242 0.22U_0603X7R
C229 0.22U_0603X7R
C225 0.22U_0603X7R
C231 0.22U_0603X7R
C230 0.22U_0603X7R
C215 0.22U_0603X7R
C227 10u_1206X5R
backside
Place these decoupling capacitors on solder
layer of processor
3
V_CORE
C44 0.22U_0603X7R
C46 0.22U_0603X7R
C35 0.22U_0603X7R
C45 0.22U_0603X7R
C36 0.22U_0603X7R
C34 0.22U_0603X7R
C47 10u_1206X5R
C41 10u_1206X5R
C32 10u_1206X5R
C38 10u_1206X5R
Place these capacitors in
uPGA socket cavity
X7R-->Y5V
+2.5VSUS
C214 0.22U_0603Y5V
C56 0.22U_0603Y5V
C61 0.22U_0603Y5V
C62 0.22U_0603Y5V
C238 0.22U_0603Y5V
C235 0.22U_0603Y5V
Near Socket
+2.5VSUS
for emi
C288 330U_6.3V
1 2
C287 330U_6.3V
1 2
Near DIMM
Place these capacitors near socket
2
1
+2.5VSUS
C211 4.7u_0805
C59 4.7u_0805
C58 4.7u_0805
C60 4.7u_0805
C236 4.7u_0805
C247 4.7u_0805
2 Near DIMM; 4
Near Socket
V_CORE
C157 4.7u_0805 C243 0.22U_0603X7R
C217 4.7u_0805
C185 4.7u_0805
C216 4.7u_0805
C139 4.7u_0805
C194 4.7u_0805
C140 4.7u_0805
Close to socket
Title
CPU SocketA (CPU_POWER / GROUND)
Size Document Number Rev
Custom
Date: Sheet
MSI CORPORATION
MS1013
1
54 1 Tuesday, January 25, 2005
0A
of
5
4
3
2
1
+2.5VSUS
DIMM1
192
132
144
156
168
180
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
NC
GND
GND
GND
104
138
126
NC
GND
GND
GND
GND
GND
GND
150
162
174
186
203
204
MD_0
5
MD_1
7
MD_2
13
MD_3
17
MD_4
6
MD_5
8
MD_6
14
MD_7
18
MD_8
19
MD_9
23
MD_10
29
MD_11
31
MD_12
20
MD_13
24
MD_14
30
MD_15
32
MD_16
41
MD_17
43
MD_18
49
MD_19
53
MD_20
42
MD_21
44
MD_22
50
MD_23
54
MD_24
55
MD_25
59
MD_26
65
MD_27
67
MD_28
56
MD_29
60
MD_30
66
MD_31
68
MD_32
127
MD_33
129
MD_34
135
MD_35
139
MD_36
128
MD_37
130
MD_38
136
MD_39
140
MD_40
141
MD_41
145
MD_42
151
MD_43
153
MD_44
142
MD_45
146
MD_46
152
MD_47
154
MD_48
163
MD_49
165
MD_50
171
MD_51
175
MD_52
164
MD_53
166
MD_54
172
MD_55
176
MD_56
177
MD_57
181
MD_58
187
MD_59
189
MD_60
178
MD_61
182
MD_62
188
MD_63
190
RN42 X_8P4R-0R_0402
71
1 2
73
3 4
79
5 6
83
7 8
1 2
72
3 4
74
5 6
80
7 8
84
RN43 X_8P4R-0R_0402
201
202
SO-DIMM1-REVERSE
DDRVREF
MB[13:0] 3,7 MD_[63:0] 7
C300
0.1u_0603
MB0
MB1
MB2
MB3
MB4
MB5
MB6
MB7
MB8
MB9
MB10
MB11
MB12
MB13
MEMBAB0 3,7
MEMBAB1 3,7
MEMBAB0
MEMBAB1
TP113
CS#2 3,7
CS#3 3,7
X_0R_0402 R161
SWEB# 3,7
SCASB# 3,7
SRASB# 3,7
SWEB#
SCASB#
SRASB#
CKE1
CKE1 3,7
DCLK4+ 3,7
DCLK4- 3,7
DCLK6+ 3,7
DCLK6- 3,7
TP108
TP107
X_0R_0402 R159
+3VRUN
TP15
C295
1000PF
TP111
TP109
MB13
TP112
TP110
DM_0
DM_1
DM_2
DM_3
DM_4
DM_5
DM_6
DM_7
DQS_0
DQS_1
DQS_2
DQS_3
DQS_4
DQS_5
DQS_6
DQS_7
SMB_DATA
SMB_CLK
TP106
112
111
110
109
108
107
106
105
102
101
115
100
99
97
117
116
98
121
122
12
26
48
62
134
148
170
184
78
119
120
118
96
95
35
37
160
158
89
91
11
25
47
61
133
147
169
183
77
193
195
194
196
198
199
197
86
85
123
124
200
VDDQ
GND
103
131
VDDQ
GND
125
143
VDDQ
GND
137
155
VDDQ
GND
149
157
VDDQ
GND
159
167
VDDQ
GND
161
179
1911022343646587082
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
GND
GND
GND
GND
GND
GND
GND
GND
173
1854162838405264768890
VDD
GND
VDD
GND
9294114
VDD
VDD
GND
GND
VDD
GND
921334557698193113
4 4
MA[13:0] 3,7
MEMBAA0 3,7
MEMBAA1 3,7
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13
MEMBAA0
MEMBAA1
TP104
CS#0 3,7
CS#1 3,7
DM_[7:0] 7
3 3
X_0R_0402 R158
SWEA# 3,7
SCASA# 3,7
SRASA# 3,7
CKE0 3,7
DCLK5+ 3,7
DCLK5- 3,7
DCLK7+ 3,7
DCLK7- 3,7
TP9
SMB_CLK 14,16
C271
TP11
X_0R_0402 R62
TP10
+3VRUN +3VRUN
C277
TP103
TP12
1000PF
MA13
TP105
TP14
DQS_[7:0] 7
SMB_DATA 14,16
2 2
DDRVREF
0.1u_0603
DM_0
DM_1
DM_2
DM_3
DM_4
DM_5
DM_6
DM_7
SWEA#
SCASA#
SRASA#
CKE0
DCLK5+
DCLK5ÂDCLK7+
DCLK7-
DQS_0
DQS_1
DQS_2
DQS_3
DQS_4
DQS_5
DQS_6
DQS_7
TP13
112
111
110
109
108
107
106
105
102
101
115
100
99
97
117
116
98
121
122
12
26
48
62
134
148
170
184
78
119
120
118
96
95
35
37
160
158
89
91
11
25
47
61
133
147
169
183
77
193
195
194
196
198
1
2
199
197
86
85
123
124
200
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
DU/A13
BA0
BA1
DU/BA2
CS0
CS1
DQM0
DQM1
DQM2
DQM3
DQM4
DQM5
DQM6
DQM7
DQM8
WE
CAS
RAS
CKE0
CKE1
CK0
CK0
CK1
CK1
CK2
CK2
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
SDA
SCL
SA0
SA1
SA2
VREF
VREF
VDDID
VDDSPD
NC//DU/RESET
NC/DU
NC/DU
NC/DU
NC/DU
3
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
GND
GND
GND
GND
GND
15273951637587
VDDQ
GND
VDDQ
GND
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
DU/A13
BA0
BA1
DU/BA2
CS0
CS1
DQM0
DQM1
DQM2
DQM3
DQM4
DQM5
DQM6
DQM7
DQM8
WE
CAS
RAS
CKE0
CKE1
CK0
CK0
CK1
CK1
CK2
CK2
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
SDA
SCL
SA0
SA1
SA2
1
VREF
2
VREF
VDDID
VDDSPD
NC//DU/RESET
NC/DU
NC/DU
NC/DU
NC/DU
921334557698193113
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
GND
GND
GND
GND
GND
GND
GND
15273951637587
3
VDDQ
GND
103
131
VDDQ
GND
125
143
VDDQ
GND
137
155
VDDQ
GND
149
157
VDDQ
GND
159
VDDQ
GND
+2.5VSUS
167
161
179
1911022343646587082
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
GND
GND
GND
GND
GND
GND
GND
GND
173
1854162838405264768890
VDD
GND
VDD
GND
9294114
VDD
VDD
GND
GND
VDD
GND
DIMM2
192
132
144
156
168
180
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
GND
GND
GND
GND
GND
GND
GND
GND
GND
104
138
150
162
174
126
186
201
202
MD_0
5
MD_1
7
MD_2
13
MD_3
17
MD_4
6
MD_5
8
MD_6
14
MD_7
18
MD_8
19
MD_9
23
MD_10
29
MD_11
31
MD_12
20
MD_13
24
MD_14
30
MD_15
32
MD_16
41
MD_17
43
MD_18
49
MD_19
53
MD_20
42
MD_21
44
MD_22
50
MD_23
54
MD_24
55
MD_25
59
MD_26
65
MD_27
67
MD_28
56
MD_29
60
MD_30
66
MD_31
68
MD_32
127
MD_33
129
MD_34
135
MD_35
139
MD_36
128
MD_37
130
MD_38
136
MD_39
140
MD_40
141
MD_41
145
MD_42
151
MD_43
153
MD_44
142
MD_45
146
MD_46
152
MD_47
154
MD_48
163
MD_49
165
MD_50
171
MD_51
175
MD_52
164
MD_53
166
MD_54
172
MD_55
176
MD_56
177
MD_57
181
MD_58
187
MD_59
189
MD_60
178
MD_61
182
MD_62
188
MD_63
190
RN44 X_8P4R-0R_0402
71
1 2
73
3 4
79
5 6
83
7 8
72
1 2
74
3 4
80
5 6
84
7 8
RN45 X_8P4R-0R_0402
SO-DIMM2-REVERSE
Unbuffered DDR333 SODIMM Sockets
Place these two decoupling caps near
DIMMs
+2.5VSUS
1 1
C286
C298
X_47u_1210
47u_1210
+2.5VSUS
C306
C290
0.1u_0402
C283
0.1u_0402
C293
0.1u_0402
C281
0.1u_0402
0.1u_0402
C280
C301
0.1u_0402
4
C282
0.1u_0402
C285
0.1u_0402
C268
C307
C284
0.1u_0402
5
0.1u_0402
0.1u_0402
0.1u_0402
+2.5VSUS
DDRVREF GEN. & DECOUPLING
R157
75 1%
R156
75 1%
C263
1000P
C262
1000P
C274
1000P
C261
1000P
DDRVREF
+2.5VSUS
C270
0.1u_0402
0.1u_0402
3
C304
C289
0.1u_0402
C267
0.1u_0402
C294
0.1u_0402
C303
0.1u_0402
C265
0.1u_0402
C302
0.1u_0402
0.1u_0402
C266
C291
0.1u_0402
C292
0.1u_0402
2
C269
0.1u_0402
ML2
DDR MYLAR
E26-1003120-SA6
+2.5VSUS
C273
C260
X_47u_1210
47u_1210
Title
DIMM1 & DIMM2 (200 PIN DDR SODIMM)
Size Document Number Rev
Custom
Date: Sheet
MSI CORPORATION
MS1013
1
64 1 Tuesday, January 25, 2005
of
0A
5
From CPU To DDR Socket
MD0
MD1
MD5
MD4
MD3
MD2
MD6
4 4
3 3
2 2
DM0 DM_0
DM3 DM_3
DM4
DM5
DM6
DM7
DQS0
DQS1
DQS2
DQS3 DQS_3
DQS4
DQS5
DQS6
DQS7
1 1
MD7
MD8
MD9
MD12
MD13
MD14
MD15
MD10
MD11
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
MD24
MD25
MD28
MD29 MD_29
MD26
MD27 MD_27
MD30
MD31
MD38
MD34
MD39
MD35
MD36
MD37
MD32
MD33
MD40
MD41
MD44
MD45 MD_45
MD47
MD42
MD43
MD46
MD48
MD49
MD53 MD_53
MD51
MD54
MD52
MD50
MD55
MD56
MD60
MD61
MD57
MD62
MD58
MD59
MD63
for EMI
MD_0
1 2
MD_1
MD_5
MD_4
MD_3
MD_2
MD_6
MD_7
MD_8
MD_9
MD_12
MD_13
MD_14
MD_15
MD_10
MD_11
MD_16
MD_17
MD_18
MD_19
MD_20
MD_21
MD_22
MD_23
MD_24
MD_25
MD_28
MD_26
MD_30
MD_31
MD_38
MD_34
MD_39
MD_35
MD_36
MD_37
MD_32
MD_33
MD_40
MD_41
MD_44
MD_47
MD_42
MD_43
MD_46
MD_48
MD_49
MD_51
MD_54
MD_52
MD_50
MD_55
MD_56
MD_60
MD_61
MD_57
MD_62
MD_58
MD_59
MD_63
DM_1 DM1
DM_2 DM2
DM_4
DM_5
DM_6
DM_7
DQS_0
DQS_1
DQS_2
DQS_4
DQS_5
DQS_6
DQS_7
RN15
8P4R-10R0402
RN18
8P4R-10R0402
RN8
8P4R-10R0402
RN7
8P4R-10R0402
RN17
8P4R-10R0402
RN16
8P4R-10R0402
RN10
8P4R-10R0402
RN9
8P4R-10R0402
RN14
8P4R-10R0402
RN12
8P4R-10R0402
RN5
8P4R-10R0402
RN4
8P4R-10R0402
RN13
8P4R-10R0402
RN11
8P4R-10R0402
RN6
8P4R-10R0402
RN3
8P4R-10R0402
MD_0
MD_1
MD_4
MD_5
MD_3
MD_2
MD_6
MD_7
MD_12
MD_8
MD_9
MD_13
MD_14
MD_15
MD_10
MD_11
MD_16
MD_17
MD_18
MD_19
MD_26
MD_27 MA2
MD_30
MD_31
MD_28
MD_29
MD_24
MD_25
MD_35
MD_39
MD_34
MD_38
MD_33
MD_32
MD_37
MD_36
MD_51
MD_53
MD_49
MD_48
MD_50
MD_55
MD_52
MD_54
MD_62
MD_58
MD_59
MD_63
MD_60
MD_61
MD_56
MD_57
MD_20
MD_21
MD_22
MD_23
MD_40
MD_41
MD_44
MD_45
MD_47
MD_42
MD_43
MD_46
DQS_0
DQS_1
DQS_2
DQS_3
DQS_4
DQS_5
DQS_6
DQS_7
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
10R_0402 R51 C297 4.7u_0805
10R_0402 R60
10R_0402 R55
10R_0402 R64
10R_0402 R48
10R_0402 R56
10R_0402 R52
10R_0402 R59
22R_0402 R50
22R_0402 R61
22R_0402 R54
22R_0402 R63
22R_0402 R49
22R_0402 R57
22R_0402 R53
22R_0402 R58
5
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
+V1.25_VTT
RN35
8P4R-68R0402
RN34
8P4R-68R0402
RN25
8P4R-68R0402
RN33
8P4R-68R0402
RN32
8P4R-68R0402
RN54
8P4R-68R0402
RN53
8P4R-68R0402
RN47
8P4R-68R0402
RN46
8P4R-68R0402
RN48
8P4R-68R0402
RN49
8P4R-68R0402
RN19
8P4R-68R0402
RN20
8P4R-68R0402
RN31
8P4R-68R0402
RN22
8P4R-68R0402
RN21
8P4R-68R0402
68R_0402 R75
68R_0402 R72
68R_0402 R71
68R_0402 R171
68R_0402 R167
68R_0402 R69
68R_0402 R168
68R_0402 R66
4
+V1.25_VTT
4
DCLK7- 3,6
DCLK6- 3,6
DCLK5- 3,6
DCLK4- 3,6
DM_0
DM_1
DM_2
DM_3
DM_4
DM_5
DM_6
DM_7
MEMBAB1 3,6
SRASB# 3,6
SCASB# 3,6
MEMBAB0 3,6
SRASA# 3,6
MEMBAA1 3,6
CKE0 3,6
CKE1 3,6
SWEA# 3,6
SCASA# 3,6
MEMBAA0 3,6
SWEB# 3,6
To DDR Socket
MEMBAB1
1 2
SRASB#
3 4
SCASB#
5 6
CS#3
7 8
MB12
1 2
MB9
3 4
MB7
5 6
MB5
7 8
MB3
1 2
MEMBAB0
3 4
MB10
5 6
SRASA#
7 8
MB11
1 2
MB8
3 4
MA7
5 6
MA10
7 8
MA4
1 2
MA5
3 4
MA8
5 6
MA6
7 8
MA0
1 2
MA13
3 4
CS#1
5 6
MEMBAA1
7 8
CKE0
1 2
3 4
MA1
5 6
MA3
7 8
MA12
1 2
CKE1
3 4
MA9
5 6
MA11
7 8
MB6
1 2
MB4
3 4
MB2
5 6
MB0
7 8
CS#0
1 2
SWEA#
3 4
SCASA#
5 6
MEMBAA0
7 8
CS#2
1 2
SWEB#
3 4
MB13
5 6
MB1
7 8
MD[63:0] 3
DQS[7:0] 3
DM[7:0] 3
MA[13:0] 3,6
MB[13:0] 3,6
MD_[63:0] 6
DQS_[7:0] 6
DM_[7:0] 6
CS#[3:0] 3,6
68R_0402 R74
68R_0402 R73
68R_0402 R70
68R_0402 R170
68R_0402 R166
68R_0402 R68
68R_0402 R169
68R_0402 R67
+V1.25_VTT
120R_0603 R34
120R_0603 R41
120R_0603 R47
120R_0603 R42
+V1.25_VTT
RN23
8P4R-47R0402
RN50
8P4R-47R0402
RN51
8P4R-47R0402
RN28
8P4R-47R0402
RN30
8P4R-47R0402
RN24
8P4R-47R0402
RN55
8P4R-47R0402
RN29
8P4R-47R0402
RN27
8P4R-47R0402
RN26
8P4R-47R0402
RN52
8P4R-47R0402
MD[63:0]
DQS[7:0]
DM[7:0]
MA[13:0]
MB[13:0]
MD_[63:0]
DQS_[7:0]
DM_[7:0]
CS#[3:0]
3
DCLK7+ 3,6
DCLK6+ 3,6
DCLK5+ 3,6
DCLK4+ 3,6
3
For EMI
+V1.25_VTT +2.5VSUS
C256 0.1u_0402
C259 0.1u_0402
C254 0.1u_0402
C264 0.1u_0402
C253 0.1u_0402
C278 0.1u_0402
C249 0.1u_0402
C255 0.1u_0402
C250 0.1u_0402
C296 0.1u_0402
C311 0.1u_0402
C309 0.1u_0402
C272 0.1u_0402
C275 0.1u_0402
C308 0.1u_0402
C310 0.1u_0402
CLOSE TO CPU
LAYOUT: Place a cap every 1 inch on VTT
trace between Clawhammer and DDR.
+V1.25_VTT +V1.25_VTT
C251 0.22U_0603X7R
C218 0.22U_0603X7R
C257 0.22U_0603X7R
+V1.25_VTT
C78 1000p_0402X7R
C203 1000p_0402X7R
LAYOUT: Add 100pF and 1000pF
VTT fill near Clawhammer and
near DIMMs (Both Sides)
2
+V1.25_VTT
C324 0.1u_0402
C323 0.1u_0402
C315 0.1u_0402
C325 100P_0402
C326 0.1u_0402
C312 0.1u_0402
C314 100P_0402
C321 100P_0402
C328 0.1u_0402
C80 100P_0402
C81 0.1u_0402
C82 100P_0402
C83 0.1u_0402
C84 100P_0402
C322 0.1u_0402
C85 0.1u_0402
C86 0.1u_0402
LAYOUT: Place alternating caps to GND and
+2.5VDIMM in a single line along VTT island.
FOR EMI CLOSE RN7,13,47,19,25,28,37,39,41,45
C279 0.22U_0603X7R
C276 0.22U_0603X7R
C258 0.22U_0603X7R
C252 4.7u_0805
+V1.25_VTT
C246 100u_1210
C48 100u_1210
LAYOUT: Locate close to
ClawHammer socket.
2
1
+V1.25_VTT
C316 100P_0402
C327 100P_0402
C329 100P_0402
C317 0.1u_0402
C333 100P_0402
C330 0.1u_0402
C331 100P_0402
C332 0.1u_0402
C334 0.1u_0402
C335 100P_0402
C336 0.1u_0402
C337 100P_0402
100p for emi
backside
Title
DDR TERMINATION
Size Document Number Rev
Custom
Date: Sheet
+2.5VSUS
C70 100P_0402
C65 100P_0402
C69 0.1u_0402
C71 0.1u_0402
C68 100P_0402
C72 0.1u_0402
C64 0.1u_0402
C63 0.1u_0402
C66 0.1u_0402
C67 0.1u_0402
C571 100P_0402
C572 0.1u_0402
C573 0.1u_0402
C574 0.1u_0402
C575 0.1u_0402
C576 0.1u_0402
C577 0.1u_0402
C578 0.1u_0402
C579 0.1u_0402
C580 0.1u_0402
C581 100P_0402
C582 100P_0402
C583 0.1u_0402
C584 0.1u_0402
C585 0.1u_0402
C586 100P_0402
C587 0.1u_0402
C588 0.1u_0402
C589 0.1u_0402
C590 100P_0402
C591 0.1u_0402
C592 0.1u_0402
C593 0.1u_0402
C594 0.1u_0402
C595 0.1u_0402
C596 0.1u_0402
C597 0.1u_0402
C598 0.1u_0402
C599 100P_0402
C600 100P_0402
C603 0.1u_0402
C604 0.1u_0402
C605 0.1u_0402
C606 0.1u_0402
C607 0.1u_0402
C608 100P_0402
C609 0.1u_0402
C610 0.1u_0402
C611 0.1u_0402
C612 0.1u_0402
MSI CORPORATION
MS1013
1
100p for emi
74 1 Tuesday, January 25, 2005
of
0A
5
4
3
2
1
U4A
R24
R25
N26
P26
N24
N25
L26
M26
J26
K26
J24
J25
G26
H26
G24
G25
L30
M30
L28
L29
J29
K29
H30
H29
E29
E28
D30
E30
D28
D29
B29
C29
L24
L25
F29
G29
M29
M28
B28
A28
HT_CADIN_H15
HT_CADIN_L15
HT_CADIN_H14
HT_CADIN_L14
HT_CADIN_H13
HT_CADIN_L13
HT_CADIN_H12
HT_CADIN_L12
HT_CADIN_H11
HT_CADIN_L11
HT_CADIN_H10
HT_CADIN_L10
HT_CADIN_H9
HT_CADIN_L9
HT_CADIN_H8
HT_CADIN_L8
HT_CADIN_H7
HT_CADIN_L7
HT_CADIN_H6
HT_CADIN_L6
HT_CADIN_H5
HT_CADIN_L5
HT_CADIN_H4
HT_CADIN_L4
HT_CADIN_H3
HT_CADIN_L3
HT_CADIN_H2
HT_CADIN_L2
HT_CADIN_H1
HT_CADIN_L1
HT_CADIN_H0
HT_CADIN_L0
HT_TXCALP
HT_TXCALN
HT_CADIN_H[15:0] 2
HT_CADIN_L[15:0] 2
HT_CLKIN_H1 2
HT_CLKIN_L1 2
HT_CLKIN_H0 2
HT_CLKIN_L0 2
HT_CTLIN_H0 2
100R1%_0603 R17
HT_CTLIN_L0 2
49.9R1%_0603 R8
49.9R1%_0603 R9
HT_CADOUT_H15
HT_CADOUT_L15
HT_CADOUT_H14
HT_CADOUT_L14
HT_CADOUT_H13
HT_CADOUT_L13
HT_CADOUT_H12
HT_CADOUT_L12
HT_CADOUT_H11
HT_CADOUT_L11
HT_CADOUT_H10
HT_CADOUT_L10
HT_CADOUT_H9
HT_CADOUT_L9
HT_CADOUT_H8
HT_CADOUT_L8
HT_CADOUT_H7
HT_CADOUT_L7
HT_CADOUT_H6
HT_CADOUT_L6
HT_CADOUT_H5
HT_CADOUT_L5
HT_CADOUT_H4
HT_CADOUT_L4
HT_CADOUT_H3
HT_CADOUT_L3
HT_CADOUT_H2
HT_CADOUT_L2
HT_CADOUT_H1
HT_CADOUT_L1
HT_CADOUT_H0
HT_CADOUT_L0
HT_RXCALN
HT_RXCALP
HT_CADOUT_H[15:0] 2
D D
C C
HT_CADOUT_L[15:0] 2
HT_CLKOUT_H1 2
HT_CLKOUT_L1 2
HT_CLKOUT_H0 2
HT_CLKOUT_L0 2
HT_CTLOUT_H0 2
HT_CTLOUT_L0 2
+1.2VRUN
W25
W24
AA25
AA24
AB26
AA26
AC25
AC24
AD26
AC26
W30
AB29
AA29
AC29
AC28
W26
W29
W28
T26
R26
U25
U24
V26
U26
R29
R28
T30
R30
T28
T29
V29
U29
Y30
Y28
Y29
Y26
P29
N29
D27
E27
HT_RXCAD15P
HT_RXCAD15N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD7P
HT_RXCAD7N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD0P
HT_RXCAD0N
HT_RXCLK1P
HT_RXCLK1N
HT_RXCLK0P
HT_RXCLK0N
HT_RXCTLP
HT_RXCTLN
HT_RXCALN
HT_RXCALP
PART 1OF6
HT_TXCAD15P
HT_TXCAD15N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD0P
HT_TXCAD0N
HYPER TRANSPORT CPU
I/F
HT_TXCLK1P
HT_TXCLK1N
HT_TXCLK0P
HT_TXCLK0N
HT_TXCTLP
HT_TXCTLN
HT_TXCALP
HT_TXCALN
RS480M_A21
B B
A A
Title
RS480-HT LINK0 I/F
Size Document Number Rev
Custom
5
4
3
2
Date: Sheet
MSI CORPORATION
MS1013
1
84 1 Tuesday, January 25, 2005
0A
of
5
4
3
2
1
D D
C C
C147 0.47u_0603
+2.5VRUN
R125
B B
0.1u_0603
C23
C22
0.1u_0603
1KR1%_0603
MEM_VREF
R122
1KR1%_0603
C43 0.47u_0603
1KR1%_0603 R22 C172
AF17
AK17
AH16
AF16
AJ22
AJ21
AH20
AH21
AK19
AH19
AJ17
AG16
AG17
AH17
AJ18
AG26
AJ29
AE21
AH24
AH12
AG13
AH8
AE8
AF25
AH30
AG20
AJ25
AH13
AF14
AG8
AG25
AH29
AF21
AK25
AJ12
AF13
AK7
AF9
AE17
AH18
AE18
AJ19
AF18
AK16
AJ16
AE28
AJ20
AK20
AJ15
AJ14
AJ7
AJ4
U4C
MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12
MEM_A13
MEM_A14
MEM_DM0
MEM_DM1
MEM_DM2
MEM_DM3
MEM_DM4
MEM_DM5
MEM_DM6
MEM_DM7
MEM_DQS0P
MEM_DQS1P
MEM_DQS2P
MEM_DQS3P
MEM_DQS4P
MEM_DQS5P
MEM_DQS6P
MEM_DQS7P
MEM_DQS0N
MEM_DQS1N
MEM_DQS2N
MEM_DQS3N
MEM_DQS4N
MEM_DQS5N
MEM_DQS6N
MEM_DQS7N
MEM_RAS#
MEM_CAS#
MEM_WE#
MEM_CS#
MEM_CKE
MEM_CKP
MEM_CKN
MEM_CAP1
MEM_CAP2
MEM_VMODE
MEM_VREF
MPVDD
MPVSS
PART 3 OF 6
MEM_A I/F
MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ8
MEM_DQ9
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15
MEM_DQ16
MEM_DQ17
MEM_DQ18
MEM_DQ19
MEM_DQ20
MEM_DQ21
MEM_DQ22
MEM_DQ23
MEM_DQ24
MEM_DQ25
MEM_DQ26
MEM_DQ27
MEM_DQ28
MEM_DQ29
MEM_DQ30
MEM_DQ31
MEM_DQ32
MEM_DQ33
MEM_DQ34
MEM_DQ35
MEM_DQ36
MEM_DQ37
MEM_DQ38
MEM_DQ39
MEM_DQ40
MEM_DQ41
MEM_DQ42
MEM_DQ43
MEM_DQ44
MEM_DQ45
MEM_DQ46
MEM_DQ47
MEM_DQ48
MEM_DQ49
MEM_DQ50
MEM_DQ51
MEM_DQ52
MEM_DQ53
MEM_DQ54
MEM_DQ55
MEM_DQ56
MEM_DQ57
MEM_DQ58
MEM_DQ59
MEM_DQ60
MEM_DQ61
MEM_DQ62
MEM_DQ63
MEM_COMPP
MEM_COMPN
RS480M_A21
AF28
AF27
AG28
AF26
AE25
AE24
AF24
AG23
AE29
AF29
AG30
AG29
AH28
AJ28
AH27
AJ27
AE23
AG22
AF23
AF22
AE20
AG19
AF20
AF19
AH26
AJ26
AK26
AH25
AJ24
AH23
AJ23
AH22
AK14
AH14
AK13
AJ13
AJ11
AH11
AJ10
AH10
AE15
AF15
AG14
AE14
AE12
AF12
AG11
AE11
AJ9
AH9
AJ8
AK8
AH7
AJ6
AH6
AJ5
AG10
AF11
AF10
AE9
AG7
AF8
AF7
AE7
AH5
AD30
MBM_COMPP
TP4
TP66
TP65
TP71
TP68
TP72
TP74
TP80
TP75
TP83
TP77
TP85
TP94
TP84
TP90
TP87
49.9R1%_0603 R30
+2.5VRUN
49.9R1%_0603 R12
1000p_0603X7R
+1.8VRUN
L7 X_28L900m_100_0805
CP1 X_COPPER
C171
4.7u_0805
MPVDD_PLL
C28 1u_0603
A A
Title
RS480-SIDE PORT MEMORY I/F
Size Document Number Rev
Custom
5
4
3
2
Date: Sheet
MSI CORPORATION
MS1013
1
94 1 Tuesday, January 25, 2005
0A
of
5
D D
C C
A_RX0P 15
A_RX0N 15
A_RX1P 15
A_RX1N 15
4
U4B
D8
GFX_RX0P
D7
GFX_RX0N
D5
GFX_RX1P
D4
GFX_RX1N
E4
GFX_RX2P
F4
GFX_RX2N
G5
GFX_RX3P
G4
GFX_RX3N
H4
GFX_RX4P
J4
GFX_RX4N
H5
GFX_RX5P
H6
GFX_RX5N
G1
GFX_RX6P
G2
GFX_RX6N
K5
GFX_RX7P
K4
GFX_RX7N
L4
GFX_RX8P
M4
GFX_RX8N
N5
GFX_RX9P
N4
GFX_RX9N
P4
GFX_RX10P
R4
GFX_RX10N
P5
GFX_RX11P
P6
GFX_RX11N
P2
GFX_RX12P
R2
GFX_RX12N
T5
GFX_RX13P
T4
GFX_RX13N
U4
GFX_RX14P
V4
GFX_RX14N
W1
GFX_RX15P
W2
GFX_RX15N
AE1
GPP_RX0P/SB_RX2P
AE2
GPP_RX0N/SB_RX2N
AB2
GPP_RX1P/SB_RX3P
AC2
GPP_RX1N/SB_RX3N
AB5
GPP_RX2P
AB4
GPP_RX2N
Y4
GPP_RX3P
AA4
GPP_RX3N
AG1
SB_RX0P
AH1
SB_RX0N
AC5
SB_RX1P
AC6
10KR1%_0603 R151
10KR1%_0603 R32
AH3
AJ3
SB_RX1N
PCE_ISET
PCE_TXISET
PART 2 OF 6
PCIE I/F TO
VIDEO
GPP_TX0P/SB_TX2P
GPP_TX0N/SB_TX2N
GPP_TX1P/SB_TX3P
GPP_TX1N/SB_TX3N
PCIE I/F TO SLOT
PCIE I/F TO SB
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
PCE_PCAL
PCE_NCAL
A7
B7
B6
B5
A5
A4
B3
B2
C1
D1
D2
E2
F2
F1
H2
J2
J1
K1
K2
L2
M2
M1
N1
N2
R1
T1
T2
U2
V2
V1
Y2
AA2
AD2
AD1
AA1
AB1
Y5
Y6
W5
W4
AF2
AG2
AC4
AD4
AH2
AJ2
3
PLACE THESE CAP CLOSE
TO CONNECTOR
SB_TX0P_C
SB_TX0N_C
SB_TX1P_C
SB_TX1N_C
C53 0.1u_0603
C54 0.1u_0603
C51 0.1u_0603
C52 0.1u_0603
150R1%_0603 R150
100R1%_0603 R36
+1.2VRUN
A_TX0P 1 5
A_TX0N 15
A_TX1P 1 5
A_TX1N 15
2
1
RS480M_A21
B B
A A
Title
RS480-PCIE LINK I/F
Size Document Number Rev
Custom
5
4
3
2
Date: Sheet
MSI CORPORATION
MS1013
1
10 41 Tuesday, January 25, 2005
0A
of
5
4
3
2
1
+3VRUN
+2.5VRUN
D D
+3VRUN
AVDDQ
+1.8VSUS
R152
10KR_0603
+1.8VRUN
+3VRUN
+1.8VRUN
L12 X_300L600m_150
CP3 X_COPPER
C C
SUS_STAT# 16
DDC1_SDATA
DDC1_SCLK
B B
R136 2.2K-0402
R135 2.2K-0402
L4 X_300L600m_150
L2 300L600m_150
AVDDQ
L6 300L600m_150
L14 300L600m_150
L20 X_300L600m_150
CP6 X_COPPER
OSC14M 14
SB_OSC_INT 16
(1.8V)
C152
C29
4.7u_0603X5R
NB STRAP PIN
ATI has internal pull up
LOAD_ROM#
R138 3K
R134 X_3K
LOAD_ROM#:LOAD ROM STRAP ENABLE strap
+3VRUN
High, LOAD ROM STRAP DISABLE
Low, LOAD ROM STRAP ENABLE
4.7u_0603X5R
VSYNC# 25
HSYNC# 25
ROUT 25
GOUT 25
BOUT 25
AVDD
+1.8VRUN
(2.5V)
C19
4.7u_0603X5R
C162
4.7u_0603X5R
C160
1u_0603
C206
1u_0603
X_22R_0603 R26
SPMEM_EN#
LOAD_ROM#
TP2
TP1
TP3
715R1%_0603 R7
DAC_SCL 25
DAC_SDAT 25
RS480M_RST# 4
NB_PWRGD 13,35
LDTSTOP# 4,15
ALLOW_LDTSTOP 15
SB_OSC_INT_R
R28 X_10K-0402
DFT_GPIO2
X_3KR_0603 R131
BMREQ# 15
DDC1_SCLK 25
DDC1_SDATA 25
NB_THRMDA 30
NB_THRMDC 30
U4D
B27
AVDD1
C27
AVDD2
D26
AVSSN1
D25
AVSSN2
C24
AVDDDI
B24
AVSSDI
E24
AVDDQ
D24
AVSSQ
B25
C
A25
Y
A24
COMP
C25
RED
A26
GREEN
B26
BLUE
A11
DACVSYNC
B11
DACHSYNC
C26
RSET
E11
DACSCL
F11
DACSDA
A14
PLLVDD
B14
PLLVSS
M23
HTPVDD
L23
HTPVSS
D14
SYSRESET#
B15
POWERGOOD
B12
LDTSTOP#
C12
ALLOW_LDTSTOP
AH4
SUS_STAT#
H13
VDDR3_1
H12
VDDR3_2
A13
OSCIN
B13
OSCOUT
B9
TVCLKIN
F12
DFT_GPIO0/RSV
E13
DFT_GPIO1/RSV
D13
DFT_GPIO2/RSV
F10
BMREQb
C10
I2C_CLK
C11
I2C_DATA
AF4
THERMALDIODE_P
AE4
THERMALDIODE_N
RS480M_A21
PART 4 OF 6
CRT/TVOUT
LVDS
PLL PWR
PM
CLOCKs
DFT_GPIO3/RSV
DFT_GPIO4/RSV
DFT_GPIO5/RSV
MIS.
TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N
TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N
TXCLK_UP
TXCLK_UN
TXCLK_LP
TXCLK_LN
LPVDD
LPVSS
LVDDR18D
LVDDR18A_1
LVDDR18A_2
LVSSR1
LVSSR2
LVSSR3
LVSSR4
LVSSR5
LVSSR6
LVSSR7
LVSSR8
LVDS_DIGON
LVDS_BLON
LVDS_BLEN
GFX_CLKP
GFX_CLKN
HTTSTCLK
HTREFCLK
SB_CLKP
SB_CLKN
TMDS_HPD
STRP_DATA
DDC_DATA
TESTMODE
D18
C18
B19
A19
D19
C19
D20
C20
LVDS_TXL0+
B16
LVDS_TXL0-
A16
LVDS_TXL1+
D16
LVDS_TXL1-
C16
LVDS_TXL2+
B17
LVDS_TXL2-
A17
E17
D17
B20
A20
LVDS_TXLCLK+
B18
LVDS_TXLCLK-
C17
E18
F17
E19
G20
H20
G19
E20
F20
H18
G18
F19
H19
F18
LVDS_DIGON
E14
LVDS_BLON
F14
LVDS_BLEN
F13
B8
A8
R120 10KR_0603
P23
N23
E8
E7
C13
C14
C15
A10
STRP_DATA
E10
DDC_DATA
B10
E12
R132
4.7K
LVDS_TXL0+ 25
LVDS_TXL0- 25
LVDS_TXL1+ 25
LVDS_TXL1- 25
LVDS_TXL2+ 25
C181
1u_0603
+3VRUN
NBSRCCLK 14
NBSRCCLK# 14
HTREFCLK 14
SBLINKCLK 14
SBLINKCLK# 14
TP79
LVDS_TXL2- 25
LVDS_TXLCLK+ 25
LVDS_TXLCLK- 25
L16 X_300L600m_150
for emi
C170
0.1u_0603
LVDS_DIGON 25
TP73
DFT_GPIO3
DFT_GPIO4
DFT_GPIO5
R40 X_10K
CP5 X_COPPER
C180
1u_0603
LVDS_BLON 25
U10
1
A0
2
A1A2SCL
3
7
WP
X_AT24C04N
SDA
VCC
GND
+1.8VRUN +1.8VRUN
X_3KR_0603 R27
X_3KR_0603 R128
X_3KR_0603 R129
+3VRUN
R37
X_2KR_0603
+3VRUN
STRP_DATA
R35
X_2KR_0603
5
6
8
4
DDC1_SCLK
C57
X_0.1u_0603
TP60
TP61
NOTE: Provide access to STRAP_DATA and I2C_CLK pins
is MANDATORY.
A A
ATI has internal pull up
SPMEM_EN#
R143 3K
R142 X_3K
SPMEM_EN#:SIDE PORT MEMORY ENABLE strap
+3VRUN
High, SIDE PORT MEMORY DISABLE
Low, SIDE PORT MEMORY ENABLE
5
4
3
DAC VDD (2.5V)
AVDD
AVDDDI DIGITAL VDD (1.8V)
DAC2 BANDGAP REF (1.8V)
PLLVDD PLL VDD (1.8V)
HTPVDD HT PLL VDD (1.2V)
Title
RS480-VIDEO I/F & CLKGEN
Size Document Number Rev
Custom
2
Date: Sheet
MSI CORPORATION
MS1013
1
11 41 Tuesday, January 25, 2005
0A
of
5
VSSA22
R5
AE5V5N3F7F5R3AA6T3M6C5F8M8Y8V3C3W3K8D3C6
VSSA1
VSSA2
VSSA3
VSSA4
VSSA5
VSSA6
VSSA7
VSSA8
D D
VSSA9
VSSA10
VSSA11
VSSA12
VSSA13
VSSA14
VSSA15
VSSA16
AA3A2AB3P8J6C8AD3V8F3
VSSA17
VSSA18
VSSA19
VSSA20
VSSA21
VSSA22
VSSA23
VSSA24
AE3
AF3M5AB7G3B4P7AA5C9C7J5R6J3AD5D6C4K3AB8T7Y7
VSSA25
VSSA26
VSSA27
VSSA28
VSSA29
VSSA30
VSSA31
VSSA32
VSSA33
VSSA34
VSSA35
VSSA36
VSSA37
VSSA38
VSSA39
VSSA40
VSSA41
PAR 6 OF 6
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
G10
G12
AD29
AD27
AC27
G15
G14
Y24
G13E9D15D9AD9
G11
F16
G30
AB28
AB25
D12
AD24
AA28
G17
Y23
AC9
R19
Y27
C28
G16
F25
B30
T24
F26
W27
D11
H11
AD25
H17
H10
H16
H14
E16
D10
VSSA42
VSSA43
VSS42
VSS43
E15
F15
VSSA44
VSSA45
VSS44
VSSA46
VSSA47
VSS45
U15
V14
VSSA48
VSS46
4
AD6K7H7M3V6H8C2
VSSA49
VSSA50
VSSA51
VSSA52
VSS47
VSS48
VSS49
VSS50
R15
T14
N15
V12
AG3L6AJ1M7V7F6E6U5U6E5L5
VSSA53
VSSA54
VSSA55
VSSA56
VSSA57
VSS51
VSS52
VSS53
VSS54
VSS55
N13
P14
U17
T16
R17
P12
VSSA59
VSSA58
VSSA59
VSS56
VSS57
T12
R13
VSSA60
VSSA61
VSS58
VSS59
W13
W17
VSSA62
VSSA63
VSS60
VSS61
P18
V18
VSSA64
VSSA65
VSS62
VSS63
M18
U13
VSSA66
VSS64
T8
VSSA67
VSSA68
GROUND
VSS65
VSS66
VSS67
VSS68
VSS69
N17
W15
V16
T18
M14
VSS70
M12
F28
H28
VSS113
VSS71
M16
P16
M24
VSS114
VSS115
VSS72
J28
N19
VSS116
U19
K28
VSS117
VSS118
VSS73
VSS74
AC16
T23
L27
VSS119
VSS75
AG18
AC23
M27
VSS120
VSS76
VSS77
AD8
AD11
H24
VSS122
VSS123
VSS78
VSS79
AD13
3
N28
P25
VSS124
VSS80
AD16
AD19
P28
VSS125
VSS126
VSS81
VSS82
AD23
E26
K25
VSS127
VSS83
AG5
AG6
U28
VSS128
VSS129
VSS84
VSS85
AG21
V25
V28
VSS130
VSS86
AD17
AG15
R23
VSS131
VSS132
VSS87
VSS88
AG12
AF30
VSS89
VSS90
AG24
VSS91
AG9
VSS92
AC19
VSS93
AG27
VSS94
AC11
VSS95
AD7
VSS96
AJ30
VSS97
AC21
VSS98
AK5
VSS99
AK10
VSS100
AC13
AD21
VSS101
VSS102
AK22
AK29
VSS103
VSS104
W19
VSS105
AE26
AE27
VSS106
VSS107
T27
R27
VSS108
VSS109
AD28
F24
VSS110
VSS111
F27
VSS112
G28
2
U4F
RS480M_A21
NB RS480 POWER STATES
Power Signal
VDDHT
VDDR,VDDRCK
VDD18
VDDC
VDDA18
VDDA12
S0
ON
ON
ON
ON
ON
ON
ON
AVDDDI
PLLVDD
HTPVDD
VDDR3
LPVDD
LVDDR18
ON
ON
ON
ON
ON
ON
S4/S5
S1
S3
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF AVDD
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
ON
LVDDR25 OFF ON ON OFF OFF
1
G3
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
VSS89
C210
10u_1206X5R
C201
0.1u_0603
C222
0.1u_0603
C159
0.1u_0603
VDDA18
C212
0.1u_0603
C187
C199
1u_0603
0.1u_0603
C221
0.1u_0603
C226
10u_1206X5R
C130
0.1u_0603
THE CAPS SHOULD PLACE UNDER
NB, ALL GND USE COPPER FLOOD
TOGETHER, AND NB POWER VIA
TREAT AS SAME.
C148
0.1u_0603
C224
X_0.1u_0603
C213
0.1u_0603
CP7 X_COPPER
C153
0.1u_0603
C196
0.1u_0603
C150
0.1u_0603
+1.2VRUN
L21 X_300L600m_150
C129
10u_1206X5R
+1.8VRUN
C191
0.1u_0603
VDDA12_13
C49
VSSA22
VDDA18_13
VSSA59
VDDHT30
VSS30
VDDHT31
VSS89
PUT DECOUPLING CAPS ON THE TOP, CLOSE
TO BALLS
10u_1206X5R
C50
10u_1206X5R
C18
10u_1206X5R
C17
10u_1206X5R
C158
0.1u_0603
C40
X_0.1u_0603
C183
0.1u_0603
VSS30
C200
0.1u_0603
C176
0.1u_0603
C174
0.1u_0603
C188
0.1u_0603
C42
0.1u_0603
C175
0.1u_0603
C192
0.1u_0603
VDDHT30
VDDHT31
C198
0.1u_0603
C189
1u_0603
AB24
AA27
AB27
AB23
AA23
AC30
AK23
AK28
AK11
AE30
AC14
AD12
AC18
AC20
AD10
AD14
AD15
AD20
AC10
AD18
AC12
AD22
AC22
AH15
AC17
AC15
N27
U27
G27
H27
G23
W23
H23
U23
D23
C23
AK4
H15
C21
C22
G21
V27
V24
K24
P27
J27
K27
P24
V23
E23
K23
J23
F23
B23
A23
A29
B21
A22
B22
F21
F22
E21
U4E
VDD_HT1
VDD_HT2
VDD_HT3
VDD_HT4
VDD_HT5
VDD_HT6
VDD_HT7
VDD_HT8
VDD_HT9
VDD_HT10
VDD_HT11
VDD_HT12
VDD_HT13
VDD_HT14
VDD_HT15
VDD_HT16
VDD_HT17
VDD_HT18
VDD_HT19
VDD_HT20
VDD_HT21
VDD_HT22
VDD_HT23
VDD_HT24
VDD_HT25
VDD_HT26
VDD_HT27
VDD_HT28
VDD_HT29
VDD_HT30
VDD_HT31
VDD_MEM1
VDD_MEM2
VDD_MEM3
VDD_MEM4
VDD_MEM5
VDD_MEM6
VDD_MEM7
VDD_MEM8
VDD_MEM9
VDD_MEM10
VDD_MEM11
VDD_MEM12
VDD_MEM13
VDD_MEM14
VDD_MEM15
VDD_MEM16
VDD_MEM17
VDD_MEM18
VDD_MEMCK
VDD_18_1
VDD_18_2
VDD_18_3
VDD_CORE47
VDD_CORE46
VDD_CORE45
VDD_CORE44
VDD_CORE43
VDD_CORE42
VDD_CORE41
VDD_CORE40
VDD_CORE39
RS480M_A21
PART 5 OF 6
VDDA_12_14
VDDA_12_1
VDDA_12_2
VDDA_12_3
VDDA_12_4
VDDA_12_5
VDDA_12_6
VDDA_12_7
VDDA_12_8
VDDA_12_9
VDDA_12_10
VDDA_12_11
VDDA_12_12
VDDA_12_13
VDDA_18_1
VDDA_18_2
VDDA_18_3
VDDA_18_4
VDDA_18_5
VDDA_18_6
VDDA_18_7
VDDA_18_8
VDDA_18_9
VDDA_18_10
VDDA_18_11
VDDA_18_12
VDDA_18_13
VDD_CORE1
VDD_CORE2
VDD_CORE3
VDD_CORE4
VDD_CORE5
VDD_CORE6
VDD_CORE7
VDD_CORE8
VDD_CORE9
VDD_CORE10
VDD_CORE11
VDD_CORE12
VDD_CORE13
VDD_CORE14
VDD_CORE15
VDD_CORE16
VDD_CORE17
VDD_CORE18
VDD_CORE19
VDD_CORE20
VDD_CORE21
VDD_CORE22
VDD_CORE23
VDD_CORE24
VDD_CORE25
VDD_CORE26
VDD_CORE27
VDD_CORE28
VDD_CORE29
VDD_CORE30
VDD_CORE31
VDD_CORE32
VDD_CORE33
VDD_CORE34
VDD_CORE35
POWER
VDD_CORE36
VDD_CORE37
VDD_CORE38
H9
AA7
G9
U8
N7
N8
U7
F9
AA8
G8
G7
J8
J7
B1
AG4
R8
AC8
AC7
AF6
AE6
L8
W8
W7
L7
R7
AF5
AK2
N16
M13
M15
W16
N18
P19
N12
P15
N14
M17
T19
G22
R12
P13
R14
V19
R18
U16
U12
T13
U14
T17
U18
E22
R16
V13
T15
P17
W18
D22
W12
V15
W14
V17
M19
H22
H21
D21
VDDA12_13
VDDA18_13
C223
1u_0603
C220
0.1u_0603
+1.2VRUN
+1.2VRUN
+1.2VRUN
C173
0.1u_0603
C209
10u_1206X5R
C163
0.1u_0603
C168
X_0.1u_0603
C197
0.1u_0603
C149
0.1u_0603
C C
+2.5VRUN
B B
10u_1206X5R
A A
C161
C156
0.1u_0603
+1.8VRUN VDD18
L15 X_300L600m_150
CP4
X_COPPER
Title
RS480-POWER
Size Document Number Rev
Custom
5
4
3
2
Date: Sheet
MSI CORPORATION
MS1013
1
12 41 Tuesday, January 25, 2005
0A
of
5
4
3
2
1
+3VSUS
D D
PM_SLP_S5# 16,28
VRM_GD 4,16,33
VTT_VDDIO_PG 34
C C
VDDA_PG 34
VTT_VDDIO_PG 34
NB_PWRGD 11,35
PM_SLP_S3# 16,28
POWER_OK
VDDA_PG
VRM_GD 4,16,33
R201
C348
X_1u_0603
+3VSUS
C347 0.1u_0402
1
2
+3VSUS
4
5
0R_0603
14 7
14 7
+3VSUS
12
13
U19A
3
74LCX08MTC
9
10
U19B
6
74LCX08MTC
14 7
+3VSUS
14 7
U20D
11
VHC32MTC
+3VSUS
C346 0.1u_0402
1
2
U19C
8
74LCX08MTC
+3VSUS
9
10
14 7
U20A
3
+3VSUS
VHC32MTC
14 7
12
13
U19D
74LCX08MTC
11
14 7
AND_PG
U20C
VHC32MTC
8
4
5
+3VSUS
VDDA_EN
14 7
U20B
6
VHC32MTC
VTT_VDDIO_EN 34
VDDA_EN 34
VDD_EN 33
VLDT_EN 35
VHC32MTC-VCC=3.0
VIH=0.7VCC
VIL=0.3VCC
VOH=2.9V
VOL=0.1V
74LCX08MTC-VCC=3.0V
VIH=2.0V
VIL=0.8V
VOH=2.4V
VOL=0.4V
B B
VRM_GD
100KR_0603 R177
C339
1u_0603
for emi
+V1.25_VTT
R184
X_100KR_0603
Q12
X_N-2N7002
VTT_VDDIO_EN 34 VDD_EN 33 VLDT_EN 35
G
5
R179
X_10KR_0603
D S
D S
G
X_10KR_0603
Q10
X_N-2N7002
R193
G
+2.5VSUS
D S
Q14
X_N-2N7002
4
R215
X_100KR_0603
Q15
X_N-2N7002
G
R202
X_10KR_0603
D S
V_CORE +5VALW +5VALW
G
D S
Q16
X_N-2N7002
R174
X_100KR_0603
X_N-2N7002
3
VRM_GD 4,16,33
NB_PWRGD
V_CORE +5VALW +3VRUN
R173
X_10KR_0603
Q9
D S
G
Q8
D S
X_N-2N7002
G
+3VSUS
U16B
14 7
LCX08_SOIC14
4
5
2
C341
1u_0402
6
Vth=2.93V
U21
3
V
X_MAX809
SB_PWRGD 16,26
+3VRUN
1 2
R478
150K_0402
POWER_OK
2
R
1
G
Title
Size Document Number Rev
A3
Date: Sheet
1 2
R491
X_100K_0402
{Title}
{Doc} {RevCode}
placement on top side
C601
1u_0402
1
D20
RB751V
A C
13 41 Tuesday, January 25, 2005
of
A