Table 5-1 Images and Directories .................................................................................................. 51
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USER MANUAL v1.0
Date: 01/20/2014
1 Board Overview
1.1 Product Introduction
The RIoTboard is an evaluation platform featuring the powerful i.MX 6Solo, a
multimedia application processor with ARM Cortex-A9 core at 1 GHz from Freescale
Semiconductor. The platform helps evaluate the rich set of peripherals and includes
a 10/100/Gb Ethernet port, HDMI v1.4, LVDS, analog headphone/microphone, uSD
and SD card interface, USB, serial port, JTAG, 2 camera interfaces, GPIO boot
configuration interface, and expansion port, as shown in Figure 1-1.
The RIoTboard can be used in the following applications:
• Netbooks (web tablets)
• Nettops (Internet desktop devices)
• High-end mobile Internet devices (MID)
• High-end PDAs
• High-end portable media players (PMP) with HD video capability
• Portable navigation devices (PNDs)
• Industrial control and Test and measurement (T&M)
• Single board computers (SBCs)
Figure 1-1 Functional Block Diagram
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1.2 Features
The RIoTboard is based on the i.MX 6Solo processor from Freescale Semiconductor
integrating all the functionalities of this multimedia application processor with the
following features:
• Mechanical Parameters
o Working Temperature: 0°C - 50°C
o Humidity Range: 20% - 90%
o Dimensions: 120mm x 75mm
o Input Voltage: +5V
• Processor
o ARM Cortex A9 MPCore™ Processor at 1 GHz
o High-performing video processing unit which covers SD-level and HD-
level video decoders and SD-level encoders as a multi-standard video
codec engine
o An OpenGL® ES 2.0 3D graphics accelerator with a shader and a 2D
graphics accelerator for superior 3D, 2D, and user interface
acceleration
• Memories
o 1GByte of 16-bit wide DDR3 @ 800MHz
o 4GB eMMC
Figure 1-2 RIoTboard top view
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USER MANUAL v1.0
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• Media Interfaces
o Analog headphone/microphone, 3.5mm audio jack
o LVDS interface
o HDMI interface
o Parallel RGB interface(Expansion port)
o Camera interface (Support CCD or CMOS camera)
o MIPI lanes at 1 Gbps
Figure 1-3 RIoTboard bottom view
•Data Transfer Interfaces oDebug Ports:
3 pin TTL level
oSerial Ports:
UART3,4,5, 3 line serial port, TTL Logic (Expansion port)
oUSB Ports:
1 x USB2.0 OTG, mini USB, high-speed, 480Mbps
4 x USB2.0 HOST, Type A, high-speed, 480Mbps
o uSD card interface
o SD card interface
o 10M/100M/Gb Ethernet Interface (RJ45 jack)
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o 2 channel I2C interface (Expansion port)
o 2 channel SPI interface (Expansion port)
o 3 channel PWM interface (Expansion port)
o GPIO (Expansion port)
o 10-pin JTAG interface
o Open SDA
• Others
o 1 Power LED
o 1 Open SDA LED
o 2 User-defined LEDs
o 1 DC Jack
o 1 Reset button
o Boot configuration interface
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USER MANUAL v1.0
Date: 01/20/2014
2 Hardware Description
2.1 Processor
The i.MX 6Solo processor represents Freescale Semiconductor’s latest achievement in
integrated multimedia applications processors, which are part of a growing family of
multimedia-focused products that offer high performance processing and are
optimized for lowest power consumption.
The processor features Freescale’s advanced implementation of the single ARM™
Cortex-A9 core, which operates at speeds up to 1 GHz. It includes 2D and 3D graphics
processors, 3D 1080p video processing, and integrated power management. The
processor provides a 16/32-bit DDR3/LVDDR3-800 memory interface and a number of
other interfaces for connecting peripherals, such as WLAN, Bluetooth™, GPS, hard drive,
displays, and camera sensors.
2.1.1 Core Features
The i.MX 6Solo processor is based on the ARM Cortex A9 MPCore™ platform with the
following features:
• ARM Cortex A9 MPCore™ CPU Processor (with TrustZone)
• The core configuration is symmetric, where the core includes:
o 32 KByte L1 Instruction Cache
o 32 KByte L1 Data Cache
o Private Timer and Watchdog
o Cortex-A9 NEON MPE (Media Processing Engine) Co-processor
• The ARM Cortex A9 MPCore™ complex includes:
o General Interrupt Controller (GIC) with 128 interrupt support
o Global Timer
o Snoop Control Unit (SCU)
o 512 KB unified I/D L2 cache
o Two Master AXI (64-bit) bus interfaces output of L2 cache
o NEON MPE coprocessor
SIMD Media Processing Architecture
NEON register file with 32x64-bit general-purpose registers
NEON Integer execute pipeline (ALU, Shift, MAC)
NEON dual, single-precision floating point execute pipeline
(FADD, FMUL)
NEON load/store and permute pipeline
• The memory system consists of the following components: o Level 1 Cache--32 KB Instruction, 32 KB Data cache per core
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o Level 2 Cache--Unified instruction and data (512 KByte)
o On-Chip Memory:
• 16/32-bit LP-DDR2-800, 16/32-bit DDR3-800 and LV-DDR3-800.
• 8-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB
page size, BA-NAND, PBA-NAND, LBA-NAND, OneNAND™ and others. BCH ECC
up to 40 bit.
• 16/32-bit NOR Flash. All WEIMv2 pin are muxed on other interfaces.
• 16/32-bit PSRAM, Cellular RAM
Figure 2-1
Block Diagram of i.MX 6Solo
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2.1.3 Interface to external devices
Each i.MX 6Solo processor enables the following interfaces to external devices
(some of them are muxed and not available simultaneously):
• Displays--Total five interfaces available. Total raw pixel rate of all interfaces is
up to 450 Mpixels/sec, 24 bpp. Up to two interfaces may be active in parallel.
o One Parallel 24-bit display port, up to 225 Mpixes/sec (for example,
WUXGA at 60 Hz or dual HD1080 and WXGA at 60 Hz)
o LVDS serial ports:One port up to 165 Mpixels/sec or two ports up to
85 MP/sec (for example, WUXGA at 60 Hz) each
o HDMI 1.4 port
o MIPI/DSI, two lanes at 1 Gbps
o EPDC, Color, and monochrome E-INK, up to 1650x2332 resolution and
5-bit grayscale
• Camera sensors:
o Two parallel Camera ports (up to 20 bit and up to 240 MHz peak)
o MIPI CSI-2 serial camera port, supporting from 80 Mbps to 1 Gbps
speed per data lane. The CSI-2 Receiver core can manage one clock
lane and up to two data lanes. Each i.MX 6Solo processor has two
lanes.
• Expansion cards: o Four MMC/SD/SDIO card ports all supporting:
1-bit or 4-bit transfer mode specifications for SD and SDIO
cards up to UHS-I SDR-104 mode (104 MB/s max)
1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards
up to 52 MHz in both SDR and DDR modes (104 MB/s max)
• USB o One high speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS
USB PHY
o Three USB 2.0 (480 Mbps) hosts
One HS host with integrated High Speed PHY
Two HS hosts with integrated HS-IC USB (High Speed Inter-Chip
USB) PHY
• Expansion PCI Express port (PCIe) v2.0 one lane o PCI Express (Gen 2.0) dual mode complex, supporting Root complex
operations and Endpoint operations. Uses x1 PHY configuration.
• Miscellaneous IPs and interfaces:
o Three I2S/SSI/AC97,up to 1.4 Mbps each
o Enhanced Serial Audio Interface ESAI), up to 1.4 Mbps per channel
o Five UARTs, up to 4.0 Mbps each
One of the five UARTs (UART1) supports 8-wire while the other
four support 4-wire. This is due to the SoC IOMUX limitation,
since all UART IPs are identical
o Four eCSPI (Enhanced CSI)
o Four I2C, supporting 400 kbps
o Gigabit Ethernet Controller(IEEE1588 compliant), 10/100/1000 Mbps
o Four Pulse Width Modulators (PWM)
o System JTAG Controller (SJC)
o GPIO with interrupt capabilities
o 8x8 Key Pad Port (KPP)
o Sony Philips Digital Interface (SPDIF), Rx and Tx
o Two Controller Area Network (FlexCAN), 1 Mbps each
o Two Watchdog timers (WDOG)
o Audio MUX (AUDMUX)
o MLB (MediaLB) provides interface to MOST Networks (MOST25, MOST50,
MOST150) with the option of DTCP cipher accelerator
2.1.4 Advanced Power Management unit
The i.MX 6Solo processors integrate advanced power management unit and
controllers:
• Provide PMU, including LDO supplies, for on-chip resources
• Use Temperature Sensor for monitoring the die temperature
• Support DVFS techniques for low power modes
• Use SW State Retention and Power Gating for ARM and MPE
• Support various levels of system power modes
• Use flexible clock gating control scheme
2.1.5 Hardware Accelerators
The i.MX 6Solo processor uses dedicated hardware accelerators to meet the targeted
multimedia performance. The use of hardware accelerators is a key factor in obtaining
high performance at low power consumption numbers, while having the CPU core
relatively free for performing other tasks.
The i.MX 6Solo processor incorporates the following hardware accelerators:
• VPU--Video Processing Unit
• IPUv3H--Image Processing Unit version 3H
• GPU3Dv5--3D Graphics Processing Unit (OpenGL ES 2.0) version 5
• GPU2Dv2--2D Graphics Processing Unit (BitBlt)
• ASRC--Asynchronous Sample Rate Converter
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Security functions are enabled and accelerated by the following hardware:
• ARM TrustZone including the TZ architecture (separation of interrupts, memory
mapping, etc.)
• SJC--System JTAG Controller. Protecting JTAG from debug port attacks by
regulating or blocking the access to the system debug features.
• CAAM--Cryptographic Acceleration and Assurance Module, containing
cryptographic and hash engines, 16 KB secure RAM and True and Pseudo
Random Number Generator (NIST certified)
• SNVS--Secure Non-Volatile Storage, including Secure Real Time Clock
• CSU--Central Security Unit. Enhancement for the IC Identification Module (IIM).
Will be configured during boot and by eFUSEs and will determine the security
level operation mode as well as the TZ policy.
• A-HAB Advanced High Assurance Boot--Hv4 with the new embedded
enhancements:SHA-256, 2048-bit RSA key, version control mechanism, warm
boot, CSU, and TZ initialization.
2.2 Expanded Chip Introduction
USER MANUAL v1.0
Date: 01/20/2014
2.2.1 MT41K256M16HA-125:E
The board has 1GB of SDRAM (2x512MB). Micron’s MT41K256M16 is a 512MB DDR3
Synchronous DRAM, ideally suited for the main memory applications which require
large memory density and high bandwidth.
2.2.2 MMPF0100NPAEP
The PF0100 Power Management Integrated Circuit (PMIC) provides a highly
programmable/ configurable architecture, with fully integrated power devices and
minimal external components. With up to six buck converters, six linear regulators, RTC
supply, and coin-cell charger, the PF0100 can provide power for a complete system,
including applications processors, memory, and system peripherals, in a wide range of
applications. With on-chip One Time Programmable (OTP) memory, the PF0100 is
available in pre-programmed standard versions, or non-programmed to support
custom programming. The PF0100 is defined to power the entire embedded MCU
platform solution similar to i.MX6 based eReader, IPTV, medical monitoring and
home/factory automation.
2.2.3 AR8035
AR8035 is a single port 10/100/1000 Mbps tri-speed Ethernet PHY feaured with low
power and low cost. AR8035 supports MAC.TM RGMII interface and IEEE 802.3az-2010,
Energy Efficient Ethernet (EEE) standard through proprietary SmartEEE technology,
improving energy efficiency in systems using legacy MAC devices without 802.3az
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USER MANUAL v1.0
Date: 01/20/2014
support. The RIOT Board can be connected to a network hub directly through a cable. It
also can be directly connected with a computer through a crossover cable which is
provided with the kit.
2.2.4 FE1.1
FE1.1 is a USB 2.0 high-speed 4-port hub solution. It uses USB3320 to provide 4
extended USB interface with support for high-speed (480MHz), full-speed (2MHz) and
low-speed (1.5MHz) mode.
2.2.5 SGTL5000
The SGTL5000 is a low power stereo Codec with Headphone Amp from Freescale, and is
designed to provide a complete audio solution for portable products needing line-in,
mic-in, line-out, headphone-out, and digital I/O. Deriving its architecture from best-inclass Freescale-integrated products currently on the market, the SGTL5000 is able to
achieve ultra low-power with very high performance and functionality, all in one of the
smallest footprints available.
Designed with features such as capless headphone and an integrated PLL to allow clock
reuse within the system, it helps customers achieve a lower overall system cost.
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J1
Pin Signal
Function
1 GND GND
2 NC NC
3 +5V Power supply (+5V)
4
A (Type)
USER MANUAL v1.0
Date: 01/20/2014
2.3 Expanded Chip Introduction
2.3.1 Power Input Jack
A 5V/4A AC-to-DC power supply needs to be plugged into the Power Jack (J1) on the
board. It is not recommended to use a higher voltage since possible damage to the
board may result due to failure of the protection circuitry.
Figure 2-2
Table 2-1
Power Interface
Power Interface
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