MOTOROLA XC33989 Technical data

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MOTOROLA

SEMICONDUCTOR

Freescale Semiconductor, Inc.

TECHNICAL DATA

Advance Information

Order this document by Rev: 4.91 Date: 10th July, 2002

XC33989

System Basis Chip with High Speed CAN Transceiver

The MC33989 is a monolithic integrated circuit combining many functions frequently used by automotive ECUs. It incorporates:

- Two voltage regulators.

- Four high voltage inputs.

- 1Mbaud CAN physical interface.

• Vdd1: Low drop voltage regulator, current limitation, over temperature detection, monitoring and reset function

• Vdd1: Total current capability 200mA.

• V2: Tracking function of Vdd1 regulator. Control circuitry for external bipolar ballast transistor for high flexibility in choice of peripheral voltage and current supply.

• Four operational modes (normal, stand-by, stop and sleep mode)

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• Low stand-by current consumption in stop and sleep modes

• High speed 1MBaud CAN physical interface.

• Four external high voltage wake-up inputs, associated with HS1 Vbat switch

• 150mA output current capability for HS1 Vbat switch allowing drive of external switches pull up resistors or relays

• Vsup failure detection

• Nominal DC operating voltage from 5.5 to 27V, extended range down to 4.5V.

• 40V maximum transient voltage

• Programmable software time out and window watchdog

• Safe mode with separate outputs for Watchdog time out and Reset

• Wake up capabilities (four wake up inputs, programmable cyclic sense, forced wake up, CAN interface, SPI and stop mode over current)

• Interface with MCU through SPI

Simplified Block Diagram

cale Semiconductor,

Frees

Vbat

Vsup

V2CTRL

Vsup monitor

Dual Voltage Regulator

Vdd1 Monitor

5V/200mA

CAN

supply

Vdd1

SYSTEM BASIS CHIP

WITH HIGH SPEED CAN

SEMICONDUCTOR

TECHNICAL DATA

DW SUFFIX

PLASTIC PACKAGE

CASE 751-F

(SO-28)

PIN CONNECTIONS

Vdd1

Reset

INTB GND GND GND GND

V2ctrl

Vsup

HS1

WDOGB CSB MOSI MISO SCLK GND GND GND GND CANL CANH L3

L2 L1

Mode control

Oscillator

Interrupt

Watchdog

Reset

SPI

CAN

INTB

WDOGB

Reset

MOSI SCLK

MISO

CSB

Gnd

Rterm

HS1

CAN H

CAN L

HS1 control

Programmable wake-up input

High Speed 1Mbit/s

Physical Interface

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This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

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Device

ORDERING INFORMATION

Operating

Temperatur e Range

TA = -40 to 125°CPC33989DW

Motorola,Inc 2002

Package

SO-28

Freescale Semiconductor, Inc.

1 MAXIMUM RATINGS

Ratings Symbol Min Typ Max Unit

ELECTRICAL RATINGS

Supply Voltage at Vsup

- Continuous voltage

- Transient voltage (Load dump)

Vsup Vsup

MC33989

-0.3 27

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Frees

Logic Inputs (Rx, Tx, MOSI, MISO, CSB, SCLK, Reset, WDOGB, INTB)

Output current Vdd1 I Internally limited A

HS1

- voltage

- output current

ESD voltage (HBM 100pF, 1.5k)

- HS1, L0, L1, L2, L3

- All other pins

ESD voltage (Machine Model) All pins except CANH and CANL

L0, L1,L2, L3

- DC Input voltage

- DC Input current

- Transient input voltage (according to ISO7637 specification) and with external component (see figure 1 below).

THERMAL RATINGS

Junction Temperature T

Storage Temperature T

Ambient Temperature (for info only) T

Thermal resistance junction to gnd pins (note 1) Rthj/p 20 °C/W

note 1: gnd pins 6, 7, 8, 9, 20, 21, 22, 23

Figure 1. : Transient test pulse for L0, L1, L2 and L3 inputs

Gnd

Vlog - 0.3 Vdd1+0.3 V

Vesdh

Vesdm -200 200 V

Vwu DC

1nF

10 k

-0.3

-4

-2

-0.3

-2

-100

- 40 +150 °C

- 55 +165 °C

- 40 +125 °C

Transient Pulse

Internally limited

Generator

(note)

Gnd

Vsup+0.3 V

+100

4 2

note: Waveform in accordance to ISO7637 part1, test pulses 1, 2, 3a and 3b.

MC33989 2

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MC33989

2 ELECTRICAL CHARACTERISTICS

From 5.5V to 18V and Tamb -40°C to 125°C)

sup

For all pins except CANH, CANL, Tx and Rx which are described in the CAN module section

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Description Symbol

Vsup pin (Device power supply)

Nominal DC Voltage range

Extended DC Voltage range 1 Vsup-ex1 4.5 5.5 V Reduced functionality

Extended DC Voltage range 2 Vsup-ex2 18 27 V (note 3)

Input Voltage during Load Dump

Input Voltage during jump start

Supply Current in Stand-by Mode (note 2,4) (includes 10mA at Vdd1)

Supply Current in Normal Mode (note 2)

Supply Current in Sleep Mode (note 2,4)

Supply current in sleep mode (note 2,4)

Supply Current in Stop mode (note 2,4) I out Vdd1 <2mA

Supply Current in Stop mode (note 2,4)

Iout Vdd1 < 2mA

BATFAIL Flag internal threshold VBF 1.5 3 4 V

BATFAIL Flag hysteresis VBF hyst 1 V guaranteed by design

Battery fall early warning threshold BFew 5.3 5.8 6.3 V In normal & standby mode

Battery fall early warning hysteresis BFewh 0.1 0.2 0.3 V In normal & standby mode

note 1: Vdd1>4V, reset high, logic pin high level reduced, device is functional. note 2: Current measured at Vsup pin. note 3: Device is fully functional. All functions are operating (All mode available and operating, Watchdog, HS1 turn ON turn OFF, CAN cell operating, L0 to L3 inputs operating, SPI read write operation). Over temperature may occur. note 4: With CAN cell in sleep-disable state. If CAN cell is sleep-enabled for wake up, an additional 60uA must be added to specified value. note 5: Oscillator running means “Forced Wake up” or “Cyclic Sense” or “Software Watchdog in stop mode” timer activated. Oscillator not running means that “Forced Wake up” and “cyclic Sense” and “Software Watchdog in stop mode” are not activated.

Vsup

VsupLD

VsupJS

Isup(stdby)

Isup(norm)

Isup

(sleep1)

Isup

(sleep2)

Isup

(sleep3)

Isup

(stop1)

Isup

(stop2)

Isup

(stop3)

Characteristics

Unit Conditions

Min Typ Max

5.5 18 V

(note 1)

40 V Load dump situation

27 V Jump start situation

12 17 mA Iout at Vdd1 =10mA

CAN recessive or sleep-

disable state

12.5 17 mA Iout at Vdd1 =10mA CAN recessive or sleep-

disable state

72 105 uA Vdd1 & V2 off, Vsup<12V,

oscillator running (note5)

CAN in sleep-disable state

57 90 uA Vdd1 & V2 off, Vsup<12V

oscillator not running (5)

CAN in sleep-disable state

100 150 uA Vdd1 & V2 off, Vsup>12V

oscillator running (5)

CAN in sleep-disable state

135 210 uA Vdd1 on, Vsup<12V

oscillator running (5)

CAN in sleep-disable state

130 410 uA Vdd1 on, Vsup<12V

oscillator not running (5)

CAN in sleep-disable state

160 230 uA Vdd on, Vsup>12

oscillator running (5)

CAN in sleep-disable state

guaranteed by design

Vdd1 (external 5V output for MCU supply). Idd1 is the total regulator output current. Vdd specification with external capacitor. Stability requirement: C>47uF ESR < 1.3 ohms (tantalum capacitor) In reset, normal request, normal and standby modes. Measures with C=47uF Tantalum.

Vdd1 Output Voltage Vdd1out 4.9 5 5.1 V Idd1 from 2 to 200mA

Vdd1 Output Voltage Vdd1out 4 V Idd1 from 2 to 200mA

Tamb -40°C to 125°C

5.5V< Vsup <27V

4.5V< Vsup <5.5V

MC33989 3

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From 5.5V to 18V and Tamb -40°C to 125°C)

sup

For all pins except CANH, CANL, Tx and Rx which are described in the CAN module section

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MC33989

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Description Symbol

Dropout Voltage Vdd1drop 0.2 0.5 V Idd1 = 200mA

Dropout Voltage, limited output current Vdd1dp2 0.1 0.25 V Idd1 = 50mA

Idd1 output current Idd1 200 285 350 mA Internally limited

Thermal Shutdown (junction) Tsd 160 200

Over temperature pre warning (junction) Tpw 125 160

Temperature Threshold difference Tsd-Tpw 20 40

Reset threshold 1 Rst-th1 4.5 4.6 4.7 V Selectable by SPI. Default

Reset threshold 2 Rst-th2 4.1 4.2 4.3 V Selectable by SPI

Vdd1 range for Reset Active Vdd

Reset Delay Time t

Line Regulation

Load Regulation

Thermal stability ThermS 30 50 mV

Vdd1 in Stop mode

Vdd1 Output Voltage Vddstop 4.75 5,00 5.25 V Idd1<=2mA

Vdd1 Output Voltage Vddstop2 4.75 5,00 5.25 V Idd1<=10mA

Idd1 stop output current to wake up SBC Idd1s-wu 10 17 25 mA

Idd1 over current wake up deglitcher time Idd1 - dglt 40 55 75 us guaranted by design

Reset threshold Rst-stop1 4.5 4.6 4.7 V

Reset threshold Rst-stop2 4.1 4.2 4.3 V

Line regulation

Load regulation

V2 tracking voltage regulator

note 3: V2 specification with external capacitor

- Stability requirement: C>42uF and ESR<1.3 ohm (tantalum capacitor), external resistor between base and emitter required.

- Measurement conditions: Ballast transistor MJD32C, C=10uF tantalum, 2.2k resistor between base and emitter of ballast transistor.

V2 Output Voltage

I2 output current (for information only) I2 200 mA Depending upon external

V2 ctrl drive current capability I2ctrl 0 10 mA Worst case at Tj=125°C

V2LOW Flag Threshold V2Lth 3.75 4 4.25 V

Logic output pins (MISO) Push pull structure with tri state condition (CSB high).

Low Level Output Voltage Vol 0 1.0 V I out = 1.5mA

High Level Output Voltage Voh Vdd1-0.9 Vdd1 V I out = -250uA

Tristated MISO Leakage Current -2 +2 uA 0V<V

Logic input pins (MOSI, SCLK, CSB)

High Level Input Voltage Vih 0.7Vdd1 Vdd1+0.3

Low Level Input Voltage Vil -0.3 0.3Vdd1 V

High Level Input Current on CSB Iih -100 -20 uA V

Low Level Input Current CSB Iil -100 -20 uA V

MOSI, SCK Input Current Iin -10 10 uA 0<V

(C at Vdd1= 47uF tantal) LR1 5 25 mV 9V<V

(C at Vdd1= 47uF tantal) LR2 10 25 mV 5.5V<V

(C at Vdd1= 47uF tantal) LD 25 75 mV 1mA<I

(C at Vdd1= 47uF tantal) LR-s 5 25 mV 5.5V<V

(C at Vdd1= 47uF tantal) LD-s 15 75 mV 1mA<I

(C at V2 = 10uF tantal) V2 0.99 1 1.01 Vdd1 I2 from 2 to 200mA

Characteristics

Min Typ Max

430us

Unit Conditions

4.5V< Vsup

°C Normal or standby mode

°C VDDTEMP bit set

°C

value after reset.

Measured at 50% of reset

not tested, guaranted by

charaterization and design

signal

<18, Idd=10mA

sup

<27V, Idd=10mA

sup

<200mA

Idd

Vsup=13.5V, I=100mA

<27V, Idd=2mA

sup

<10mA

Idd

5.5V< Vsup <27V

ballast transistor

<Vdd

miso

=4V

=1V

<Vdd

MC33989 4

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From 5.5V to 18V and Tamb -40°C to 125°C)

sup

For all pins except CANH, CANL, Tx and Rx which are described in the CAN module section

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MC33989

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Description Symbol

Reset Pin (output pin only, supply from Vdd1. Structure switch to gnd with pull up current source)

High Level Output current Ioh -300 -250 -150 uA 0<V

Low Level Output Voltage (I

Reset pull down current Ipdw 2.3 5 mA V>0.9V

Reset Duration after Vdd1 High reset-dur 3 3.4 4 ms

Wdogb output pin (Push pull structure)

Low Level Output Voltage (I

High Level Output Voltage (I

INT Pin( Push pull structure)

Low Level Output Voltage (I

High Level Output Voltage (I

HS1: 150mA High side output pin

Rdson at Tj=25°C, and Iout -150mA Ron25 2 2.5 Ohms Vsup>9V

Rdson at Ta=125°C, and Iout -150mA Ron125 4.5 Ohms Vsup>9V

Rdson at Ta=125°C, and Iout -120mA Ron125-2 3.5 5.5 Ohms 5.5<Vsup<9V

Output current limitation Ilim 160 500 mA

Over temperature Shutdown Ovt 155 190

Leakage current Ileak 10 uA

Output Clamp Voltage at Iout= -10mA Vcl -1.5 -0.3 V no inductive load drive

L0, L1, L2, L3 inputs

Negative Switching Threshold Vthn 2

Positive Switching Threshold Vthp 2.7

Hysteresis Vhyst 0.6 1.3 V 5.5V<Vsup<27

Input current Iin -10 10 uA -0.2V < Vin < 40V

Wake up Filter Time Twuf 8 20 38 us

DIGITAL INTERFACE TIMING

SPI operation frequency Freq 0.25 4 MHz

SCLK Clock Period t

SCLK Clock High Time t

SCLK Clock Low Time t

Falling Edge of CS to Rising Edge of SCLK

Falling Edge of SCLK to Rising Edge of CS

MOSI to Falling Edge of SCLK t

Falling Edge of SCLK to MOSI t

MISO Rise Time (CL = 220pF) t

MISO Fall Time (CL = 220pF) t

Time from Falling or Rising Edges of CS to:

- MISO Low Impedance

- MISO High Impedance

Time from Rising Edge of SCLK to MISO Data Valid

=1.5mA) Vol 0 0.9 V 5.5v<V

=tbd mA) Vol 0 0.9 V 1v<V

=1.5mA) Vol 0 0.9 V 1v<V

=-250uA) Voh Vdd1-0.9 Vdd1

=1.5mA) Vol 0 0.9 V

=-250uA) Voh Vdd1-0.9 Vdd1

pCLK

wSCLKH

wSCLKL

lead

lag

SISU

SIH

rSO

fSO

SOEN

SODIS

valid

Characteristics

Min Typ Max

2.5

2.7

3.5

250 N/A ns

125 N/A ns

100 N/A ns

40 N/A ns

2.5 3

3.2

3.3 4

4.2

25 50 ns

3.6

3.7

3.8

4.6

4.7

50 50

50 ns

Unit Conditions

<0.7Vdd

out

<27V

sup

<5.5V

sup

<27V

sup

°C

capability

V 5.5V<Vsup<6V

6V<Vsup<18V 18V<Vsup<27

0.2 V1=<MISO>=0.8V1, =200pF

MC33989 5

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From 5.5V to 18V and Tamb -40°C to 125°C)

sup

For all pins except CANH, CANL, Tx and Rx which are described in the CAN module section

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MC33989

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Description Symbol

STATE MACHINE TIMING note 1: delay starts at falling edge of clock cycle #8 of the SPI command and start of “Turn on” or “Turn off” of HS1 or V2.

Delay between CSB low to high transistion (at end of SPI stop command) and Stop mode activation

Interrupt low level duration Tint 7 10 13 us SBC in stop mode

Internal oscillator frequency Osc-f1 100 kHz

Internal low power oscillator frequency Osc-f2 100 kHz

Watchdog period 1 Wd1 8.58 9.75 10.92 ms Normal and standby modes

Watchdog period 2 Wd2 39.6 45 50.4 ms Normal and standby modes

Watchdog period 3 Wd3 88 100 112 ms Normal and standby modes

Watchdog period 4 Wd4 308 350 392 ms Normal and standby modes

Watchdog period accuracy F1acc -12 12 % Normal and standby modes

Normal request mode timeout NRtout 308 350 392 ms Normal request mode

Watchdog period 1 - stop Wd1stop 6.82 9.75 12.7 ms Stop mode

Watchdog period 2- stop Wd2stop 31.5 45 58.5 ms Stop mode

Watchdog period 3 - stop Wd3stop 70 100 130 ms Stop mode

Watchdog period 4 - stop Wd4stop 245 350 455 ms Stop mode

Stop mode watchdog period accuracy F2acc -30 30 % Stop mode

Cyclic sense/FWU timing 1 CSFWU1 3.22 4.6 5.98 ms Sleep and stop modes

Cyclic sense/FWU timing 2 CSFWU2 6.47 9.25 12 ms Sleep and stop modes

Cyclic sense/FWU timing 3 CSFWU3 12.9 18.5 24 ms Sleep and stop modes

Cyclic sense/FWU timing 4 CSFWU4 25.9 37 48.1 ms Sleep and stop modes

Cyclic sense/FWU timing 5 CSFWU5 51.8 74 96.2 ms Sleep and stop modes

Cyclic sense/FWU timing 6 CSFWU6 66.8 95.5 124 ms Sleep and stop modes

Cyclic sense/FWU timing 7 CSFWU7 134 191 248 ms Sleep and stop modes

Cyclic sense/FWU timing 8 CSFWU8 271 388 504 ms Sleep and stop modes

Cyclic sense On time Ton 200 350 500 us in sleep and stop modes

Cyclic sense/FWU timing accuracy Tacc -30 +30 % in sleep and stop mode

Delay between SPI command and HS1 turn on (note 1)

Delay between SPI command and HS1 turn off (note 1)

Delay between SPI and V2 turn on (note 1)

Delay between SPI and V2 turn off (note 1)

Delay between Normal Request and Normal mode, after W/D trigger command

Delay between SPI and “CAN normal mode”

Delay between SPI and “CAN sleep mode”

Tcsb-stop 18 34 us

Ts-HSon 22 us

Ts-HSoff 22 us

Ts-V2on 9 22 us Standby mode

Ts-V2off 9 22 us Normal modes

Ts-NR2N 15 35 70 us Normal request mode

Ts-CANn 10 us

Ts-CANs 10 us

Characteristics

Unit Conditions

Min Typ Max

Guaranteed by design

detected by V2 off

All modes except Sleep and Stop, guaranted by

design

Sleep and Stop modes,

guaranted by design

threshold and condition to

be added

Normal or standby mode

Vsup>9V

Normal or standby mode

Vsup>9V

SBC Normal mode

guaranteed by design

SBC Normal mode

guaranteed by design

MC33989 6

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From 5.5V to 18V and Tamb -40°C to 125°C)

sup

For all pins except CANH, CANL, Tx and Rx which are described in the CAN module section

Freescale Semiconductor, Inc.

MC33989

Description Symbol

Delay between CSB wake up (CSB low to high) and SBC normal request mode (Vdd1 on & reset high)

Delay between CSB wake up (CSB low to high) and first accepted SPI command

Delay between INT pulse and 1st SPi command accepted

CSB

Tlead

nc...

SCLK

MOSI

Undefined

Twclkh

Tw-csb 15 40 90 us SBC in stop mode

Tw-spi 90 N/A us SBC in stop mode

Ts-1stspi 20 N/A us In stop mode after wake up

Figure 2. SPI Timing characteristic

Tpclk

Twclkl

Tsi s u

Di 0

Tsi h

Don’t Care

Characteristics

Unit Conditions

Min Typ Max

Tlag

Di 8 Don’t Care

cale Semiconductor,

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Tvalid

Tsoen

MISO

Note: Incomming data at MOSI pin is sampled by the SBC at SCLK falling edge. Outcoming data at MISO pin is set by the SBC at SCLK rising edge (after Tvalid delay time).

Do 0

Do 8

Tsodis

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MC33989

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3 CAN MODULE SPECIFICATION

MAXIMUM RATING

Ratings Symbol Min Typ Max Unit

ELECTRICAL RATINGS

CANL,CANH Continuous voltage VcanH,L -27 40 V

CANL,CANH Continuous current IcanH,L 200 mA

CANH, CANL Transient voltage (Load dump, note1) VtrH,L 40 V

CANH, CANL Transient voltage (note2) VtrH,L -40 40 V

Logic Inputs (Tx, Rx) U - 0.5 6 V

ESD voltage (HBM 100pF, 1.5k), CANL, CANH Vesd-ch -4 4 kV

ESD voltage (Machine Model) CANH, CAN L Vesd-cm -200 200 V

ELECTRICAL CHARACTERISTICS

= 4,75 to 5,25; V

DD1

=5.5 to 27V; T

sup

= -40 to 125°C unless otherwise specified

amb

nc...

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Frees

Descriptions Symbol Min Typ Max Unit Conditions

Supply

Supply current of CAN cell

Supply current of CAN cell CAN in sleep state wake up enable

Supply current of CAN cell CAN in sleep state wake up disabled

CANH and CANL

Bus pins common mode voltage -27 40 V

Differential input voltage

Differential input voltage 900 mV Common mode

Differential input hysteresis (Rx) 100 mV

Ires

Idom

Isleep

Idis 1 uA V2 regulator off

Vcanh-

Vcanl

1.5 3 mA Recessive state

2 6 mA Dominant state, without

bus load

55 70 uA V2 regulator off

(guaranteed by design)

500 mV Common mode

between -3 and +7V.

Recessive state at Rx

between -3 and +7V.

Dominant state at Rx

Input resistance

Differential input resistance

Unpowered node input current 1.5 mA

CANH output voltage 2.75 4.5 V TX dominant state

CANL output voltage 0.5 2.25 V Tx dominant state

Differential output voltage 1.5 3 V Tx dominant state

CANH output voltage 3 V Tx recessive state

CANL output voltage 2 V Tx recessive state

Differential output voltage 100 mV Tx recessive state

Rin

Rind

5 100 Kohms

10 100 Kohms

8 MC33989

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Descriptions Symbol Min Typ Max Unit Conditions

CAN H output current capability Icanh -35 mA Dominant state

CAN L output current capability Icanl 35 mA Dominant state

MC33989

DEVICE DESCRIPTION

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Over temperature shutdown Tshut 160 180°C

CAN L over current detection Icanl-oc 60 200 mA Error reported in CANR

CAN H over current detection Icanh-oc -200 -60 mA Error reported in CANR

TX and RX

Tx Input High Voltage Vih 0.7 Vdd Vdd+0.4 V

Tx Input Low Voltage Vilp -0.4 0.3 Vdd V

Tx High Level Input Current, Vtx=Vdd Iih -10 10 uA

Tx Low Level Input Current, Vtx=0V Iil -100 -50 -20 uA

Rx Output Voltage High, Irx=-250uA Voh Vdd-1 V

Rx Output Voltage Low, Irx=+1mA Vol 0.5 V

Timing

Dominant State Timeout Tdout 200 360 520 us

Propagation loop delay Tx to Rx, Recessif to dominant

Propagation delay Tx to CAN

Propagation delay CAN to Rx, recessif to dominant

Propagation loop delay Tx to Rx, Dominat to recessif

Propagation delay Tx to CAN

Tlrd 70

80 100 110

Ttrd 20

60 100

Trrd 30 80 140 ns

Tldr 70

90 100 130

Ttdr 60

140 155 180 220

80 120 160

120 135 160 200

110 120 150 190

210 225 255 310

110 150 200 300

170 180 220 260

130 150 200 300

°C

ns slew rate 3

slew rate 2 slew rate 1 slew rate 0

ns slew rate 3

slew rate 2 slew rate 1 slew rate 0

ns slew rate 3

slew rate 2 slew rate 1 slew rate 0

ns slew rate 3

slew rate 2 slew rate 1 slew rate 0

Propagation delay CAN to Rx, dominant to recessif

Non differential slew rate (CanL or CanH)

note 1: Load dump test according to ISO7637 part 1 note 2: Transient test according to ISO7637 part 1, pulses 1,2,3a and 3b, according to schematic figure below. note 3: Human Body Model; C=100pF, R=1.5Kohms note 4: Machine Model; C=200pF, R=25ohms

Trdr 20 40 60 ns

Tsl 3 Tsl 2 Tsl 1 Tsl 0

4 3 2 1

13.5 8 5

40 20 15 10

V/us slew rate 3

slew rate 2 slew rate 1 slew rate 0

MC33989 9

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Figure 3. Transient test pulses for CANH and CANL

1nF

CAN H

CAN L

Gnd

note: Waveform in accordance to ISO7637 part1, test pulses 1, 2, 3a and 3b.

nc...

1nF

Figure 4. Transceiver AC characteristics

MC33989

DEVICE DESCRIPTION

Transient Pulse

Generator

(note)

Gnd

cale Semiconductor,

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3.1 CAN error detection and wake up

The error and the wake up are reported in the CANR register.

3.1.1 Dominant State Time-out

This protection is based on the fact that all CAN signals can not have more than five bits in a row with the same state. In case of a condition the Tx pin is stuck at 0v, the transceiver would hold the bus in dominant state making it impossible to the others CAN modules to use the bus. The protection acts releasing the bus when a dominant signal with more than 350uS typical (

time)

is present in the Tx signal. After entering the fault condition the driver is disabled. To clear this disabled state the CAN

transceiver needs to have its input going to recessive state.

3.1.2 Internal Error output flags

There are internal error flags to signals when one of the below condition happens. The errors are reported in CAN register.

• Thermal protection activated (bit THERM)

• Over Current detection in CANL or CANH pins (bit CUR).

• Time-out condition for dominant state (bit TXF).

3.1.3 Sleep mode & Wake-up via CAN bus feature

The HSCAN interface enters in a low consumption mode when the “CAN sleep mode” is enabled. In this mode the HSCAN module will have a 60uA consumption via internal 5V.

When in sleep mode the transmitter and the receiver are disabled, the only part of circuit which remains working is the wake up module which contains a special low power receiver to check the bus lines and according to its activity generate a wake up output signal. The conditions for the wake is meet when there are 3 valid pulses in a row. A valid signal must have a pulse width bigger than 0.5us and no more than 0.5ms.

Tdout

MC33989 10

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