MOTOROLA SCM6800 User Manual



Freescale Semiconductor, Inc.

EC000 Core Processor

nc...
, I

or

emiconduct

eescale S
Fr

(SCM68000)

User’s Manual

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different
applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not
convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems
intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola
product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims,
costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are
registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

MOTOROLA, 1995

For More Information On This Product,

Go to: www.freescale.com

µ

nc...
, I

Freescale Semiconductor, Inc.

68K FAX-IT

Documentation Comments

FAX [phone]—Documentation Comments Only

The Motorola High-Performance Embedded Systems Technical Communications Depart­ment provides a fax number for you to submit any questions or comments about this docu­ment or how to order other documents. We welcome your suggestions for improving our
documentation. Please do not fax technical questions.

Please provide the part number and revision number (located in upper right-hand corner of
the cover) and the title of the document. When referring to items in the manual, please ref­erence by the page number, paragraph number, figure number, table number, and line num­ber if needed.

or

emiconduct

eescale S
Fr

When sending a fax, please provide your name, company, fax number, and phone number
including area code.

Applications and Technical Information

For questions or comments pertaining to technical information, questions, and applications,
please contact one of the following sales offices nearest you.

MOTOROLA

EC000 CORE PROCESSOR USER’S MANUAL

For More Information On This Product,

Go to: www.freescale.com

iii

iv

Freescale Semiconductor, Inc.

— Sales Offices —

Field Applications Engineering Available Through All Sales Offices

nc...
, I

or

emiconduct

eescale S
Fr

ALABAMA , Huntsville [phone]

UNITED STATES

ARIZONA , Tempe [phone]
CALIFORNIA , Agoura Hills [phone]
CALIFORNIA , Los Angeles [phone]
CALIFORNIA , Irvine [phone]
CALIFORNIA , Rosevllle [phone]
CALIFORNIA , San Diego [phone]
CALIFORNIA , Sunnyvale [phone]
COLORADO , Colorado Springs [phone]
COLORADO , Denver [phone]
CONNECTICUT , Wallingford [phone]
FLORIDA , Maitland [phone]
FLORIDA , Pompano Beach/

Fort Lauderdale [phone]

FLORIDA , Clearwater [phone]
GEORGlA , Atlanta [phone]
IDAHO , Boise [phone]
ILLINOIS , Chicago/Hoffman Estates [phone]
INDlANA , Fort Wayne [phone]
INDIANA , Indianapolis [phone]
INDIANA , Kokomo [phone]
IOWA , Cedar Rapids [phone]
KANSAS , Kansas City/Mission [phone]
MARYLAND , Columbia [phone]
MASSACHUSETTS , Marborough [phone]
MASSACHUSETTS , Woburn [phone]
MICHIGAN , Detroit [phone]
MINNESOTA , Minnetonka [phone]
MISSOURI , St. Louis [phone]
NEW JERSEY , Fairfield [phone]
NEW YORK , Fairport [phone]
NEW YORK , Hauppauge [phone]
NEW YORK , Poughkeepsie/Fishkill [phone]
NORTH CAROLINA , Raleigh [phone]
OHIO , Cleveland [phone]
OHIO , Columbus/Worthington [phone]
OHIO , Dayton [phone]
OKLAHOMA , Tulsa [phone]
OREGON , Portland [phone]
PENNSYLVANIA , Colmar [phone]

Philadelphia/Horsham [phone]

TENNESSEE , Knoxville [phone]
TEXAS , Austin [phone]
TEXAS , Houston [phone]
TEXAS , Plano [phone]
VIRGINIA , Richmond [phone]
WASHINGTON , Bellevue [phone]

Seattle Access [phone]

WISCONSIN , Milwaukee/Brookfield [phone]
BRITISH COLUMBIA , Vancouver [phone]

ONTARIO , Toronto [phone]
ONTARIO , Ottawa [phone]
QUEBEC , Montreal [phone]

AUSTRALIA , Melbourne (61-3)887-0711
AUSTRALIA , Sydney (61(2)906-3855
BRAZIL , Sao Paulo 55(11)815-4200
CHINA , Beijing 86 505-2180
FINLAND , Helsinki 358-0-35161191

Car Phone [phone]

FRANCE , Paris/Vanves 33(1)40 955 900

CANADA

INTERNATIONAL

GERMANY , Langenhagen/ Hanover 49(511)789911
GERMANY , Munich 49 89 92103-0
GERMANY , Nuremberg 49 911 64-3044
GERMANY , Sindelfingen 49 7031 69 910
GERMANY , Wiesbaden 49 611 761921
HONG KONG , Kwai Fong 852-4808333

Tai Po 852-6668333

INDIA , Bangalore (91-812)627094
ISRAEL , Tel Aviv 972(3)753-8222
ITALY , Milan 39(2)82201
JAPAN , Aizu 81(241)272231
JAPAN , Atsugi 81(0462)23-0761
JAPAN , Kumagaya 81(0485)26-2600
JAPAN , Kyushu 81(092)771-4212
JAPAN , Mito 81(0292)26-2340
JAPAN , Nagoya 81(052)232-1621
JAPAN , Osaka 81(06)305-1801
JAPAN, Sendai 81(22)268-4333
JAPAN,
JAPAN,
JAPAN
KOREA , Pusan 82(51)4635-035
KOREA , Seoul 82(2)554-5188

MALAYSIA , Penang 60(4)374514
MEXICO , Mexico City 52(5)282-2864
MEXICO , Guadalajara 52(36)21-8977

Marketing 52(36)21-9023
Customer Service 52(36)669-9160

NETHERLANDS , Best (31)49988 612 11
PUERTO RICO , San Juan [phone]
SINGAPORE
SPAIN , Madrid 34(1)457-8204

or 34(1)457-8254

SWEDEN , Solna 46(8)734-8800
SWITZERLAND , Geneva 41(22)7991111
SWITZERLAND , Zurich 41(1)730 4074
TAlWAN , Taipei 886(2)717-7089
THAILAND , Bangkok (66-2)254-4910
UNITED KINGDOM , Aylesbury 44(296)395-252

COLORADO , Grand Junction

Cheryl Lee Whltely [phone]

KANSAS , Wichita

Melinda Shores/Kelly Greiving [phone]

NEVADA , Reno

Galena Technology Group [phone]

NEW MEXICO , Albuquerque

S&S Technologies, lnc. [phone]

UTAH , Salt Lake City

Utah Component Sales, Inc. [phone]

WASHINGTON , Spokane

Doug Kenley [phone]

ARGENTINA , Buenos Aires

Argonics, S.A. [phone]
Elmo Semiconductor [phone]

Minco Technology Labs Inc. [phone]
Semi Dice Inc. [phone]

Tachikawa 81(0425)23-6700
Tokyo 81(03)3440-3311

, Yokohama 81(045)472-2751

(65)2945438

FULL LINE REPRESENTATIVES

HYBRID COMPONENTS RESELLERS

EC000 CORE PROCESSOR USER’S MANUAL

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

Freescale Semiconductor, Inc.

PREFACE

The

EC000 Core Processor User's Manual

operation of the SCM68000 (EC000 core); the

Manual

vides a brief description of the FlexCore program.
The organization of this manual is as follows:

provides instruction details for the EC000 core; and the

Section 1 Overview
Section 2 Signal Description
Section 3 Bus Operation
Section 4 Exception Processing
Section 5 8-Bit Instruction Execution Times

describes the programming, capabilities, and

MC68000 Family Programmer’s Reference

FlexCore Product Brief

pro-

nc...
, I

or

emiconduct

eescale S
Fr

Section 6 16-Bit Instruction Execution Times
Section 7 Electrical Characteristics

TRADEMARKS

• Composer, Verilog, Verifault, and Veritime are trademarks of Cadence Design Sys­tems, Inc.

• Synopsys is a registered trademark of Synopsys, Inc.

• TDS is a registered trademark of Summit Design, Inc.

MOTOROLA

EC000 CORE PROCESSOR USER’S MANUAL

For More Information On This Product,

Go to: www.freescale.com

v

Freescale Semiconductor, Inc.

nc...
, I

or

emiconduct

eescale S
Fr

vi EC000 CORE PROCESSOR USER’S MANUAL MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

TABLE OF CONTENTS

Section 1
Overview

1.1 FlexCore Integrated Processors...................................................................1-2

1.1.1 FlexCore Advantages .................................................................................1-4

1.1.2 FlexCore Module Types..............................................................................1-4

1.2 Development Cycle.......................................................................................1-5

1.3 Programming Model......................................................................................1-7

1.4 Data Types and Addressing Modes..............................................................1-9

nc...
, I

or

1.5 Data Organization.......................................................................................1-10

1.5.1 Data Registers..........................................................................................1-10

1.5.2 Address Registers ....................................................................................1-10

1.5.3 Data Organization In Memory...................................................................1-10

1.6 Instruction Set Summary.............................................................................1-11

emiconduct

eescale S
Fr

Section 2

Signal Description

2.1 Address Bus (A31–A0) .................................................................................2-1

2.2 Data Bus (D15–D0).......................................................................................2-1

2.3 Clock (CLKI, CLKO)......................................................................................2-1

2.4 Asynchronous Bus Control ...........................................................................2-3

2.4.1 Address Strobe (ASB) ................................................................................2-3

2.4.2 Read/Write (RWB) and Early Read/Write (ERWB).....................................2-3

2.4.3 Upper and Lower Data Strobes (UDSB, LDSB), and Data Strobe (DSB) ..2-4

2.4.4 Data Transfer Acknowledge (DTACKB) .....................................................2-4

2.4.5 Data Transfer Size (SIZ1–SIZ0) .................................................................2-4

2.4.6 Read-Modify-Write (RMCB)........................................................................2-5

2.5 Bus Arbitration Control..................................................................................2-5

2.5.1 Bus Request (BRB) ....................................................................................2-5

2.5.2 Bus Grant (BGB).........................................................................................2-5

2.5.3 Bus Grant Acknowledge (BGACKB)—3-Wire Protocol Only......................2-5

2.6 Interrupt Control (IPLB2–IPLB0)...................................................................2-5

2.7 System Control .............................................................................................2-6

2.7.1 Bus Error (BERRB).....................................................................................2-6

2.7.2 Reset External/Internal (RESETIB, RESETOB) .........................................2-6

2.7.3 Halt External/Internal (HALTIB, HALTOB)..................................................2-6

2.7.4 Mode (MODE).............................................................................................2-7

2.7.5 Disable Control (DISB) ...............................................................................2-7

2.7.6 Test Mode (TEST) ......................................................................................2-7

2.7.7 Test Clock (TESTCLK) ...............................................................................2-7

2.7.8 Autovector (AVECB)...................................................................................2-8

MOTOROLA

EC000 CORE PROCESSOR USER’S MANUAL

For More Information On This Product,

Go to: www.freescale.com

vii

Table of Contents

2.8 Three-State Control...................................................................................... 2-8

2.8.1 Address Output Enable (AOEB).................................................................2-8

2.8.2 Control Output Enable (COEB) ..................................................................2-8

2.8.3 Data Output Enable (DOEB) ......................................................................2-8

2.9 Processor Status ..........................................................................................2-8

2.9.1 Function Codes (FC2–FC0) .......................................................................2-8

2.9.2 Address Three-State Control (TSCAE) ......................................................2-9

2.9.3 Stop Instruction Indicator (STOP)...............................................................2-9

2.9.4 Interrupt Pending (IPENDB) ....................................................................... 2-9

2.9.5 CPU Pipe Refill (REFILLB).........................................................................2-9

2.9.6 Microsequencer Status Indication (STATUSB) ..........................................2-9

2.10 Multiplexing Pins...........................................................................................2-9

nc...

Freescale Semiconductor, Inc.

Section 3

Bus Operation

, I
or

emiconduct

eescale S
Fr

3.1 Data Transfer Operations............................................................................. 3-1

3.1.1 Read Cycle.................................................................................................3-2

3.1.2 Write Cycle .................................................................................................3-8

3.1.3 Read-Modify-Write Cycle..........................................................................3-13

3.2 Bus Arbitration............................................................................................3-17

3.2.1 Requesting the Bus .................................................................................. 3-18

3.2.2 Receiving the Bus Grant...........................................................................3-18

3.2.3 Acknowledgment of Mastership (3-Wire Bus Arbitration Only).................3-19

3.3 Bus Arbitration Control................................................................................ 3-22

3.4 Bus Error and Halt Operation .....................................................................3-30

3.4.1 Bus Error Operation..................................................................................3-30

3.4.2 Retrying the Bus Cycle.............................................................................3-32

3.4.3 Halt Operation ..........................................................................................3-32

3.4.4 Double Bus Fault......................................................................................3-35

3.5 Asynchronous Operation............................................................................3-35

3.6 Synchronous Operation..............................................................................3-38

3.7 The Relationship of DTACKB, BERRB, and HALTIB.................................3-42

Section 4

Exception Processing

4.1 Privilege Modes............................................................................................ 4-1

4.1.1 Supervisor Mode ........................................................................................4-2

4.1.2 User Mode..................................................................................................4-2

4.1.3 Privilege Mode Changes ............................................................................4-2

4.1.4 Reference Classification............................................................................. 4-3

4.1.5 CPU Space Cycle....................................................................................... 4-3

4.1.5.1 Interrupt Acknowledge Cycle.................................................................... 4-3

4.1.5.2 Autovectored Interrupt Acknowledge Cycle .............................................4-7

4.2 Exception Processing Description..............................................................4-11

4.2.1 Exception Vectors.....................................................................................4-11

viii

EC000 CORE PROCESSOR USER’S MANUAL

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

nc...
, I

or

4.2.2 Kinds of Exceptions ..................................................................................4-13

4.2.3 Multiple Exceptions...................................................................................4-13

4.2.4 Exception Stack Frames...........................................................................4-14

4.2.5 Exception Processing Sequence..............................................................4-14

4.3 Processing of Specific Exceptions..............................................................4-15

4.3.1 Reset ........................................................................................................4-15

4.3.1.1 Reset Operation .....................................................................................4-16

4.3.1.1.1 Reset Using RESETIB and HALTIB.....................................................4-16

4.3.1.1.2 Reset Instruction...................................................................................4-16

4.3.1.1.3 Reset Using Only RESETIB.................................................................4-17

4.3.1.2 Initializing the SCM68000 for Simulation................................................4-18

4.3.2 Interrupts...................................................................................................4-19

4.3.2.1 Level Seven Interrupts............................................................................4-20

4.3.2.2 Uninitialized Interrupt..............................................................................4-20

4.3.2.3 Spurious Interrupt...................................................................................4-20

4.3.3 Instruction Traps.......................................................................................4-21

4.3.4 Illegal and Unimplemented Instructions....................................................4-21

4.3.5 Privilege Violations ...................................................................................4-21

4.3.6 Tracing......................................................................................................4-22

4.3.7 Bus Error...................................................................................................4-22

4.3.8 Address Error............................................................................................4-23

Freescale Semiconductor, Inc.

Table of Contents

emiconduct

eescale S
Fr

Section 5

8-Bit Instruction Execution Times

5.1 Operand Effective Address Calculation Times .............................................5-1

5.2 MOVE Instruction Execution Times..............................................................5-2

5.3 Standard Instruction Execution Times..........................................................5-3

5.4 Immediate Instruction Execution Times........................................................5-4

5.5 Single Operand Instruction Execution Times................................................5-5

5.6 Shift/Rotate Instruction Execution Times......................................................5-6

5.7 Bit Manipulation Instruction Execution Timess .............................................5-6

5.8 Conditional Instruction Execution Times.......................................................5-6

5.9 JMP, JSR, LEA, PEA, and MOVEM Instruction Execution Times................5-7

5.10 Multiprecision Instruction Execution Times...................................................5-7

5.11 Miscellaneaous Instruction Execution Times................................................5-8

5.12 Exception Processing Execution Times........................................................5-9

Section 6

16-Bit Instruction Execution Times

6.1 Operand Effective Address Calculation Times .............................................6-1

6.2 MOVE Instruction Execution Times..............................................................6-2

6.3 Standard Instruction Execution Times..........................................................6-3

6.4 Immediate Instruction Execution Times........................................................6-4

6.5 Single Operand Instruction Execution Times................................................6-5

6.6 Shift/Rotate Instruction Execution Times......................................................6-6

MOTOROLA

EC000 CORE PROCESSOR USER’S MANUAL

For More Information On This Product,

Go to: www.freescale.com

ix

nc...
, I

or

x

Table of Contents

6.7 Bit Manipulation Instruction Execution Times...............................................6-6

6.8 Conditional Instruction Execution Times....................................................... 6-7

6.9 JMP, JSR, LEA, PEA, and MOVEM Instruction Execution Times................6-7

6.10 Multiprecision Instruction Execution Times................................................... 6-7

6.11 Miscellaneous Instruction Execution Times..................................................6-8

6.12 Exception Processing Execution Times........................................................ 6-9

7.1 Maximum Ratings.........................................................................................7-1

7.2 CMOS Considerations..................................................................................7-1

7.3 Power Consumption .....................................................................................7-1

7.4 AC Electrical Specification Definitions..........................................................7-1

7.5 AC Electrical Specifications—Clock Timing.................................................. 7-2

7.6 AC Electrical Specifications—Read and Write Cycles.................................. 7-2

7.7 AC Electrical Specifications—SCM68000 to External Peripherals...............7-6

7.8 AC Electrical Specifications—Bus Arbitration............................................... 7-7

7.9 AC Electrical Specifications—Core Applications Signals ...........................7-11

Freescale Semiconductor, Inc.

Section 7

Electrical Characteristics

emiconduct

eescale S
Fr

EC000 CORE PROCESSOR USER’S MANUAL

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

Freescale Semiconductor, Inc.

LIST OF ILLUSTRATIONS

1-1 FlexCore Integrated Processor Typical Die Layout............................................1-3

1-2 Standard Cell Design Flow.................................................................................1-6

1-3 Programming Model...........................................................................................1-7

1-4 Status Register...................................................................................................1-8

1-5 Word Organization in Memory..........................................................................1-10

1-6 Data Organization in Memory...........................................................................1-12

2-1 Input/Output Signals...........................................................................................2-2

3-1 Word Read Cycle Flowchart for 16-Bit Mode.....................................................3-2

nc...
, I

or

emiconduct

eescale S
Fr

3-2 Byte Read Cycle Flowchart for 8-Bit Mode ........................................................3-3

3-3 Byte Read Cycle Flowchart for 16-Bit Mode ......................................................3-3

3-4 Read and Write Cycle Timing Diagram for 8-Bit Mode ......................................3-4

3-5 Read and Write Cycle Timing Diagram for 16-Bit Mode ....................................3-5

3-6 Word and Byte Read Cycle Timing Diagram for 16-Bit Mode............................3-6

3-7 Word Write Cycle Flowchart for 16-Bit Mode.....................................................3-8

3-8 Byte Write Cycle Flowchart for 8-Bit Mode.........................................................3-9

3-9 Byte Write Cycle Flowchart for 16-Bit Mode.......................................................3-9

3-10 Write Cycle Timing Diagram for 8-Bit Mode.....................................................3-10

3-11 Word and Byte Write Cycle Timing Diagram for 16-Bit Mode..........................3-11

3-12 Read-Modify-Write Cycle Flowchart.................................................................3-13

3-13 Read-Modify-Write Cycle Timing Diagram.......................................................3-14

3-14 3-Wire Bus Arbitration Cycle Flowchart............................................................3-18

3-15 2-Wire Bus Arbitration Cycle Flowchart............................................................3-19

3-16 3-Wire Bus Arbitration Timing Diagram............................................................3-20

3-17 2-Wire Bus Arbitration Timing Diagram............................................................3-21

3-18 Bus Arbitration Unit State Diagrams.................................................................3-23

3-19 3-Wire Bus Arbitration Timing Diagram—SCM68000 Active ...........................3-24

3-20 3-Wire Bus Arbitration Timing Diagram—Bus Inactive.....................................3-25

3-21 3-Wire Bus Arbitration Timing Diagram—Special Case...................................3-26

3-22 2-Wire Bus Arbitration Timing Diagram—SCM68000 Active ...........................3-27

3-23 2-Wire Bus Arbitration Timing Diagram—Bus Inactive.....................................3-28

3-24 2-Wire Bus Arbitration Timing Diagram—Special Case...................................3-29

3-25 Bus Error Timing Diagram................................................................................3-31

3-26 Retry Bus Cycle Timing Diagram.....................................................................3-33

3-27 Halt Operation Timing Diagram........................................................................3-34

3-28 External Asynchronous Signal Synchronization...............................................3-35

3-29 Fully Asynchronous Read Cycle ......................................................................3-36

3-30 Fully Asynchronous Write Cycle.......................................................................3-36

3-31 Pseudo-Asynchronous Read Cycle..................................................................3-37

3-32 Pseudo-Asynchronous Write Cycle..................................................................3-38

MOTOROLA

EC000 CORE PROCESSOR USER’S MANUAL

For More Information On This Product,

Go to: www.freescale.com

xi

nc...
, I

or

emiconduct

List of Illustrations

3-33 Synchronous Read Cycle................................................................................. 3-39

3-34 Synchronous Write Cycle.................................................................................3-40

4-1 CPU Space Address Encoding..........................................................................4-3

4-2 Interrupt Acknowledge Cycle Timing Diagram...................................................4-4

4-3 Autovector Operation Timing Diagram...............................................................4-8

4-4 Autovector Operation Timing Diagram—Best Case........................................... 4-9

4-5 Autovector Operation Timing Diagram—Worst Case ......................................4-10

4-6 Exception Vector Format.................................................................................. 4-11

4-7 Address Translated from 8-Bit Vector Number................................................4-11

4-8 Interrupt Vector Number Format......................................................................4-13

4-9 Groups 1 and 2 Exception Stack Frame..........................................................4-15

4-10 Reset Circuit..................................................................................................... 4-16

4-11 Reset Operation Timing Diagram..................................................................... 4-17

4-12 RESETOB Timing Diagram.............................................................................. 4-18

4-13 Initialization of the SCM68000 for Simulation Timing Diagram........................4-19

4-14 Supervisor Stack Order for Bus or Address Error Exception...........................4-23

7-1 Clock Input Timing Diagram...............................................................................7-2

7-2 Read Cycle Timing Diagram..............................................................................7-4

7-3 Write Cycle Timing Diagram ..............................................................................7-5

7-4 SCM68000 to External Peripherals Timing Diagram .........................................7-6

7-5 Bus Arbitration Timing Diagram.........................................................................7-7

7-6 Bus Arbitration Timing Diagram—Idle Bus Case...............................................7-8

7-7 Bus Arbitration Timing Diagram—Active Bus Case...........................................7-9

7-8 Bus Arbitration Timing Diagram—Multiple Bus Request.................................. 7-10

7-9 Core Application Signals Timing Diagram........................................................ 7-12

Freescale Semiconductor, Inc.

eescale S
Fr

xii

EC000 CORE PROCESSOR USER’S MANUAL

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

Freescale Semiconductor, Inc.

LIST OF TABLES

1-1 Data Addressing Modes.....................................................................................1-9

1-2 Notational Conventions....................................................................................1-13

1-3 Instruction Set Summary..................................................................................1-14

2-1 Signal Summary.................................................................................................2-2

2-2 Upper and Lower Data Strobe Control of Data Bus...........................................2-4

2-3 Lower Data Strobe Control of Data Bus.............................................................2-4

2-4 Data Transfer Size .............................................................................................2-5

2-5 Interrupt Levels and Mask Values......................................................................2-6

2-6 Function Code Outputs ......................................................................................2-8

nc...
, I

or

emiconduct

eescale S
Fr

2-7 Status Indication Exceptions..............................................................................2-9

2-8 Pin Multiplexing Priority....................................................................................2-10

3-1 DTACKB, BERRB, and HALTIB Assertion Results..........................................3-43

3-2 BERRB and HALTIB Negation Results............................................................3-44

4-1 Reference Classification.....................................................................................4-3

4-2 Exception Vector Assignment ..........................................................................4-12

4-3 Exception Grouping and Priority.......................................................................4-14

5-1 Effective Address Calculation Times..................................................................5-2

5-2 Move Byte Instruction Execution Times.............................................................5-2

5-3 Move Word Instruction Execution Times............................................................5-3

5-4 Move Long Instruction Execution Times ............................................................5-3

5-5 Standard Instruction Execution Times................................................................5-4

5-6 Immediate Instruction Execution Times .............................................................5-5

5-7 Single Operand Instruction Execution Times.....................................................5-5

5-8 Shift/Rotate Instruction Execution Times ...........................................................5-6

5-9 Bit Manipulation Instruction Execution Times.....................................................5-6

5-10 Conditional Instruction Execution Times............................................................5-7

5-11 JMP, JSR, LEA, PEA, and MOVEM Instruction Execution Times......................5-7

5-12 Multiprecision Instruction Execution Times........................................................5-8

5-13 Miscellaneous Instruction Execution Times .......................................................5-8

5-14 Move Peripheral Instruction Execution Times....................................................5-9

5-15 Exception Processing Execution Times.............................................................5-9

6-1 Effective Address Calculation Times..................................................................6-2

6-2 Move Byte and Word Instruction Execution Times.............................................6-2

6-3 Move Long Instruction Execution Times ............................................................6-3

6-4 Standard Instruction Execution Times................................................................6-4

6-5 Immediate Instruction Execution Times .............................................................6-5

6-6 Single Operand Instruction Execution Times.....................................................6-5

6-7 Shift/Rotate Instruction Execution Times ...........................................................6-6

6-8 Bit Manipulation Instruction Execution Times.....................................................6-6

6-9 Conditional Instruction Execution Times............................................................6-7

MOTOROLA

EC000 CORE PROCESSOR USER’S MANUAL

For More Information On This Product,

Go to: www.freescale.com

xiii

List of Tables

6-10 JMP, JSR, LEA, PEA, and MOVEM Instruction Execution Times .....................6-7

6-11 Multiprecision Instruction Execution Times........................................................6-8

6-12 Miscellaneous Instruction Execution Times.......................................................6-8

6-13 Move Peripheral Instruction Execution Times....................................................6-9

6-14 Exception Processing Execution Times.............................................................6-9

Freescale Semiconductor, Inc.

nc...
, I

or

emiconduct

eescale S
Fr

xiv

EC000 CORE PROCESSOR USER’S MANUAL

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

Freescale Semiconductor, Inc.

SECTION 1
OVERVIEW

nc...
, I

or

emiconduct

eescale S

This document contains a summary of the use and operation of the SCM68000 micropro­cessor core (also referred to as the EC000 core)
specifications. Refer to the
(M68000UM/AD) for detailed information on the operation of the instruction set, addressing
modes, and bus architecture for this core.

The SCM68000 is a core implementation of the MC68000 32-bit microprocessor and is
designed to be used as part of the FlexCore Program. In the FlexCore program, high-volume
manufacturers can create their own integrated microprocessor containing a core processor,
such as the SCM68000, and their own proprietary technology. A FlexCore integrated pro­cessor allows significant reductions in component count, power consumption, board space,
and cost while yielding much higher system reliability and performance.

The main features of the SCM68000 include:

• Low-Power HCMOS Implementation Requires Only 15 mA at 3.3 V

• 32-Bit Performance for 16-Bit Applications—2.7 MIPS at 16 MHz

• Statically Selectable 8-Bit or 16-Bit Data Bus Operation

• 32-Bit Address Bus Directly Addresses up to 4 Gbytes of Address Space

• Static Operation Provides Almost Zero Power Consumption During Idle Periods

• Sixteen General-Purpose 32-Bit Data and Address Registers

• Fifty-Six Powerful Instruction Types That Support High-Level Programming Languages

• Fourteen Addressing Modes and Five Main Data Types Allow Compact, Efficient Code

• Seven Priority Level Interrupt Control

M68000 8-/16-/32-Bit Microprocessor User’s Manual

1

and a detailed set of timing and electrical

Fr

• Special Core Interfacing Signals

• Emulation Support Signals Including Pipeline Refill, Processor Status, and Interrupt
Pending Signals

• Both 3.3-V and 5-V Operation

The SCM68000 has a statically selectable 8-bit or 16-bit data bus. The address bus is 32­bits wide and may be used as either a 24-bit address bus as on the MC68000 microproces­sors, or as a 32-bit address bus to fully support the internal architecture. The 32-bit address

1.

The SCM68000 is the name of the Verilog model for the EC000 core. The remainder of this section

will refer to the EC000 core as only the SCM68000.

MOTOROLA

EC000 CORE PROCESSOR USER’S MANUAL

For More Information On This Product,

Go to: www.freescale.com

1-1



Overview

bus allows direct addressing of up to 4 Gbytes. Logic can be added to implement dynamic
bus sizing.

The SCM68000 is upward code compatible with all other members of the M68000 micropro­cessor family. Any user-mode programs using the SCM68000 instruction set will run
unchanged on any MC680x0, MC68EC0x0, or MC683xx processor. This is possible
because the user programming model is identical for all processors and the instruction sets,
addressing modes, and data types for the SCM68000 are proper subsets of the complete
architecture.

The SCM68000 also includes some functions not found on the standard MC68000 and
MC68EC000 microprocessors such as the processor status, pipeline refill, and interrupt
pending signals. These signals permit emulation support and facilitate interfacing between
the SCM68000 and on-chip logic.

Freescale Semiconductor, Inc.

1.1 FLEXCORE INTEGRATED PROCESSORS

nc...
, I

or

emiconduct

eescale S
Fr

FlexCore allows designers of high-volume digital systems and third-party technology provid­ers to place their proprietary circuitry on chip with a Motorola microprocessor. By using Flex­Core, a designer can reduce the total system cost, component count, and power
consumption while providing higher performance and greater reliability. Up to 100,000 gates
or more of custom logic, memory, and peripheral modules can be added to a core processor
to produce the most cost-effective solution for a designer's system. The core processors
provide special power-management features such as 5 V, 3.3 V, and static operation. The
68000 Family of core processors offers the designer a range of performance from 3 to 12
million instructions per second (MIPS) (to be extended to 100 MIPS) while maintaining com­plete code compatibility throughout the Family. The 68000 processors have a proven archi­tecture with a broad base of application and system software support, including real-time
kernels, operating systems, and compilers, in addition to a wide range of tools to support
software development. In the future, additional processing architectures will be included in
the FlexCore program, including PowerPC
1 shows a typical die layout for a FlexCore integrated processor.

Complete product lines can be created using FlexCore by implementing one base design
using a variety of core processors. Designers already familiar with 68000 Family design can
easily migrate to FlexCore processors as the core processors use the same bus interfaces
found on the standard 68000 Family members. Additionally, many peripheral modules and
memory elements are available for integration. Motorola has developed a complete design
system to put into the hands of the customer that includes both a broad cell-based library
and effective computer-aided design (CAD) tools. By building on Motorola's proven 68000
microprocessor architecture and superior manufacturing capabilities, FlexCore offers
designers the best path to higher system integration.

and digital signal processing (DSP). Figure 1-

1-2

EC000 CORE PROCESSOR USER’S MANUAL

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

Freescale Semiconductor, Inc.

Overview

nc...
, I

or

CUSTOMER-DESIGNED 

LOGIC

SPECIAL-FUNCTION 

BLOCK/

MEMORY BLOCK

SPECIAL-FUNCTION 

BLOCK/

MEMORY BLOCK



68000 FAMILY

PROCESSOR

Figure 1-1. FlexCore Integrated Processor Typical Die Layout

FlexCore custom processors are ideal for:

• High-volume users of 8-, 16-, and 32-bit integrated solutions requiring higher system
performance whose needs are not met by standard 68300 Family devices.

• Designers of high-volume applications who need to reduce cost, space, and/or power
consumption.

• Third-party technology providers who want to deliver their proprietary application-spe­cific technology to a worldwide marketplace.

emiconduct

To develop a solution that best suits system requirements in the shortest time frame, inte­grated processor design is performed by the designer using a methodology created, tested,
and documented by Motorola. The resulting netlist is then laid out by Motorola, verified, and
fabricated in silicon. This enables FlexCore integrated processors to be produced quickly
and cost-effectively, with the resulting device containing all features needed for the system.

To implement the application-specific logic, the designer uses Motorola's standard cell
library. This library offers an extensive range of design elements, memory configurations,

eescale S

and an expanding array of peripheral modules. Each cell in the library has been designed
for optimum size and performance. The added flexibility of high-speed, high-density cells

Fr

allows the designer to achieve the most cost-effective solution while satisfying critical timing
requirements. The standard cell library has been thoroughly characterized and maintained
to ensure a smooth transition from a simulated design to working silicon. A custom part may
also become a standard product if both Motorola and the customer desire to do so. Standard
products are sold on the open market, allowing costs to be spread over additional units,
resulting in lower component prices for high-volume users.

Third-party technology providers can use the same methodology to combine their applica­tion-specific systems expertise with a core processor. The resulting device is manufactured
by Motorola and can be delivered to the marketplace through either the technologist’s or
Motorola’s marketing and sales channels.

MOTOROLA

EC000 CORE PROCESSOR USER’S MANUAL

For More Information On This Product,

Go to: www.freescale.com

1-3

Overview

Freescale Semiconductor, Inc.

1.1.1 FlexCore Advantages

Developers face tough challenges in reducing product cost. By incorporating user-designed
logic and Motorola-supplied functions into a single FlexCore processor, a system designer
can realize significant savings in cost, power consumption, board space, and pin count. The
equivalent functionality can easily require 20 separate components. Each component might
have 16–64 pins, totaling over 350 connections. Each connection is a candidate for a bad
solder joint or misrouted trace. Each component is another part to qualify, purchase, inven­tory, and maintain. Each component requires a share of the printed circuit board. Each com­ponent draws power—often to drive large buffers and circuit board traces to get signals to
another chip. Each component must be individually placed and attached to a printed circuit
board. The signals between the core processor unit and a peripheral might not be compat­ible nor run from the same clock, requiring time delays or other special design consider­ations.

In a FlexCore integrated processor, the major functions and glue logic are all properly con­nected internally, timed with the same clock, and fully tested. Only essential signals are

nc...
, I

brought out to pins. The processor is assembled in a surface-mount package for the small­est possible footprint.

or

emiconduct

eescale S
Fr

1.1.2 FlexCore Module Types

The three types of FlexCore modules are:

• Hard Module
—Not alterable
—Laid out
—Has a tech file
—Has a defined test scheme

• Soft Module
—Netlist
—Not alterable other than by clock tree insertion
—Not laid out
—Has a defined test scheme
—Simulation test fixture

• Parameterizable
—Alterable via insertion of predefined parameters
—Behavioral model
—Definition of parameters defines test scheme
—Customer selects parameter values and Motorola synthesizes the design

The SCM68000 core processor is available as a hard module.

1-4

EC000 CORE PROCESSOR USER’S MANUAL

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

nc...
, I

or

Freescale Semiconductor, Inc.

Overview

1.2 DEVELOPMENT CYCLE

There are several steps that must be followed in order to create a FlexCore integrated mi­croprocessor with an SCM68000. Figure 1-2 illustrates the standard cell design flow and the
tools required to complete each step. These steps include:

• Convert Design to Standard Cells Design—Begin by implementing the required system
functions with an SCM68000, peripherals, memory blocks, and cells from the Motorola
standard cell library.

• Capture Design on Workstation—Use the engineering workstation to capture the logic
schematic of cells and their interconnections.

• Logic Synthesis—The structural level description of the design is mapped to a more ef­ficient structural description, which is accomplished by converting the Boolean equa­tions for the design to a two-level sum of products representation and minimized.

• Generate Test Patterns—The stimulus and test patterns for the design are generated
for the functional simulation.

• Functional Simulation—Ensure that the logic of the schematic is functionally sound by
using Verilog, the encrypted C models and synthesis models provided by Motorola. No
timing information is yet associated with the simulations, and all propagation delays are
preset to 1 ns.

emiconduct

eescale S
Fr

• Calculate Node Delays— Motorola software (mdaDecal) calculates the estimated prop­agation delays of each node in the circuit. The design software estimates delays based
on the fanout, drive characteristics, and estimated interconnect capacitances of the
netlist and reveals potential timing problems.

• Path Delay Analysis—With path delay information from the Veritime software, the de­lays between the clocked elements of the circuit can be determined, and the critical
paths that limit the clock rate can be identified. Checking for setup, hold, and pulse­width violations can also be accomplished.

• Perform Real-Time Simulation—The real-time simulation is run to verify full functionality
using the estimated propagation delays calculated by the design tools.

• Extract Test Vectors—The simulator records the input/output patterns generated during
the real-time simulation. The test vectors that Motorola will use to test the prototypes
are derived from these patterns.

• Automatic Place & Route—The circuit’s physical layout is created from the netlist using
automatic place and route software.

• Interconnect Analysis—After the cells are placed and routed, the interconnect capaci­tances are extracted. These capacitances replace those estimated earlier during the
calculation of the node delays.

• Re-Simulate—The circuit is re-simulated with Verilog to ensure no problems have aris­en due to a change in load conditions. If changes have occurred or the simulation is dif­ferent in any way, the test vectors must also be extracted again.

MOTOROLA

EC000 CORE PROCESSOR USER’S MANUAL

For More Information On This Product,

Go to: www.freescale.com

1-5

Overview

Freescale Semiconductor, Inc.

nc...
, I

or

SYNTHESIS MODULES

LOGIC SYNTHESIS

(SYNOPSYS)

ENCRYPTED C

MODULES

GENERATE TEST PATTERNS

(STL/SYNOPSYS)

FUNCTIONAL SIMULATION

(VERILOG)

CALCULATE NODE DELAYS

(mdaDECAL)

PATH DELAY ANALYSIS

(VERITIME)

PERFORM REAL-TIME

SIMULATION

(VERILOG)

CONVERT DESIGN TO

STANDARD CELLS

CAPTURE DESIGN ON

WORKSTATION

(COMPOSER, VERILOG

HDL, VHDL)

PERFORM FAULT GRADING

(VERIFAULT)

emiconduct

eescale S
Fr

EXTRACT TEST VECTORS

(Summit Design)

AUTOMATIC PLACE & ROUTE

INTERCONNECT ANALYSIS

(mdaDECAL)

RE-SIMULATE

(VERILOG)

PATTERN, MASK AND
WAFER GENERATION

ASSEMBLY / TEST

NETLIST COMPARISON

(LVS)

1-6

MOTOROLA CUSTOMER

Figure 1-2. Standard Cell Design Flow

EC000 CORE PROCESSOR USER’S MANUAL

SHIP TESTED PROTOTYPES

For More Information On This Product,

Go to: www.freescale.com

FINAL TEST PROGRAM

MOTOROLA

nc...
, I

or

emiconduct

eescale S
Fr

Freescale Semiconductor, Inc.

Overview

1.3 PROGRAMMING MODEL

The SCM68000 programming model is illustrated in Figure 1-3. It is separated into two
modes of access: user and supervisor. The user mode provides the execution environment
for the majority of application programs. The supervisor mode, which allows some additional
instructions and privileges, is used by the operating system and other system software.
Detailed information about the programming model can be found in the

grammer's Reference Manual

31 16 15 8 7 0

31 16 15

31

(M68000PM/AD).

(a) USER PROGRAMMING MODEL

D0
D1

D2
D3

EIGHT
DATA

D4

REGISTERS

D5
D6
D7

0

A0
A1
A2

SEVEN

A3

ADDRESS
REGISTERS

A4
A5

A6

A7

USER STACK

(USP) POINTER

0

70

PC

CCR

PROGRAM
COUNTER

CONDITION CODE
REGISTER

M68000 Family Pro-



MOTOROLA

31 16 15 0

15 8 7 0

CCR

(b) SUPERVISOR PROGRAMMING MODEL

Figure 1-3. Programming Model

EC000 CORE PROCESSOR USER’S MANUAL

For More Information On This Product,

Go to: www.freescale.com

A7'

SUPERVISOR STACK

(SSP)

POINTER

STATUS REGISTER

SR

1-7

Overview

Freescale Semiconductor, Inc.

The user mode (see Figure 1-3(a)) provides access to 16 32-bit general-purpose registers
(D0–D7, A0–A7), a 32-bit program counter, and an 8-bit condition code register. The first
eight registers (D0–D7) are used as data registers for byte (8-bit), word (16-bit), and long­word (32-bit) operations. The second set of seven registers (A0–A6) and the user stack
pointer (A7/USP) can be used as software stack pointers and base address registers. In
addition, the address registers can be used for word and long-word operations. All of the 16
registers can be used as index registers.

The supervisor mode (see Figure 1-3(b)) provides access to two supplementary registers,
the status register (high-order byte) and the supervisor stack pointer (A7'/SSP). The status
register (SR) (see Figure 1-4) contains the interrupt mask (eight levels available) and the
following condition codes: overflow (V), zero (Z), negative (N), carry (C), and extend (X).
Additional status bits indicate whether the SCM68000 is in the trace (T) mode and/or in the
supervisor (S) state. Bits 5, 6, 7, 11, 12, and 14 are undefined and reserved for future expan­sion.

nc...
, I

SYSTEM BYTE USER BYTE

or

emiconduct

eescale S
Fr

TRACE MODE

SUPERVISOR

STATE

INTERRUPT

MASK

15 13 10 8 4 0

S

T

III

210

XNZVC

Figure 1-4. Status Register

EXTEND
NEGATIVE
ZERO

OVERFLOW
CARRY

CONDITION
CODES

1-8

EC000 CORE PROCESSOR USER’S MANUAL

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

Freescale Semiconductor, Inc.

Overview

1.4 DATA TYPES AND ADDRESSING MODES

Detailed information about the data types and addressing modes can be found in the

M68000 Family Programmer's Reference Manual

ports the five basic data types of the M68000 family:

1. Bit

2. Binary-Coded-Decimal (BCD) Digit (4 Bits)

3. Byte (8 Bits)

4. Word (16 Bits)

5. Long Word (32 Bits)

In addition, the instruction set supports operations on other data formats such as memory
addresses, status word, data, etc.

The SCM68000 also supports the basic addressing modes of the M68000 family. The reg­ister indirect addressing modes support postincrementing, predecrementing, offsetting, and

nc...
, I

indexing capabilities. The program counter relative mode also supports indexing and offset­ting. Table 1-1 lists a summary of the data addressing modes for the SCM68000.

(M68000PM/AD). The SCM68000 sup-

or

emiconduct

eescale S
Fr

Table 1-1. Data Addressing Modes

Addressing Modes

Register Direct Addressing
Data Register Direct
Address Register Direct

Absolute Data Addressing
Absolute Short
Absolute Long

Program Counter Relative Addressing
Relative with Offset
Relative with Index and Offset

Register Indirect Addressing
Register Indirect
Postincrement Register Indirect
Predecrement Register Indirect
Register Indirect with Offset
Indexed Register Indirect with Offset

Immediate Data Addressing
Immediate
Quick Immediate

Implied Addressing
Implied Register

NOTES:

EA = Effective Address

Dn = Data Register
An = Address Register

( ) = Contents of

PC = Program Counter

d8= 8-Bit Offset (Displacement)

d

= 16-Bit Offset (Displacement)

16

N = 1 for byte, 2 for word, and 4 for long word. If An is the stack pointer and the

←

Xn = Address or Data Register Used as Index Register

SR = Status Register

USP = User Stack Pointer

SSP = Supervisor Stack Pointer

(xxx) = Absolute Address

operand size is byte, N = 2 to keep the stack pointer on a word boundary.

= Replaces

EA = Dn
EA = An

EA = (Next Word)
EA = (Next Two Words)

EA = (PC) + d
EA = (PC) + d8

EA = (An)
EA = (An), An ← An + N
An ← An – N, EA = (An)
EA = (An) + d

EA = (An) + (Xn) + d8

DATA = Next Word(s)
Inherent Data

EA = SR, USP, SSP, PC SR, USP, SSP, PC

Generation Syntax

Dn
An

(xxx).W
(xxx).L

16

16

(d16,PC)
(d8,PC,Xn)

(An)
(An)+
–(An)
(d16,An)

(d8,An,Xn)

#<data>

MOTOROLA

EC000 CORE PROCESSOR USER’S MANUAL

For More Information On This Product,

Go to: www.freescale.com

1-9

Overview

Freescale Semiconductor, Inc.

1.5 DATA ORGANIZATION

The eight data registers support data operands of 1, 8, 16, or 32 bits. The seven address
registers and the active stack pointer support address operands of 32 bits.

1.5.1 Data Registers

Each data register is 32 bits wide. Byte operands occupy the low-order 8 bits, word oper­ands, the low-order 16 bits, and long-word operands, the entire 32 bits. The least significant
bit is addressed as bit zero; the most significant bit is addressed as bit 31.

When a data register is used as either a source or a destination operand, only the appropri­ate low-order portion is changed; the remaining high-order portion is neither used nor
changed. For example, if 8 bits are to be moved into a data register, bits 0 through 7 will be
modified and bits 8 through 31 will not be changed.

1.5.2 Address Registers

nc...
, I

or

emiconduct

eescale S
Fr

Each address register (and the stack pointer) is 32 bits wide and holds a full 32-bit address.
Address registers do not support byte-sized operands. Therefore, when an address register
is used as a source operand, either the low-order word or the entire long-word operand is
used, depending upon the operation size. When an address register is used as the destina­tion operand, the entire register is affected, regardless of the operation size. If the operation
size is word, operands are sign-extended to 32 bits before the operation is performed.

1.5.3 Data Organization In Memory

Bytes are individually addressable. As shown in Figure 1-5, the high-order byte of a word
has the same address as the word. The low-order byte has an odd address, one count
higher. Instructions and multibyte data are accessed only on word (even byte) boundaries.
If a long-word operand is located at address n (n even), then the second word of that oper­and is located at address n+2.

15 7 0141312111098 654321

ADDRESS

$000000

BYTE 000000 BYTE 000001

$000002

BYTE 000002 BYTE 000003

WORD 0

WORD 1

1-10

$FFFFFE

BYTE FFFFFE BYTE FFFFFF

WORD 7FFFFF

Figure 1-5. Word Organization in Memory

EC000 CORE PROCESSOR USER’S MANUAL

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

Freescale Semiconductor, Inc.

The data types supported by the SCM68000 are bit data, integer data of 8, 16, and 32 bits,
32-bit addresses, and binary-coded-decimal data. Each data type is stored in memory as
shown in Figure 1-6.

Overview

1.6 INSTRUCTION SET SUMMARY

Table 1-2 lists the notational conventions used throughout this manual unless otherwise
specified. Table 1-3 lists the SCM68000 instruction set by opcode. In the syntax descrip­tions, the left operand is the source operand, and the right operand is the destination oper­and.

nc...
, I

or

emiconduct

eescale S
Fr

MOTOROLA

EC000 CORE PROCESSOR USER’S MANUAL

For More Information On This Product,

Go to: www.freescale.com

1-11

Overview

Freescale Semiconductor, Inc.

nc...
, I

or

emiconduct

eescale S
Fr

BIT DATA:

INTEGER DATA:

MSB

n

n + 2

MSB

n
n + 2
n + 4

MSB

n
n + 2
n + 4
n + 6
n + 8

n + 10

ADDRESSES:

MSB

n
n + 2
n + 4
n + 6
n + 8

n + 10

MSB = MOST SIGNIFICANT BIT
LSB = LEAST SIGNIFICANT BIT

1 BYTE = 8 BITS

7

1 BYTE = 8 BITS

89101112131415

7

BYTE 0
BYTE 2 BYTE 3

LSB

1 WORD = 16 BITS

89101112131415

7

WORD 0
WORD 1
WORD 2

1 LONG WORD = 32 BITS

89101112131415

7

HIGH ORDER
LONG WORD 0

LOW ORDER

LONG WORD 1

LONG WORD 2

1 ADDRESS = 32 BITS

89101112131415

7

HIGH ORDER

ADDRESS 0
LOW ORDER

ADDRESS 1

ADDRESS 2

BYTE 1

LSB

LSB

LSB

0123456

0123456

n + 1
n + 3

0123456

0123456

0123456

1-12

DECIMAL DATA:

MSD LSD

MSD = MOST SIGNIFICANT DIGIT
LSD = LEAST SIGNIFICANT DIGIT

BCD 0 BCD 1
BCD 4 BCD 5

2 BINARY CODED DECIMAL DIGITS = 1 BYTE

Figure 1-6. Data Organization in Memory

EC000 CORE PROCESSOR USER’S MANUAL

For More Information On This Product,

Go to: www.freescale.com

89101112131415

7

BCD 2 BCD 3
BCD 6 BCD 7

0123456

MOTOROLA

nc...
, I

or

emiconduct

eescale S
Fr

≠

×

÷

Λ

⊕

→

↔

Overview

Freescale Semiconductor, Inc.

Table 1-2. Notational Conventions

Single- and Double-Operand Operations

Not equal.
+ Arithmetic addition or postincrement indicator.
– Arithmetic subtraction or predecrement indicator.

Arithmetic multiplication.

Arithmetic division or conjunction symbol.
~ Invert; operand is logically complemented.

Logical AND

V Logical OR

Logical exclusive OR

Source operand is moved to destination operand.

Two operands are exchanged.
< Relational test; true if source operand is less than destination operand.
> Relational test; true if source operand is greater than destination operand.

<operand> Data used as an operand.

<operand> tested Operand is compared to zero and the condition codes are set appropriately.

<operand> sign-ex-

tended <operand>

<operand> shifted by

<count>

<operand> rotated by

<count>

bit number of <oper-

and>

TRAP
STOP Enter the stopped state, waiting for interrupts.

<operand>

If <condition>

then <operations>

else <operations>

#<xxx> or #<data>

10

An

Ax, Ay Source and destination address registers, respectively.

Dn Any Data Register n (example: D5 is data register 5)

Dx, Dy Source and destination data registers, respectively.

Rn Any Address or Data Register

Rx, Ry Any source and destination registers, respectively.

Xn Index Register—An, Dn, or suppressed.

<fmt>

( ) Identifies an indirect address in a register.

[ ] Identifies an indirect address in memory.

d

n

CCR

PC Program Counter
SR Status Register

All bits of the upper portion are made equal to the high-order bit of the lower portion.

The source operand is shifted by the number of count.

The source operand is rotated by the number of count.

Selects a single bit of the operand.

Other Operations

1 → S-bit of SR;

SSP – 4 → SSP; PC → (SSP); SSP – 2 → SSP;

SR → (SSP); Vector Address → PC

The operand is BCD; operations are performed in decimal.

Test the condition. If true, the operations after “then” are performed. If the condition is false and

the optional “else” clause is present, the operations after “else” are performed. If the condition

is false and "else" is omitted, the instruction performs no operation. Refer to the Bcc instruction

description as an example.

Register Specification

Any Address Register n (example: A3 is address register 3)

Data Format and Type

Operand Data Format: Byte (B), Word (W), Long (L)

Subfields and Qualifiers

Immediate data following the instruction word(s).

Displacement Value, n Bits Wide (example: d16 is a 16-bit displacement).

Register Names

Condition Code Register (lower byte of status register)

1-13

EC000 CORE PROCESSOR USER’S MANUAL

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

nc...
, I

or

emiconduct

eescale S
Fr

Overview

Freescale Semiconductor, Inc.

Table 1-2. Notational Conventions (Continued)

Register Codes

C

cc Condition Codes from CCR

N Negative Bit in CCR
U Undefined, Reserved for Motorola Use
V Overflow Bit in CCR
X Extend Bit in CCR

Z Zero Bit in CCR

SP
SSP Supervisor (Master or Interrupt) Stack Pointer
USP User Stack Pointer

Í

<label> Assembly Program Label

<list> List of registers, for example D3–D0.

Carry Bit in CCR

Stack Pointers

Active Stack Pointer

Miscellaneous

Effective Address

Table 1-3. Instruction Set Summary

Opcode

ABCD
ADD Source + Destination → Destination

ADDA Source + Destination → Destination ADDA <ea>,An
ADDI Immediate Data + Destination → Destination ADDI # <data>,<ea>
ADDQ Immediate Data + Destination → Destination ADDQ # <data>,<ea>

ADDX Source + Destination + X → Destination
AND Source Λ Destination → Destination

ANDI Immediate Data Λ Destination → Destination ANDI # <data>, <ea>
ANDI to CCR Source Λ CCR → CCR ANDI # <data>, CCR

ANDI to SR

ASL, ASR Destination Shifted by <count> → Destination
Bcc

BCHG
BCLR
BKPT

BRA
BSET
BSR
BTST ~ (<bit number> of Destination) → Z;

CHK If Dn < 0 or Dn > Source then TRAP to CHK Instruction Vector CHK <ea>,Dn
CLR 0 → Destination CLR <ea>
CMP Destination – Source → cc CMP <ea>,Dn

Source10 + Destination10 + X → Destination

If supervisor state

then Source Λ SR → SR

else TRAP to Privilege Violation Trap

If (condition true) then PC + dn → PC
~ (<bit number> of Destination) → Z;

~ (<bit number> of Destination) → <bit number> of Destination
~ (<bit number> of Destination) → Z;

0 → <bit number> of Destination
Run breakpoint acknowledge cycle;

TRAP as illegal instruction
PC + dn → PC

~ (<bit number> of Destination) → Z;
1 → <bit number> of Destination

SP – 4 → SP; PC → (SP); PC + dn → PC

Operation Syntax

ABCD Dy,Dx
ABCD –(Ay), –(Ax)

ADD <ea>,Dn
ADD Dn,<ea>

ADDX Dy, Dx
ADDX –(Ay), –(Ax)

AND <ea>,Dn
AND Dn,<ea>

ANDI # <data>, SR
ASd Dx,Dy

ASd # <data>,Dy
ASd <ea>

Bcc <label>
BCHG Dn,<ea>

BCHG # <data>,<ea>
BCLR Dn,<ea>

BCLR # <data>,<ea>
BKPT # <data>

BRA <label>
BSET Dn,<ea>

BSET # <data>,<ea>
BSR <label>
BTST Dn,<ea>

BTST # <data>,<ea>

1-14

EC000 CORE PROCESSOR USER’S MANUAL

For More Information On This Product,

Go to: www.freescale.com

MOTOROLA

nc...
, I

or

emiconduct

eescale S
Fr

Overview

Freescale Semiconductor, Inc.

Table 1-3. Instruction Set Summary (Continued)

CMPA Destination – Source → cc CMPA <ea>,An
CMPI Destination – Immediate Data → cc CMPI # <data>,<ea>
CMPM Destination – Source → cc CMPM (Ay)+, (Ax)+

DBcc
DIVS Destination ÷ Source → Destination DIVS.W <ea>,Dn32/16 → 16r:16q

DIVU Destination ÷ Source → Destination DIVU.W <ea>,Dn32/16 → 16r:16q
EOR Source ⊕ Destination → Destination EOR Dn,<ea>
EORI Immediate Data ⊕ Destination → Destination EORI # <data>,<ea>
EORI to CCR Source ⊕ CCR → CCR EORI # <data>,CCR

EORI to SR

EXG Rx ↔ Ry

EXT Destination Sign-Extended → Destination

ILLEGAL
JMP Destination Address → PC JMP <ea>

JSR
LEA <ea> → An LEA <ea>,An

LINK

LSL,LSR Destination Shifted by <count> → Destination

MOVE Source → Destination MOVE <ea>,<ea>
MOVEA Source → Destination MOVEA <ea>,An
MOVE to

CCR
MOVE from

SR
MOVE to SR

MOVE USP

MOVEM

MOVEP Source → Destination
MOVEQ Immediate Data → Destination MOVEQ # <data>,Dn

MULS Source × Destination → Destination MULS.W <ea>,Dn16 x 16 → 32
MULU Source × Destination → Destination MULU.W <ea>,Dn16 x 16 → 32

NBCD
NEG 0 – (Destination) → Destination NEG <ea>

NEGX 0 – (Destination) – X → Destination NEGX <ea>
NOP None NOP
NOT ~Destination → Destination NOT <ea>

OR Source V Destination → Destination

If condition false then (Dn – 1 → Dn;
If Dn ≠ –1 then PC + dn → PC)

If supervisor state

then Source ⊕SR → SR

else TRAP to Privilege Violation Trap

SSP – 4 → SSP; PC → (SSP);
SSP – 2 → SSP; SR → (SSP);
Illegal Instruction Vector Address → PC

SP – 4 → SP; PC → (SP)
Destination Address → PC

SP – 4 → SP; An → (SP)
SP → An, SP + dn → SP

Source → CCR MOVE <ea>,CCR
SR → Destination MOVE SR,<ea>

If supervisor state

then Source → SR

else TRAP to Privilege Violation Trap
If supervisor state

then USP → An or An → USP

else TRAP to Privilege Violation Trap
Registers → Destination;

Source → Registers

0 – (Destination10) – X → Destination

DBcc Dn,<label>

EORI # <data>,SR
EXG Dx,Dy

EXG Ax,Ay
EXG Dx,Ay
EXG Ay,Dx

EXT.W Dnextend byte to word
EXT.L Dnextend word to long word

ILLEGAL

JSR <ea>

LINK An, # <displacement>
LSd Dx,Dy

LSd # <data>,Dy
LSd Í

MOVE <ea>,SR

MOVE USP,An
MOVE An,USP

MOVEM <list>,<ea>
MOVEM <ea>,<list>

MOVEP Dx,(d16,Ay)
MOVEP (d16,Ay),Dx

NBCD <ea>

OR <ea>,Dn
OR Dn,<ea>

1-15 EC000 CORE PROCESSOR USER’S MANUAL MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

nc...
, I

or

emiconduct

eescale S
Fr

Overview

Freescale Semiconductor, Inc.

Table 1-3. Instruction Set Summary (Continued)

ORI Immediate Data V Destination → Destination ORI # <data>,<ea>
ORI to CCR Source V CCR → CCR ORI # <data>,CCR

ORI to SR
PEA Sp – 4 → SP; <ea> → (SP) PEA <ea>
RESET

ROL, ROR Destination Rotated by <count> → Destination

ROXL,
ROXR

RTE

RTR
RTS (SP) → PC; SP + 4 → SP RTS
SBCD

Scc

STOP

SUB Destination – Source → Destination
SUBA Destination – Source → Destination SUBA <ea>,An

SUBI Destination – Immediate Data → Destination SUBI # <data>,<ea>
SUBQ Destination – Immediate Data → Destination SUBQ # <data>,<ea>

SUBX Destination – Source – X → Destination
SWAP Register [31:16] ↔ Register [15:0] SWAP Dn
TAS

TRAP
TRAPV If V then TRAP to TRAPV Instruciton Vector TRAPV

TST Destination Tested → Condition Codes TST <ea>
UNLK An → SP; (SP) → An; SP + 4 → SP UNLK An
NOTE: d is direction, L or R.

If supervisor state
else TRAP to Privilege Violation Trap

If supervisor state
else TRAP to Privilege Violation Trap

Destination Rotated with X by <count> → Destination

If supervisor state

else TRAP to Privilege Violation Trap
(SP) → CCR; SP + 2 → SP;

(SP) → PC; SP + 4 → SP

Destination
If condition true

else 0s → Destination
If supervisor state

else TRAP to Privilege Violation Trap

Destination Tested → Condition Codes; 1 → bit 7 of
1 → S-bit of SR;

SSP – 4 → SSP; PC → (SSP); SSP – 2 → SSP;
SR → (SSP); Vector Address → PC

then Source V SR → SR

then Assert RESETOB Line

then (SP) → SR; SP + 2 → SP; (SP) → PC;
SP + 4 → SP;
restore state and deallocate stack according to (SP)

– Source

10

then 1s → Destination

then Immediate Data → SR; STOP

Destination

– X → Destination

10

ORI # <data>,SR

RESET
ROd Dx,Dy

ROd # <data>,Dy
ROd Í

ROXd Dx,Dy
ROXd # <data>,Dy
ROXd Í

RTE

RTR

SBCD Dx,Dy
SBCD –(Ax),–(Ay)

Scc <ea>

STOP # <data>
SUB <ea>,Dn

SUB Dn,<ea>

SUBX Dx,Dy
SUBX –(Ax),–(Ay)

TAS <ea>

TRAP # <vector>

1-16 EC000 CORE PROCESSOR USER’S MANUAL MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

SECTION 2
SIGNAL DESCRIPTION

nc...
, I

or

emiconduct

This section contains descriptions of the SCM68000 (EC000 core)
The input and output signals are shown in Figure 2-1. Table 2-1 lists the pins, signal names,
type, and whether they are three-stateable. The following paragraphs provide brief descrip­tions of the signals and references (where applicable) to other paragraphs that contain more
information about the signals.

NOTE

The terms
manual to avoid confusion when describing a mixture of "active­low" and "active-high" signals. The term
used to indicate that a signal is active or true, independently of
whether that level is represented by a high or low voltage. The

negate

term
tive or false.

assertion

or

negation

and

negation

is used to indicate that a signal is inac-

are used extensively in this

assert

1

input and output signals.

or

assertion

is

2.1 ADDRESS BUS (A31–A0)

This 32-bit, unidirectional, three-state bus is capable of addressing 4 Gbytes of address
space. This bus provides the address for bus operation during all cycles except interrupt
acknowledge cycles. During interrupt acknowledge cycles, address lines A1, A2, and A3
provide the level number of the interrupt being acknowledged, and address lines A31–A4
and A0 are driven to a logic high.

eescale S
Fr

2.2 DATA BUS (D15–D0)

This 16-bit, bidirectional, three-state bus is the general-purpose data-path. The data bus
transfers and accepts data in either word or byte length if the SCM68000 is operating in the
16-bit mode. If the SCM68000 is operating in the 8-bit mode, it drives the entire bus during
writes, but only the lower eight bits (D7–D0) contain valid data. In the 8-bit mode, the
SCM68000 ignores the data on data lines D15–D8 during read cycles. During an interrupt
acknowledge cycle, the external device supplies the vector number on data lines D7–D0.

2.3 CLOCK (CLKI, CLKO)

The CLKI input is internally buffered for development of the internal clocks needed by the
SCM68000. This clock signal is a constant-frequency square wave that requires no stretch­ing or shaping. The clock signal must conform to minimum and maximum pulse-width times

1.

The SCM68000 is the name of the Verilog model for the EC000 core. The remainder of this section will

refer to the EC000 core as only the SCM68000.

MOTOROLA

EC000 CORE PROCESSOR USER’S MANUAL

For More Information On This Product,

Go to: www.freescale.com

2-1