MCM6343
1
MOTOROLA FAST SRAM
Product Preview
256K x 16 Bit 3.3 V Asynchronous
Fast Static RAM
The MCM6343 is a 4,194,304–bit static random access memory organized as
262,144 words of 16 bits. Static design eliminates the need for external clocks
or timing strobes.
The MCM6343 is equipped with chip enable (E
), write enable (W), and output
enable (G
) pins, allowing for greater system flexibility and eliminating bus con-
tention problems. Separate byte enable controls (LB
and UB) allow individual
bytes to be written and read. LB
controls the lower bits DQ0 to DQ7, while UB
controls the upper bits DQ8 to DQ15.
The MCM6343 is available in a 400 mil, 44–lead small–outline SOJ package
and a 44–lead TSOP Type II package.
• Single 3.3 V ± 0.3 V Power Supply
• Fast Access Time: 12/15 ns
• Equal Address and Chip Enable Access Time
• All Inputs and Outputs are TTL Compatible
• Data Byte Control
• Fully Static Operation
• Power Operation: 250/240/230 mA Maximum, Active AC
• Commercial and Standard Industrial Temperature Option: – 40 to + 85°C
BLOCK DIAGRAM
OUTPUT
ENABLE
BUFFER
ADDRESS
BUFFERS
WRITE
ENABLE
BUFFER
BYTE
ENABLE
BUFFER
ROW
DECODER
COLUMN
DECODER
256K x 16
BIT
MEMORY
ARRAY
HIGH
BYTE
OUTPUT
BUFFER
8
HIGH
BYTE
WRITE
DRIVER
LOW
BYTE
OUTPUT
BUFFER
LOW
BYTE
WRITE
DRIVER
SENSE
AMPS
G
W
LB
8
8
8
8
88
8
9
A
CHIP
ENABLE
BUFFER
E
UB
9
HIGH BYTE OUTPUT ENABLE
LOW BYTE OUTPUT ENABLE
HIGH BYTE WRITE ENABLE
LOW BYTE WRITE ENABLE
16
18
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
Order this document
by MCM6343/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MCM6343
YJ PACKAGE
400 MIL SOJ
CASE 919–01
PIN ASSIGNMENT
A0 – A17 Address Input. . . . . . . . . . . . . . . . .
E
Chip Enable. . . . . . . . . . . . . . . . . . . . . . . . .
W
Write Enable. . . . . . . . . . . . . . . . . . . . . . .
G
Output Enable. . . . . . . . . . . . . . . . . . . . . .
UB
Upper Byte. . . . . . . . . . . . . . . . . . . . . . . .
LB
Lower Byte. . . . . . . . . . . . . . . . . . . . . . . . .
DQ0 – DQ15 Data Input/Output. . . . . . . . . .
V
DD
+ 3.3 V Power Supply. . . . . . . . . . . . . .
V
SS
Ground. . . . . . . . . . . . . . . . . . . . . . . . . .
NC No Connection. . . . . . . . . . . . . . . . . . . . .
PIN NAMES
5
4
3
2
1
10
9
8
7
6
11
36
37
38
39
40
41
42
35
43
44
34
E
A
A
A
A
DQ1
DQ0
A
V
DD
DQ3
DQ2
UB
G
A
A
A
DQ12
DQ13
DQ14
V
SS
DQ15
LB
25
26
27
28
29
30
31
24
32
33
23
12
13
14
15
16
17
18
19
20
21
22
DQ8
DQ9
DQ10
DQ11
V
DD
A
A
A
A
A
NCW
DQ6
DQ5
DQ4
V
SS
A
A
DQ7
A
A
A
TS PACKAGE
TSOP TYPE II
CASE 924A–02
REV 2
2/10/98
Motorola, Inc. 1998
MCM6343
2
MOTOROLA FAST SRAM
TRUTH TABLE (X = Don’t Care)
E G W LB UB Mode VDD Current DQ0 – DQ7 DQ8 – DQ15
H X X X X Not Selected I
SB1
, I
SB2
High–Z High–Z
L H H X X Output Disabled I
DDA
High–Z High–Z
L X X H H Output Disabled I
DDA
High–Z High–Z
L L H L H Low Byte Read I
DDA
D
out
High–Z
L L H H L High Byte Read I
DDA
High–Z D
out
L L H L L Word Read I
DDA
D
out
D
out
L X L L H Low Byte Write I
DDA
D
in
High–Z
L X L H L High Byte Write I
DDA
High–Z D
in
L X L L L Word Write I
DDA
D
in
D
in
ABSOLUTE MAXIMUM RATINGS (See Notes)
Rating Symbol Value Unit
Supply Voltage V
DD
– 0.5 to + 4.6 V
Voltage on Any Pin V
in
– 0.5 to VDD + 0.5 V
Output Current per Pin I
out
± 20 mA
Package Power Dissipation P
D
TBD W
Temperature Under Bias Commercial
Industrial
T
bias
– 10 to + 85
– 45 to + 90
°C
Operating Temperature Commercial
Industrial
T
A
0 to + 70
– 45 to + 85
°C
Storage Temperature T
stg
– 55 to + 150 °C
NOTES:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
2. All voltages are referenced to VSS.
3. Power dissipation capability will be dependent upon package characteristics and use
environment.
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid application of any voltage higher than maximum
rated voltages to these high–impedance circuits.
This CMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board and
transverse air flow of at least 500 linear feet per
minute is maintained.
MCM6343
3
MOTOROLA FAST SRAM
DC OPERA TING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V ± 0.3 V, TA = 0 to 70°C, Unless Otherwise Noted)
(TA = – 40 to + 85°C for Industrial Temperature Offering)
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Typ Max Unit
Power Supply Voltage V
DD
3.0 3.3 3.6 V
Input High Voltage V
IH
2.2 —
VDD + 0.3**
V
Input Low Voltage V
IL
– 0.5*
— 0.8 V
*VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.
**VIH (max) = VDD + 0.3 V dc; VIH (max) = VDD + 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.
DC CHARACTERISTICS
Parameter Symbol Min Max Unit
Input Leakage Current (All Inputs, Vin = 0 to VDD) I
lkg(I)
— ±1.0 µA
Output Leakage Current (E = VIH, V
out
= 0 to VDD) I
lkg(O)
— ±1.0 µA
Output Low Voltage (IOL = + 4.0 mA)
(IOL = + 100 µA)
V
OL
— 0.4
VSS + 0.2
V
Output High Voltage (IOH = – 4.0 mA)
(IOH = – 100 µA)
V
OH
2.4
VDD – 0.2
— V
POWER SUPPLY CURRENTS
Parameter Symbol 0 to 70°C
– 40 to
+ 85°C
Unit
AC Active Supply Current MCM6343–12: t
AVAV
= 12 ns
(I
out
= 0 mA, VCC = max) MCM6343–15: t
AVAV
= 15 ns
I
CC
240
230
240
mA
AC Standby Current (VCC = max, E = VIH, MCM6343–12: t
AVAV
= 12 ns
No other restrictions on other inputs) MCM6343–15: t
AVAV
= 15 ns
I
SB1
50
45
55
50
mA
CMOS Standby Current (E ≥ VCC – 0.2 V , Vin ≤ VSS + 0.2 V or ≥ VCC – 0.2 V)
(VCC = max, f = 0 MHz)
I
SB2
5 5
mA
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T
A
= 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter Symbol Typ Max Unit
Address Input Capacitance C
in
— 6 pF
Control Input Capacitance C
in
— 6 pF
Input/Output Capacitance C
I/O
— 8 pF
MCM6343
4
MOTOROLA FAST SRAM
AC OPERA TING CONDITIONS AND CHARACTERISTICS
(VCC = 3.3 V ± 0.3 V, TA = 0 to + 70°C, Unless Otherwise Noted)
(TA = – 40 to + 85°C for Industrial Temperature Offering)
Logic Input Timing Measurement Reference Level 1.50 V. . . . . . . .
Logic Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time 2 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Timing Reference Level 1.50 V. . . . . . . . . . . . . . . . . . . . . . . . .
Output Load See Figure 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ CYCLE TIMING (See Notes 1, 2, and 3)
MCM6343–12 MCM6343–15
Parameter Symbol
Min Max Min Max
Unit Notes
Read Cycle Time t
AVAV
12 — 15 — ns 4
Address Access Time t
AVQV
— 12 — 15 ns
Enable Access Time t
ELQV
— 12 — 15 ns 5
Output Enable Access Time t
GLQV
— 6 — 7 ns
Output Hold from Address Change t
AXQX
3 — 3 — ns
Enable Low to Output Active t
ELQX
3 — 3 — ns 6, 7, 8
Output Enable Low to Output Active t
GLQX
0 — 0 — ns 6, 7, 8
Enable High to Output High–Z t
EHQZ
0 6 0 7 ns 6, 7, 8
Output Enable High to Output High–Z t
GHQZ
0 6 0 7 ns 6, 7, 8
Byte Enable Access Time t
BLQV
— 6 — 7 ns
Byte Enable Low to Output Active t
BLQX
0 — 0 — ns 6, 7, 8
Byte High to Output High–Z t
BHQZ
0 6 0 7 ns 6, 7, 8
NOTES:
1. W
is high for read cycle.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. Device is continuously selected (E
≤ VIL, G ≤ VIL).
4. All read cycle timings are referenced from the last valid address to the first transitioning address.
5. Addresses valid prior to or coincident with E
going low.
6. At any given voltage and temperature, t
EHQZ
max t t
ELQX
min, and t
GHQZ
max t t
GLQX
min, both for a given device and from device
to device.
7. This parameter is sampled and not 100% tested.
8. Transition is measured ± 200 mV from steady–state voltage.
The table of timing values shows either a minimum
or a maximum limit for each parameter. Input requirements are specified from the external system point of
view. Thus, address setup time is shown as a minimum
since the system must supply at least that much time.
On the other hand, responses from the memory are
specified from the device point of view. Thus, the access time is shown as a maximum since the device
never provides data later than that time.
TIMING LIMITS
OUTPUT
Z0 = 50
Ω
RL = 50
Ω
VL = 1.5 V
Figure 1. AC Test Load
MCM6343
5
MOTOROLA FAST SRAM
Q (DATA OUT)
A (ADDRESS)
DATA VALIDPREVIOUS DATA VALID
t
AVAV
t
AXQX
t
AVQV
READ CYCLE 1 (See Note 8)
t
EHQZ
DATA VALID
t
GHQZ
t
AVAV
t
ELQX
t
ELQV
E (CHIP ENABLE)
Q (DATA OUT)
A (ADDRESS)
t
AVQV
t
BLQX
t
GLQV
G (OUTPUT ENABLE)
t
BHQZ
t
BLQV
LB, UB (BYTE ENABLE)
t
GLQX
READ CYCLE 2 (See Note 4)
MCM6343
6
MOTOROLA FAST SRAM
WRITE CYCLE 1 (W Controlled; See Notes 1, 2, and 3)
MCM6343–12 MCM6343–15
Parameter Symbol
Min Max Min Max
Unit Notes
Write Cycle Time t
AVAV
12 — 15 — ns 4
Address Setup Time t
AVWL
0 — 0 — ns
Address Valid to End of W rite t
AVWH
10 — 12 — ns
Address Valid to End of W rite (G High) t
AVWH
9 — 10 — ns
Write Pulse Width t
WLWH
t
WLEH
10 — 12 — ns
Write Pulse Width (G High) t
WLWH
t
WLEH
9 — 10 — ns
Data Valid to End of W rite t
DVWH
6 — 7 — ns
Data Hold Time t
WHDX
0 — 0 — ns
Write Low to Data High–Z t
WLQZ
0 6 0 7 ns 5, 6, 7
Write High to Output Active t
WHQX
3 — 3 — ns 5, 6, 7
Write Recovery Time t
WHAX
0 — 0 — ns
NOTES:
1. A write occurs during the overlap of E
low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. If G
goes low coincident with or after W goes low, the output will remain in a high–impedance state.
4. All write cycle timings are referenced from the last valid address to the first transitioning address.
5. This parameter is sampled and not 100% tested.
6. Transition is measured ± 200 mV from steady–state voltage.
7. At any given voltage and temperature, t
WLQZ
max < t
WHQX
min both for a given device and from device to device.
DATA VALID
t
DVWH
t
AVWL
t
AVWH
t
AVAV
t
WHAX
t
WLWH
t
WHDX
t
WLQZ
t
WHQX
HIGH–Z
HIGH–Z
A (ADDRESS)
W
(WRITE ENABLE)
E
(CHIP ENABLE)
Q (DATA OUT)
D (DATA IN)
t
WLEH
LB, UB (BYTE ENABLE)
WRITE CYCLE 1
(W Controlled; See Notes 1, 2, and 3)
MCM6343
7
MOTOROLA FAST SRAM
WRITE CYCLE 2 (E Controlled; See Notes 1, 2, and 3)
MCM6343–12 MCM6343–15
Parameter Symbol
Min Max Min Max
Unit Notes
Write Cycle Time t
AVAV
12 — 15 — ns 4
Address Setup Time t
AVEL
0 — 0 — ns
Address Valid to End of W rite t
AVEH
10 — 12 — ns
Address Valid to End of W rite (G High) t
AVEH
9 — 10 — ns
Enable to End of Write t
ELEH,
t
ELWH
10 — 12 — ns 5, 6
Enable to End of Write (G High) t
ELEH,
t
ELWH
9 — 10 — ns 5, 6
Data Valid to End of W rite t
DVEH
6 — 7 — ns
Data Hold Time t
EHDX
0 — 0 — ns
Write Recovery Time t
EHAX
0 — 0 — ns
NOTES:
1. A write occurs during the overlap of E
low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. If G
goes low coincident with or after W goes low, the output will remain in a high–impedance state.
4. All write cycle timing is referenced from the last valid address to the first transitioning address.
5. If E
goes low coincident with or after W goes low, the output will remain in a high–impedance condition.
6. If E
goes high coincident with or before W goes high, the output will remain in a high–impedance condition.
t
EHDX
t
DVEH
t
EHAX
t
ELWH
t
ELEH
t
AVEL
t
AVEH
DATA VALID
t
AVAV
HIGH–Z
A (ADDRESS)
W
(WRITE ENABLE)
E (CHIP ENABLE)
Q (DATA OUT)
D (DATA IN)
LB, UB (BYTE ENABLE)
WRITE CYCLE 2
(E Controlled; See Notes 1, 2, and 3)
MCM6343
8
MOTOROLA FAST SRAM
WRITE CYCLE 3 (E Controlled; See Notes 1, 2, and 3)
MCM6343–12 MCM6343–15
Parameter Symbol
Min Max Min Max
Unit Notes
Write Cycle Time t
AVAV
12 — 15 — ns 4
Address Setup Time t
AVBL
0 — 0 — ns
Address Valid to End of W rite t
AVBH
10 — 12 — ns
Address Valid to End of W rite (G High) t
AVBH
9 — 10 — ns
Byte Pulse Width t
BLWH
t
BLEH
10 — 12 — ns
Byte Pulse Width (G High) t
BLWH
t
BLEH
9 — 10 — ns
Data Valid to End of W rite t
DVBH
6 — 7 — ns
Data Hold Time t
BHDX
0 — 0 — ns
NOTES:
1. A write occurs during the overlap of E
low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. If G
goes low coincident with or after W goes low, the output will remain in a high–impedance state.
4. All write cycle timings are referenced from the last valid address to the first transitioning address.
DATA VALID
t
DVBH
t
AVBL
t
AVBH
t
AVAV
t
BLWH
t
BHDX
HIGH–Z
HIGH–Z
A (ADDRESS)
W
(WRITE ENABLE)
E (CHIP ENABLE)
Q (DATA OUT)
D (DATA IN)
t
BLEH
LB, UB (BYTE ENABLE)
WRITE CYCLE 3
(E Controlled; See Notes 1, 2, and 3)
MCM6343
9
MOTOROLA FAST SRAM
Motorola Memory Prefix
Part Number
Package (YJ = 400 mil SOJ, TS = TSOP Type II)
Full Commercial Part Numbers — MCM6343YJ12 MCM6343YJ12R MCM6343TS12
MCM6343YJ15 MCM6343YJ15R MCM6343TS15
Shipping Method (R = Tape and Reel, Blank = Rails)
Speed (12 = 12 ns, 15 = 15 ns)
XCM 6943 XX XX X
ORDERING INFORMATION
(Order by Full Part Number)
Full Industrial Part Numbers —SCM6343YJ12A SCM6343YJ12AR SCM6343TS12A*
SCM6343YJ15A SCM6343YJ15AR SCM6343TS15A*
*Not available in Tape and Reel.
P ACKAGE DIMENSIONS
YJ PACKAGE
44–LEAD
400 MIL SOJ
CASE 919–01
23
22
44
1
R1
A
E
VIEW A–A
44X R
22 ZONES 2X
42X
b144X
SEATING
PLANE
D
B
E1
A
L
0.007 C AB
C
e
M
0.007 C AB
b44X
e
/2
A3
C0.004
A
A
M
0.007 C AB
B0.015
A2
A1
E2
E2 /2
DIM MIN MAX
INCHES
A 0.128 0.148
A1 0.025 –––
A2 0.082 –––
A3 0.035 0.045
b 0.015 0.020
b1 0.026 0.032
D 1.120 1.130
E 0.435 0.445
E1 0.395 0.405
E2 0.370 BSC
e 0.050 BSC
R1 0.030 0.040
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
TIE BAR BURRS AND GATE BURRS. MOLD
FLASH, TIE BAR BURRS AND GATE BURRS
SHALL NOT EXCEED 0.006 PER END. DIMENSION
E1 DOES NOT INCLUDE INTERLEAD FLASH.
INTERLEAD FLASH SHALL NOT EXCEED 0.010
PER SIDE.
4. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM. DIMENSIONS D AND E1 AND,
HENCE, DATUMS A AND B, ARE DETERMINED AT
THE OUTERMOST EXTREMES OF THE PLASTIC
BODY EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD FLASH,
BUT INCLUDING ANY MISMATCH BETWEEN THE
TOP AND BOTTOM OF THE PLASTIC BODY.
5. DIMENSION b1 DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE
SHOULDER WIDTH TO EXCEED b1 MAX BY
MORE THAN 0.005. THE DAMBAR INTRUSION(S)
SHALL NOT REDUCE THE SHOULDER WIDTH TO
LESS THAN 0.001 BELOW b1 MIN.
MCM6343
10
MOTOROLA FAST SRAM
TS PACKAGE
44–LEAD
TSOP TYPE II
CASE 924A–02
NOTES:
1. DIMENSIONINS AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE MOLD PROTRUSION
IS 0.15 PER SIDE.
4. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSIONS. DAMBAR PROTRUSION SHALL
NOT CAUSE THE LEAD WIDTH TO EXCEED 0.58.
B
M
0.2 C
B
A
e
C
44 23
122
A2
AA
E1
D
42X
e4X
44X
0.004 (0.1) C
SEATING
PLANE
22X E
A
VIEW A
A1
L
b
q
ROTATED 90 CLOCKWISE
VIEW A
40 PLACES
SECTION A–A
_
c
/2
B
M
0.2 C
DIM MIN MAX
MILLIMETERS
A ––– 1.20
A1 0.05 0.15
A2 0.95 1.05
b 0.30 0.45
c 0.12 0.21
D 18.28 18.54
e 0.80 BSC
E 11.56 11.96
E1 10.03 10.29
L 0.40 0.60
q
0 5
__
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
Mfax is a trademark of Motorola, Inc.
How to reach us:
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MCM6343/D
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