MOTOROLA PC33889 Technical data

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MOTOROLA

Semiconductor Technical Data

Freescale Semiconductor, Inc.

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Rev 5.6, 23th July 02

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System Basis Chip Lite with Low
Speed Fault Tolerant CAN Interface

The MC33889 is a monolithic integrated circuit combining many functions
frequently used by au tomot ive ECU s. It i ncorpo rates a low sp eed fa ult toleran t
CAN physical interface.

Main features:

• Vdd1: 5V Low drop voltage regulator, current limitation, over temperature
detection, monitoring and reset function. Total current capability 200mA.

• V2: Tracking function of Vdd1 regulator. C ontrol circuitry for external bipolar
ballast transistor for high flexibility in choice of peripheral voltage and current
supply.

• Four operational m odes: norma l, stand-b y , stop and sleep modes.

• Low stand-by c urrent consum ption in s top and sle ep modes

• Built in Low speed 125KBaud fault tolerant CAN physical interface,
compatible wit h Motorol a MC33388.

nc...

I

• External high vol tage wake-u p input, as sociated with HS1 Vbat s witch

• 150mA output current cap ability for HS1 Vbat switch all owing drive of external
switches pull up resistors o r relays

• Vsup monitoring and failure detection

• DC Operating vol tage from 5 to 27V

• 40V maximum transient voltag e

• Programmable softwa re time out and window watchdog

• Separate output s for W atchdog time out sign al (WDOGB) and Reset (Res et).

• Wake up capabilities: wake up input, programmable cyclic sense, forced
wake up, CAN interface , SPI (CSB pin) and stop m ode over cur rent.

• Interface with MCU through 4 Mhz SPI.

• SO28WB package w ith thermal en hanced lea d frame.

Simplified Block Diagram

Q1

cale Semiconductor,

Vbat

Vsup

V2CTRL

Vsup monitor

Dual Voltage Regulator

Vdd1 Monitor

V2

5V/200mA

5V

CAN

supply

Frees

Mode control

Oscillator

Interrupt

Watchdog

Reset

SPI Interface

V2

Rrth

Rrtl

HS1

L0
L1

Rth

CAN H

CAN L

Rtl

HS1 control

Programmable
wake-up input

Vsup

Low Speed 125Kbit/s

Fault Tolerant CAN

Physical Interface

Vdd1

INTB

WDOGB

Reset

MOSI
SCLK

MISO

CSB

Txd
Rxd

Gnd

5V/200mA

PC33889

PASS3

System Basis

Chip Lite

SILICON MONOLITHIC
INTEGRATED CIRCUIT

DW SUFFIX

PLASTIC PACKAGE

CASE 751F

SO-28

PIN CONNECTIONS

1

RX

2

TX

3

Vdd1

4

Reset

5

INTB

6

GND

7

GND

8

GND

9

GND

10

V2ctrl

11

Vsup

12

HS1

13

L0

14

L1

ORDERING INFORMATION

Device

Operating

Temperature Range

TA = -40 to 125°CPC33889DW

28
27
26
25
24
23
22
21
20
19

18

17
16
15

WDOGB
CSB

MOSI
MISO
SCLK
GND
GND
GND

GND

CANL
CANH
Rtl
Rth

V2

Package

SO-28

This document contains information on a product under development. Motorola reserves the right
to change or discontinue this product without notice.

For More Information On This Product,

Go to: www.freescale.com

© Motorola, Inc., 2002. All rights reserved.

Freescale Semiconductor, Inc.

PC33889

1 MAXIMUM RATINGS

Ratings Symbol Min Typ Max Unit

ELECTRICAL RATINGS

Supply Voltage at Vsup

- Continuous voltage

- Transient voltage (Load dump)
Logic Inputs (Rx, Tx, MOSI, MISO, CSB, SCLK, Reset,

WDOGB, INTB)
Output current Vdd1 I Internally limited A
HS1

- voltage

- output current
ESD voltage (HBM 100pF, 1.5k)

- CANL, CANH, Rtl, Rth, HS1, L0, L1

- All other pins
ESD voltage (Machine Model) All pins Vesdm -200 200 V

Vsup
Vsup

Vlog - 0.3 Vdd1+0.3 V

V

I

Vesdh

-0.3 27

-0.2
Internally limited

-4

-2

Vsup+0.3 V

40

4
2

V

A

kV

nc...

I

cale Semiconductor,

Frees

L0, L1

- DC Input voltage

- DC Input current

- Transient input current (according to ISO7637 specifi­cation) and with external component tbd.

CAN related pins: CANH, CANL, RTL, RTH, Tx, Rx
(refer to CAN section)

THERMAL RATINGS

Junction Temperature T
Storage Temperature T
Ambient Temperature (for info only) T
Thermal resistance junction to gnd pin (note 1) Rthj/p 20 °C/W

Note 1: gnd pins 6,7,8,9,20, 21, 22, 23.

Figure 1. T ransient test pul se for L0 and L1 inputs

Lx

10 k

Gnd

1nF

Vwu DC

j

s

a

-0.3

-2

tbd

- 40 +150 °C

- 55 +165 °C

- 40 +125 °C

Transient Pulse

Generator

(note)

Gnd

40

tbd

2

mA
mA

V

note: Waveform in accordance to ISO7637 part1, test pulses 1, 2, 3a and 3b.

PC33889 2

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2 ELECTRICAL CHARACTERISTICS

(V

From 5.5V to 18V and Tj from -40°C to 125°C) unless otherwise noted. For all pins except can related pins

sup

PC33889

nc...

I

cale Semiconductor,

Frees

Description Symbol

Vsup pin (Device power supply)

Nominal DC Voltage range
Extended DC Voltage range 1 Vsup-ex1 4.5 5.5 V Reduced functionality

Extended DC Voltage range 2 Vsup-ex2 18 27 V (note 3)
Input Voltage during Load Dump
Input Voltage during jump start
Supply Current in Sleep Mode (note 2,4)

Supply Current in Sleep Mode (note 2,4)

Supply current in sleep mode (note 2,4)

Supply Current in Stand-by Mode
(note 2,4)

Supply Current in Normal Mode (note 2)

Supply Current in Stop mode (note 2,4)
I out Vdd1 <2mA

Supply Current in Stop mode (note 2,4)
Iout Vdd1 < 2mA

Supply Current in Stop mode (note 2,4)

Iout Vdd1 < 2mA

Supply Fail Flag internal threshold Vthresh 1.5 3 4 V
Supply Fail Flag hysteresis Vdet hyst 1 V guaranteed b y design
Battery fall early warning threshold BFew 5.9 6.1 6.3 V In normal & standby mode
Battery fall early warning hysteresis BFewh 0.1 0.2 0.3 V In normal & standby mode,

note 1: Vdd1>4V, reset high, logic pin high level reduced, device is functional.
note 2: current measured at Vsup pin.
note 3: Device is fully functional. All modes available and operating, Watchdog, HS1 turn ON turn OFF, CAN cell operating, L0 and L1 inputs
operating, SPI read write operation. Over temperature may occur.
note 4: Excluding the CAN cell current. An additional 30uA typical must be added to specified value.
note 5: Oscillator running means “Forced Wake Up” or “Cyclic Sense” or “Software Watchdog” timer activated.
note 6: Vdd is ON with2mA typical output current capability.

Vsup

VsupLD
VsupJS

Isup

(sleep1)

Isup

(sleep2)

Isup

(sleep3)

Isup(stdby)

Isup(norm)

Isup

(stop1)

Isup

(stop2)

Isup

(stop3)

Characteristics

Unit Conditions

Min Typ Max

5.5 18 V

(note 1)

40 V Load dump situation
27 V Jump start situation

75 tbd uA Vdd1 & V2 off, Vsup<12V,

oscillator running (note 5)

excluding CAN current

60 tdb uA Vdd1 & V2 off, Vsup<12V

oscillator not running (note5)

excluding CAN current,

150 tbd uA Vdd1 & V2 off, Vsup>12V

oscillator running (note 5)

excluding CAN current

15 mA Iout at Vdd1 =10mA, CAN

recessive state or disabled

15 mA Iout at Vdd1 =10mA, CAN

recessive state or disabled

120 tbd uA Vdd1 on (note 6), Vsup<12V

oscillator running (note 5)

excluding CAN current,

110 tbd uA Vdd1 on (note 6), Vsup<12V

oscillator not running (note 5)

excluding CAN current

180 tbd uA Vdd1 on (note6), Vsup>12

oscillator running (note 5)

excluding CAN current

guaranteed by design

Vdd1 (external 5V output for MCU supply). Idd1 is the total regulator output current. Vdd specification with external capacitor
C>=22uF and ESR<1O ohm.

Vdd1 Output Voltage Vdd1out 4,9 5 5,1 V Idd1 from 2 to 200mA

Vdd1 Output Voltage Vdd1out 4 V Idd1 from 2 to 200mA

Drop Voltage Vsup>Vddout Vdd1drop 0.2 0,5 V Idd1 = 200mA
Drop Voltage Vsup>Vddout, limited out-

put current
Idd1 Output Current Idd1 200 270 350 mA Internally limited
Vdd1 Output Voltage in stop mode Vddstop 4,75 5,00 5,25 V Iout < 2mA

Vdd1dp2 0,1 0,25 V Idd1 = 50mA

5.5V< Vsup <27V

4.5V< Vsup <5.5V

4.5V< Vsup <27V

PC33889 3

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(V

From 5.5V to 18V and Tj from -40°C to 125°C) unless otherwise noted. For all pins except can related pins

sup

Freescale Semiconductor, Inc.

PC33889

Description Symbol

Idd1 stop output current to wake up SBC Idd1s-wu1 2 3.5 5 mA Selectable by SPI. Default

Idd1 stop output current to wake up SBC Idd1s-wu2 10 14 18 mA Selectable by SPI
Idd1 over current wake deglitcher (with

Idd1s-wu1 selected)
Idd1 over current wake deglitcher (with

Idd1s-wu2 selected)
Thermal Shutdown Tsd 160 190
Over temperature pre warning Tpw 130 160
Temperature Threshold difference Tsd-Tpw 20 40
Reset threshold 1 Rst-th1 4.5 4.6 4.7 Selectable by SPI. Default

Reset threshold 2 Rst-th2 4.1 4.2 4.3 Selectable by SPI
Reset duration reset-dur 0.85 1 2 ms
Vdd1 range for Reset Active Vdd

nc...

I

Reset Delay Time t
Line Regulation LR1 5 25 mV 9V<V

Line Regulation LR2 10 25 mV 5.5V<V
Load Regulation LD 20 50 mV 1mA<I
Thermal stability ThermS 5 mV Vsup=13.5V, I=100mA

Idd1-dglt1 40 75 55 us Guarant eed by design

Idd1-dglt2 150 us Guarant eed by design

r

d

Characteristics

Min Typ Max

1V
520us

Unit Conditions

value after reset.

°C Normal or standby mode
°C VDDTEMP bit set
°C

value after reset.

measured at 50% of reset sig-

nal. Guaranteed by design

<18, Idd=10mA

sup

<27V, Idd=10mA

sup

<200mA

Idd

cale Semiconductor,

Frees

V2 tracking voltage regulator

note 7: V2 specification with external capacitor

- option 1: C>=22uF and ESR<1O ohm

- option2: 1uF<C<22uF and ESR<10 ohm. In this case depending upon ballast transistor gain an additional resistor and capacitor netwo rk
between emitter and base of PNP ballast transistor might be required.

V2 Output Voltage V2 0.99 1 1.01 Vdd1 I2 from 2 to 200mA

I2 output current (for information only) I2 200 mA Depending upon external bal-

V2 ctrl drive current I2ctrl tbd 10 tbd mA

Logic outpu t pi ns (MISO)

Low Level Output Voltage Vol 1.0 V I out = 1.5mA
High Level Output Voltage Voh Vdd1-0.9 V I out = -250uA
Tristated MISO Leakage Current -2 +2 uA 0V<V

Logic input pins (MOSI, SCLK, CSB)

High Level Input Voltage Vih 0.7Vdd1
Low Level Input Voltage Vil -0.3 0.3Vdd1 V

High Level Input Current on CSB Iih -100 -20 uA V
Low Level Input Current CSB Iil -100 -20 uA V
MOSI, SCLK Input Current Iin -10 10 uA 0<V

Reset Pin (output pin only)

High Level Output current Ioh -250 uA 0<V
Low Level Output Voltage (I
Low Level Output Voltage (I
Reset pull down current Ipdw 2.4 5 mA
Reset Duration after Vdd High reset-dur 1 2 ms

Wdogb output pin

=1.5mA) Vol 0 0.9 V 5.5v<V

0

=tb d mA) Vol 0 0.9 V 1v<V

0

Vdd1+0.3

V

5.5V< Vsup <27V

last transistor

<Vdd

miso

=4V

i

=1V

i

<Vdd

IN

<0.7Vdd

out

<27V

sup

dd1

PC33889 4

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(V

From 5.5V to 18V and Tj from -40°C to 125°C) unless otherwise noted. For all pins except can related pins

sup

Freescale Semiconductor, Inc.

PC33889

nc...

I

cale Semiconductor,

Frees

Description Symbol

Low Level Output Voltage (I0=1.5mA) Vol 0 0.9 V 5.5v<V
High Level Output Voltage (I

INT Pin

Low Level Output Voltage (I
High Level Output Voltage (I

HS1: 150mA High side output pin

Rdson at Tj=25°C, and Iout -150mA Rdson25 2.5 Ohms Vsup>9V
Rdson at Tj=125°C, and Iout -150mA Rdson125 5 Ohms Vs up>9V
Rdson at Tj=125°C, and Iout -120mA Ron125-2 4 5.5 Ohms 5.5 V<Vs up<9V
Output current limitation Ilim 200 500 mA
Over temperature Shutdown Ovt 155 190
Leakage current Ileak 10 uA
Output Clamp Voltage at Iout= -1mA Vcl -1.5 -0.3 V no inductive load drive capa-

Cyclic sense period (refer to SPI) T1 ms in sleep and stop modes
Cyclic sense On time (refer to SPI) T2 100 us in sleep and stop modes
Timing accuracy (cyclic sense period and

on time)

L0 and L1 inputs

L0 Negative Switching Threshold Vth0n 1.7

L0 Positive Switching Threshold Vth0p 2.2

L1 Negative Switching Threshold Vth1n 2

L1 Positive Switching Threshold Vth1p 2.7

Hysteresis Vhyst 0.6

Input current Iin -10 10 uA -0.2V < Vin < 40V
Wake up Filter Time (enable/disable

option on L0 input)

DIGITAL INTERFACE TIMING

SPI operation frequency Freq 4 MHz
SCLK Clock Period t
SCLK Clock High Time t
SCLK Clock Low Time t
Falling Edge of CS to Rising

Edge of SCLK
Falling Edge of SCLK to Rising Edge of

CS
MOSI to Falling Edge of SCLK t
Falling Edge of SCLK to MOSI t
MISO Rise Time (CL = 220pF) t
MISO Fall Time (CL = 220pF) t

=-250uA) Voh Vdd1-0.9 Vdd1

0

=1.5mA) Vol 0 0.9 V

0

=-250uA) Voh Vdd1-0.9 Vdd1

0

Tacc -30 +30 % in sleep and stop mode

pCLK
wSCLKH
wSCLKL

t

lead

t

lag

SISU

SIH
rSO
fSO

Characteristics

Min Typ Max

2
2

2.5

2.5

2.5

2.7

3

3.5

82038

250 ns
125 ns
125 ns

100 50 ns

100 50 ns

40 25 ns
40 25 ns

tbd

tbd
tbd

tbd

2.5
3

3.2

3.3
4

4.2

tbd

25 50 ns
25 50 ns

3
3

3.1
4

4

4.1
3

3.6

3.7

3.8

4.6

4.7

1.3 V 5.5V<Vsup<18V

Unit Conditions

<27V

sup

°C

bility

V 5.5V<Vsup<6V

V 5.5V<Vsup<6V

V 5.5V<Vsup<6V

V 5.5V<Vsup<6V

us

6V<Vsup<18V

18V<Vsup<27V

6V<Vsup<18V

18V<Vsup<27V

6V<Vsup<18V

18V<Vsup<27V

6V<Vsup<18V

18V<Vsup<27V

18V<Vsup<27V

(If filter enable)

PC33889 5

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(V

From 5.5V to 18V and Tj from -40°C to 125°C) unless otherwise noted. For all pins except can related pins

sup

Freescale Semiconductor, Inc.

PC33889

nc...

I

cale Semiconductor,

Frees

Description Symbol

Time from Falling o r R isi ng Edge s of CS t o:

- MISO Low Impedance

- MISO High Impedance
Time from Rising Edge of SCLK to MISO

Data Valid

STATE MACHINE TIMING
note 1: delay starts at rising edge of CSB (end of SPI command) and start of Turn on or Turn off of HS1 or V2.

Delay between CSB low to high transition
(at end of SPI stop command) and Stop
or sleep mode activation

Interrupt low level duration Tint 7 10 13 us SBC in stop mode

Internal oscillator frequency Osc-f1 100 kHz

Internal low power oscillator frequency Osc-f2 100 kHz
Watchdog period 1 Wd1 8.58 9.75 10.92 ms Normal and standby modes

Watchdog period 2 Wd2 39.6 45 50.4 ms Normal and standby modes
Watchdog period 3 Wd3 88 100 112 ms Normal and standby modes
Watchdog period 4 Wd4 308 350 392 ms Normal and standby modes
Watchdog period accuracy F1acc -12 12 % Normal and standby modes
Normal request mode timeout NRtout 308 350 392 ms Normal request mode
Watchdog period 1 - stop Wd1stop 6.82 9.75 12.7 ms Stop mode
Watchdog period 2- stop Wd2stop 31.5 45 58.5 ms Stop mode
Watchdog period 3 - stop Wd3stop 70 100 130 ms Stop mode
Watchdog period 4 - stop Wd4stop 245 350 455 ms Stop mode
Stop mode watchdog period accuracy F2acc -30 30 % Stop mode
Cyclic sense/FWU timing 1 CSFWU1 3.22 4.6 5.98 ms Sleep and stop modes
Cyclic sense/FWU timing 2 CSFWU2 6.47 9.25 12 ms Sleep and stop modes
Cyclic sense/FWU timing 3 CSFWU3 12.9 18.5 24 ms Sleep and stop modes
Cyclic sense/FWU timing 4 CSFWU4 25.9 37 48.1 ms Sleep and stop modes
Cyclic sense/FWU timing 5 CSFWU5 51.8 74 96.2 ms Sleep and stop modes
Cyclic sense/FWU timing 6 CSFWU6 66.8 95.5 124 ms Sleep and stop modes
Cyclic sense/FWU timing 7 CSFWU7 134 191 248 ms Sleep and stop modes
Cyclic sense/FWU timing 8 CSFWU8 271 388 504 ms Sleep and stop modes
Cyclic sense On time Ton 200 350 500 us in sleep and stop modes

Cyclic sense/FWU timing accuracy Tacc -30 +30 % in sleep and stop mode
Delay between SPI command and HS1

turn on (note 1)
Delay between SPI command and HS1

turn off (note 1)
Delay between SPI and V2 turn on

(note 1)
Delay between SPI and V2 turn off

(note 1)
Delay between Normal Request and Nor-

mal mode, after W/D trigger command

t

SOEN

t

SODIS

t

valid

Tcsb-stop 18 34 us

Ts-HSon 22 us

Ts-HSoff 22 us

Ts-V2on 9 22 us St andby mode

Ts-V2off 9 22 us Normal modes

Ts-NR2N 15 35 70 us Normal request mode

Characteristics

Min Typ Max

50
50

50 ns

Unit Conditions

ns

0.2 V1≤SO≥ 0.8V1,
C

=200pF

L

Guaranteed by design

detected by V2 off

All modes except Sleep

and Stop, guaranteed by

Sleep and Stop modes,

threshold and condition to

Normal or standby mode

Normal or standby mode

design

guaranteed by design

be added

Vsup>9V

Vsup>9V

PC33889 6

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Delay between SPI and “CAN normal
mode”

Delay between SPI and “CAN sleep
mode”

Delay between CSB wake up (CSB low
to high) and SBC normal request mode
(Vdd1 on & reset high)

Delay between CSB wake up (CSB low
to high) and first accepted SPI command

Delay between INT pulse and 1st SPI
command accepted

CSB

Ts-CANn 10 us

Ts-CANs 10 us

Tw-csb 15 40 90 us SBC in stop mode

Tw-spi 90 N/A us SBC in stop mode

Ts-1stspi 20 N/A us In stop mode after wake up

Figure 2. Timing Characteristics

Tpclk

PC33889

SBC Normal mode

guaranteed by design

SBC Normal mode

guaranteed by design

Tvalid

Twclkh

D0

Tsi s u

D0

Tsi h

Twclkl

Don’t Care

Don’t Care

Tlag

D8 Don’t Care

Tsodis

D8

Tlead

SCLK

nc...

I

MOSI

MISO

Undefined

Tsoen

cale Semiconductor,

Frees

PC33889 7

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PC33889

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3 CAN MODULE SPECIFICATION (COMPATIBLE WITH MC33388)

ELECTRICAL RA TINGS

Ratings Symbol Min Typ Max Unit

nc...

I

cale Semiconductor,

Frees

DC Voltage On Pins Tx, Rx

DC voltage at V2 (V2int)

DC Voltage On Pins CANH, CANL

Transient V oltage At Pins CANH, CANL
0 < V

Transient V oltage On Pins CANH, CANL (Coupled Through
1nF Capacitor)

DC Voltage On Pins R th, R tl

Transient V oltage At Pins R tH, R tL
0 < V

RTH, RTL Termination Resistance

Supply current described below are the CAN module internal supply current from internal V2 (V2-int) and Vsup

Internal V2 Supply Current (CAN and SBC in Normal
Mode). TX= 5V, CAN in Recessive State

Internal V2 Supply Current (CAN and SBC in Normal
Mode). TX = 0V, No Load, CAN in Dominant State

Total supply Current (CAN in Receive Only Mode, SBC in
Normal mode). Internal V2 = 5V; V

Internal V2 Supply Current (CAN in Bus TermVbat mode)
V

TX Pin

High Level Input Voltage V

Low Level Input Voltage V

< 5.5V; V

2-int

< 5.5V; V

2-int

≥ 0; T < 500ms

sup

≥ 0; T < 500ms

sup

ELECTRICAL CHARAC TERISTICS (V

Conditions Symbol Min Typ Max Unit

= 12V

sup

= 12V

sup

From 5.5V to 18V, V2int from 4.75 to 5.25V and Tj from -40°C to 150°C unless otherwise noted).

sup

Vlogic -0.3 V

V2int 0 5.25 V

V

BUS

V

CANH/VCANL

V

tr

, V

V

rtl

V

RtH/VRtL

R

I

V2-int

I

V2-int

I

+ I

V2-int

I

V2-int

ih

il

rth

t

SUP-int

-20 +27 V

-40 40 V

-150 100 V

-0.3 +27 V

-0.3 40 V

500 16000 ohm

45.66.5mA

4.2 5.8 6.7 mA

11.4mA

36 tbd uA

0.7*V

2-int

-0.3 0.3 * V

DD1

V

+ 0.3 V

+0.3V V

2-int

2-int

V

TX High Level Input Current (V

TX Low Level Input Current (V

RX Pin

High Level Output Voltage RX (I

Low Level Output Voltage (I

CANH, CANL Pins

Differential Receiver, Recessive To Dominant Threshold
(By Definition, V

diff=VCANH-VCANL

= 4V) I

i

= 1V) I

i

= -250µA) V

0

= 1.5mA) V

0

)

TX

TX

oh

ol

V

diff1

-100 -50 -25 uA

-100 -50 -25 uA

V

- 0.9 V

2-int

00.9V

-3.2 -2.5 V

2-int

V

PC33889 8

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PC33889

Conditions Symbol Min Typ Max Unit

nc...

I

cale Semiconductor,

Frees

Differential Receiver, Dominant To Recessive Threshold
(Bus Failures 1, 2, 5)

CANH Recessive Output Volt age
TX = 5V; R

CANL Recessive Output Volt age
TX =5V; R

CANH Output Voltage, Dominant
TX = 0V; I

CANL Output Voltage, Dominant
TX = 0V; I

CANH Output Current (V

CANL Output Current (V

Detection Threshold For Short-circuit T o Battery Volt age
(Normal Mode)

Detection Threshold For Short-circuit T o Battery Volt age
(T erm Vbat Mode)

CANH Output Current (T erm Vbat Mode; V
Failure3)

CANL Output Current (T erm Vbat Mode; V

= 12V , Failure 4)

V

BAT

CANL Wake Up V oltage Threshold V

CANH Wake Up Vol tage Threshold V

Wake Up Threshold Difference (Hysteresis) V

CANH Single Ended Receiver Threshold (Failures 4, 6, 7) V

CANL Single Ended Receiver Threshold (Failures 3, 8) V

CANL Pull Up Current (Normal Mode) I

CANH Pull Down Current (Normal Mode) I

Receiver Differential Input Impedance CANH / CANL R

Differential Receiver Common Mode Volt age Range V

CANH T o Ground Capacit ance C

< 4k

(RTH)

< 4k

(RTL)

= -40mA; Normal Operating Mode

CANH

= 40mA; Normal Operating Mode

CANL

= 0 ; TX = 0) I

CANH

= 14V; TX = 0) I

CANL

CANH

CANL

= 12V ,

= 0V;

V

V

V

V

V

CANH

V

I

wakeL-VwakeH

SE, CANH

SE, CANL

CANL,pu

CANH,pd

V

diff2

CANH

CANL

CANH

CANL

CANH

CANL

, V

CANH

CANL

wake,L

wake,H

diff

com

CANH

CANL

-3.2 -2.5 V

0.2 V

V

- 0.2 V

2-int

V

- 1.4 V

2-int

1.4 V

50 75 100 mA

50 90 130 mA

7.3 7.9 8.9 V

V

/2 +3 V

BAT

510uA

02uA

2.5 3 3.9 V

1.2 2 2.7 V

0.2 V

1.5 1.85 2.15 V

2.8 3.05 3.4 V

45 75 90 uA

45 75 90 uA

100 300 kohm

-10 10 V

/2+5 V

BAT

50 pF

CANL T o Ground Capacit ance C

to C

C

CANL

RTH, RTL Pins

RTL to V2-int Switch On Resistance (I
Operating Mode)

RTL to BA T Switch Series Resistance (term Vbat Mode) R

RTH To Ground Switch On Resistance (I
Operating Mode)

Thermal Shutdown

Capacitor Difference (Absolute V alue) DC

CANH

< -10mA; Normal

out

<10mA; Normal

out

CANL

can

R

rtl

rtl

R

rth

10 30 90 ohms

8 12.5 20 kohm

10 30 90 ohm

50 pF

10 pF

PC33889 9

For More Information On This Product,

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