Motorola MVME2431-1, MVME2403-1, MVME2431-3, MVME2401-1, MVME2432-1 Installation And Use Manual

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MVME2400 Series

VME Processor Module

Installation and Use

V2400A/IH3

August 2001

Printed in the United States of America.

Motorola

PowerStack PowerPC

and the Motorola symbol are registered trademarks of Motorola, Inc.

, VMEmoduleTM, and VMEsystemTM are trademarks of Motorola, Inc.

is a registered trademark and AIXTM, PowerPC 603TM, and PowerPC 604TM are trademarks of Internat ional Business Machine s Corporation and ar e used by Motorola, Inc. under license from International Business Machines Corporation.

SNAPHAT

, TIMEKEEPER®, and ZEROPOWER® are registered trademar ks of

STMicroelectronics. All other products ment io ned i n this document are tradema rks or registered trade marks of

their respective holders.

Safety Summary

The following general safety precautions must be observed during all phases of operation, service, and repair of this equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual could result in personal injury or damage to the equipment.

The safety precaut ions listed be low represent warnings of ce rtain danger s of which Mot orola is awar e. You, as the user of the product, should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment.

Ground the Instrument.

To minimize shock hazard, the equipment chassis and enclosure must be connected to an electrical ground. If the equipment is su pplied wi th a three-c onductor A C power ca ble, the po wer cable m ust be plug ged into an a pproved three-contact electrical outlet, with the grounding wire (green/yellow) reliably connected to an electrical ground (safety ground) at the power outlet. The power jack and mating plug of the power cable meet International Electrotechnical Commission (IEC) safety standards and local electrical regulatory codes.

Do Not Operate in an Explosive Atmosphere.

Do not operate the equipment in any explosive atmosphere such as in the presence of flammable gases or fumes. Operation of any electrical equipment in such an environment could result in an explosion and cause injury or damage.

Keep Away From Live Circuits Inside the Equipment.

Operating personnel must not remove equipment covers. Only Factory Authorized Service Personnel or other qualified service personnel may remove equipment covers for internal subassembly or component replacement or any internal adjust ment. Service pe rsonnel should n ot replace compon ents with power c able connected. Under certain conditions, dangerous voltages may exist even with the power cable removed. To avoid injuries, such personnel should always disconnect power and discharge circuits bef or e touching component s.

Use Caution When Exposing or Handling a CRT.

Breakage of a Cathode-Ray Tube (CRT) causes a high-velocity scattering of glass fragments (implosion). To prevent CRT implosion, do not handl e the CRT and avoid rough handling o r jarring of t he equipment . Handling o f a CRT should be done only by qualified service personnel using approved safety mask and gloves.

Do Not Substitute Parts or Modify Equipment.

Do not install substitute parts or perform any unauthorized modification of the equipment. Contact your local Motorola representative for service and repair to ensure that all safety features are maintained.

Observe Warnings in Manual.

W arn ings , such as th e exa mple be low, prece de po tent ially danger ous p roce dures th roug hout th is manu al . Instr uction s contained in the warnings m ust be follow ed. You should also employ all ot her safety precautions w hich you dee m necessary for the operation of the equ i pm ent in your operating environment.

To prevent serious injury or death from dangerous voltages, use extreme caution when handling, testing, and adjusting this equipment and its

Warning

components.

Flammability

All Motorola PWBs (printed wiring boards ) are manufactured with a flammability rating of 94V-0 by UL-recognized manufacturers.

EMI Caution

This equipment ge ner ates, uses a nd can radi ate el ectro magne tic energy . It

Caution

This product contains a lithium battery to power the clock and calendar circuitry.

Caution

may cause or be susceptible to electromagnetic interference (EMI) if not installed and used with adequate EMI protection.

Lithium Battery Caution

Danger of explosion if battery is re placed incorrect ly. Replace battery only with the same or equivalent type recommended by the equipment

manufacturer. Dispose of used batteries according to the manufacturer’s instructions.

Attention

Vorsicht

Il y a danger d’explosion s’il y a remplacement incorrect de la batterie. Remplacer uniquement avec une batterie du même type ou d’un type équivalent recommandé par le constructeur. Mettre au rebut les batteries usagées conformément aux instructions du fabricant.

Explosionsgefahr bei unsachgemäßem Austausch der Batterie. Ersatznur durch denselben ode r einen vom Herstel ler empfohle nen Typ. Entsorgu ng gebrauchter Batterien nach Angaben des Herstellers.

CE Notice (European Community)

Motorola Compute r Group pro ducts wi th the CE mar king co mply with the EMC Dir ective (89/336/EEC). Compliance with this directive implies conformity to the following European Norms:

EN55022 “Limits and Methods of Meas urement of Radio Int erferen ce Chara cteri stic s of Information Technology Equipment”; this product tested to Equipment Class B

EN55024 “Information te chnology equipment—Immunity char acteristics—Limits and methods of measurement”

Board products are tested in a representative system to show compliance with the above mentioned requirements. A proper installation in a CE-marked system will maintain the required EMC performance.

In accordance with European Community directives, a “Declaration of Conformity” has been made and is available on request. Please contact your sales representative.

Notice

While reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. a ssumes n o lia bility r esulti ng from any omissio ns in this docu ment, or from the use of the information obtained therein. Motorola reserves the right to revise th is document and to ma ke c hanges from time to time in the conten t he reof without obligation of Motorola to notify any person of such revision or changes.

Electronic versions of this material may be read online, downloaded for personal use, or referenced in another docu ment as a URL to the Motorol a Comput er Group web si te. The text itself may not b e published commerci ally in print o r electronic for m, edited, transla ted, or otherwise altered without the permission of Motorola, Inc.

It is possible th at t hi s publication may contain reference to or infor m at ion about Motorola products (machines and pr ograms), progra mming, or services that are not av ailable in your country. Such references or information must not be construed to mean that Motorola intends to announce such Motorola products, programming, or services in your country.

Limited and Restricted Rights Legend

If the documentation contained herein is supplied, directly or indirectly, to the U.S. Government, the following notice shall apply unless otherwise agreed to in writing by Motorola, Inc.

Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (b)(3) of t he Rig hts i n Technical Data clause a t DFARS 252.227-7013 (Nov.

1995) and of the Rights in Noncommerc ial Computer Software and Docume ntation c lause at DFARS 252.227-7014 (Jun. 1995).

Motorola, Inc. Computer Group 2900 South Diablo Way Tempe, Arizona 85282

About This Manual

Summary of Changes.................................................................................................xvi

Overview of Contents................................................................................................xvi

Comments and Suggestions......................................................................................xvii

Conventions Used in This Manual...........................................................................xviii

CHAPTER 1 Hardware Preparation and Installation

Introduction ................................................................................................................1-1

Description.................................................................................................................1-1

MVME240x Module...........................................................................................1-2

PMCspan Expansion Mezzanine........................................................................1-2

PCI Mezzanine Cards (PMCs)............................................................................1-3

VMEsystem Enclosure .......................................................................................1-3

System Console Terminal ...................................................................................1-3

Overview of Start-Up Procedures..............................................................................1-4

Unpacking Instructions..............................................................................................1-6

Hardware Configuration ............................................................................................1-6

MVME2400 Base Board Preparation........................................................................1-7

Flash Bank Selection (J8)...................................................................................1-9

System Controller Selection (J9)........................................................................1-9

Software-Readable Header (SRH) Switch (S3)................................................1-10

PMC Preparation......................................................................................................1-11

PMCspan Preparation ..............................................................................................1-11

System Console Terminal Preparation.....................................................................1-11

Hardware Installation...............................................................................................1-12

PMC Module Installation..................................................................................1-12

Primary PMCspan Installation..........................................................................1-14

Secondary PMCspan Installation......................................................................1-17

MVME240x Installation...................................................................................1-20

System Considerations.............................................................................................1-22

CHAPTER 2 Operating Instructions

Overview....................................................................................................................2-1

Applying Power.........................................................................................................2-1

vii

Switches..............................................................................................................2-3

ABT (S1).....................................................................................................2-3

RST (S2)............................................ ...... ..... ...............................................2-3

Front Panel Indicators (DS1 – DS4)...................................................................2-4

BFL (DS1).................................................... ...... ...... ...................................2-4

CPU (DS2)..................................................................................................2-4

PMC2 (DS3)................................................................................................2-4

PMC1 (DS4)................................................................................................2-4

10/100BaseT Port...............................................................................................2-5

DEBUG Port............................................. ..........................................................2-5

PMC Slots...........................................................................................................2-7

PCI MEZZANINE CARD (PMC Slot 1)....................................................2-7

PCI MEZZANINE CARD (PMC Slot 2)....................................................2-7

PMCspan ...................................................................................................................2-8

CHAPTER 3 Functional Description

Introduction ...............................................................................................................3-1

Features......................................................................................................................3-1

General Description...................................................................................................3-3

Block Diagram...........................................................................................................3-3

MPC750 Processor.............................................. ...... ...... ...................................3-5

L2 Cache .....................................................................................................3-5

Hawk System Memory Controller (SMC)/PCI Host Bridge (PHB) ASIC........3-6

PCI Bus Latency .........................................................................................3-7

PPC Bus Latency.........................................................................................3-9

Assumptions..............................................................................................3-11

Clock Ratios and Operating Frequencies..................................................3-11

PPC60x Originated....................................................................................3-11

PCI Originated ..........................................................................................3-12

SDRAM Memory.............................................................................................3-12

SDRAM Latency.......................................................................................3-13

Flash Memory...................................................................................................3-16

ROM/Flash Performance ..........................................................................3-17

Ethernet Interface.............................................................................................3-19

PCI Mezzanine Card (PMC) Interface.............................................................3-20

PMC Slot 1 (Single-Width PMC).............................................................3-21

PMC Slot 2 (Single-Width PMC).............................................................3-21

PMC Slots 1 and 2 (Double-Width PMC)................................................3-22

PCI Expansion........................................................................................... 3-22

VMEbus Interface ............................................... .................................. ...... .....3-22

viii

Asynchronous Debug Port................................................................................3-23

PCI-ISA Bridge (PIB) Controller.....................................................................3-23

Real-Time Clock/NVRAM/Timer Function.....................................................3-24

PCI Host Bridge (PHB)....................................................................................3-25

Interrupt Controller (MPIC)..............................................................................3-25

Programmable Timers.......................................................................................3-26

Interval Timers ..........................................................................................3-26

16/32-Bit Timers........................................................................................3-26

CHAPTER 4 Programming Details

Introduction................................................................................................................4-1

Memory Maps........................................ ...... ...... ........................................................4-1

Processor Bus Memory Map...............................................................................4-2

Default Processor Memory Map..................................................................4-2

PCI Local Bus Memory Map..............................................................................4-3

VMEbus Memory Map.......................................... .............................................4-3

Programming Considerations.....................................................................................4-4

PCI Arbitration ...................................................................................................4-4

Interrupt Handling...............................................................................................4-6

DMA Channels...................................................................................................4-8

Sources of Reset..................................................................................................4-8

Endian Issues....................................................................................................4-10

Processor/Memory Domain....................................... ................................4-10

PCI Domain...............................................................................................4-10

VMEbus Domain............................................ ...........................................4-11

CHAPTER 5 PPCBug

PPCBug Overview.....................................................................................................5-1

PPCBug Basics ..........................................................................................................5-1

Memory Requirements ..................................................... ...... ............................5-3

PPCBug Implementation....................................................................................5-3

MPU, Hardware, and Firmware Initialization ...........................................................5-3

Using PPCBug ...........................................................................................................5-5

Debugger Commands .........................................................................................5-6

Diagnostic Tests................................................................................................5-11

CHAPTER 6 Environment Modification

Overview....................................................................................................................6-1

CNFG – Configure Board Information Block........................................................... 6-2

ENV – Set Environment............................................................................................6-3

Configuring the PPCBug Parameters................................................................. 6-3

Configuring the VMEbus Interface..................................................................6-13

APPENDIX A Specifications

Specifications............................................................................................................A-1

Cooling Requirements..............................................................................................A-3

EMC Regulatory Compliance ..................................................................................A-4

APPENDIX B Connector Pin Assignments

Introduction .............................................................................................................. B-1

Pin Assignments....................................................................................................... B-1

VMEbus Connector – P1................................................................................... B-2

VMEbus Connector – P2................................................................................... B-3

Serial Port Connector – DEBUG (J2) ............................................................... B-5

Ethernet Connector – 10BaseT (J3).................................................................. B-5

CPU Debug Connector – J1.............................................................................. B-6

PCI Expansion Connector – J6.........................................................................B-11

PCI Mezzanine Card Connectors – J11 through J14....................................... B-14

PCI Mezzanine Card Connectors – J21 through J24....................................... B-17

APPENDIX C Troubleshooting

Solving Startup Problems.........................................................................................C-1

APPENDIX D Related Documentation

Motorola Computer Group Documents....................................................................D-1

Manufacturers’ Documents......................................................................................D-2

Related Specifications ..............................................................................................D -4

List of Figures

Figure 1-1. MVME2400 Switches, Headers, Connectors, Fuses, LEDs...................1-8

Figure 1-2. Software-Readable Header....................................................................1-10

Figure 1-3. Typical Single-width PMC Module Placement on MVME240x ..........1-14

Figure 1-4. PMCspan-002 Installation on an MVME240x .....................................1-16

Figure 1-5. PMCspan-010 Installation on a PMCspan-002/MVME240x...............1-18

Figure 2-1. PPCBug Firmware System Startup.........................................................2-2

Figure 2-2. MVME240x DEBUG Port Configuration ..............................................2-6

Figure 3-1. MVME240x Block Diagram...................................................................3-4

Figure 3-2. Timing Definitions for PPC Bus to SDRAM Access............................3-15

Figure 4-1. VMEbus Master Mapping.......................................................................4-5

Figure 4-2. MVME240x Interrupt Architecture........................................................4-7

List of T ables

T ab le 1-1. PMCspan Models.................................................... ...... ...... ......................1-3

T ab le 1-2. Start-Up Overview........................................................ ...... ..... .................1-4

T ab le 1-3. Jumper Settings............................................ .............................................1-7

T ab le 3-1. MVME240x Features ...............................................................................3-1

T ab le 3-2. Power Requirements........................................................... ..... ...... ...........3-5

Table 3-3. PCI Originated Latency Matrix................................................................3-7

Table 3-4. PCI Originated Bandwidth Matrix............................................................3-8

Table 3-5. PPC60x Originated Latency Matrix .........................................................3-9

Table 3-6. PPC60x Originated Bandwidth Matrix...................................................3-10

Table 3-7. Clock Ratios and Operating Frequencies................................................3-11

Table 3-8. 60x Bus to SDRAM Access Timing (100 MHz/PC100 SDRAMs).......3-13

Table 3-9. PPC Bus to ROM/Flash Access Timing (120ns @ 100 MHz)...............3-17

Table 3-10. PPC Bus to ROM/Flash Access Timing (80ns @ 100 MHz)...............3-18

Table 3-11. PPC Bus to ROM/Flash Access Timing (50ns @ 100MHz)................3-18

Table 3-12. PPC Bus to ROM/Flash Access Timing (30ns @ 100 MHz)...............3-19

Table 4-1. Processor Default View of the Memory Map...........................................4-2

T ab le 4-2. PCI Arbitration Assignments........................................ ...... ......................4-6

Table 4-3. Classes of Reset and Effectiveness...........................................................4-9

T ab le 5-1. Debugger Command s........................................ .......................................5-7

Table 5-2. Diagnostic Test Groups...........................................................................5-12

Table A-1. Specifications .........................................................................................A-1

Table B-1. P1 VMEbus Connector Pin Assignments .............................................. B-2

Table B-2. P2 Connector Pin Assignment ...............................................................B-3

Table B-3. DEBUG (J2)Connector Pin Assignments ..............................................B-5

Table B-4. 10/100 BASET (J3) Connector Pin Assignments ..................................B-5

Table B-5. Debug Connector Pin Assignments .......................................................B-6

Table B-6. J6 - PCI Expansion Connector Pin Assignments .................................B-11

Table B-7. J11 - J12 PMC1 Connector Pin Assignments ......................................B-14

Table B-8. J13 - J14 PMC1 Connector Pin Assignments ......................................B-15

Table B-9. J21 and J22 PMC2 Connector Pin Assignments .................................B-17

Table B-10. J23 and J24 PMC2 Connector Pin Assignments ...............................B-18

Table C-1. Troubleshooting MVME240x Modules .................................................C-1

Table D-1. Motorola Computer Group Documents .................................................D-1

Table D-2. Manufacturers’ Documents ...................................................................D-2

Table D-3. Related Specifications ...........................................................................D-4

xiii

About This Manual

The MVME2400 Series VME Processor Modules Installation and Use manual provides information to install and use your MVME2400 Series VME Processor Modules.

As of the publication date , the information presented in t his manual applies to the following MVME2400 series models:

Model Number Description

MVME2401-1 233 MHz MPC750, 32MB ECC SDRAM MVME2401-3 233 MHz MPC750, 64MB ECC SDRAM MVME2403-1 233 MHz MPC750, 32MB ECC SDRAM MVME2403-3 233 MHz MPC750, 32MB ECC SDRAM MVME2431-1 350 MHz MPC750, 32MB ECC SDRAM MVME2431-3 350 MHz MPC750, 32MB ECC SDRAM MVME2432-1 350 MHz MPC750, 64MB ECC SDRAM MVME2432-3 350 MHz MPC750, 64MB ECC SDRAM MVME2433-1 350 MHz MPC750, 128MB ECC SDRAM MVME2433-3 350 MHz MPC750, 128MB ECC SDRAM MVME2434-1 350 MHz MPC750, 256MB ECC SDRAM MVME2434-3 350 MHz MPC750, 256MB ECC SDRAM MVME2400-0321 450 MHz MPC750, 32MB ECC SDRAM MVME2400-0323 450 MHz MPC750, 32MB ECC SDRAM MVME2400-0331 450 MHz MPC750, 64MB ECC SDRAM MVME2400-0333 450 MHz MPC750, 64MB ECC SDRAM MVME2400-0341 450 MHz MPC750, 128MB ECC SDRAM MVME2400-0343 450 MHz MPC750, 128MB ECC SDRAM MVME2400-0351 450 MHz MPC750, 256MB ECC SDRAM MVME2400-0353 450 MHz MPC750, 256MB ECC SDRAM MVME2400-0361 450 MHz MPC750, 512MB ECC SDRAM MVME2400-0363 450 MHz MPC750, 512MB ECC SDRAM

Summary of Changes

This is the third edition of the Installation and Use manual. It supersedes the March 2000 edition and incorporates the following updates.

Date Changes

August 2001 All data referring to the VME CSR Bit Set Register

(VCSR_SET) and VM E CSR Bit Clear Regist e r (VCSR_CLR) has been deleted. These registers of the Universe II are unavailable for implementation as intended by the MVME materials and the Universe II User Manual.

March 2000 Addition of the 450 MHz produ ct confi gurations and a

general review of the manual’s accuracy and content.

Overview of Contents

Chapter 1, Hardware Preparation and Installation, provides a brief

description of the MVME2400 Seri es VME Processor Modul e along with instructions for preparing and installing the hardware.

Chapter 2, Operating I nst ructions, provides operating instruc tions for the

MVME2400, including information about powering up the system, and functionality of the switches, status indicators, and I/O ports on the front panels of the MVME2400 and PMCspan modules.

xvi

Chapter 3, Functional Des cription, provides a functi onal description of the

MVME2400, including an overview of the product and a detailed description of several blocks of circuitry.

Chapter 4, Programming Details, provides information useful in

programming the MVME2400, including a description of memory maps, control and statu s regi sters , PCI a rbitr atio n, inte rr upt handl ing, so urces o f reset, and big/little-endian issues .

Chapter 5, PPCBug, describes the basics of the PPCBug and its

architecture, along with the monitor (inter active command portion of the firmware), and gives information on using the PPCBug and the special commands.

Chapter 6, Environment Modification, contains information about the

CNFG and ENV commands. These two commands are used to change configuration information and command parameters interactively.

Appendix A, Specifications, lists the general specifications for the

MVME2400 VME processor module.

Appendix B, Connector Pin Assignments, pro vides the pin assignments for

the interconnect signals for the MVME2400.

Appendix C, Troubleshooting, provides simple troubleshooting tips for

your MVME2400 VME Processor Modules.

Appendix D, Related Documentation, includes all documentation related

to the MVME2400.

Comments and Suggestions

Motorola welcomes and appreciates your comments on its doc umentation. We want to know what y ou think about our manuals and how we can make them better. Mail comments to:

Motorola Computer Group Reader Comments DW164 2900 S. Diablo Way Tempe, Arizona 85282

You can also submit comments to the following e-mail address:

reader-comments@mcg.mot.com

In all your corres pondence , plea se li st your name, po siti on, and c ompan y. Be sure to include the title and par t number of the manual and tell how you used it. Then tell us your feelings about its strengths and weaknesses and any recommendations for improvements.

xvii

Conventions Used in This Manual

The following typographical conventions are used in this document: Unless otherwise s pecified, all address references are i n hexadecimal. An

asterisk (*) following the signal name for signals which are level significant denotes that the signal is true or valid when the signal is low. An asterisk (*) following the signal name for signals which are edge significant deno tes that the a ctions init iated by th at signal occu r on high to low transitio n.

$ do llar specifies a hexadecimal number & ampersand specifies a decimal number % percent specifies a binary number

bold

is used for user inpu t that you t ype just as i t appears ; it is al so used for commands, options and arguments to commands, and names of programs, directories and files.

italic

is used for names of variables to which you assign values. Italic is also used for comments in screen dis plays and examples, and to introduce new terms.

xviii

courier

is used for system output (for example, screen displays, reports), examples, and system prompts.

<CR> represents the carriage return or Enter key.

CTRL

represents the Control key. Execute control character s by pressing the Ctrl key and the letter simultaneously, for example, Ctrl-d.

In this manual, assertion and negation are used to specify forcing a signal to a particular stat e. In parti cular, a ssertion and asser t refe r to a signal tha t is active or true; negation and negate indicate a signal that is inactive or false. These terms ar e used independently of the vo ltage level (high or l ow) that they represent.

Data and address sizes are defined as follows:

❏ A byte i s eight bits, numb ered 0 through 7, wit h bit 0 being the leas t

significant.

❏ A word is 16 bits, numbered 0 th rough 15, wit h bit 0 bei ng the le ast

significant.

❏ A longword is 32 bi ts, numbered 0 through 31, with bit 0 being the

least significant.

The terms control bit, status bit, true, and false are used extensively in this document. The term control bit is used to describe a bit in a register that can be set and cleared under software control. The term true is use d to indicate that a bit is in the state that enables the fu nction it controls. The term false is used to indicate that the bit is in the state that disables the function it controls. In all tables, the terms 0 and 1 are used to describe the actual value that sh ould be written to the bit, or the value that it yields when read. The term status bit is used to describe a bit in a regi ster that reflects a specific condition. The status bit can be read by software to determine operational or exception conditions.

xix

1Hardware Preparation and

Introduction

This chapter provides a brief descr iption of the MVME2400 Series VME Processor Module. It also provides instruc tions for preparing an d installing

the hardware.Unless otherwise specified, the designation “MVME240x” refers to all models of the MVME2400 series modules.

Description

The MVME240x is a PCI Me zzanine Card (PMC) ca rrier board. It is based on the PowerPC

Two front panel cutouts provi de acce ss to PMC I/ O. One doubl e-wid th or two single-width PMCs can be installed directly on the MVME240x. Optionally, one or two PMCspan PCI expansion mezzanine modules can be added to provide the capability of up to four additional PMC modules.

Two RJ-45 connectors on the front panel provide the interface to 10/100BaseT Ethernet, and to a debug serial port.

Installation

™

750 microprocessor, MPC750.

The following list is of equipment that is appropriate for use in an MVME240x system:

❏ PMCspan PCI expansion mezzanine module ❏ Peripheral Component Interconnect (PCI) Mezzanine Cards

(PMC)s

❏ VMEsystem enclosure ❏ System console terminal ❏ Disk drives (and/or other I/O) and controllers ❏ Operating system (and/or application software)

1-1

Hardware Preparation and Installation

MVME240x Module

The MVME240x is a powerful, low-cost embedded VME controller and intelligent PMC carrier board. It includes support circuitry such as ECC SDRAM, PROM/Flash memory, and bridges to the Industry Standard

Architecture (ISA) bus and the VMEbus. The unit’s PMC carrier architecture al lo ws fl exible configuration options and easy upgrades. It is also designed to support one or two PMCs, plus one or two optional PCI expansion mezzanin e modules that eac h support up t o two PMCs. The un it occupies a single VMEmodule slot (except when optional PCI expansion mezzanine modules are also used).

The MVME240x interfaces t o the VMEbus via th e P1 and P2 connect ors, which use the new 5-row 160-p in c onnectors as specified in the proposed VME64 Extension Standard. It also draws +5V, +12V, and –12V power from the VMEbus backplane through these two con nectors. The +3.3V and

2.5V power, used for the PCI bridge chip and possibly for the PMC mezzanine, is derived onboard from the +5V power.

Support for two IEEE P1386.1 PCI mezza nine car ds is pro vided vi a eight 64-pin SMT connectors. Front panel openings are provided on the board for the two PMC slots.

In addition, there are 64 pins of I/O from PMC slot 1 and 46 pins of I/O from PMC slot 2 that are ro uted to P2. The two PMC slo ts may contain two single-wide PMCs or one double-wide PMC. There are also two RJ-45 connectors on the front panel: one for the Ethernet 10BaseT/100BaseTX interface, and one for the async serial debug port. The front panel also includes reset and abort switches and status LEDs.

PMCspan Expansion Mezzanine

An optional PCI expansion mezzanine module or PMC carrier board, PMCspan, provides the capability of adding two additional PMCs. Two PMCspans can be stacked on an MVME240x, providing four additional

1-2 Computer Group Literature Center Web Site

PMC slots, for a total of six slots including the two onboard the MVME240x. The following table lists the PMCspan models that are available for use with the MVME240x.

Table 1-1. PMCspan Models

Expansion Module Description

PMCSPAN-002 Primary PCI expansion mezzanine module. Allows two PMC

modules for the MVME240x. Includes 32-bit PCI bridge.

PMCSPAN-010 Secondary PCI expansion mezzanine module. Allows two

additional PMC modules for the MVME240x. Does not include 32-bit PCI bridge; requires a PMCSPAN-002.

PCI Mezzanine Cards (PMCs)

The PMC slots on the MVME240x board are IEEE P1386.1 compliant. P2 I/O-based PMCs that follow the PMC commi ttee recommendat ion for PCI I/O when using the 5-row VME64 extension connector will be pin-out compatible with the MVME240x.

Description

The MVME240x board supports both front panel I/ O and rear panel P 2 I/O through either PMC slot 1 o r PMC slot 2. 64 pins o f I/O from slot 1 and 46 pins of I/O from slot 2 are routed directly to P2.

VMEsystem Enclosure

Your MVME240x board must be installed in a VMEsystem chassis with both P1 and P2 backplane connections. It requires a single slot, except when PMCspan carrier boards are used. Allow one extra slot for each PMCspan.

System Console Terminal

In normal operation, connection of a debug console terminal is required

only if you intend to use the MVME240x’s debug firmware, PPCBug, interactively. An RJ-45 connector is provided on the front panel of the MVME240x for this purpose.

http://www.motorola.com/computer/literature 1-3

Hardware Preparation and Installation

Overview of Start-Up Procedures

The following table li sts the th ings you will need to do bef ore you can use this board, and tells where to find the information you need to perform each step. Read this chapter in its entirety along with all Caut ion and Warning notes before beginning.

Table 1-2. Start-Up Overview

What you need to do... Refer to...

Unpack the hardware. Unpacking Instructions on page 1-6 Set jumpers on the MVME240x

module. Prepare the PMCs. PMC Preparation on page 1-11

Prepare the PMCspan module(s). PMCspan Pr ep ar at i on on page 1-11

Prepare any other optional

devices or equipment you’ll be using.

Install the PMCs on the MVME240x module.

Install the primary PMCspan module (if used).

Install the secondary PMCspan module (if used) (Cont’d).

Hardware Configuration on page 1-6

For additional information on PMCs, refer to the PMC manuals provided with these cards.

For additional information on PMCspan, refer to the PMCspan PMC Adapter Carrier Module Installation

and Use manual, listed in Appendix D, Related

Documen tation.

For more information on optional devices and equipment, refer to the documentation provided with that equipment.

PMC Module Installation on page 1-12 PMC Slots on page 2-7

For additional information on PMCs, refer to the PMC manuals provided with these cards.

Primary PMCspan Installation on page 1-14

For additional information on PMCspan, refer to the PMCspan PMC Adapter Carrier Module Installation

and Use manual, listed in Appendix D, Related

Documen tation. Secondary PMCspan Installation on page 1-17

For additional information on PMCspan, refer to the PMCspan PMC Adapter Carrier Module Installation

and Use manual, listed in Appendix D, Related

Documen tation.

1-4 Computer Group Literature Center Web Site

Overview of Start-Up Procedures

Table 1-2. Start-Up Overview (Continued)

What you need to do... Refer to...

Install the MVME240x module in a chassis.

Connect a console terminal. System Consideratio ns on page 1-22

Connect any other optiona l devices or equipment you will b e using.

Power up the system. Applying Power on page 2-1

Examine the environmental parameters and make any changes needed.

Program the MVME240x module and PMCs as needed for your applications.

MVME240x Installation on page 1-20

DEBUG Port on page 2-5

Appendix B, Connector Pin As signments

For more information on optional devices and equipment, refer to the documentation provided with that equipment.

Front Panel Indicators (DS1 – DS4) on page 2-4

If any problems occur, refer to Diagnostic Tests on

page 5-11.

You may also wish to obtain the PPCBug Diagnostics

Manual, listed in Appendix D, Related

Documentation. ENV – Set Environment on page 6-3

You may also wish to obtain the PPCBug Firmwar e Package User’s Manual, listed in Appendix D,

Related Documentation. MVME2400 Base Board Preparation on page 1-7

Chapter 4, Pr ogramming Details

For additional information on PMCs, refer to the PMC manuals provided with these cards.

You may also wish to obtain the MVME2400 Series

VME Processor Module Programmer’s Reference Guide, listed in Appendix D, Related Documentation.

http://www.motorola.com/computer/literature 1-5

Hardware Preparation and Installation

Unpacking Instructions

Note If the shipping carton is damaged upon receipt, request that the

carrier’s agent be present during the unpa cking and inspe ction of the equipment.

Unpack the equipment fr om the shipping carton. Refer to the packing list and verify that al l items are present. Save the packi ng mat er ia l for storing and reshipping of equipment.

Avoid touching areas of integrated circuitry; static discharge can damage

Caution

these circuits.

Hardware Configuration

To produce the desired configuration and ensure proper operation of the MVME2400, you may need to carry out certain hardware modifications before installing the module.

The MVME2400 provides software control over most options: by setting bits in control registers after installing the module in a system, you can modify its configur ation . The MVME24 00 con trol regist ers ar e descr ib ed in Chapter 3, Functional Description, and/or in the MVME2400 Series VME Processor Module Programmer’s Reference Guide listed under

Appendix D, Related Documentation.

Some options, however, are not sof tware-programmabl e. Such options are controlled through manual installation or removal of header jumpers or interface modules on the base board.

1-6 Computer Group Literature Center Web Site

MVME2400 Base Board Preparation

Figure 1-1 illustrates the placement of the switches , jumper headers,

connectors, and LED indicators on the MVME240x. Manually configurable ite ms on the base board are liste d in the following table. Refer to the sections or figures listed along side the jumper function for more information.

Table 1-3. Jumper Settings

Jumper Function

J8 Flash Bank Selection (J8) on page 1-9 J9 System Controller Selection (J9) on page 1-9

S3 Software-Readable Header (SRH) Switch (S3) on page 1-10

The MVME240x has been factory tested and is shipped with the configurations described in the following sections. The MVME240x factory-installed debug monitor, PPCBug, operates with those factory settings.

http://www.motorola.com/computer/literature 1-7

Hardware Preparation and Installation

MVME

DEBUG

ABT

RST

10/100 BASET

PCI MEZZANINE CARD PCI MEZZANINE CARD

240x

BFL

CPU

PMC

DEBUG

PORT

SWITCH

ABORT

S1 S2

SWITCH

RESET

ETHERNET

PORT

189 190

FLASH SOCKETS

XU1 XU2

U10

PMC 2 PMC1

264

J21

264

J23

A1B1C1

264

A32

B32

C32

D32

J22

264

J24

264

U22U17

U19

2427 9812

U21U16

U20U15

1 2 3 4 5 6 7 8

U23U18

U25

113 114

J11

264

J13

A1B1C1

264

J12

264

J14

D32D1

A32

B32

C32

VME BUS

Figure 1-1. MVME2400 Switches, Headers, Connectors, Fuses, LEDs

1-8 Computer Group Literature Center Web Site

Flash Bank Selection (J8)

Bank B consists of 1MB of 8 -bit Fla sh memory in two 32- pin PLCC 8-b it sockets.

Bank A consists of four 16-bit devices that are populated with 16Mbit Flash devices (8MB). A jumper header, J8, associated with the first set of four Flash devices provides a total of 64KB of hardware-protected boot block. Only 32-bit wri tes are sup ported for thi s bank of Fla sh. The address of the reset vector is jumper-selectable. A jumper must be installed either between J8 pins 1 and 2 for Bank A factory configuration, or between J8 pins 2 and 3 for Bank B. When the jumper is installed, the SMC (System Memory Controller) of the Hawk ASIC maps 0xFFF00100 to the Bank B sockets.

MVME2400 Base Board Preparation

1 2

Bank A (factory configuration)

System Controller Selection (J9)

The MVME240x is factory-configured in automatic system controller mode; that is, a jumper is installed across pins 2 and 3 of header J9. This means that the MVME 240x de termi nes if i t is syste m cont roll er at syst em power-up or reset by its position on the bus; if it is in slot 1 on the VME system, it configures itself as the system controller.

Remove the jumper from J9 if you intend to operate the MVME240x as system controller in all cases.

Install the jumper acro ss pins 1 and 2 if the MVME240x will not to ope rate as system controller under any circumstances.

1 2

Bank B

http://www.motorola.com/computer/literature 1-9

Hardware Preparation and Installation

1 2

Automatic System Controller

(factory configuration)

System Controller Enabled

1 2

System Controller Disabled

Software-Readable Header (SRH) Switch (S3)

Switch S3 is an eight pole single-throw switch wi th software re adable switch settings. These settings can be read as a register at ISA I/O address $801 (hexadecimal). Each switch pole can be set to either logic 0 or

logic 1. A logic 0 means the switch is in the “ON” position for that particular bit. A logi c 1 means t he switc h is in t he “OFF” pos ition for tha t particular bit. SRH Regi ster Bit 0 is asso ciated with Pin 1 and Pin 16 of the SRH, and SRH Register Bit 7 is associated with Pin 8 and Pin 9 of the SRH. The SRH is a read-only register.

If Motorola’s PowerPC firmware, PPCBug, is being used, it reserves all bits, SRH0 to SRH7. If it is not being used, the switch can be used for other applications.

1 2

12345678

16 16

ON ON

SRH0 = 0 SRH1 = 0 SRH2 = 0 SRH3 = 0 SRH4 = 0 SRH5 = 0 SRH6 = 0 SRH7 = 0

12345678

SRH0 = 1 SRH1 = 1 SRH2 = 1 SRH3 = 1 SRH4 = 1 SRH5 = 1 SRH6 = 1 SRH7 = 1

Figure 1-2. Software-Readable Header

1-10 Computer Group Literature Center Web Site

PMC Preparation

For a discussion of any configurable it ems on the PMCs, refer to the user’s manual for the particular PMCs.

PMCspan Preparation

You will need to use an additional slot in the VME chassis for each PMCspan expansion module you plan to us e. Before installing a PMCspan on the MVME240x, you must install t he selecte d PMCs on the PMCspan. Refer to the PMCspan PMCAdapter Carrier Module Installation and Use manual for instructions.

System Console Terminal Preparation

Ensure that the switc hes are set in the proper positi on for all bits on switch S3 of the MVME240x board as shown in Figure 1-2. This is necessary when the PPCBug firmware is used. Connect the ter minal via a cable to th e RJ-45 DEBUG connector J2. See Table B-3 on page B-5 for pin signal assignments. Set up the terminal as follows:

PMC Preparation

❏ Eight bits per character ❏ One stop bit per character ❏ Parity disabled (no parity) ❏ Baud rate = 9600 baud (default baud rate of the port at power-up);

after power-up, you can reconfigure the baud rate with PPCBug’s PF command

http://www.motorola.com/computer/literature 1-11

Hardware Preparation and Installation

Hardware Installation

The following paragraphs discuss installing PMCs onto the MVME240x, installing PMCspan modules onto the MVME240x, installing the MVME240x into a VME chassis, and connecting an optional system console terminal.

Use ESD

Wrist Strap

Motorola strongly recommends that you use an a ntistatic wrist stra p and a conductive foam pad when installing or upgrading a system. Electronic components, such as d isk dr ives, c omputer boards , and memor y modules , can be extremely sensitive to electrostatic discharge (E SD). After removing the component from its protective wrapper or from the system, place the componen t flat on a grounded, static -free surface (an d, in the case of a board, component side up). Do not slide the component over any surface.

If an ESD station is not available, you can avoid damage resulting from ESD by wearing an antistatic wrist strap (available at electronics stores) that is attached to an active electrical ground. Note that a system chassis may not be grounded if it is unplugged.

PMC Module Installation

PCI mezzanine card (PMC) modules mount on top of the MVME240x module, and/or on a PMCspan. Refer to Figure 1-3 on page 1-14 and perform the following st eps to install a PMC on your MVME240 x module.

Note This procedure assu mes that you have read t he user’s manual t hat

came with your PMCs.

1. Attach an ESD strap to your wri st. Att ach the o ther en d of the ESD strap to the chassis as a ground. The ESD strap must be secured to your wrist and to ground throughout the procedure.

2. Perform an operating system shutdown. Turn the AC or DC power off and remove the AC cord or DC power lines from the system. Remove chassis or system cover(s) as necessary for access to the VME modules.

1-12 Computer Group Literature Center Web Site

Caution

Warning

Caution

Hardware Installation

Inserting or removing modules with power applied may result in damage to module components.

Dangerous voltages, capable of causing death, are present in this equipment. Use extreme caution when handling, testing, and adjusting.

3. Carefully remove the MVME2400 from its VMEbus card slot and lay it flat, with connectors P1 and P2 facing you.

Avoid touching areas of integrated circuitry; static discharge can damage these circuits.

4. Remove the PCI filler pla te fr om the selec ted PMC slo t in t he fron t panel of the MVME240x. If inst alling a double-width PMC, remove the filler plates from both PMC slots .

5. Slide the edge connector (s) of the PMC mo dule into the fr ont panel opening(s) from behind and place the PMC module on top of the MVME240x. The four connectors on the underside of the PMC module should then connect smoothly with the corresponding connectors for a single-width PMC (J11/J12/J13/J14 or J21/J22/J23/J24, all eight for a double-width PMC) on the MVME240x.

http://www.motorola.com/computer/literature 1-13

Hardware Preparation and Installation

Figure 1-3. Typical Single-width PMC Module Placement on MVME240x

6. Insert the two short Phi llips screws t hrough the holes at the forward corners of the PMC module, i nto t he st andoff s on t he MVME240x . Tighten the screws.

7. If installing two singl e-width PMCs, repeat the abo ve procedure for the second PMC.

Primary PMCspan Installation

To install a PMCspan-002 PCI expansion module on your MVME240x, refer to Figure 1-4 on page 1-16 and perform the following steps:

Note This procedure assu mes that you have read t he user’s manual t hat

was furnished with the PMCsp an, and t hat you have instal led the selected PMCs on the PMCspan according to the instructions given in the PMCspan and PMC manuals.

1-14 Computer Group Literature Center Web Site

Caution

Warning

Hardware Installation

1. Attach an ESD strap to your wri st. Att ach the o ther en d of the ESD strap to the chassis as a ground. The ESD strap must be secured to your wrist and to ground throughout the procedure.

Inserting or removing modules with power applied may result in damage to module components.

Dangerous voltages, capable of causing death, are present in this equipment. Use extreme caution when handling, testing, and adjusting.

3. Carefully remove the MVME2700 from its VMEbus card slot and lay it flat, with connectors P1 and P2 facing you.

Avoid touching areas of integrated circuitry; static discharge can damage

Caution

http://www.motorola.com/computer/literature 1-15

these circuits.

4. Attach the four standoffs to the MVME240x module. For each standoff:

– Insert the threaded end into the standoff hole at each corner of

the VME processor module. – Thread the locking nuts onto the standoff tips. – Tighten the nuts with a box- end wrenc h or a pair of needl e nose

pliers.

Hardware Preparation and Installation

2081 9708

Figure 1-4. PMCspan-002 Installation on an MVME240x

1-16 Computer Group Literature Center Web Site

5. Place the PMCspan on top of the MVME240x module. Align the mounting holes in each corner to the standoff s, and align PMCspan connector P4 with MVME240x connector J6.

6. Gently press the PMCspan an d MVME240 x tog et her , ma kin g sur e that P4 is fully seated in J6.

7. Insert the four short Phi llips s crews thr ough the holes at the corn ers of the PMCspan and into the standoffs on the MVME240x module. Tighten the screws.

Note The screws have two different head diameters. Use the screws

with the smaller heads on the standoffs next to VMEbus connectors P1 and P2.

Secondary PMCspan Installation

The PMCspan-010 PCI expansion module mounts on top of a PMCspan-002 PCI expansion module. To insta ll a PMCspan-010 on your MVME240x, refer to Figure 1-5 and perform the following steps:

Hardware Installation

Note This procedure assu mes that you have read t he user’s manual t hat

was furnished with the PMCsp an, and t hat you have instal led the selected PMCs on the PMCspan according to the instructions given in the PMCspan and PMC manuals.

1. Attach an ESD strap to your wri st. Att ach the o ther en d of the ESD strap to the chassis as a ground. The ESD strap must be secured to your wrist and to ground throughout the procedure.

http://www.motorola.com/computer/literature 1-17

Hardware Preparation and Installation

2065 9708

Figure 1-5. PMCspan-010 Installation on a PMCspan-002/MVME240x

1-18 Computer Group Literature Center Web Site

Caution

Warning

Caution

Hardware Installation

Inserting or removing modules with power applied may result in damage to module components.

Dangerous voltages, capable of causing death, are present in this equipment. Use extreme caution when handling, testing, and adjusting.

3. If the Primary PMC Carrier Module/MVME240x assembly is already installed in the VME chassis, carefully remove the twoboard assembly from the VMEbus card slots and lay it fl at, with the P1 and P2 connectors facing you.

Avoid touching areas of integrated circuitry; static discharge can damage these circuits.

4. Remove the four short Phillips screws from the standoffs in each corner of the primary PCI expansion module, PMCspan-002.

5. Attach the four standoffs to the PMCspan-002.

6. Place the PMCspan-010 on top of the PMCspan-002. Align the mounting holes in each corner to the standoffs, an d align PMCspan010 connector P3 with PMCspan-002 connector J3.

7. Gently press the two PMCspan modules togethe r, making sure th at P3 is fully seated in J3.

8. Insert the four short Phi llips s crews thr ough the holes at the corn ers of PMCspan-010 and into the standoffs on the primary PMCspan-

002. Tighten the screws.

Note The screws have two different head diameters. Use the screws

with the smaller heads on the standoffs next to VMEbus connectors P1 and P2.

http://www.motorola.com/computer/literature 1-19

Hardware Preparation and Installation

MVME240x Installation

Before installing the MVME240x in to you r VME ch ass is, ensure that the jumpers on the MVME240x J8, J9, and S3 switch are configured, as previously described. This procedure assumes that you have already installed the PMCspan( s) if de sired, and any PMCs th at you have selecte d.

Proceed as follows to install the MVME240x in the VME chassis:

1. Attach an ESD strap to your wri st. Att ach the o ther en d of the ESD strap to the chassis as a ground. The ESD strap must be secured to your wrist and to ground throughout the procedure.

Inserting or removing modules with power applied may result in damage

Caution

to module components.

Dangerous voltages, capable of causing death, are present in this

Warning

1-20 Computer Group Literature Center Web Site

equipment. Use extreme caution when handling, testing, and adjusting.

3. Remove the filler panel from the card slot where you are going to install the MVME240x. If you have install ed one or more PMCspan PCI expansion modules onto your MVME240x, you will need to remove filler panels from one additional card slot for each PMCspan, above the card slot for the MVME240x.

– If you intend to use the MVME240x as system c ontroller, it must

occupy the left-most card slot (slot 1). The system controller must be in slot 1 to correctly initiate the bus-grant daisy-chain and to ensure proper operation of the IACK daisy-chain driver.

– If you do not int end to use the MVME240x as s ystem contro ller,

it can occupy any unused card slot.

Caution

Hardware Installation

Avoid touching areas of integrated circuitry; static discharge can damage these circuits.

4. Slide the MVME240x (and PMCspans if used) into the selected card slot(s). Be sure the module or modules is/are seated properly in the P1 and P2 connectors on t he backpla ne. Do not damage or bend connector pins.

5. Secure the MVME240x (and PMCspans if us ed) in the chass is with the screws provided, making good contact with the transverse mounting rails to minimize RF emissions.

Note Some VME backplanes (for example, those used in Motorola

“Modular Chassis” systems) have an auto-jumpering feature for automatic propagatio n of th e IACK and BG signals. Step 6 does not apply to such backplane designs.

6. On the chassis backplane, remove the (IACK) and

BUS GRANT (BG) jumpers from the header for t he card

INTERRUPT ACKNOWLEDGE

slot occupied by the MVME240x.

7. If you intend to use PPCBug interactivel y, connect the terminal that is to be used as the PPCBug system console to the

DEBUG port on

the front panel of the MVME240x. In normal operation the host CPU controls MVME240x operation

via the VME bus Universe registers.

8. Replace the chassis or system cover(s), cable peripherals to the panel connectors as a ppr opriate, reconnect the system to the AC or DC power source, and turn the equipment power on.

9. The MVME240x’s green confidence tests is run, and the debugger prompt

CPU LED indicates activity as a set of

PPC1-Bug>

appears.

http://www.motorola.com/computer/literature 1-21

Hardware Preparation and Installation

System Considerations

The MVME240x draws power from the VMEbus backplane connectors P1 and P2. P2 is also used for the upper 16 bits of data in 3 2-bit tr ansfers, an d for the upper eight address lines in extended addressing mode. The MVME240x may not function properly wit hout it s main boar d connect ed to VMEbus backplane connectors P1 and P2.

Whether the MVME240x operates as a VMEbus master or as a VMEbus slave, it is c onfigured for 3 2 bits of address and 32 bits o f data (A32/D32). However, it handles A1 6 or A24 devi ces in the address ran ges indicated in

Chapter 4, Programming Details. D8 and/or D16 devices in the system

must be handled by the PowerPC processor software. Refer to the memory maps in Chapter 4, Programming Details.

The MVME240x contains shared onboard DRAM whose base address is software-selectable. Both the onboard processor and off-board VMEbus devices see this local DRAM at base physical address $00000000, as programmed by the PPCBug fi rmware. This may be ch anged via software to any other base address. Refer to the MVME240x Programmer’s Reference Guide for more information.

If the MVME240x tries to access off-board resources in a nonexistent location and is not system controller, and if the system does not have a global bus timeout, the MVME240x waits forever for the VMEbus cycle to complete. This will cause the system to lock up. There is only one situation in which th e syste m might lack th is gl obal bus timeou t: when t he MVME240x is not the system controller and th ere is no global bus timeout elsewhere in the system.

Multiple MVME240x boards may be installed in a single VME chassis. Each must have a unique Universe address, selected by setting jumper s on its J17 header, as described in MVME2400 Base Board Preparation. In general, hardware multiprocessor features are supported.

Other MPUs on the VMEbus can interrupt, disable, communicate with, and determine the opera tional status of the proc essor(s). One registe r of the Universe set incl udes four bits that function as location monit ors to allow

1-22 Computer Group Literature Center Web Site

System Considerations

one MVME240x processor to b roadcast a si gnal to any other MVME240x processors. All eight registers are accessible from any local processor as well as from the VMEbus.

http://www.motorola.com/computer/literature 1-23

2Operating Instructions

Overview

This chapter provides operating instructions for the MVME240x. This includes information about powering up the system, and functionality of the switches, status indicators, and I/O ports on the front pane ls of the MVME240x and PMCspan modules.

Applying Power

After you have verified that all necessary hardware preparation has been done, that all connections have been made correctly, and that the installation is complete, you can power up the system. The MPU, hardware, and firm ware initializa tion process is perf ormed by the PPCBug firmware power-up or system reset. The fi rmware initializes t he devices on the MVME240x module in preparation for booting the operating system.

The firmware is shipped from the factory with an appropriate set of defaults. In most cases there is no need to mo dify the firmware configuration before you boot the operating system. Refer to Chapter 6,

Environment Modification for furthe r information about modifyin g

defaults. The following flowchart in Figure 2-1 shows the basic initialization

process that takes place during MVME240x system start-ups. For further information on PPCbug, refer to the following items:

❏ Chapter 5, PPCBug ❏ Appendix C, Troubleshooting ❏ PPCBug documentation listed in Appendix D, Related

Documentation.

2-1

Operating Instructions

STARTUP

INITIALIZATION

POST

BOOTING

MONITOR

Power-up/reset initialization

Initialize devices on the MVME240x module/system

Power On Self Test diagnostics

Firmware-configured boot mechanism, if so configured. Default is no boot.

Interactive, command-driven on-line PowerPC debugger, when terminal connected.

Figure 2-1. PPCBug Firmware System Startup

2-2 Computer Group Literature Center Web Site

Applying Power

Switches

ABT (S1)

RST (S2)

There are two switches (ABT and RST) located on the MVME240x front panel.

When activated by software, the Abort switch,

ABT, can generate an

interrupt signal from the base board to the processor at a userprogrammable level. The interrupt is normally used to abort program execution and return cont rol to the debugger firmware located in the MVME240x Flash memory. The interrupt signal reaches the processor module via ISA bus interrup t line IRQ8

∗. The signal is also available from

the general purpose I/O port, which allows software to poll the Abort switch after an IRQ8* interrupt and verify that it has been pressed.

The interrupter connect ed to the

ABT switch is an edge-sensitive circuit,

filtered to remove switch bounce.

The Reset switch, be asserted in the MPC603 or MPC604. It also drives a

RST, resets all onboard devices and cau ses HRESET* to

SYSRESET*

signal if the MVME240x VME proce ssor modu le i s the syst em co ntroller .

The Universe ASIC includes both a global and a local reset driver. When the Universe operates as the VMEbus system controller, the reset driver provides a global system reset by asserting the VMEbus signal SYSRESET*. A SYSRESET* signal may be generated by the RESET switch, a power-up reset, a watchdog timeout, or by a control bit in the Miscellaneous Control Register (MISC_CTL) in the Universe ASIC. SYSRESET* remains asserted for at least 200 ms, as required by the VMEbus specification.

http://www.motorola.com/computer/literature 2-3

Operating Instructions

Front Panel Indicators (DS1 – DS4)

There are four LED (light-emitting diode) front panel indicators located on the MVME240x front panel:

CPU

, PMC2, and PMC1.

BFL (DS1)

The yellow the BRDFAIL* signal line is active.

BFL LED indicates board f ai lu re; l ig hts whe n

BFL,

MVME

DEBUG

ABT

RST

10/100 BASET

240x

BFL

CPU

PMC

CPU (DS2)

The green

CPU LED indicates CPU activity; lights when

the DBB* (Data Bus Busy) signal line on the processor bus is active.

PCI MEZZANINE CARD PCI MEZZANINE CARD

PMC2 (DS3)

The top green

PMC LED indicates PCI activity; lights

when the PCI bus grant to PMC2 signal line on the PCI bus is active. This ind icates that a PMC installed on slot 2 is active.

PMC1 (DS4)

The bottom green

PMC LED indicates PCI activity; lights

when the PCI bus grant to PMC1 signal line on the PCI bus is active. This ind icates that a PMC installed on slot 1 is active.

2-4 Computer Group Literature Center Web Site

Applying Power

10/100BaseT Port

The RJ-45 port on the front p anel of the MVME240x labeled 10 /100 BASET supplies the Ethernet LAN 10BaseT/100Base TX interface, implemented with a DEC 21140/21143 device.

Similarly, the Universe ASIC sup pli es an inpu t si gnal and a control bit to initiate a local reset operation. By setting a control bit, software can maintain a board in a reset state, disabling a faulty board from participating in normal system operation. The local reset driver is enabled even when the Universe ASIC i s not syst em controll er. Local rese ts may be g enerated

RST switch, a power-up reset, a watchdog timeout, a VMEbus

by the SYSRESET*, or a control bit in the MISC_CTL register.

DEBUG Port

The RJ-45 port labeled DEBUG on the front panel of the MVME240x supplies the MVME240x serial communications interface, implemented via a UART PC16550 controller chip from National Semiconductor. It is asynchronous only. This se ri al port is configured for EIA-232-D DTE, as shown in Figure 2-2.

DEBUG port may be used for connect ing a terminal to the MVME2 40x

The to serve as the firmware console for the factory installed deb ugger, PPCBug. The port is configur ed as follows:

❏ 8 bits per character ❏ 1 stop bit per character ❏ Parity disabled (no parity) ❏ Baud rate = 9600 baud (default baud rate at power-up)

After power-up, the baud rate of the

DEBUG port can be reconfigured by

using the debugger’s Port Format (PF) command. Refer to Chapte r 5,

PPCBug and Chapter 6, Environment Mo dif i cation for information about

the PPCBug.

http://www.motorola.com/computer/literature 2-5

Operating Instructions

SOUT RTS*

DTR* SIN CTS* DCD*

PC16550

MVME240x

4 2 8 5 7 1 3

Debug RJ45

Figure 2-2. MVME240x DEBUG Port Configuration

2-6 Computer Group Literature Center Web Site

Applying Power

PMC Slots

Two openings located on the front panel provide I/O expansion by allowing access to one or two 4-port singlewide or one 8-port double-wide PCI Mezzanine Card (PMC), connected to the PMC connectors on the MVME240x. Refer to Appendix B, Connector Pin

Assignments for additional information on pin as si gnment s

for the PMC connectors.

Do not attempt to install any PMC boards without

Warning

PCI MEZZANINE CARD (PMC Slot 1)

performing an operati ng system shutdown and following t he

procedures given in the user’s manual for the particular PMC.

The right-most (lower) opening labeled

CARD on the MVME240x front panel provides front panel

I/O access to a PMC that is connected to the 64-pi n connectors J11 through J14 on the MVME240x module. Connector J14 allows rear panel P2 I/O.

PCI MEZZANINE

PMC2

PMC1

PCI MEZZANINE CARD PCI MEZZANINE CARD

This slot is MVME240x Port 1.

PCI MEZZANINE CARD (PMC Slot 2)

The left-most (upper) opening labeled

CARD on the MVME240x front panel provides front panel

PCI MEZZANINE

I/O access to a PMC that is connected to the 64-pi n connectors J21 through J24 on the MVME240x module. Connector J24 allows rear panel P2 I/O.

This slot is MVME240x Port 2.

http://www.motorola.com/computer/literature 2-7

Operating Instructions

PMCspan

A PMCspan front panel is pictured on the previous page. The front panel is the same for all PMCspan model s.

There are two PMC slots, labeled either two single-wide PMCs or one double-wide PMC.

The PMCspan board has two sets of three 32-bit connectors for PMC interface to a secondary PCI bus and a user-specific I/O. It also has a P1 connector and a 5-row P2 connector for power and VMEbus I/O.

The PMCspan has two green LEDs on its front panel, one for each PMC slot, labeled individual LED is illuminated whenever a PMC has been granted bus mastership of the secondary PCI bus.

The right-most (l ower) opening l abeled panel is Port 1.

The left-most (upper) ope ni ng la bel ed panel is Port 2.

PCI MEZZANINE CARD, which support

PMC2 and PMC1. Both LEDs are illuminated du ring rese t. An

PCI MEZZANINE CARD on the front

2-8 Computer Group Literature Center Web Site

3Functional Description

Introduction

This chapter provides a functional description of the MVME240x. This includes an overview of the produ ct, followed by a detailed descri ption of several blocks of circuitry. Figure 3-1 depicts a block diagram of the overall board architecture.

Detailed descriptions of other MVME240x blocks, including programmable registe rs in the ASICs and peripheral c hips, can be f ound in the MVME2400 Series VME Processor Module Programmer’ s Refere nce Guide, listed in Appendix D, Related Documentation.

Features

The following table summarizes the features of the MVME240x.

Table 3-1. MVME240x Features

Feature Des cription

233 MHZ MPC750 PowerPC

Microprocessor

Form factor 6U VMEbus SDRAM

L2 Cache

Flash memory

Memory Controller Hawk’s SMC (System Memory Controller)

PCI Host Bridge Hawk’s PHB (PCI Host Bridge) Interrupt Controller Hawk’s MPIC (Multi-Processor Interrupt Controller)

350 MHZ MPC750 PowerPC 450 MHZ MPC750 PowerPC

Double-Bit-Error detect, Single-Bit-Error correct across 72 bits 32MB, 64MB, or 128MB SDRAM

Build-option for 1MB back side L2 Cache using late write or burstmode SRAMS

Sockets for 1MB 8MB Soldered on-board

processor processor processor

3-1

Functional Descr iption

Table 3-1. MVME240x Features (Continued)

Feature Des cription

PCI Interface 32/64-bit Data, 33 MHz operation Real-time clock

Peripheral Support

Switches Reset Status LEDs Four: Board fail (BFL), CPU, PMC (one for PMC slot 2, one for slot 1)

Timers

VME I/O VMEbus P2 connector

PCI interface

VMEbus interface

8KB NVRAM with RTC and battery backup (SGS-Thomson M48T559)

One 16550-compatible async serial port routed to front panel RJ-45 10BaseT/100BaseTX Ethernet interface routed to front panel RJ-45

(RST) and Abort (ABT)

One 16-bit timer in W83C553 ISA bridge; four 32-bit timers in MPIC device

Watchdog timer provided in SGS-Thomson M48T59

Two IEEE P1386.1 PCI Mezzanine Card (PMC) slots for one doublewidth or two single-width PMCs

Front panel and/or VMEbus P2 I/O on both PMC slots One 114-pin Mi ct or conn ector for optional PMCspan expansion module VMEbus system controller functions 64-bit PCI (Universe II) VMEbus-to-local-bus interface (A32/A24/A16, D64 (MBLT)

D32//D16/D08 Master and Slave Local-bus-to-VMEbus interface (A16/A24/A32, D8/D16/D32) VMEbus interrupter VMEbus interrupt handler Global Control/Status Register (GCSR) for interprocessor

communications DMA for fast local memory/VMEbus transfers (A16/A24/A32,

D16/D32/D64)

3-2 Computer Group Literature Center Web Site

General Description

The MVME240x is a VME processor module equipped with a PowerPC 604 RISC (MPC750) microprocessor.

As shown in the Features section, the MVME240x offers many standard

features desirable in a computer system—including Ethernet and debug ports, Boot ROM, Flash memory, SDRAM, and interface for two PCI Mezzanine Cards (PMCs), contained in a one-slot VME package. Its flexible mezzani ne ar chite cture al lows r elat ively ea sy upgr ades o f the I/O.

There are four standard buses on the MVME240x:

PowerPC Processor Bus ISA Bus PCI Local Bus VMEbus

As shown in Figure 3-1, the PCI Bridge portion of the Hawk ASIC provides the interface from the Processor Bus to the PCI. A W83C553 PCI/ISA Bridge (PIB) Controller device performs the bridge function between PCI and ISA. The Universe ASIC device provides the interface between the PCI Local Bus and t he VMEbus. Part of the Hawk ASIC is the ECC memory controller.

General Description

The Peripheral Component Interface (PCI) local bus is a key feature. In addition to the on-board local bus peripherals, the PCI bus supports an industry-standard mezzanine interface, IEEE P1386.1 PMC (PCI Mezzanine Card).

Block Diagram

Figure 3-1 is a block diagram of the MVME2400’s overall architecture.

http://www.motorola.com/computer/literature 3-3

Functional Descr iption

Debug Connector

PIB

W83c553

ISA Bus

Bus

100 MHz MPC604 Processor

Hawk ASIC

System Memory Controller (SMC)

Local Bus

ISA

Registers

RTC/NVRAM/WD

MK48T559

L2 Cache

512KB

or 1M

Processor

MPC750

Clock

Generator

33MHz 32/64-bit PCI

2,64-bit PMC Slo t

Ethernet

DEC21143

RJ45

10/100TX

RJ45

serial port

TL16C550

UART

SDRAM

32/64/128MB

Flash

1MB to 9MB

System

Registers

and PCI Host Bridge (PHB)

VME Bridge

Universe

Buffers

PCI Expansion

Slot2

PMC Front I/O

SLot1

Front Panel

PMC Front IO

VME P2

VME P1

2067 9708

Figure 3-1. MVME240x Block Diagram

3-4 Computer Group Literature Center Web Site

MPC750 Processor

The MVME240x can be ordered with a PowerPC 750 pr ocessor c hip with 32MB to 512MB of ECC SDRAM, and up to 9MB of Flash memory.

The PowerPC 750 is a 64-bi t pro ces sor with 32KB on -chip caches (32KB data cache and 32KB instruction cache).

The PHB bridge controll er por tion of the Hawk ASIC prov ides t he bri dge between the PowerPC microprocessor bus and the PCI local bus. Electrically, the Hawk is a 64-bit PCI co nnection. Four programmable ma p decoders in each direction provide flexible addressing between the PowerPC microprocessor bus and the PCI local bus.

The power requirements for the MVME240x are shown in Table 3-2.

Table 3-2. Power Requirements

Configuration +5V Power +12V and –12V Power

Block Diagram

233 or 350 MHz 750 3.3 A typical

4.0 A maximum

PMC-dependent (Refer to Appendix A,

Specifications)

L2 Cache

The MVME2400 SBC utilizes a back-door L2 cache structure via the

MPC750 processor chip. The MCP 750’s L2 cache is implemente d with an onchip 2-way set-associative tag memory and external direct-mapped synchronous SRAMs for data storage. The external SRAMs are accessed through a dedicated 72-bit wide (64 bits of data and 8 bits of parity) L2 cache port. The board i s populated wit h 1MB of L2 cache SRAMs. The L2 cache can operate in copyback or writethru modes and supports system cache coherency throug h snooping. Parity generat ion and checking may be disabled by programming the MCP750 accordingly. Refer to the

MVME2400 Programmer’s Reference Guide for additional information.

http://www.motorola.com/computer/literature 3-5

Functional Descr iption

Hawk System Memory Controller (SMC)/PCI Host Bridge (PHB) ASIC

The Hawk ASIC provides the bridge function between the MPC60x bus and the PCI Local Bus. It provides 32-bit addressing and 64-bit data. The 64-bit addressing (dual address cycle) is not supported. The Hawk supports various PowerPC processor external bus frequencies up to 100 MHz.

There are four programmable map decoders for each direction to provide flexible address m appings between th e MPC and the PCI Local Bus. Re fer to the MVME2400 Programmer’s Reference Guide for additional information.

The Hawk ASIC also provides an MPIC Interrupt Controller to handle various interrupt sources. The interrupt sources are: Four MPIC Timer Interrupts, the interrupts from all PCI devices, the two software interrupts, and the ISA interr upts. The ISA in terr upts a ctually ar e hand led a s a s ingle 8259 interrupt at INT0.

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PCI Bus Latency

The following table s list the l atency of PCI originated transactio ns and the bandwidth of originated transactions for five different clock ratios: 5:2, 3:2, 3:1, 2:1, and 1:1. The MVME2400 uses a 3:1 clock ratio:

Block Diagram

Table 3-3. PCI Originated Latency Matrix

32-bit PCI 6 4-bit PCI

Transaction

Burst Read9111129111125:2 Burst Write3111631116 Single Read 9 - - - 9 9 - - - 9 Single Write3---33---3 Burst Read121111512111153:2 Burst Write31116 31116 Single Read12---1212---12 Single Write3---33---3 Burst Read9111129111123:1 Burst Write31116 31116 Single Read 9 - - - 9 - - - - Single Write3---3----Burst Read111111411111142:1 Burst Write31116 31116 Single Read11---11----Single Write3---3----Burst Read161111916111191:1 Burst Write31116 31116 Single Read16---16----Single Write3---3-----

Beat1Beat2Beat3Beat

Total

Beat1Beat2Beat3Beat

Total

Clock

Ratio

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Functional Descr iption

Table 3-4. PCI Originated Bandwidth Matrix

Transaction

64-bit Writes 10 213 18 237 26 246 4 266 5:2 64-bit Reads 16 133 24 178 32 200 4 266 32-bit Writes 18 118 3 4 125 50 128 8 133 32-bit Reads 24 89 40 107 56 114 8 133 64-bit Writes 10 427 18 474 26 492 4 533 3:2 64-bit Reads 19 225 27 316 37 346 4 533 32-bit Writes 18 237 34 251 50 256 8 267 32-bit Reads 28 152 44 194 60 213 8 267 64-bit Writes 10 213 18 237 26 246 4 266 3:1 64-bit Reads 16 133 24 178 32 200 4 266 32-bit Writes 18 118 3 4 125 50 128 8 133 32-bit Reads 24 89 40 107 56 114 8 133 64-bit Writes 10 213 18 237 26 246 4 266 2:1 64-bit Reads 18 118 26 164 34 188 4 266 32-bit Writes 18 118 3 4 125 50 128 8 133 32-bit Reads 26 82 42 102 58 110 8 133 64-bit Writes 10 427 18 474 30 427 5 427 1:1 64-bit Reads 23 186 34 251 46 278 5.5 388 32-bit Writes 18 237 34 251 50 256 8 267 32-bit Reads 31 138 47 182 63 203 8 267

First 2

Cache Lines

Clks

MBytes

sec

First 4

Cache Lines

Clks

MBytes

sec

First 6

Cache Lines

Clks

MBytes

sec

Continuous

Clks/

Line

MBytes

sec

Clock

Ratio

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PPC Bus Latency

The following tables list the latency of PPC or iginated transact ions and the bandwidth of originated transactions for five different clock ratios: 5:2, 3:2, 3:1, 2:1, and 1:1. The MVME2400 uses a 3:1 clock ratio:

Table 3-5. PPC60x Originated Latency Matrix

Block Diagram

32-bit PCI 64-bit PCI

Transaction

Burst Read401114329111325:2 Burst Write51118 51118 Single Read22---22----Single Write5---5----Burst Read261112920111233:2 Burst Write51118 51118 Single Read16---16----Single Write5---5----Burst Read451114833111363:1 Burst Write51118 51118 Single Read24---24----Single Write5---5----Burst Read331113625111282:1 Burst Write51118 51118 Single Read19---19----Single Write5---5----Burst Read201112316111191:1 Burst Write51118 51118 Single Read13---13----Single Write5---5-----

Beat1Beat2Beat3Beat

Total

Beat1Beat2Beat3Beat

Total

Clock

Ratio

http://www.motorola.com/computer/literature 3-9

Functional Descr iption

Table 3-6. PPC60x Originated Bandwidth Matrix

Transaction

64-bit Writes 14 381 58 184 108 148 25 107 5:2 64-bit Reads - - - - - - 32.5 82 32-bit Writes 14 381 78 137 148 108 35 76 32-bit Reads - - - - - - 42.5 63 64-bit Writes 14 457 38 337 68 282 15 213 3:2 64-bit Reads - - - - - - 22.5 142 32-bit Writes 14 457 50 256 92 209 21 152 32-bit Reads - - - - - - 28.5 112 64-bit Writes 14 457 67 191 127 151 30 107 3:1 64-bit Reads - - - - - - 36 89 32-bit Writes 14 457 98 131 182 105 42 76 32-bit Reads - - - - - - 48 67 64-bit Writes 14 305 48 178 88 145 20 107 2:1 64-bit Reads - - - - - - 28 76 32-bit Writes 14 305 64 133 120 107 28 76 32-bit Reads - - - - - - 36 59 64-bit Writes 14 305 29 294 49 261 10 213 1:1 64-bit Reads - - - - - - 18 118 32-bit Writes 14 305 37 231 65 197 14 152 32-bit Reads - - - - - - 22 97

First 2

Cache Lines

Clks

MBytes

Sec

First 4

Cache Lines

Clks

MBytes

Sec

First 6

Cache Lines

Clks

MBytes

Sec

Continuous

Clks/

Line

MBytes

Sec

Clock Ratio

3-10 Computer Group Literature Center Web Site

Assumptions

Certain assumptions have been made with regard to MVME2400 performance. Some things, which are assumed in making the previous tables, include the following:

Clock Ratios and Operating Frequencies

Performance is based on the appropriate clock ratio and corresponding operating frequency:

Table 3-7. Clock Ratios and Operating Frequencies

Block Diagram

Ratio

5:2 83 33 8 3:2 100 66 8 3:1 100 33 8 2:1 66 33 10 1:1 66 66 10

PPC60x Originated

❏ Count represents number of PPC60x bus clock cycles. ❏ Assumes write posting FIFO is initially empty. ❏ Does not include time taken to obtain grant for PPC60x bus. The

❏ PPC60x bus is idle at the time of t he start of the transa ction. (t hat is,

❏ Cache aligned transfer, not critical word first. ❏ PCI medium responder with no zero states.

PPC60x

Clock

(MHz)

PCI Clock

(MHz)

SDRAM

Speed

(ns)

count starts on the same clock period that TS_ is asserted.

no pipelining effects).

❏ One clock request/one clock grant PCI arbitration. ❏ Write posting enabled.

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Functional Descr iption

❏ Default FIFO threshold settings ❏ Single beat writes are aligned 32-bit transfer, always executed as

32-bit PCI.

❏ Clock counts represent best case alignment between PCI and

PPC60x clock domains. An exception to this is continuous bandwidth which reflects the average affects of clock alignment.

PCI Originated

❏ Count represents number of PCI Bus clock cycles. ❏ Assumes write posting FIFO is initially empty ❏ L2 caching is not en abled, all tran sactions exclus ively contro lled by

the SMC.

❏ Does not include time taken to obtai n grant for PCI Bus. The count

starts on the same clock period that FRAME_ is asserted.

❏ One clock request/one clock grant PPC60x bus arbitration. ❏ PPC60x bus traffic limited to PHB transactions only. ❏ Write posting and read ahead enabled. ❏ Default FIFO threshold settings. ❏ One cache line = 32 bytes.

SDRAM Memory

The MVME2400 SDRAM memory size can be 32MB, 64MB, or 128MB. The SDRAM blocks are controlled by the Hawk ASIC which provides

single-bit error corr ection and double-bit error detection. ECC is calculated over 72-bits.

The memory block size is de pen dant upon the SDRAM devices installed. Installing five 64Mbit (16-bit data) devices provides 32MB of memory. With 64Mbit (8bit data) devices, there are two blocks consisting of nine devices each that total 64MB per block. In this case, either block can be

3-12 Computer Group Literature Center Web Site

Block Diagram

populated for 64MB or 1 28MB of onboard memory. With 128Mbit (8-bit data) devices, the blocks can be populated for 128MB and 256MB. If 64Mbit (4-bit data) devices are installed, there is one block consisting of 18 devices that t otal 12 8MB. With 128Mbit (4-bi t data) devices , the bl ock contains 256MB. When populated, these blocks appear as Block A and Block B to the Hawk.

Refer to the MVME2400 Series VME Processor Module Programmer’s Reference Guide for additional information and programming details.

SDRAM Latency

The following table shows the performance summary for SDRAM when operating at 100 MHz using PC 100 SDRAM with a CAS_latency of 2. The figure on the next page defines the times that are specified in the table.

Table 3-8. 60x Bus to SDRAM Access Timing (100 MHz/PC100 SDRAMs)

ACCESS TYPE

4-Beat Read after idle, SDRAM Bank Inactive

4-Beat Read after idle, SDRAM Bank Active - Page Miss

4-Beat Read after idle, SDRAM Bank Active - Page Hit

4-Beat Read after 4-Beat Read, SDRAM Bank Active - Page Miss

4-Beat Read after 4-Beat Read, SDRAM Bank Active - Page Hit

4-Beat Write after idle, SDRAM Bank Active or Inactive

4-Beat Write after 4-Beat Write, SDRAM Bank Active - Page Miss

Access Time

(tB1-tB2-tB3-tB4)

10-1-1-1

12-1-1-1

7-1-1-1

5-1-1-1

2.5-1-1-1 2.5-1-1-1 is an average of 21-1-1 half of the time and 31-1-1 the other half.

4-1-1-1

6-1-1-1

Comments

http://www.motorola.com/computer/literature 3-13

Functional Descr iption

Table 3-8. 60x Bus to SDRAM Access Timing (100 MHz/PC100 SDRAMs)

ACCESS TYPE

Access Time

(tB1-tB2-tB3-tB4)

Comments

4-Beat Write after 4-Beat Write, SDRAM Bank Active - Page Hit

1-Beat Read after idle, SDRAM Bank Inactive

1-Beat Read after idle, SDRAM Bank Active - Page Miss

1-Beat Read after idle, SDRAM Bank Active - Page Hit

1-Beat Read after 1-Beat Read, SDRAM Bank Active - Page Miss

1-Beat Read after 1-Beat Read, SDRAM Bank Active - Page Hit

1-Beat Write after idle, SDRAM Bank Active or Inactive

3-1-1-1 3-1-1-1 for the second burst

write after idle. 2-1-1-1 for subsequent burst

writes.

1-Beat Write after 1-Beat Write, SDRAM Bank Active - Page Miss

1-Beat Write after 1-Beat Write, SDRAM Bank Active - Page Hit

Notes

1. SDRAM speed attributes are programmed for the following: CAS_latency = 2, tRCD = 2 CLK Periods, tRP = 2 CLK Periods, tRAS = 5 CLK Periods, tRC = 7 CLK Periods, tDP = 2 CLK Periods, and the swr_dpl bit is set in the SDRAM Speed Attribut es Register.

3-14 Computer Group Literature Center Web Site

Block Diagram

2. The Hawk is configured for “no e xtern al re giste rs” on the SDRAM

control signals.

3. tB1, tB2, tB3, and tB4 are specified in the following figure.

tB4 tB3

tB2

tB1(From Idle) tB1(Back-to-Back)

Figure 3-2. Timing Definitions for PPC Bus to SDRAM Access

Notes

1. When the initial bus state is idle, tB1 reflects the number of CLK periods from the rising edge of the CLK that drives TS_low, to the rising edge of the CLK that s amples the first TA_low.

2. When the bus is busy and TS_ is being asse rted as soon as poss ible after Hawk asserts AACK_ the back-to-back condition occurs. When back-to-back cycles occur, tB1 reflects the number of CLK periods from the rising edge of the CLK that samples the last TA_

http://www.motorola.com/computer/literature 3-15

Functional Descr iption

low of a data tenure to the rising edge of the CLK that samples the first TA_ low of the next data tenure.

3. The tB2 function refle cts the number of CLK periods fr om the rising

edge of the CLK that samp les the first TA_ low in a burst data tenure to the rising edge of the CLK that samples the second TA_ low in that data tenure.

4. The tB3 function refle cts the number of CLK periods fr om the rising edge of the CLK that samples the second TA_ low in a burst data tenure to the rising edge of the CLK that samples the third TA_ low in that data tenure.

5. The tB4 function refle cts the number of CLK periods fr om the rising edge of the CLK that samples the third TA_ low in a burst data tenure to the rising edge of the CLK that samples the last TA_ low in that data tenure.

Flash Memory

The MVME240x base board contains two banks of Flash memory. Bank B consists of two 32-pin devices which can be populated with 1MB of Flash memory. Only 8-bit writes are supported for this bank. Bank A has four 16-bit Smart Voltage Flash SMT devices. With the 16Mbit Flash devices, the Flash size is 8MB. A jumper header associated with the first set of eight Flash devic es provides a total of 12 8KB of hardware-prote cted boot block. Only 32-bit writes are supported for this bank of Flash. There will be a jumper to tell the Hawk chi p where to fetch the reset vector. When the jumper is installe d, the Hawk chi p maps 0xFF F00100 to the se soc kets (Bank B).

The onboard monitor/debugger, PPCBug, resides in the Flash chips. PPCBug provides functionality for:

❏ Booting the system ❏ Initializing after a reset ❏ Displaying and modifying configuration variables ❏ Running self-tests and diagnostics

3-16 Computer Group Literature Center Web Site

❏ Updating firmware ROM

Under normal operation, the Flash devices are in “read-only” mode, their contents are pre-def ined, an d they are pr otected against i nadvert ent write s due to loss of power conditions. However, for programming purposes, programming voltage is always supplied to the de vices and the Flash contents may be modified by executing the proper program command sequence. Refer to the PFLASH command in the PPCbug Debugging

Package User’s Manual for further device-specific information on modifying Flash contents.

ROM/Flash Performance

The SMC provides the interface for two blocks of ROM/Flash. Access times to ROM/Flash are programmable for each block. Access times are also affected by b lock width . The foll owing tabl es in t his subsect ion show access times for ROM/Flash when configured for different device access times.

Table 3-9. PPC Bus to ROM/Flash Access Timing (120ns @ 100 MHz)

Block Diagram

CLOCK PERIODS REQUIRED FOR:

ACCESS TYPE

4-Beat Read 70 22 64 16 64 16 64 16 262 70 4-Beat Write N/A N/A 1-Beat Read (1 byte) 2222------2222 1-Beat Read (2 to 8 bytes)7022------7022 1-Beat Write 2121------2121

1st Beat 2nd Beat 3rd Beat 4th Beat

Bits

Clocks

Bits

Total

Bits

Note The information in Table 3-9 is appropriate when configured

with devices with an access time equal to 12 CLK periods.

http://www.motorola.com/computer/literature 3-17

Functional Descr iption

Table 3-10. PPC Bus to ROM/Flash Access Timing (80ns @ 100 MHz)

CLOCK PERIODS REQUIRED FOR:

ACCESS TYPE

4-Beat Read 54 18 48 12 48 12 48 12 198 54 4-Beat Write N/A N/A 1-Beat Read (1 byte) 1818------1818 1-Beat Read (2 to 8 bytes)5418------5418 1-Beat Write 2121------2121

1st Beat 2nd Beat 3rd Beat 4th Beat

Bits

Clocks

Bits

Total

Bits

Note The information in Table 3-10 is appropriate when configur ed

with devices with an access time equal to 8 CLK periods.

Table 3-11. PPC Bus to ROM/Flash Access Timing (50ns @ 100MHz)

ACCESS TYPE

CLOCK PERIODS REQUIRED FOR:

1st Beat 2nd Beat 3rd Beat 4th Beat

Bits

Clocks

Bits

Total

Bits

4-Beat Read 42 15 36 9 36 9 36 9 150 42 4-Beat Write N/A N/A 1-Beat Read (1 byte) 1515------1515 1-Beat Read (2 to 8 bytes)4215------4215 1-Beat Write 2121------2121

Note The information in Table 3-11 is appropriate when configur ed

with devices with an access time equal to 5 CLK periods.

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Block Diagram

Table 3-12. PPC Bus to ROM/Flash Access Timing (30ns @ 100 MHz)

CLOCK PERIODS REQUIRED FOR:

ACCESS TYPE

4-Beat Read 34 13 28 7 28 7 28 7 118 34 4-Beat Write N/A N/A 1-Beat Read (1 byte) 1313------1313 1-Beat Read (2 to 8 bytes)3413------3413 1-Beat Write 2121------2121

1st Beat 2nd Beat 3rd Beat 4th Beat

Bits

Clocks

Bits

Total

Bits

Note The information in Table 3-12 is appropriate when configur ed

with devices with an access time equal to 3 CLK periods.

Ethernet Interface

The MVME240x module uses Intel’s DECchip 21143 PCI Fast Ethernet LAN controller to implemen t an Ethernet in terface that supports 10BaseT/100BaseTX connections, via an RJ-45 connector on the front panel. The balanc ed differe ntial tra nsceiver lines are coupled via on-board transformers.

Every MVME240x is assigned an Ethe rnet stati on address. Th e address i s $08003E2xxxxx, where xxxxx is the unique 5-nibble number assigned to the board (that is, every board has a different value for xxxxx).

Each MVME240x displays it s Ethernet station a ddress on a label at tached to the base board in the PMC connec tor ke epout a rea jus t behi nd the fron t panel. In addition, the six byt es incl udi ng th e Ethernet station address are stored in the NVRAM (BBRAM) configuration area specified by boot ROM. That is, the value 08003E2xxxxx is stored in NVRAM. The MVME240x debugger, PPCBug, has the capa bility to retrieve the Etherne t station add ress via the CNFG command.

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Functional Descr iption

Note The unique Ethernet address is set at the factory and should not

be changed. Any attempt to change thi s address may cre ate node or bus contention and thereby render the board inoperable.

If the data in NVRAM is lost, use the number on the label in the PMC connector keepout area to restore it.

For the pin assignments of the 10BaseT/100BaseTX connector, refer to

Appendix B, Connector Pin Assignments.

At the physical layer, the Ethernet interface bandwidth is 10Mbit/second for 10BaseT. For the 100BaseTX, it is 100Mbit/second. Refer to the BBRAM/TOD Clock memory map description in the MVME2400 Series VME Processor Module Programmer’s Reference Guide for detailed programming information.

PCI Mezzanine Card (PMC) Interface

A key feature of the MVME240x fami ly is the PCI bus. In addition to the on-board local bus devices (Ethernet, etc.), the PCI bus supports an industry-standard mezzanine interface, IEEE P1386.1 PCI Mezzanine Card (PMC).

PMC modules offer a variety of possibilities for I/O expansion such as FDDI (Fiber Distributed Data Interface), ATM (Asynchronous Transfer Mode), graphics, Ethernet, or SCSI ports. For a complete listing of

available PMCs, go to the GroupIPC’s Web site at

http://www.groupipc.com/. The MVME240x supports PMC front panel

and rear P2 I/O. There is also provision for stacking one or two PMC carrier boards, or PMCspan PCI expansion modules, on the MVME240x for additional expansi on.

The MVME240x supports two PMC slots. Two sets of four 64-pin connectors on the base board (J11 - J14, and J21 - J24) interface with 32-bit/64-bit IEEE P1386.1 PMC-compatible mezzanines to add any desirable function.

3-20 Computer Group Literature Center Web Site

Refer to Appendix B, Connector Pin Assignments for the pin a ssignmen ts of the PMC connector s. For detailed programming information, refer to the PCI bus descriptions in the MVME2400 Series VME Processor Module Programmer’s Reference Guide and to the user documentation for the PMC modules you intend to use.

PMC Slot 1 (Single-Width PMC)

PMC slot 1 has the following characteristics:

Mezzanine Type PCI Mezzanine Card (PMC) Mezzanine Size PMC Connectors J11 to J14 (32/64-bit PCI with front and rear I/O)

Signaling Voltage V

For P2 I/O configurations, all I/O pins of PMC slot 1 are routed to the 5-row power adapter card. Pins 1 through 64 of J14 are rout ed to row C and row A of P2.

Block Diagram

S1B: Single width, s tandard dept h (75 mm x 150 mm) with front panel

= 5.0Vdc

PMC Slot 2 (Single-Width PMC)

PMC slot 2 has the following characteristics:

Mezzanine Type PCI Mezzanine Card (PMC) Mezzanine Size PMC Connectors J 21 to J24 (32/64-bit PCI with front and rear I/O)

Signaling Voltage V

S1B: Single width, s tandard dept h (75 mm x 150 mm) with front panel

= 5.0Vdc

For P2 I/O configurations, 46 I/O pins of PMC slot 2 are routed to the 5-row power adapter card. Pins 1 through 46 of J24 are routed to row D and row Z of P2.

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Functional Descr iption

PMC Slots 1 and 2 (Double-Width PMC)

PMC slots 1 and 2 with a double-width PMC have the following characteristics:

Mezzanine Type PCI Mezzanine Card (PMC) Mezzanine Size

PMC Connectors Signaling Voltage V

Double width, standard depth (150 mm x 150 mm) with front panel

J11 to J14 and J21 to J24 (32/64-bit PCI) with front and rear I/O

= 5.0Vdc

PCI Expansion

The PMCspan expansion module connector, J6, is a 114-pin Mictor connector. It is locat ed near P2 on the primary side of the MVME240x. Its interrupt lines are rout ed to the MPIC .

VMEbus Interface

The VMEbus interface is implemented with the CA91C142 Universe ASIC. The Universe chip inte rfaces the 32/64-bit PCI local bus to the VMEbus.

The Universe ASIC provides:

❏ The PCI-bus-to-VMEbus interface ❏ The VMEbus-to-PCI-bus interface ❏ The DMA controller functions of the local VMEbus

The Universe chip includes Universe Control and Status Registers (UCSRs) for interprocessor communications. It can provide the VMEbus system controller functions as well. For detailed programming information, refer to the Universe User’s Manual and to th e discussion s in the MVME2400 Series VME Processor Module Programmer's Reference Guide.

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Maximum performance is achieved with D64 Multiplexed Block Transfers (MBLT). The on-chip DMA channel should be used to move large blocks of dat a to/ fr om t he VMEbu s. T he Un ive rs e s houl d be able to reach 50MB/second in 64-bit MBLT mode.

The MVME2400 interfaces t o the VMEbus via th e P1 and P2 connect ors, which use the new 5-row 160-pin connectors as specified in the VME64

extension standard. It also draws +5V, +12V, and –12V power from the VMEbus backplane through these two conn ectors. 3.3V and 2.5V supplies are regulated onboard from the +5 power.

Asynchronous Debug Port

A Texas Instrument’s Universal Asynchronous Receiver/Transmitter (UART) provides the asynchronous debug port. TTL-l evel si gnals fo r the port are routed through appr opriate EIA-23 2-D drivers and recei vers to an RJ-45 connector on the front panel. The external signals are ESD protected.

For detailed programming information, refer to the MVME2400 Series VME Processor Module Programmer’s Reference Guide and to Texas Instrument’s data sheet #SLLS057D, dated August 1989, revised March 1996 for Asynchronous Communications Element (ACE) TL16C550A.

Block Diagram

PCI-ISA Bridge (PIB) Controller

The MVME240x uses a Winbond W83C553 PCI/ISA Bridge (PIB) Controller to supply the interface between the PCI local bus and the ISA system I/O bus (diagrammed in Figure 3-1 on page 3-4).

The PIB controller provides the following functions:

❏ PCI bus arbitration for:

– ISA (Industry Standard Architecture) bus DMA (not functional

on MVME240x)

– The PHB (PCI Host Bridge) MPU/local bus interface function,

implemented by the Hawk ASIC – All on-board PCI devices – The PMC slot

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Functional Descr iption

❏ ISA bus arbitration for DMA devices ❏ ISA interrupt mapping for four PCI interrupts

❏ Interrupt controller functionality to support 14 ISA interrupts ❏ Edge/level control for IS A interrupts ❏ Seven independently programmable DMA channels ❏ One 16-bit timer ❏ Three interval counters/timers

Accesses to the configuration space for the PIB controller are performed by way of the CONADD and CONDAT (Conf iguration Address and Data) registers in the PHB. The regist ers are located at offsets $CF8 and $CFC, respectively, from the PCI I/O base address.

Real-Time Clock/NVRAM/Timer Function

The MVME240x employs an SGS-Thomson surface-mount M48T559 RAM and clock chip to provide 8KB of non-volatile static RAM, a realtime clock, and a watchdog timer function. This chip supplies a clock, oscillator, crysta l, power fail ure detectio n, memory write pr otection , 8KB of NVRAM, and a battery in a package consisting of two parts:

❏ A 28-pin 330mil SO device containing the real-time clock, the

oscillator, power failure detection circuitry, timer logic, 8KB of static RAM, and gold-plated sockets for a battery

❏ A SNAPHAT

battery housing a crystal along with the battery

The SNAPHAT battery package is mounted on top of the M48T559 device. The battery housing is keyed to prevent reverse insertion.

The clock furnishes seconds, minut es, hours, da y, date, month, and year in BCD 24-hour format. Corrections for 28-, 29- (leap year), and 30-day months are made automatically. The clock generates no interrupts. Although the M48T559 is an 8-bit device, 8-, 16-, and 32-bit access es from the ISA bus to the M48T559 are su pported. Refer to the MVME2400 Seri es

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VME Processor Module Programmer’s Reference Guide and to the M48T559 data sheet for detailed programming and battery life information.

PCI Host Bridge (PHB)

The PHB portion of the Hawk ASIC pro vides the bri dge function be tween the MPC60x bus and the PCI Local Bus. It provides 32 bit addressi ng and 64 bit data. The 64 bit a ddressing (dual addres s cycle) is not supported. Th e Hawk supports various Po werPC pro cessor ex ternal bus f requenci es up to 100MHz and PCI frequencies up to 33 MHz.

There are four programmable map decoders for each direction to provide flexible address mapp ings between the M PC and the PCI Local Bus. Re fer to the MVME2400 Series VME Processor Module Programmer’s Reference Guide for additional information and programming details.

Interrupt Controller (MPIC)

The MPIC Interrupt Controller portion of the Hawk ASIC is designed to handle various interrupt sources. The interrupt sources are:

Block Diagram

❏ Four MPIC timer interrupts ❏ Processor 0 self interrupt ❏ Memory Error interrupt from the SMC ❏ Interrupts from all PCI d evices ❏ Two software interrupts ❏ ISA interrupts (actually handles as a single 8259 interrupt at INT0)

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Functional Descr iption

Programmable Timers

Among the resources available to the local processor are a number of

Interval Timers

programmable timers. Timers are incorporated into the PCI/ISA Bridge (PIB) controller and the Hawk de vice ( dia gramme d in Fi gure 3- 1 on page

3-4). They can be programmed to generate periodic interrupts to the

processor.

The PIB controller has three built-in counters that are equivale nt to those found in an 82C54 programmab le interval timer. The co unters are grouped into one timer unit, Timer 1, in the PIB controller. Each counter output has a specific function:

❏ Counter 0 is associated with interrupt request line IRQ0. It can be

used for system timing functions, such as a timer interrupt for a time-of-day function.

❏ Counter 1 generates a refresh request signal for ISA memory. This

timer is not used in the MVME240x.

❏ Counter 2 provides the tone for the speaker output function on the

PIB controller (the

SPEAKER_OUT signal which can be cabled to an

external speaker via the remote reset connector). This fu nction is not used on the MVME240x.

The interval timers use the OSC clock input as their clock source. The MVME240x drives the OSC pin with a 14.31818 MHz clock source.

16/32-Bit Timers

There is one 16-bit timer and four 32-bit timers on the MVME240x. The 16-bit timer is pr ovided by the PIB. T he Hawk device provi des the four 32 bit timers that may be used for system timing or to generate periodic interrupts. For information on programming these timers, refer to the data sheet for the W83C553 PIB control ler and to the MVME2400 Series VME Processor Module Programmer’s Reference Guide.

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4Programming Details

Introduction

This chapter provides information useful in programming the MVME240x. This includes a description of memory maps, control and status registers, PCI arbitration, interrupt handling, sources of reset, and big/little-endian issues.

For additional programming information about the MVME240x, refer to the MVME2400 Series VME Processor Module Programmer’s Ref erence Guide, listed in Appendix D, Related Documentation.

For programming information about the PMCs, refer to the applicable

user’s manual furnished with the PMCs.

Memory Maps

There are multiple buses on the MVME240x and each bus domain has its own view of the memory map. The following sections describe the MVME240x memory organization from the following three points of view:

❏ The mapping of all resourc es as vi ewed by t he MPU ( processo r bus

memory map)

❏ The mapping of onboard resources as viewed by PCI local bus

masters (PCI bus memory map)

❏ The mapping of onboard resources as viewed by VMEbus masters

(VMEbus memory map)

Additional, more detailed memory maps can be found in the MVME2400

Series VME Processor Module Programmer’s Reference Guide.

4-1

Programming Details

Processor Bus Memory Map

The processor memory map configur ation is und er the control of the PHB and SMC portions of the Hawk ASIC. The Hawk adjusts syste m mapping to suit a given application via programmable map decoder registers. At system power-up or reset, a default processor memory map takes over.

Default Processor Memory Map

The default processor memory map that is valid at power-up or reset remains in effect until reprogrammed for sp ecific applications. The table below defines the entire default map ($00000000 to $FFFFFFFF).

Table 4-1. Processor Default View of the Memory Map

Processor Address Size Definition

Start End

00000000 7FFFF FFF 2GB Not Mapped 80000000 8001FFFF 128KB PCI/ISA I/O Space

80020000 FEF7FFFF 2GB-16MB-640KB Not Mapped FEF80000 FEF8FFFF 64KB SMC Registers FEF90000 FEFEFFFF 384KB Not Mapped FEFF0000 FEFFFFFF 64KB PHB Registers FF000000 FFEFFFFF 15MB Not Mapped FFF00000 FFFFFFFF 1MB Flash Bank A or Bank B (See Note)

Note The first 1MB of Flash bank A (soldered Flash up to 8MB)

appears in this range after a reset if the rom_b_rv con trol bit in

the SMC’s ROM B Base/Size r egister is cleared . If the rom_b_rv control bit is set, this address range maps to Flash bank B (socketed 1MB Flash).

For detailed processor memory maps, including suggested CHRP- and PREP-compatible memory maps, refer to the

MVME2400 Series VME Processor Module Programmer’s Reference Guide.

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PCI Local Bus Memory Map

The PCI memory map is control led by the MPU/PCI bus br idge controll er portion of the Hawk ASIC and by the Universe PCI/VME bus bridge ASIC. The Hawk and Universe devices adjust system mapping to suit a given application via programmable map decoder re gisters.

Memory Maps

No default P CI memory map exi sts. Resetting the system tur ns the PCI map decoders off, and they must be reprogrammed in software for the intended application.

For detailed PCI memory maps, including suggested CHRP- and PREPcompatible memory maps, refer to the MVME2400 Series VME Processor Module Programmer’s Reference Guide.

VMEbus Memory Map

The VMEbus is programmable. Like other parts of the MVME240x memory map, the mapping of local resources as viewed by VMEbus masters varies among applications.

The Universe PCI/VME bus bridge ASIC includes a user-programmable map decoder for the VMEbus-to-local-bus interface. The address translation ca pabi l it ies of the Universe enable the proce ss or to access any range of addresses on the VMEbus.

Recommendations for VMEbus mapping, including suggested CHRP- and PREP-compatible memory maps, can be found in the MVME2400 Series VME Processor Module Programmer’s Reference Guide. Figure 4-1 shows the overall mapping approach from the standpoint of a VMEbus master.

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Programming Details

Programming Considerations

Good programming practice dictates that only one MPU at a time have control of the MVME240x control registers. Of particular note are:

❏ Registers that modify the address map

❏ Registers that require two cycles to access ❏ VMEbus in terrupt request registers

PCI Arbitration

There are seven potential PCI bus masters on the MVME240x:

❏ Hawk ASIC (MPU/PCI bus bridge controller) ❏ Winbond W83C553 PIB (PCI/ISA bus bridge controller) ❏ DECchip 21143 Ethernet controller ❏ Universe II ASIC (PCI/VME bus bridge controller) ❏ PMC Slot 1 (PCI mezzanine card) ❏ PMC Slot 2 (PCI mezzanine card) ❏ PCI Expansion Slot

The Winbond W83C553 PIB device supplies the PCI arbitration support for these seven types of devices. The PIB supports flexible arbitration modes of fixed priority, rotating priority, and mixed priority, as appropriate in a g iven appl ication. Det ails on P CI arbit ration c an be foun d in the MVME2400 Series VME Processor Module Programmer’s Reference Guide.

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Programming Considerations

ONBOARD

MEMORY

PCI MEMORY

SPACE

PCI/ISA

MEMORY SPACE

PCI

I/O SPACE

NOTE 1

PCI MEMORYPROCESSOR

VMEBUS

PROGRAMMAB LE

SPACE

NOTE 2

VME A24

VME A16

NOTE 3

VME A24

VME A16

VME A24

VME A16

VME A24

VME A16

MPC

RESOURCES

1. Programmable m apping done by Hawk ASI C .

NOTES:

2. Programmable m apping performed via PCI Slave images in Universe ASIC.

3. Programmable m apping performed via Special Slave image (SLSI) in Universe ASIC.

11553.00 9609

Figure 4-1. VMEbus Master Mapping

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Programming Details

The arbitration assignments for the MVME240x are shown in the following table:

Table 4-2. PCI Arbitration Assignments

PCI Bus Request PCI Master(s)

PIB (Internal) PIB

CPU Hawk ASIC Request 0 PMC Slot 2 Request 1 PMC Slot 1 Request 2 PCI Expansion Slot Request 3 Ethernet Request 4 Universe ASIC (VMEbus)

Interrupt Handling

The Hawk ASIC, which controls the PHB (PCI Host Bridge) and the MPU/local bus interfac e functions on t he MVME240x, performs i nterrupt handling as well. Sources of interrupts may be any of the following:

❏ The Hawk ASIC itself (timer int errupts , transfer error inter rupts, or

memory error interrupts)

❏ The processor (processor self-interrupts) ❏ The PCI bus (interrupts from PCI devices) ❏ The ISA bus (interrupts from ISA devices)

Figure 4-2 illustrate s interrupt ar chitecture on the MVME240x. For details

on interrupt handling, refer to the MVME2400 Series VME Processor Module Programmer’s Reference Guide.

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PIB

(8529 Pair)

Programming Considerations

INT

INT_

Processor

MCP_

Hawk MPIC

SERR_& PERR_

PCI Interrupts

ISA Interrupts

1155 9. 00 9609

Figure 4-2. MVME240x Interrupt Architecture

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Programming Details

The MVME240x routes the int er rup ts from the PMCs and PCI expansion slots as follows:

PMC Slot 1

INTA# INTB# INTC#

INTD#

INTA# INTB# INTC#

PMC Slot 2

INTD#

INTA#

PCIX Slot

INTB# INTC#

INTD#

IRQ10

IRQ9

IRQ11 IRQ12

Hawk MPIC

DMA Channels

The PIB supports seven DMA channels. They are not functional on the MVME240x.

Sources of Reset

The MVME240x has eight potential sources of reset:

1. Power-on reset

RST switch (resets the VMEbus when the MVME240x is system

2. controller)

3. Watchdog timer Reset function controlled by the SGS-Thomson MK48T59 TIMEKEEPER device (resets the VMEbus when the MVME240x is system controller)

ALT_RST∗ function controlled by the Port 92 register in the PIB

4. (resets the VMEbus when the MVME240x is system controller)

5. PCI/ISA I/O Reset functio n controlled by the Clock Divi sor register in the PIB

6. The VMEbus

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SYSRESET∗ signal

Programming Considerations

7. VMEbus Reset sources from the Universe ASIC (PCI/VME bus bridge controller): the System Software reset and Local Software reset

Note On the MVME2400, Watchdog Timer 2 is a sou rce of r eset only

if component R25 is installed on the board. Consult your local Motorola Computer Group (MCG) sales representative if this feature needs to be enabled.

Table 4-3 shows which devices ar e affecte d by the vari ous types of res ets.

For details on us ing resets, refer to the MVME2400 Serie s VME Processor Module Programmer’s Reference Guide.

Table 4-3. Classes of Reset and Effectiveness

Device Affected Processor Hawk

Reset Source

Power-On reset Reset switch Watchdog reset VME

SYSRESET∗signal VME System SW

reset VME Local SW reset Hot reset (Port 92) PCI/ISA reset

√√√√√ √√√√√ √√√√√ √√√√√

√√√√√

√√√√ √√√√

ASIC

PCI

Devices

√√

ISA

Devices

VMEbus

(as system

controller

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Programming Details

Endian Issues

The MVME240x supports both litt le -e ndi an (for example, Windows NT) and big-endian (for exampl e, AIX) softwar e. The PowerPC processor and the VMEbus are inherently big-endian, while the PCI bus is inherently little-endian. The following sections summari ze how the MVME240x

Processor/Memory Domain

handles software and hardware differences in big- and little-endian operations. For further details on endian considerations, refer to the

MVME2400 Series VME Processor Module Programmer’s Reference Guide.

The MPC750 processor can operate in both big-endian and little-endian mode. However, it always treats the external processor/memory bus as big-endian by performing address rearrangement and reordering when running in little-endian mode. The MPC registers in the Hawk MPU/PCI bus bridge controller, SMC memory controller, as well as DRAM, Flash, and system registers, always appear as big-endian.

Role of the Hawk ASIC

Because the PCI bus is li ttle-endian, the PHB portion of the Hawk performs byte swapping i n both directi ons (from PCI to memory and from the processor to PCI) to main tain address in variance while progr ammed to operate in big-en dian mode with the proces sor and the memory subsyst em.

In little-endian mode, the P HB reverse-rearranges the address for PCI-bound accesses and rearranges the address for memory-bound accesses (from PCI). In this case, no byte swapping is done.

PCI Domain

The PCI bus is inherently little-endian. All devices connected directly to the PCI bus operate in little-endian mode, regardless of the mode of

operation in the processor’s domain.

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PCI and Ethernet

Ethernet is byte-stream-oriented; the byte having the lowest address in memory is the first one to be tra nsferred regardless of the endian mode. Since the PHB maintains address invariance in both little-endian and big-endian mode, no endian issues should arise for Ethernet data. Big-endian software must still take the byte-swapping effect into account when accessing the regi sters of the PCI/Ethernet device.

Role of the Universe ASIC

Because the PCI bus is li ttle-endian w hile the VMEbus is big-endian, the Universe PCI/VME bus bridge ASIC performs byte swapping in both directions (from PCI to VMEbus and from VMEbus to PCI) to maintain

address invariance , regard les s of the mode of ope ra tion in th e proces sor’s domain.

VMEbus Domain

The VMEbus is inherently big-endian. All devices connected directly to the VMEbus must operate in big-endian mode, regardless of the mode of operation in the processor’s domain.

Programming Considerations

In big-endian mode, byte-swapping is performed first by the Universe ASIC and then by the PHB. The result is transparent to big- endian software (a desirable effect).

In little-endian mode, however, software must take the byte-swapping effect of the Un iverse ASI C and th e addres s revers e-rea rranging effect of the PHB into account.

For further details on endian considerations, refer to the MVME2400

Series VME Processor Module Programmer’s Reference Guide.

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PPCBug Overview

The PPCBug firmware is the layer of software just above the hardware. The firmware provides the proper initialization for the devices on the MVME240x module upon power-up or reset.

This chapter describes the basics of the PPCBug and its architecture , along with the monitor (intera ctive command portion of the firmwar e), and gives information on using t he PPCBug and t he spe cial c ommands. A compl ete list of PPCBug commands appears at the end of the chapter.

Chapter 6, Environment Modification contai ns information about the

CNFG and ENV commands, system calls, and o ther ad van ced user topic s. For full user information about PPCbug, refer to the PPCBug Firmware

Package User’s Manual and the PPCBug Diagnostics Manual, listed in

Appendix D, Related Documentation.

5PPCBug

PPCBug Basics

The PowerPC debug firmware, PPCBug, is a powerful evaluation and debugging tool for syst ems built around the Motorola PowerPC microcomputers. Facilities are available for loading and executing user programs under complete operator control for system evaluation.

PPCBug provides a high degree of functionality, user friendliness, portability, and ease of maintenance.

It achieves good portability and comprehensibility because it was written entirely in the C programming language, except where necessary to use assembler functions.

5-1

PPCBug

PPCBug includes commands for:

❏ Display and modification of memory ❏ Breakpoint and tracing capabilities ❏ A powerful assembler and disassembler useful for patching

programs

❏ A self-test at power-up feature which verifies the integrity of the

system

PPCBug consists of three parts:

1. A command-driven, user-int eractive software debugger, described in the PPCBug Firmware Package User’s Manual. It is he reafter

referred to as “the debugger” or “PPCBug.”

2. A command-driven diagnostics package for the MVME240x hardware, hereafter referred to as “the diagnostics.” The diagn ostics package is described in the PPCBug Diagnostics Manual.

3. A user interface or debug/diagnostics monitor that accepts commands from the system console terminal.

When using PPCBug, you operate out of e it her the debugger directory or the diagnostic directory if:

❏ You are in the debugge r dire ctory, t he debug ger prompt PPC4-Bug>

is displayed and you have all of the debugger commands at your disposal.

❏ You are in the diagnostic directory, the diagnostic prompt PPC4-

Diag> is displayed and you have all of the dia gnosti c commands at your disposal as well as all of the debugger commands.

Because PPCBug is command-driv en, it performs it s various operatio ns in response to user commands entered at the keyboard. When you enter a command, PPCBug executes the command and the prompt reappears. However, if you enter a command that causes executi on of user target code (for example, GO), then control may or may not return to PPCBug, depending on the outcome of the user program.

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Memory Requirements

PPCBug requires a maximum of 768KB of read/write memory (that is, DRAM). The debugger allocates this space from the top of memory. For example, a system containing 64MB ($04000000) of read/write memory will place the PPCBug memory page at locations $03F40000 to $03FFFFFF.

MPU, Hardware, and Firmware Initialization

PPCBug Implementation

PPCBug is written largely in the C programming language, providing benefits of portability and maintainability. Where necessary, assembly language has been used in the form of separately compiled program modules containing only as sembler code. No mixed-lang uage modules are used.

Physically, PPCBug is contained in two socketed 32-pin PLCC Flash devices that together provide 1MB of storage. The executable code is checksummed at every power-on or reset firmware entry, and the result (which includes a preca lculated checks um contained in the Fla sh devices), is verified against the expected checksum.

MPU, Hardware, and Firmware Initialization

The debugger performs the MPU, hardware, and firmware initialization process. This process occurs each time the MVME240x i s reset or powered up. The steps below are a high-level outline; not all of the detailed steps are listed.

1. Sets MPU.MSR to known value.

2. Invalidates the MPU’s data/instruction caches.

3. Clears all segment registers of the MPU.

4. Clears all block address translation registers of the MPU.

5. Initializes the MPU-bus-to-PCI-bus bridge device.

6. Initializes the PCI-bus-to-ISA-bus bridge device.

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PPCBug

7. Calculates the external bus clock speed of the MPU.

8. Delays for 750 milliseconds.

9. Determines the CPU base board type.

10. Sizes th e local read/w rite memory (that is, DRAM).

11. Initializes the read/write memory controller. Sets base address o f memory to $00000000.

12. Retrieve s the speed of read/write memory.

13. Initializes the read/write memory contro ller with the speed of read/write memory .

14. Retrieves the speed of read only memory (that is, Flash).

15. Initializes the read o nly memory controller with th e speed of read only memory .

16. Enables the MPU’s instruction cache.

17. Copies the MPU’s exception vector table from $FFF00000 to $00000000.

18. Verifies MPU type.

19. Enables the superscalar feature of the MPU (superscalar processor boards only).

20. Verifies the external bus clock speed of the MPU.

21. Determines the debugger’s console/host ports, and initializes the PC16550A.

22. Displays the debugger’s copyright message.

23. Displays any hardware i nitialization e rrors that may ha ve occurred.

24. Checksums the debugger obj ect, and di splays a war ning messag e if the checksum failed to verify.

25. Displays the amount of local read/write memory found.

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Using PPCBug

26. Verifies the configuration data that is resident in NVRAM, and displays a warning message if the verification failed.

27. Calculates and displ ays the MPU clock spee d, verifies that the MPU clock speed matches the configura tion data , and displ ays a warni ng message if the verification fails.

28. Displays the BUS clock speed, verifies that the BUS clock speed matches the configuration data, and displays a warning message if the verification fails.

29. Probes PCI bus for supported network devices.

30. Probes PCI bus for supported mass storage devices.

31. Initializes the memory/IO addresses for the supported PCI bus devices.

32. Executes Self-Test, if so configured. (Default is no Self-Test.)

33. Extinguishes the board fail LED, if Self-Test passed, and outputs any warning messages.

34. Executes boot program, if so configured. (Default is no boot.)

35. Executes the debugger moni tor (that is, issues the prompt).

PPC4-Bug>

Using PPCBug

PPCBug is command-driven; it pe rforms its various operatio ns in response to commands that you e nter at the key board. When the PPC4-B ug prompt appears on the screen, the debugger is ready to accept debugger commands. When the PPC4-Diag prompt appears on the screen, the debugger is ready to accept diagnostics commands. To switch from one mode to the other, enter SD.

What you key in is stored in an internal buff er. Execution begi ns only after you press the Return or Ent er key . This al lows you t o co rrect ent ry err ors, if necessary, with the control characters described in the PPCBug Firmware Package User’s Manual.

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PPCBug

After the debugger executes the command, the prompt reappears. However, if the command causes execution of user target code (for example GO) then control may or may not return to the debugger, depending on what the user progra m does. For example, if a breakpoint has been specified, t hen control retu rns to the debugger when the breakp oint is encountered during execution of the user program. Alternately, the user program could return to the deb ugger by means of the System Call Handler routine RETURN (described in the PPCBug Firmware Package User’s Manual). For more about this, refer to the GD, GO, and GT command

descriptions in the PPCBug Firmware Package User’s Manual. A debugger command is made up of the following parts:

❏ The command name, either uppercase or lowercase (for example,

MD or md).

❏ Any required arguments, as specified by command. ❏ At least one space before the first argument. Precede all other

arguments with either a space or comma.

❏ One or more options. Precede an option or a string of options with

a semicolon (;). If no option is entered, the command’s default option conditions are used.

Debugger Commands

The individual debugger commands are listed in the following table. The commands are described in detail in the PPCBug Firmware Package

User’s Manual

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Using PPCBug

Note You can list all the available de bugger commands by entering the

Help (HE) command alone. You can view the syntax for a particular command by ente ring HE and the command mnemonic, as listed below.

Table 5-1. Debugger Commands

Command Description

AS One Line Assembler BC Block of Memory Compare BF Block of Memory Fill BI Block of Memory Initialize BM Block of Memory Move BR Bre ak poi n t Ins ert NOBR Breakpoint Delete BS Block of Memory Search BV Block of Memory Verify CACHE Modify Cache State CM Concurrent Mode NOCM No Concurrent Mode CNFG Configure Board Information Block CS Checksum CSAR PCI Configuration Space READ Access CSAW PCI Configuration Space WRITE Access DC Data Conversion DS One Line Disassembler

DU Dump S-Records ECHO Echo String ENV Set Environment FORK Fork Idle MPU at Address FORKWR F ork Idle MPU with Registers

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PPCBug

Table 5-1. Debugger Commands (Continued)

Command Description

GD Go Direct (Ignore Breakpoints) GEVBOOT Global Environment Variable Boot GEVDEL Global Environment Variable Delete GEVDUMP Global Environment Vari able(s) Dump

GEVEDIT Global Environment Variable Edit GEVINIT Global Environment Variable Initialization GEVSHOW Global Environment Variable(s) Display GN Go to Next Instruction G, GO Go Execute User Program GT G o to Temporary Breakpoint HE Help IDLE Idle Master MPU IOC I/O Control for Disk IOI I/O Inquiry IOP I/O Physical (Direct Disk Access) IOT I/O Teach for Configuring Disk Controller IRD Idle MPU Register Display IRM Idle MPU Register Modify IRS Idle MPU Register Set LO Load S-Records from Host MA Macro Define/Display NOMA Macro Delete MAE Macro Edit MAL Enable Macro Listing NOMAL Disable Macro Listing MAR Load Macros MAW Save Macros

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Table 5-1. Debugger Commands (Continued)

Command Description

MD, MDS Memory Display MENU System Menu M, MM Memory Modify MMD Memory Map Diagnostic

Using PPCBug

MS Memory Set MW Memory Write NAB Automatic Network Boot NAP Nap MPU NBH Network Boot Operating System, Halt NBO Network Boot Operating System NIOC Network I/O Control NIOP Network I/O Physical NIOT Network I/O Teach (Configuration) NPING Network Ping OF Offset Registers Display/Modify PA Printer Attach NOPA Printer Detach PBOOT Bootstrap Operating System PF Port Format NOPF Port Detach PFLASH Program FLASH Memory PS Put RTC into Power Save Mode

RB ROMboot Enable NORB ROMboot Disable RD Register Display REMOTE Remote RESET Cold/Warm Reset

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PPCBug

Table 5-1. Debugger Commands (Continued)

Command Description

RL Read Loop RM Register Modify RS Register Set RUN MPU Execution/Status

SD Switch Directories SET Set Time and Date SROM SROM Examine/Modify SYM Symbol Table Attach NOSYM Symbol Table Detach SYMS Symbol Table Display/Search T Trace TA Terminal Attach TIME Display Time and Date TM Transparent Mode TT Trace to Temporary Breakpoint VE Verify S-Records Against Memory VER Revision/Version Display WL Write Loop

Although a command to allow the erasing and reprogramming of Flash

Caution

memory is available t o you, kee p in mind that reprogr amming any po rtion of Flash memory will erase everything currently contained in Flash, including the PPCBug debugger.

Note Both banks A and B of Flash contain the PPCBug debugger.

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Motorola MVME2431-1, MVME2403-1, MVME2431-3, MVME2401-1, MVME2432-1 Installation And Use Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

List of Figures

List of T ables

About This Manual

Summary of Changes

Overview of Contents

Comments and Suggestions

Conventions Used in This Manual

Introduction

Description

MVME240x Module

PMCspan Expansion Mezzanine

PCI Mezzanine Cards (PMCs)

VMEsystem Enclosure

System Console Terminal

Overview of Start-Up Procedures

Unpacking Instructions

Hardware Configuration

MVME2400 Base Board Preparation

Flash Bank Selection (J8)

System Controller Selection (J9)

Software-Readable Header (SRH) Switch (S3)

PMC Preparation

PMCspan Preparation

System Console Terminal Preparation

Hardware Installation

PMC Module Installation

Primary PMCspan Installation

Secondary PMCspan Installation

MVME240x Installation

System Considerations

2Operating Instructions

Overview

Applying Power

Switches

ABT (S1)

RST (S2)

Front Panel Indicators (DS1 – DS4)

BFL (DS1)

CPU (DS2)

PMC2 (DS3)

PMC1 (DS4)

10/100BaseT Port

DEBUG Port

PMC Slots

PCI MEZZANINE CARD (PMC Slot 1)

PCI MEZZANINE CARD (PMC Slot 2)

PMCspan

3Functional Description

Introduction

Features

General Description

Block Diagram

MPC750 Processor

L2 Cache

Hawk System Memory Controller (SMC)/PCI Host Bridge (PHB) ASIC

PCI Bus Latency

PPC Bus Latency

Assumptions

Clock Ratios and Operating Frequencies

PPC60x Originated

PCI Originated

SDRAM Memory

SDRAM Latency

Flash Memory

ROM/Flash Performance

Ethernet Interface

PCI Mezzanine Card (PMC) Interface

PMC Slot 1 (Single-Width PMC)

PMC Slot 2 (Single-Width PMC)

PMC Slots 1 and 2 (Double-Width PMC)

PCI Expansion

VMEbus Interface

Asynchronous Debug Port

PCI-ISA Bridge (PIB) Controller

Real-Time Clock/NVRAM/Timer Function