Motorola MVME2301, MVME2303, MVME2302, MVME2304, MVME2305 Installation And Use Manual

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MVME2300-Series

VME Processor Module

Installation and Use

V2300A/IH2

Page 2

Notice

While reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes.

No part of this material may be reproduced or copied in any tangible medium, or stored in a retrieval system, or transmitted in any form, or by any means, radio, electronic, mechanical, photocopying, recording or facsimile, or otherwise, without the prior written permission of Motorola, Inc.

It is possible that this publication may contain reference to, or information about Motorola products (machines and programs), programming, or services that are not announced in your country. Such references or information must not be construed to mean that Motorola intends to announce such Motorola products, programming, or services in your country.

Restricted Rights Legend

If the documentation contained herein is supplied, directly or indirectly, to the U.S. Government, the following notice shall apply unless otherwise agreed to in writing by Motorola, Inc.

Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227-7013.

Motorola, Inc.

Computer Group

2900 South Diablo Way

Tempe, Arizona 85282

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Preface

The

MVME2300-Series VME Processor Module Installation and Use

information you will need to install and use your MVME2300-series VME processor module. The MVME2300 VME processor module is based on an MPC603 or MPC604 PowerPC microprocessor, and features dual PCI Mezzanine Card (PMC) slots with front panel and/or P2 I/O. The MVME2300 is currently available in the following conÞgurations:

Model MPC Memory

MVME2301 MPC603

MVME2302 32MB ECC DRAM

MVME2303 64MB ECC DRAM

MVME2304 128MB ECC DRAM

MVME2305 MPC604

MVME2306 32MB ECC DRAM

MVME2307 64MB ECC DRAM

MVME2308 128MB ECC DRAM

@ 200 MHz

@ 300 MHz

16MB ECC DRAM

The MVME2300-series module is compatible with optional double-width or single-width PCI Mezzanine Cards (PMCs) , and the PMCspan PCI expansion mezzanine module. By utilizing the two onboard PMC slots and stacking PMCspan(s), the MVME2300 provides support for up to six PMCs.

manual provides

This manual includes hardware preparation and installation instructions for the MVME2300-series module, information about using the front panel, a functional description, information about programming the board, using the PPCBug debugging Þrmware, and advanced debugger topics. Other appendices provide the MVME2300-series speciÞcations, connector pin assignments, and a glossary of terms. Additional manuals you may wish to obtain are listed in Appendix A,

Ordering Related Documentation

The information in this manual applies principally to the MVME2300-series module. The PMCspan and PMCs are described brießy here but are documented in detail in separate publications, furnished with those products. Refer to the individual product documentation for complete preparation and installation instructions. These manuals are listed in Appendix A,

Documentation

Ordering Related

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This manual is intended for anyone who wants to design OEM systems, supply additional capability to an existing compatible system, or work in a lab environment for experimental purposes. A basic knowledge of computers and digital logic is assumed.

Document T erminology

Throughout this manual, a convention is used which precedes data and address parameters by a character identifying the numeric format as follows:

$ Dollar 0x Zero-x % Percent Specifies a binary number & Ampersand Specifies a decimal number

Specifies a hexadecimal character

For example, Ò12Ó is the decimal number twelve, and Ò$12Ó (hexadecimal) is the equivalent of decimal number eighteen. Unless otherwise speciÞed, all address references are in hexadecimal.

An asterisk (*) following the signal name for signals which are

level-significant

denotes that the signal is true or valid when the signal is low.

An asterisk (*) following the signal name for signals which are

edge-significant

denotes that the actions initiated by that signal occur on high-to-low transition.

In this manual,

assertion

particular state. In particular, true;

negation

and

negation

assertion

negate

indicate a signal that is inactive or false. These terms are

are used to specify forcing a signal to a

and

assert

refer to a signal that is active or

used independently of the voltage level (high or low) that they represent.

Data and address sizes are deÞned as follows:

Byte 8 bits, numbered 0 through 7, with bit 0 being the least significant. Half word 16 bits, numbered 0 through 15, with bit 0 being the least significant. Word 32 bits, numbered 0 through 31, with bit 0 being the least significant. Double word 64 bits, numbered 0 through 63, with bit 0 being the least si

gnificant.

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Safety Summary

Safety Depends On You

The following general safety precautions must be observed during all phases of operation, service, and repair of this equipment. Failure to comply with these precautions or with speciÞc warnings elsewhere in this manual violates safety standards of design, manufacture, and intended use of the equipment. Motorola, Inc. assumes no liability for the customer's failure to comply with these requirements.

The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You, as the user of the product, should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment.

Ground the Instrument.

To minimize shock hazard, the equipment chassis and enclosure must be connected to an electrical ground. The equipment is supplied with a three-conductor AC power cable. The power cable must be plugged into an approved three-contact electrical outlet. The power jack and mating plug of the power cable meet International Electrotechnical Commission (IEC) safety standards.

Do Not Operate in an Explosive Atmosphere.

Do not operate the equipment in the presence of ßammable gases or fumes. Operation of any electrical equipment in such an environment constitutes a deÞnite safety hazard.

Keep Away From Live Circuits.

Operating personnel must not remove equipment covers. Only Factory Authorized Service Personnel or other qualiÞed maintenance personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment. Do not replace components with power cable connected. Under certain conditions, dangerous voltages may exist even with the power cable removed. To avoid injuries, always disconnect power and discharge circuits before touching them.

Do Not Service or Adjust Alone.

Do not attempt internal service or adjustment unless another person capable of rendering Þrst aid and resuscitation is present.

Use Caution When Exposing or Handling the CRT.

Breakage of the Cathode-Ray Tube (CRT) causes a high-velocity scattering of glass fragments (implosion). To prevent CRT implosion, avoid rough handling or jarring of the equipment. Handling of the CRT should be done only by qualiÞed maintenance personnel using approved safety mask and gloves.

Do Not Substitute Parts or Modify Equipment.

Because of the danger of introducing additional hazards, do not install substitute parts or perform any unauthorized modiÞcation of the equipment. Contact your local Motorola representative for service and repair to ensure that safety features are maintained.

Dangerous Procedure Warnings.

Warnings, such as the example below, precede potentially dangerous procedures throughout this manual. Instructions contained in the warnings must be followed. You should also employ all other safety precautions which you deem necessary for the operation of the equipment in your operating environment.

Dangerous voltages, capable of causing death, are present in

WARNING

this equipment. Use extreme caution when handling, testing, and adjusting.

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This equipment generates, uses, and can radiate electro-magnetic energy. It

WARNING

EN55022 (CISPR 22) Radio Frequency Interference EN50082-1 (IEC801-2, IEC801-3, IEC801-4) Electromagnetic Immunity The product also fulfills EN60950 (product safety) which is essentially the requirement for the

Low Voltage Directive (73/23/EEC). This board product was tested in a representative system to show compliance with the above

mentioned requirements. A proper installation in a CE-marked system will maintain the required EMC/safety performance. For minimum RF emissions, it is essential that you implement the following conditions:

1. Install shielded cables on all external I/O ports.

2. Connect conductive chassis rails to earth ground to provide a path for connecting shields to earth ground.

3. Tighten all front panel screws.

may cause or be susceptible to electro-magnetic interference (EMI) if not installed and used in a cabinet with adequate EMI protection.

If any modifications are made to the product, the modifier assumes responsibility for radio frequency interference issues. Changes or modifications not expressly approved by Motorola Computer Group could void the userÕs authority to operate the equipment.

European Notice: Board products with the CE marking comply with the EMC Directive (89/336/EEC). Compliance with this directive implies conformity to the following European Norms:

All Motorola PWBs (printed wiring boards) are manufactured by UL-recognized manufacturers, with a ßammability rating of 94V-0.

The computer programs stored in the Read Only Memory of this device contain material copyrighted by Motorola Inc., 1995, and may be used only under a license such as those contained in MotorolaÕs software licenses.

The software described herein and the documentation appearing herein are furnished under a license agreement and may be used and/or disclosed only in accordance with the terms of the agreement.

The software and documentation are copyrighted materials. Making unauthorized copies is prohibited by law.

No part of the software or documentation may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language or computer language, in any form or by any means without the prior written permission of Motorola, Inc.

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Motorola¨ and the Motorola symbol are registered trademarks of Motorola, Inc. PowerPCª is a trademark of International Business Machines Corporation and is used by Motorola with permission.

All other products mentioned in this document are trademarks or registered trademarks of their respective holders.

Printed in the United States of America

April 1998

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Contents

Chapter 1 Preparing and Installing the MVME2300-Series Module

Introduction ..........................................................................................................1-1

MVME230x Description ......................................................................................1-1

MVME230x Module ......................................................................................1-2

PMCspan Expansion Mezzanine.................................................................1-3

PCI Mezzanine Cards (PMCs) .....................................................................1-3

VMEsystem Enclosure ..................................................................................1-4

System Console Terminal .............................................................................1-4

Overview of Start-Up Procedures......................................................................1-4

Unpacking the MVME230x Hardware..............................................................1-7

Preparing the MVME230x Hardware................................................................1-7

MVME230

Setting the Flash Memory Bank A/Bank B Reset Vector

Header (J15) ......................................................................................... 1-10

Setting the VMEbus System Controller Selection Header (J16) .... 1-10

Setting the General-Purpose Software-Readable Header (J17) ..... 1-11

PMCs .............................................................................................................1-12

PMCspan.......................................................................................................1-12

System Console Terminal ...........................................................................1-12

Installing the MVME230x Hardware ..............................................................1-13

Taking ESD Precautions..............................................................................1-13

PMCs .............................................................................................................1-13

Primary PMCspan .......................................................................................1-15

Secondary PMCspan ...................................................................................1-18

MVME230

Installation Considerations ........................................................................1-23

.....................................................................................................1-7

...................................................................................................1-21

Chapter 2 Operating Instructions

Introduction ..........................................................................................................2-1

Applying Power ...................................................................................................2-1

MVME230

Switches...........................................................................................................2-2

............................................................................................................2-2

ABT (S1)................................................................................................... 2-3

Page 10

RST (S2) ................................................................................................... 2-3

Status Indicators ............................................................................................ 2-4

BFL (DS1) ................................................................................................ 2-4

CPU (DS2) ............................................................................................... 2-4

PMC (DS3) .............................................................................................. 2-4

PMC (DS4) .............................................................................................. 2-4

10/100 BASET Port .......................................................................................2-4

DEBUG Port ................................................................................................... 2-5

PMC Slots .......................................................................................................2-6

PCI MEZZANINE CARD (PMC Slot 1) ............................................. 2-6

PCI MEZZANINE CARD (PMC Slot 2) ............................................. 2-6

PMCspan............................................................................................................... 2-7

Chapter 3 Functional Description

Introduction ..........................................................................................................3-1

Features .................................................................................................................3-1

General Description............................................................................................. 3-3

Block Diagram ...................................................................................................... 3-3

MPC603/604 Processor ................................................................................3-3

PCI Bus Latency ..................................................................................... 3-5

DRAM Memory............................................................................................. 3-7

DRAM Latency....................................................................................... 3-8

Flash Memory .............................................................................................. 3-11

Flash Latency........................................................................................ 3-12

Ethernet Interface ........................................................................................3-12

PCI Mezzanine Card (PMC) Interface...................................................... 3-13

PMC Slot 1 (Single-Width PMC) ....................................................... 3-14

PMC Slot 2 (Single-Width PMC) ....................................................... 3-14

PMC Slots 1 and 2 (Double-Width PMC)......................................... 3-15

PCI Expansion ...................................................................................... 3-15

VMEbus Interface........................................................................................ 3-15

Asynchronous Debug Port......................................................................... 3-16

PCI-ISA Bridge (PIB) Controller................................................................ 3-16

Real-Time Clock/NVRAM/Timer Function ........................................... 3-17

PCI Host Bridge........................................................................................... 3-18

Interrupt Controller (MPIC).......................................................................3-18

Programmable Timers ................................................................................ 3-19

Interval Timers ..................................................................................... 3-19

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16/32-Bit Timers................................................................................... 3-19

Chapter 4 Programming the MVME230x

Introduction ..........................................................................................................4-1

Memory Maps.......................................................................................................4-1

Processor Bus Memory Map ........................................................................4-2

Default Processor Memory Map.......................................................... 4-2

PCI Local Bus Memory Map........................................................................4-3

VMEbus Memory Map .................................................................................4-3

Programming Considerations ............................................................................4-4

PCI Arbitration...............................................................................................4-4

Interrupt Handling........................................................................................4-6

DMA Channels...............................................................................................4-8

Sources of Reset..............................................................................................4-8

Endian Issues................................................................................................4-10

Processor/Memory Domain............................................................... 4-10

PCI Domain........................................................................................... 4-10

VMEbus Domain.................................................................................. 4-11

Chapter 5 PPCBug

PPCBug Overview ...............................................................................................5-1

PPCBug Basics ......................................................................................................5-1

Memory Requirements .................................................................................5-3

PPCBug Implementation..............................................................................5-3

MPU, Hardware, and Firmware Initialization.................................................5-3

Using PPCBug ......................................................................................................5-5

Debugger Commands...................................................................................5-6

Diagnostic Tests............................................................................................5-10

Chapter 6 Modifying the Environment

Overview ...............................................................................................................6-1

CNFG - ConÞgure Board Information Block ...................................................6-2

ENV - Set Environment.......................................................................................6-3

ConÞguring the PPCBug Parameters .........................................................6-3

ConÞguring the VMEbus Interface...........................................................6-13

Motorola Computer Group Documents ..........................................................A-1

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ManufacturersÕ Documents............................................................................... A-2

Related SpeciÞcations.........................................................................................A-5

SpeciÞcations ........................................................................................................B-1

Cooling Requirements.........................................................................................B-3

EMC Regulatory Compliance ............................................................................B-4

Introduction ......................................................................................................... C-1

Pin Assignments.................................................................................................. C-1

VMEbus Connector - P1 ..............................................................................C-2

VMEbus Connector - P2 ..............................................................................C-4

Serial Port Connector - DEBUG (J2)........................................................... C-6

Ethernet Connector - 10BASET (J3) ........................................................... C-6

CPU Debug Connector - J1.......................................................................... C-7

PCI Expansion Connector - J18................................................................. C-12

PCI Mezzanine Card Connectors - J11 through J14............................... C-15

PCI Mezzanine Card Connectors - J21 through J24............................... C-18

Solving Startup Problems .................................................................................. D-1

Abbreviations, Acronyms, and Terms to Know ...........................................GL-1

xii

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Figures

Figure 1-1. MVME230x Switches, LEDs, Headers, Connectors....................1-9

Figure 1-2. General-Purpose Software-Readable Header............................ 1-12

Figure 1-3. Typical Single-width PMC Module Placement on

MVME230x......................................................................................................... 1-15

Figure 1-4. PMCspan-002 Installation on an MVME230x............................1-17

Figure 1-5. PMCspan-010 Installation onto a

PMCspan-002/MVME230x..............................................................................1-19

Figure 2-1. MVME230x DEBUG Port ConÞguration......................................2-5

Figure 3-1. MVME230x Block Diagram............................................................3-4

Figure 3-2. Memory Block Diagram..................................................................3-8

Figure 4-1. VMEbus Master Mapping ..............................................................4-5

Figure 4-2. MVME230x Interrupt Architecture ...............................................4-7

xiii

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xiv

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Tables

Table 1-1. MVME230x Models............................................................................1-2

Table 1-2. PMCspan Models ...............................................................................1-3

Table 1-3. Start-Up Overview .............................................................................1-4

Table 3-1. MVME230x Features..........................................................................3-1

Table 3-2. Power Requirements..........................................................................3-5

Table 3-3. PowerPC 60x Bus to PCI Access Timing .........................................3-6

Table 3-4. PCI to ECC Memory Access Timing ................................................3-7

Table 3-5. PowerPC 60x Bus to DRAM Access Timing using 60ns Page

Devices ................................................................................................................3-9

Table 3-6. PowerPC 60x Bus to DRAM Access Timing Using 50ns, EDO

Devices ..............................................................................................................3-10

Table 3-7. PowerPC 60x Bus to FLASH Access Timing for Bank B

(16-bit Port).........................................................................................................3-12

Table 4-1. Processor Default View of the Memory Map .................................4-2

Table 4-2. PCI Arbitration Assignments............................................................4-6

Table 4-3. Classes of Reset and Effectiveness ................................................... 4-9

Table 5-1. Debugger Commands........................................................................5-7

Table 5-2. Diagnostic Test Groups.................................................................... 5-11

Table A-1. Motorola Computer Group Documents........................................A-1

Table A-2. ManufacturersÕ Documents.............................................................A-2

Table A-3. Related SpeciÞcations ......................................................................A-5

Table B-1. MVME230x SpeciÞcations ............................................................... B-1

Table C-1. P1 VMEbus Connector Pin Assignments...................................... C-2

Table C-2. P2 Connector Pin Assignment........................................................ C-4

Table C-3. DEBUG (J2)Connector Pin Assignments....................................... C-6

Table C-4. 10/100 BASET (J3) Connector Pin Assignments..........................C-6

Table C-5. Debug Connector Pin Assignments............................................... C-7

Table C-6. J18 - PCI Expansion Connector Pin Assignments......................C-12

Table C-7. J11 - J12 PMC1 Connector Pin Assignments............................... C-15

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Table C-8. J13 - J14 PMC1 Connector Pin Assignments............................... C-16

Table C-9. J21 and J22 PMC2 Connector Pin Assignments......................... C-18

Table C-10. J23 and J24 PMC2 Connector Pin Assignments....................... C-19

Table D-1. Troubleshooting MVME230x Modules .........................................D-2

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1Preparing and Installing the

MVME2300-Series Module

Introduction

This chapter provides a brief description of the MVME2300-Series VME Processor Module, and instructions for preparing and installing the hardware.

In this manual, the name MVME230 MVME2300-series boards, unless otherwise specified.

MVME230x Description

The MVME2300-series VME processor module is a PCI Mezzanine Card (PMC) carrier board. It is based on the PowerPCª 603 or 604 microprocessor, MPC603 or MPC604.

Two front panel cutouts provide access to PMC I/O. One doublewidth or two single-width PMCs can be installed directly on the MVME230x. Optionally, one or two PMCspan PCI expansion mezzanine modules can be added to provide the capability of up to four additional PMC modules.

refers to all models of the

Two RJ45 connectors on the front panel provide the interface to 10/100Base-T Ethernet, and to a debug serial port.

The following list is of equipment that is appropriate for use in an MVME230x system:

❏

PMCspan PCI expansion mezzanine module

❏

Peripheral Component Interconnect (PCI) Mezzanine Cards (PMC)s

❏

VMEsystem enclosure

❏

System console terminal

❏

Disk drives (and/or other I/O) and controllers

❏

Operating system (and/or application software)

1-1

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Preparing and Installing the MVME2300-Series Module

MVME230x Module

The MVME230x module is a powerful, low-cost embedded VME controller and intelligent PMC carrier board. The MVME230x is currently available in the configurations shown in Table 1-1.

The MVME230x includes support circuitry such as ECC DRAM, PROM/Flash memory, and bridges to the Industry Standard Architecture (ISA) bus and the VMEbus. The MVME230xÕs PMC carrier architecture allows flexible configuration options and easy upgrades. It is designed to support one or two PMCs, plus one or two optional PCI expansion mezzanine modules that each support up to two PMCs. It occupies a single VMEmodule slot, except when optional PCI expansion mezzanine modules are also used:

Table 1-1. MVME230x Models

MVME230x MPC Type

MVME2301 MPC603 MVME2302 32MB ECC DRAM MVME2303 64MB ECC DRAM MVME2304 128MB ECC DRAM MVME2305 MPC604 MVME2306 32MB ECC DRAM MVME2307 64MB ECC DRAM MVME2308 128MB ECC DRAM

@ 200 MHz

@ 300 MHz

16MB ECC DRAM

1-2

The MVME230x interfaces to the VMEbus via the P1 and P2 connectors. It also draws +5V, +12V, and -12V power from the VMEbus backplane through these two connectors. The +3.3V power, used for the PCI bridge chip and possibly for the PMC mezzanine, is derived onboard from the +5V power.

Support for two IEEE P1386.1 PCI mezzanine cards is provided via eight 64-pin SMT connectors. Front panel openings are provided on the MVME230x board for the two PMC slots.

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MVME230x Description

In addition, there are 64 pins of I/O from PMC slot 1 and 46 pins of I/O from PMC slot 2 that are routed to P2. The two PMC slots may contain two single-wide PMCs or one double-wide PMC.

PMCspan Expansion Mezzanine

An optional PCI expansion mezzanine module or PMC carrier board, PMCspan, provides the capability of adding two additional PMCs. Two PMCspans can be stacked on an MVME230x, providing four additional PMC slots, for a total of six slots including the two onboard the MVME230x. Table 1-2 lists the PMCspan models that are available for use with the MVME230x.

Table 1-2. PMCspan Models

Expansion Module Description

PMCSPAN-002 Primary PCI expansion mezzanine module. Allows two PMC

modules for the MVME230

PMCSPAN-010 Secondary PCI expansion mezzanine module. Allows two

additional PMC modules for the MVME230 32-bit PCI bridge; requires a PMCSPAN-002.

. Includes 32-bit PCI bridge.

. Does not include

PCI Mezzanine Cards (PMCs)

The PMC slots on the MVME230x board are IEEE P1386.1 compliant. P2 I/O-based PMCs that follow the PMC committee recommendation for PCI I/O when using the 5-row VME64 extension connector will be pin-out compatible with the MVME230x.

The MVME230x board supports both front panel I/O and rear panel P2 I/O through either PMC slot 1 or PMC slot 2. 64 pins of I/O from slot 1 and 46 pins of I/O from slot 2 are routed directly to P2.

1-3

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Preparing and Installing the MVME2300-Series Module

VMEsystem Enclosure

Your MVME230x board must be installed in a VMEsystem chassis with both P1 and P2 backplane connections. It requires a single slot, except when PMCspan carrier boards are used. Allow one extra slot for each PMCspan.

System Console Terminal

In normal operation, connection of a debug console terminal is required only if you intend to use the MVME230xÕs debug firmware, PPCBug, interactively. An RJ45 connector is provided on the front panel of the MVME230x for this purpose.

Overview of Start-Up Procedures

The following table lists the things you will need to do before you can use this board, and tells where to find the information you need to perform each step. Be sure to read this entire chapter and read all Caution and Warning notes before beginning.

Table 1-3. Start-Up Overview

What you need to do ... Refer to ... On page ...

Unpack the hardware. Set jumpers on the

MVME230x module.

Prepare the PMCs.

1-4

Unpacking the MVME230x Hardware

Preparing the MVME230x Hardware

MVME230x

PMCs

For additional information on PMCs, refer to the PMC manuals provided with these cards.

1-7 1-7 1-7 1-14

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Overview of Start-Up Procedures

Table 1-3. Start-Up Overview (Continued)

What you need to do ... Refer to ... On page ...

Prepare the PMCspan module(s).

Prepare a console terminal. Prepare any other optional

devices or equipment you will be using.

Install the PMCs on the MVME230x module.

Install the primary PMCspan module (if used).

Install the secondary PMCspan module (if used).

Install and connect the MVME230x module.

Connect a console terminal.

PMCspan

For additional information on PMCspan, refer to the

Carrier Module Installation and Use

manual, listed in Appendix A,

Unpacking the MVME230x Hardware

Note If the shipping carton(s) is/are damaged upon receipt,

request that the carrier's agent be present during the unpacking and inspection of the equipment.

Unpack the equipment from the shipping carton(s). Refer to the packing list(s) and verify that all items are present. Save the packing material for storing and reshipping of equipment.

Avoid touching areas of integrated circuitry; static

Caution

discharge can damage these circuits.

Preparing the MVME230x Hardware

MVME230

To produce the desired configuration and ensure proper operation of the MVME230x, you may need to carry out certain modifications before and after installing the modules.

The following paragraphs discuss the preparation of the MVME230x hardware components prior to installing them into a chassis and connecting them.

The MVME230x provides software control over most options; by setting bits in control registers after installing the MVME230x in a system, you can modify its configuration. The MVME230x control registers are briefly described in Chapter 4, with additional information in the MVME2300-Series VME Processor Module

Programmer's Reference Guide as listed in the table Motorola Computer Group Documents in Appendix A, Ordering Related Documents.

1-7

Page 24

Preparing and Installing the MVME2300-Series Module

Some options, however, are not software-programmable. Such options are controlled through manual installation or removal of header jumpers or interface modules on the MVME230x or the associated modules.

Figure 1-1 illustrates the placement of the switches, jumper headers, connectors, and LED indicators on the MVME230x. Manually configurable items on the MVME230x include:

❏ Flash memory bank A/bank B reset vector (J15) ❏ VMEbus system controller selection header (J16) ❏ General-purpose software-readable header (J17)

The MVME230x has been factory tested and is shipped with the configurations described in the following sections. The MVME230x factory-installed debug monitor, PPCBug, operates with those factory settings.

1-8

Page 25

Preparing the MVME230x Hardware

MVME

230x

189 190

DEBUG

PORT

A1B1C1

ABT

BFL

CPU

RST

PMC

10/100 BASET

PCI MEZZANINE CARD PCI MEZZANINE CARD

ABORT

RESET

ETHERNET

PORT

264

J21

J22

XU2 XU1

PMC 2 PMC1

FLASH SOCKETS

264

J23

264

J11

264

J24

J12

264

A32

B32

C32

264

A1B1C1

264

VME BUS

264

SWITCH

S1 S2

SWITCH

2063 9708

J14

J13

READEABLE

SOFTWARE

HEADER

J15

J16

113 114

16 15

J17

J18

Figure 1-1. MVME230x Switches, LEDs, Headers, Connectors

C32

B32

A32

1-9

Page 26

Preparing and Installing the MVME2300-Series Module

Setting the Flash Memory Bank A/Bank B Reset Vector Header (J15)

Bank B consists of 1 MB of 8-bit Flash memory in two 32-pin PLCC 8-bit sockets.

Bank A consists of four 16-bit Smart Voltage SMT devices that can be populated with 8Mbit Flash devices (4 MB) or 4Mbit Flash devices (2 MB). A jumper header, J15, associated with the first set of four Flash devices provides a total of 64KB of hardware-protected boot block. Only 32-bit writes are supported for this bank of Flash. The address of the reset vector is jumper-selectable. A jumper must be installed either between J15 pins 1 and 2 for Bank A factory configuration, or between J15 pins 2 and 3 for Bank B. When the jumper is installed, the Falcon chipset maps 0xFFF00100 to the Bank B sockets..

J15

1 2

Bank A (factory configuration)

J15

1 2

Bank B

Setting the VMEbus System Controller Selection Header (J16)

The MVME230x is factory-configured in automatic system controller mode; i.e., a jumper is installed across pins 2 and 3 of header J16. This means that the MVME230x determines if it is system controller at system power-up or reset by its position on the bus; if it is in slot 1 on the VME system, it configures itself as the system controller.

Remove the jumper from J16if you intend to operate the MVME230x as system controller in all cases.

Install the jumper across pins 1 and 2 if the MVME230x is not to operate as system controller under any circumstances.

1-10

Page 27

Preparing the MVME230x Hardware

J16

1 2

Automatic System Controller

(factory configuration)

System Controller Enabled

J16

1 2

System Controller Disabled

Setting the General-Purpose Software-Readable Header (J17)

Header J17 provides eight readable jumpers. These jumpers can be read as a register at ISA I/O address $801 (hexadecimal). Bit 0 is associated with header pins 1 and 2; bit 7 is associated with pins 15 and 16. The bit values are read as a and as a

1 when the jumper is removed. The MVME230x is shipped

from the factory with J17 set to all

0 when the jumper is installed,

0s (jumpers on all pins), as shown

in Figure 1-2.

The PowerPC firmware, PPCBug, reserves all bits, SRH0 to SRH7.

With the jumper installed between pins 3 and 4 (factory configuration), the debugger uses the current user setup/operation parameters in Flash. When the jumper is removed (making the bit a 1), the debugger uses the default setup/operation parameters in NVRAM instead. Refer to the ENV command description in Chapter 6 for the NVRAM defaults.

J16

1 2

1-11

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Preparing and Installing the MVME2300-Series Module

Figure 1-2. General-Purpose Software-Readable Header

PMCs

PMCspan

PPCBug INSTALLED

Reserved for future use

Setup parameter source (In=Flash; Out=NVRAM)

Reserved for future use

16Bit 7 (SRH7)

Reserved for future use

Bit 0 (SRH0)

Bit 1 (SRH1)

Bit 2 (SRH2)

Bit 3 (SRH3)

Bit 4 (SRH4)

Bit 5 (SRH5)

Bit 6 (SRH6)

J17

For a discussion of any configurable items on the PMCs, refer to the userÕs manual for the particular PMCs.

You will need to use an additional slot in the VME chassis for each PMCspan expansion module you plan to use. Before installing a PMCspan on the MVME230x, you must install the selected PMCs on the PMCspan. Refer to the PMCspan PMCAdapter Carrier Module Instllation and Use manual for instructions.

System Console Terminal

Ensure that jumpers are installed on all bits on header J17 of the MVME230x board as shown in Figure 1-2. This is necessary when the PPCBug firmware is used. Connect the terminal via a cable to the RJ45 DEBUG connector J2. See Table C-3 for pin signal assignments. Set up the terminal as follows:

1-12

Page 29

Installing the MVME230x Hardware

Ð Eight bits per character Ð One stop bit per character Ð Parity disabled (no parity) Ð Baud rate = 9600 baud (default baud rate of the port at

power-up); after power-up, you can reconfigure the baud rate with PPCBugÕs PF command

Installing the MVME230x Hardware

The following paragraphs discuss installing PMCs onto the MVME230x, installing PMCspan modules onto the MVME230x, installing the MVME230x into a VME chassis, and connecting an optional system console terminal.

Taking ESD Precautions

Use ESD

Wrist Strap

PMCs

Motorola strongly recommends that you use an antistatic wrist strap and a conductive foam pad when installing or upgrading a system. Electronic components, such as disk drives, computer boards, and memory modules, can be extremely sensitive to Electro-Static Discharge (ESD). After removing the component from the system or its protective wrapper, place the component flat on a grounded, static-free surface (and in the case of a board, component side up). Do not slide the component over any surface.

If an ESD station is not available, you can avoid damage resulting from ESD by wearing an antistatic wrist strap (available at electronics stores) that is attached to an unpainted metal part of the system chassis.

PCI mezzanine card (PMC) modules mount on top of the MVME230x module, and/or on a PMCspan. Refer to Figure 1-3 and perform the following steps to install a PMC on your MVME230x module. This procedure assumes that you have read the userÕs manual that came with your PMCs.

1-13

Page 30

Preparing and Installing the MVME2300-Series Module

1. Attach an ESD strap to your wrist. Attach the other end of the ESD strap to the chassis as a ground. The ESD strap must be secured to your wrist and to ground throughout the procedure.

2. Perform an operating system shutdown. Turn the AC or DC power off and remove the AC cord or DC power lines from the system. Remove chassis or system cover(s) as necessary for access to the VMEmodules.

Inserting or removing modules with power applied

Caution

Warning

may result in damage to module components.

Dangerous voltages, capable of causing death, are present in this equipment. Use extreme caution when handling, testing, and adjusting.

3. If the MVME230x has already been installed in a VMEbus card slot, carefully remove it. Lay the MVME230x flat, with connectors P1 and P2 facing you.

Caution

1-14

Avoid touching areas of integrated circuitry; static discharge can damage these circuits.

4. Remove the PCI filler plate from the selected PMC slot in the front panel of the MVME230x. If installing a double-width PMC, remove the filler plates from both PMC slots.

Page 31

Installing the MVME230x Hardware

2064 9708

Figure 1-3. Typical Single-width PMC Module Placement on MVME230x

5. Slide the edge connector(s) of the PMC module into the front panel opening(s) from behind and place the PMC module on top of the MVME230x. The four connectors on the underside of the PMC module should then connect smoothly with the corresponding connectors for a single-width PMC (J11/J12/J13/J14 or J21/J22/J23/J24, all eight for a doublewidth PMC) on the MVME230x.

6. Insert the two short Phillips screws through the holes at the forward corners of the PMC module, into the standoffs on the MVME230x. Tighten the screws.

7. If installing two single-width PMCs, repeat the above procedure for the second PMC.

Primary PMCspan

To install a PMCspan-002 PCI expansion module on your MVME230x, refer to Figure 1-4 and perform the following steps. This procedure assumes that you have read the userÕs manual that

1-15

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Preparing and Installing the MVME2300-Series Module

was furnished with the PMCspan, and that you have installed the selected PMCs on the PMCspan according to the instructions given in the PMCspan and PMC manuals.

1. Attach an ESD strap to your wrist. Attach the other end of the ESD strap to the chassis as a ground. The ESD strap must be secured to your wrist and to ground while you are performing the installation procedure.

Inserting or removing modules with power applied

Caution

Warning

may result in damage to module components.

Dangerous voltages, capable of causing death, are present in this equipment. Use extreme caution when handling, testing, and adjusting.

Caution

1-16

3. If the MVME230x has already been installed in the chassis, carefully remove it from the VMEbus card slot and lay it flat, with connectors P1 and P2 facing you.

Avoid touching areas of integrated circuitry; static discharge can damage these circuits.

Page 33

Installing the MVME230x Hardware

J18

Figure 1-4. PMCspan-002 Installation on an MVME230x

2081 9708

1-17

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Preparing and Installing the MVME2300-Series Module

4. Attach the four standoffs to the MVME230x module. For each standoff:

Ð Insert the threaded end into the standoff hole at each

corner of the VME processor module.

Ð Thread the locking nuts onto the standoff tips.

Ð Tighten the nuts with a box-end wrench or a pair of needle

nose pliers.

5. Place the PMCspan on top of the MVME230x module. Align the mounting holes in each corner to the standoffs, and align PMCspan connector P4 with MVME230x connector J18.

6. Gently press the PMCspan and MVME230x together, making sure that P4 is fully seated into J18.

7. Insert the four short Phillips screws through the holes at the corners of the PMCspan and into the standoffs on the MVME230x module. Tighten the screws.

Note The screws have two different head diameters. Use the

screws with the smaller heads on the standoffs next to VMEbus connectors P1 and P2.

Secondary PMCspan

The PMCspan-010 PCI expansion module mounts on top of a PMCspan-002 PCI expansion module. To install a PMCspan-010 on your MVME230x, refer to Figure 1-5 and perform the following steps. This procedure assumes that you have read the userÕs manual that was furnished with the PMCspan, and that you have installed the selected PMCs on the PMCspan according to the instructions given in the PMCspan and PMC manuals.

1-18

Page 35

Installing the MVME230x Hardware

2065 9708

Figure 1-5. PMCspan-010 Installation onto a PMCspan-002/MVME230x

1-19

Page 36

Preparing and Installing the MVME2300-Series Module

Inserting or removing modules with power applied

Caution

Warning

Caution

may result in damage to module components.

Dangerous voltages, capable of causing death, are present in this equipment. Use extreme caution when handling, testing, and adjusting.

3. If the Primary PMC Carrier Module/MVME230x assembly is already installed in the VME chassis, carefully remove the two-board assembly from the VMEbus card slots and lay it flat, with the P1 and P2 connectors facing you.

Avoid touching areas of integrated circuitry; static discharge can damage these circuits.

1-20

4. Remove the four short Phillips screws from the standoffs in each corner of the primary PCI expansion module, PMCspan-002.

5. Attach the four standoffs to the PMCspan-002.

6. Place the PMCspan-010 on top of the PMCspan-002. Align the mounting holes in each corner to the standoffs, and align PMCspan-010 connector P3 with PMCspan-002 connector J3.

7. Gently press the two PMCspan modules together, making sure that P3 is fully seated in J3.

8. Insert the four short Phillips screws through the holes at the corners of PMCspan-010 and into the standoffs on the primary PMCspan-002. Tighten the screws.

Note The screws have two different head diameters. Use the

screws with the smaller heads on the standoffs next to VMEbus connectors P1 and P2.

Page 37

Installing the MVME230x Hardware

MVME230

Caution

Before installing the MVME230x into your VME chassis, ensure that the jumpers on the MVME230x J15, J16, and J17 headers are configured, as previously described. This procedure assumes that you have already installed the PMCspan(s) if desired, and any PMCs that you have selected.

Proceed as follows to install the MVME230x in the VME chassis:

1. Attach an ESD strap to your wrist. Attach the other end of the ESD strap to the chassis as a ground. The ESD strap must be secured to your wrist and to ground throughout the procedure.

2. Perform an operating system shutdown:

a. Turn the AC or DC power off and remove the AC cord or

DC power lines from the system.

Inserting or removing modules with power applied may result in damage to module components.

Warning

Dangerous voltages, capable of causing death, are present in this equipment. Use extreme caution when handling, testing, and adjusting.

b. Remove chassis or system cover(s) as necessary for access

to the VMEmodules.

3. Remove the filler panel from the card slot where you are going to install the MVME230x. If you have installed one or more PMCspan PCI expansion modules onto your MVME230x, you will need to remove filler panels from one additional card slot for each PMCspan, above the card slot for the MVME230x.

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Preparing and Installing the MVME2300-Series Module

Ð If you intend to use the MVME230x as system controller, it

must occupy the leftmost card slot (slot 1). The system controller must be in slot 1 to correctly initiate the busgrant daisy-chain and to ensure proper operation of the IACK daisy-chain driver.

Ð If you do not intend to use the MVME230x as system

controller, it can occupy any unused card slot.

Avoid touching areas of integrated circuitry; static

Caution

discharge can damage these circuits.

4. Slide the MVME230x (and PMCspans if used) into the selected card slot(s). Be sure the module or modules is/are seated properly in the P1 and P2 connectors on the backplane. Do not damage or bend connector pins.

5. Secure the MVME230x (and PMCspans if used) in the chassis with the screws provided, making good contact with the transverse mounting rails to minimize RF emissions.

1-22

Note Some VME backplanes (e.g., those used in Motorola

ÒModular ChassisÓ systems) have an auto-jumpering feature for automatic propagation of the IACK and BG signals. Step 6 does not apply to such backplane designs.

6. On the chassis backplane, remove the

ACKNOWLEDGE (IACK) and BUS GRANT (BG) jumpers from

the header for the card slot occupied by the MVME230x.

7. If you intend to use PPCBug interactively, connect the terminal that is to be used as the PPCBug system console to the

DEBUG port on the front panel of the MVME230x.

In normal operation the host CPU controls MVME230x operation via the VMEbus Universe registers.

INTERRUPT

Page 39

Installing the MVME230x Hardware

8. Replace the chassis or system cover(s), cable peripherals to the panel connectors as appropriate, reconnect the system to the AC or DC power source, and turn the equipment power on.

9. The MVME230xÕs green confidence tests is run, and the debugger prompt appears.

Installation Considerations

The MVME230x draws power from the VMEbus backplane connectors P1 and P2. P2 is also used for the upper 16 bits of data in 32-bit transfers, and for the upper 8 address lines in extended addressing mode. The MVME230x may not function properly without its main board connected to VMEbus backplane connectors P1 and P2.

Whether the MVME230x operates as a VMEbus master or as a VMEbus slave, it is configured for 32 bits of address and 32 bits of data (A32/D32). However, it handles A16 or A24 devices in the address ranges indicated in Chapter 4. D8 and/or D16 devices in the system must be handled by the PowerPC processor software. Refer to the memory maps in Chapter 4.

The MVME230x contains shared onboard DRAM whose base address is software-selectable. Both the onboard processor and offboard VMEbus devices see this local DRAM at base physical address $00000000, as programmed by the PPCBug firmware. This may be changed via software to any other base address. Refer to the MVME230x programmer's reference guide for more information.

If the MVME230x tries to access off-board resources in a nonexistent location and is not system controller, and if the system does not have a global bus timeout, the MVME230x waits forever for the VMEbus cycle to complete. This will cause the system to lock up. There is only one situation in which the system might lack this global bus timeout: when the MVME230x is not the system controller and there is no global bus timeout elsewhere in the system.

CPU LED indicates activity as a set of

PPC1-Bug>

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Preparing and Installing the MVME2300-Series Module

Multiple MVME230x boards may be installed in a single VME chassis. Each must have a unique Universe address, selected by setting jumpers on its J17 header, as described in Preparing the MVME230x. In general, hardware multiprocessor features are supported.

Other MPUs on the VMEbus can interrupt, disable, communicate with, and determine the operational status of the processor(s). One register of the Universe set includes four bits that function as location monitors to allow one MVME230x processor to broadcast a signal to any other MVME230x processors. All eight registers are accessible from any local processor as well as from the VMEbus.

1-24

Page 41

2Operating Instructions

Introduction

This chapter provides information about powering up the MVME230x system, and functionality of the switches, status indicators, and I/O ports on the front panels of the MVME230x and PMCspan modules.

Applying Power

After you have verified that all necessary hardware preparation has been done, that all connections have been made correctly, and that the installation is complete, you can power up the system. The MPU, hardware, and firmware initialization process is performed by the PPCBug firmware power-up or system reset. The firmware initializes the devices on the MVME230x module in preparation for booting the operating system.

The firmware is shipped from the factory with an appropriate set of defaults. In most cases there is no need to modify the firmware configuration before you boot the operating system. Refer to Chapter 6 for further information about modifying defaults.

The following flowchart shows the basic initialization process that takes place during MVME230x system start-ups.

For further information on PPCbug, refer to Chapter 5, PPCBug; to Appendix D, Troubleshooting the MVME230x; or to the PPCBug documentation listed in Appendix A.

2-1

Page 42

Operating Instructions

STARTUP

INITIALIZATION

POST

BOOTING

MONITOR

Power-up/reset initialization

Initialize devices on the MVME230x module/system

Power On Self Test diagnostics

Firmware-conﬁgured boot mechanism, if so conﬁgured. Default is no boot.

Interactive, command-driven on-line PowerPC debugger, when terminal connected.

MVME230

The front panel of the MVME230x module is shown on a following page.

Switches

There are two switches (ABT and RST) and four LED (light-emitting diode) status indicators ( MVME230x front panel.

2-2

BFL, CPU, PMC (two)) located on the

Page 43

MVME230x

ABT (S1)

RST (S2)

When activated by software, the Abort switch,

ABT, can generate an

interrupt signal from the base board to the processor at a userprogrammable level. The interrupt is normally used to abort program execution and return control to the debugger firmware located in the MVME230x Flash memory. The interrupt signal reaches the processor module via ISA bus interrupt line IRQ8

∗. The

signal is also available from the general purpose I/O port, which allows software to poll the Abort switch after an IRQ8* interrupt and verify that it has been pressed.

The interrupter connected to the

ABT switch is an edge-sensitive

circuit, filtered to remove switch bounce.

The Reset switch,

RST, resets all onboard devices and causes

HRESET* to be asserted in the MPC603 or MPC604. It also drives a SYSRESET* signal if the MVME230x VME processor module is the system controller.

The Universe ASIC includes both a global and a local reset driver. When the Universe operates as the VMEbus system controller, the reset driver provides a global system reset by asserting the VMEbus signal SYSRESET*. A SYSRESET* signal may be generated by the RESET switch, a power-up reset, a watchdog timeout, or by a control bit in the Miscellaneous Control Register (MISC_CTL) in the Universe ASIC. SYSRESET* remains asserted for at least 200 ms, as required by the VMEbus specification.

Similarly, the Universe ASIC supplies an input signal and a control bit to initiate a local reset operation. By setting a control bit, software can maintain a board in a reset state, disabling a faulty board from participating in normal system operation. The local reset driver is enabled even when the Universe ASIC is not system controller. Local resets may be generated by the

RST switch, a

power-up reset, a watchdog timeout, a VMEbus SYSRESET*, or a control bit in the MISC_CTL register.

2-3

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Operating Instructions

Status Indicators

There are four LED (light-emitting diode) status indicators located on the MVME230x front panel.:

BFL, CPU

BFL (DS1)

The yellow when the BRDFAIL* signal line is active.

, PMC2, and PMC1.

BFL LED indicates board failure; lights

MVME

230x

DEBUG

ABT

BFL

CPU

RST

PMC

10/100 BASET

CPU (DS2)

The green

CPU LED indicates CPU activity; lights

when the DBB* (Data Bus Busy) signal line on the processor bus is active.

PMC (DS3)

The top green

PMC LED indicates PCI activity; lights

PCI MEZZANINE CARD PCI MEZZANINE CARD

when the PCI bus grant to PMC2 signal line on the PCI bus is active. This indicates that a PMC installed on slot 2 is active.

PMC (DS4)

The bottom green lights when the PCI bus grant to PMC1 signal line on the PCI bus is active. This indicates that a PMC installed on slot 1 is active.

10/100 BASET Port

The RJ45 port on the front panel of the MVME230x labeled 10BaseT/100Base TX interface, implemented with a DEC 21140/21143 device.

2-4

10/100 BASET supplies the Ethernet LAN

PMC LED indicates PCI activity;

Page 45

MVME230x

DEBUG Port

The RJ45 port labeled DEBUG on the front panel of the MVME230x supplies the MVME230x serial communications interface, implemented via a UART PC16550 controller chip from National Semiconductor. It is asynchronous only. This serial port is configured for EIA-232-D DTE, as shown in Figure 2-1.

The MVME230x to serve as the firmware console for the factory installed debugger, PPCBug. The port is configured as follows:

After power-up, the baud rate of the reconfigured by using the debuggerÕs Port Format (PF) command. Refer to Chapters 5 and 6 for information about PPCBug.

DEBUG port may be used for connecting a terminal to the

❏ 8 bits per character ❏ 1 stop bit per character ❏ Parity disabled (no parity) ❏ Baud rate = 9600 baud (default baud rate at power-up)

DEBUG port can be

SOUT RTS*

DTR* SIN CTS* DCD*

PC16550

MVME230x

4 2 8 5 7 1

3 6

Debug RJ45

Figure 2-1. MVME230x DEBUG Port Conﬁguration

2-5

Page 46

Operating Instructions

PMC Slots

Two openings located on the front panel provide I/O expansion by allowing access to one or two 4-port single-wide or one 8-port double-wide PCI Mezzanine Card (PMC), connected to the PMC connectors on the MVME230x. For pin assignments for the PMC connectors, refer to Appendix C.

Do not attempt to install any PMC boards without

Warning

PCI MEZZANINE CARD (PMC Slot 1)

performing an operating system shutdown and following the procedures given in the userÕs manual for the particular PMC.

The right-most (lower) opening labeled MVME230x front panel provides front panel I/O access to a PMC that is connected to the 64-pin connectors J11 through J14 on the MVME230x module. Connector J14 allows rear panel P2 I/O.

This slot is MVME230x Port 1.

PCI MEZZANINE CARD on the

PCI MEZZANINE CARD (PMC Slot 2)

The left-most (upper)opening labeled MVME230x front panel provides front panel I/O access to a PMC that is connected to the 64-pin connectors J21 through J24 on the MVME230x module. Connector J24 allows rear panel P2 I/O.

This slot is MVME230x Port 2.

2-6

PCI MEZZANINE CARD on the

Page 47

PMCspan

A PMCspan front panel is pictured at the right. The front panel is the same for all PMCspan models.

There are two PMC slots, labeled

CARD

or one double-wide PMC.

The PMCspan board has two sets of three 32-bit connectors for PMC interface to secondary PCI bus and user-specific I/O. It also has a P1 connector and a 5-row P2 connector for power and VMEbus I/O.

The PMCspan has two green LEDs on its front panel, one for each PMC slot, labeled LEDs are illuminated during reset. An individual LED is illuminated whenever a PMC has been granted bus mastership of the secondary PCI bus.

The right-most (lower) opening labeled

MEZZANINE CARD

The left-most (upper)opening labeled

CARD

PCI MEZZANINE

, which support either two single-wide PMCs

PMC2 and PMC1. Both

PCI

on the front panel is Port 1.

PCI MEZZANINE

on the front panel is Port 2.

PMC2

PMC1

PCI MEZZANINE CARD PCI MEZZANINE CARD

2-7

Page 48

Operating Instructions

2-8

Page 49

Introduction

This chapter describes the MVME230x VME processor module on a block diagram level. The General Description provides an overview of the MVME230x, followed by a detailed description of several blocks of circuitry. Figure 3-1 shows a block diagram of the overall board architecture.

Detailed descriptions of other MVME230x blocks, including programmable registers in the ASICs and peripheral chips, can be found in the MVME2300-Series VME Processor Module ProgrammerÕs Reference Guide (part number V2300A/PG). Refer to it for a functional description of the MVME230x in greater depth.

Features

The following table summarizes the features of the MVME230x VME processor module.

3Functional Description

Table 3-1. MVME230x Features

Feature Description

200 MHZ MPC603 PowerPC

Microprocessor

Form factor 6U VMEbus

ECC DRAM

Flash memory

(MVME2301 - 2304 models) 300 MHZ MPC604 PowerPC

(MVME2305 - 2308 models)

Two-way interleaved, ECC-protected 16MB, 32MB, 64MB, or 128MB

Bank B consists of two 32-pin PLCC sockets that can be populated with 1MB 8-bit Flash devices

Bank A consists of four 16-bit Smart Voltage SMT devices that can be populated with 8Mbit Flash devices (4MB) or 4Mbit (2MB)

processor

3-1

Page 50

Features

Table 3-1. MVME230x Features (Continued)

Feature Description

Real-time clock Switches Reset (RST) and abort (ABT)

Status LEDs Four: Board fail (BFL), CPU, PMC (one for PMC slot 2, one for slot 1)

Timers

Interrupts

VME I/O VMEbus P2 connector Serial I/O One asynchronous debug port via RJ45 connector on front panel

Ethernet I/O

PCI interface

VMEbus interface

8KB NVRAM with RTC and battery backup (SGS-Thomson M48T59/T559)

One 16-bit timer in W83C553 ISA bridge; four 32-bit timers in Raven (MPIC) device)

Watchdog timer provided in SGS-Thomson M48T59 Software interrupt handling via Raven (PCI-MPU bridge) and

Winbond (PCI-ISA bridge) controllers

10Base-T/100Base-TX connections via RJ45 connector on front panel

Two IEEE P1386.1 PCI Mezzanine Card (PMC) slots for one double-width or two single-width PMCs

Front panel and/or VMEbus P2 I/O on both PMC slots One 114-pin Mictor connector for optional PMCspan expansion

module VMEbus system controller functions VME64 extension VMEbus-to-local-bus interface (A24/A32, D8/D16/D32/block

transfer [D8/D16/D32/D64]) Local-bus-to-VMEbus interface (A16/A24/A32, D8/D16/D32) VMEbus interrupter VMEbus interrupt handler Global Control/Status Register (GCSR) for interprocessor

communications DMA for fast local memory/VMEbus transfers (A16/A24/A32,

D16/D32/D64)

3-2

Page 51

General Description

The MVME230x is a VME processor module equipped with a PowerPCª 603 or 604 microprocessor.

As shown in the Features section, the MVME230x offers many standard features desirable in a computer systemÑincluding Ethernet and debug ports, Boot ROM, Flash memory, DRAM, and interface for two PCI Mezzanine Cards (PMCs), contained in a oneslot VME package. Its flexible mezzanine architecture allows relatively easy upgrades of the I/O.

There are four standard buses on the MVME230x:

PowerPC Processor Bus ISA Bus PCI Local Bus VMEbus

As shown in Figure 3-1, a Raven PCI Bridge ASIC provides the interface from the Processor Bus to PCI. A W83C553 PCI/ISA Bridge (PIB) Controller device performs the bridge function between PCI and ISA. The Universe ASIC device provides the interface between the PCI Local Bus and the VMEbus. A Falcon chipset is the ECC memory controller.

Functional Description

The Peripheral Component Interface (PCI ) local bus is a key feature. In addition to the on-board local bus peripherals, the PCI bus supports an industry-standard mezzanine interface, IEEE P1386.1 PMC (PCI Mezzanine Card).

Block Diagram

Figure 3-1 is a block diagram of the MVME2300Õs overall architecture.

MPC603/604 Processor

The MVME230x can be ordered with a PowerPC 603 or a PowerPC 604 processor chip with 16MB to 128MB of ECC DRAM, and up to 5MB of Flash memory.

3-3

Page 52

Block Diagram

CLOCK

GENERATOR

DEBUG CONNECTOR

DRAM

16/32/64/128MB

FLASH

3MB or 5MB

SYSTEM

REGISTERS

VME BRIDGE

UNIVERSE

BUFFERS

PCI EXPANSION

64-BIT PMC SLOT

PROCESSOR

MPC603/604

PHB & MPIC

RAVEN ASIC

10BT/100BTX

PORT

SERIAL

ETHERNET

DEC21140

PC16550

UART

MEMORY CONTROLLER

66MHz MPC604 PROCESSOR BUS

33MHz 32/64-BIT PCI LOCAL BUS

PIB

W83C553

ISA BUS

FALCON CHIPSET

RTC/NVRAM/WD

MK48T59/559

ISA

REGISTERS

3-4

PMC FRONT I/O SLOT

FRONT PANEL

VME P2 VME P1

Figure 3-1. MVME230x Block Diagram

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Page 53

Functional Description

The PowerPC 603 is a 64-bit processor with 16KB on-chip caches (16KB data cache and 16KB instruction cache). The PowerPC 604 is a 64-bit processor with 32 KB on-chip caches (32KB data cache and 32KB instruction cache).

The Raven bridge controller ASIC provides the bridge between the PowerPC microprocessor bus and the PCI local bus. Electrically, the Raven chip is a 64-bit PCI connection. Four programmable map decoders in each direction provide flexible addressing between the PowerPC microprocessor bus and the PCI local bus.

The power requirements for the MVME230x are shown in Table 3-2.

Table 3-2. Power Requirements

ConÞguration +5V Power +12V and -12V Power

200MHz 603 4.0A typical

300MHz 604 4.5A typical

PCI Bus Latency

Writes to PCI can be posted. The read access latency for PCI-bound cycles initialted by the MPMC60x bus master consists of the following components:

start

arb

delay

PMC-dependent

4.75A maximum

5.5A maximum

Start-up time (TS# to PCI bus Request). T

(Refer to Appendix B)

start

is 6

system clocks.

PCI bus arbitration time

PCI access time (FRAME# to TRDY#)

Delay time from TRDY# on PCI to TA# on 60X bus.

is 4 system clocks.

delay

3-5

Page 54

Block Diagram

The following table shows the access timings for various types of transfers initiated by a 60X system bus master to PCI:

Table 3-3. PowerPC 60x Bus to PCI Access Timing

System Clock Periods Required For:

Access Type

1st Beat 2nd Beat 3rd Beat 4th Beat

Total

Clocks

4-Beat Read (64-bit PCI Target)

4-Beat Read (32-bit PCI Target)

4-Beat Write (64-bit PCI Target)

4-Beat Write (32-bit PCI Target)

1-Beat Read (aligned, 4 bytes or less)

1-Beat Write 4 - - - 4

27 1 1 1 30

351 1138

41 117

20- --20

Notes 1. Write cycles are posted by the Raven ASIC.

2. Assumes no pipeline. Pipelined cycles would improve these numbers.

3. T

4. T

is assumed to be 4 system clocks (2 PCI clocks).

arb

is assumed to be 6 system clocks (3 PCI clocks):

Medium DEVSEL# target, zero wait PCI timing.

3-6

The following table shows the ECC memory access latency for PCIinitiated cycles.

Page 55

Functional Description

Table 3-4. PCI to ECC Memory Access Timing

PCI Clock Periods Required for:

Access Type

1st Beat 2nd Beat 3rd Beat nth Beat

64-bit Burst Reads 10 1 1 1

64-bit Burst Writes 3111

32-bit Burst Reads 10 1 1 1

32-bit Burst Writes 3111

1-Beat Read 10 - - -

1-Beat Write

---

Notes 1. The latency assumes two system clocks for 60X

system bus arbitration.

2. The latency is based on 60ns, fast-page DRAM timing. It is also assumed that L2 is either disabled or missed.

3. Write timings assume write posting FIFO is initially empty.

Maximum

Bandwidth

DRAM Memory

The MVME2300 DRAM memory size can be 16MB, 32MB, 64MB, or 128MB.

The DRAM blocks are controlled by the Falcon chipset which performs two-way interleaving and provides single-bit error correction and double-bit error correction. ECC is calculated over 72-bits.

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Block Diagram

There are one or two blocks of DRAMs that provides 16M/32M or 64M/128M of ECC DRAM. The DRAM blocks consists of 9 devices each. Either 1Mx16 (Page) 50-pin TSOPII DRAM or 4Mx16 (EDO)

50-pin TSOPII DRAM are used to provide 16/32/64/128M. When populated, these blocks appears as Block A and Block B to the Falcon chipset.

Refer to the MVME2300-Series VME Processor Module ProgrammerÕs Reference Guide for additional information and programming details.

The block diagram for the memory interface is shown in the following figure:

Memory Controller

Falcon Chipset

a a

ECC DRAM

16M to 128M

FLASH

3M to 5M

Buffers

Address & Control

BuffersBuffers

Figure 3-2. Memory Block Diagram

DRAM Latency

The ECC memory access latency times for 60ns, fast page DRAMs are shown in the following table.

3-8

Page 57

Functional Description

Table 3-5. PowerPC 60x Bus to DRAM Access Timing using 60ns Page

Devices

Clock Periods Required for:

Access Type

1st Beat 2nd Beat 3rd Beat 4th Beat

Total

Clocks

4-Beat Read after Idle (Quad-word aligned)

4-Beat Read after Idle (Quad-word misaligned)

4-Beat Read after 4-Beat Read (Quad-word aligned)

4-Beat Read after 4-Beat Read (misaligned)

4-Beat Write after Idle

4-Beat Write after 4-Beat Write (Quad-word aligned)

1-Beat Read after Idle

1-Beat Read after 1-Beat Read

1-Beat Write after Idle

1-Beat Write after 1-Beat Write

91 2113

93 1114

7/3

6/2 1 3 1111/7

41 11

7/3

9- - -

8/6

12/10

1 2 1 11/7

1 1 1 10/6

---

- --4

- - - 12/10

8/6

Notes 1. These numbers assume that the PowerPC 60x bus

master is doing address pipelining with TS* occurring at the minimum time after AACK* is asserted. Also the two numbers shown in the 1st beat column are for page miss/page hit.

2. In some cases, the numbers shown are averages and specific instances may be longer or shorter.

3-9

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Block Diagram

If all blocks of DRAMs are 50ns, EDO devices then the latency times for the ECC memory would be as follows:

Table 3-6. PowerPC 60x Bus to DRAM Access Timing Using 50ns, EDO

Devices

Clock Periods Required for:

Access Type

1st Beat 2nd Beat 3rd Beat 4th Beat

4-Beat Read after Idle (Quad-word aligned)

4-Beat Read after Idle (Quad-word misaligned)

4-Beat Read after 4-Beat Read (Quad-word aligned)

4-Beat Read after 4-Beat Read (misaligned)

4-Beat Write after Idle 4 1 1 1 7

4-Beat Write after 4-Beat Write (Quad-word aligned)

1-Beat Read after Idle

1-Beat Read after 1-Beat Read

1-Beat Write after Idle

1-Beat Write after 1-Beat Write

81 1111

82 1112

5/2

4/2 1 2 1 1 8/6

4/3

7/5

9/7

1 1 1 8/5

1 1 1 7/6

- --8

---

- --4

- - - 9/7

Total

Clocks

7/5

3-10

Notes 1. These numbers assume that the PowerPC 60x bus

master is doing address pipelining with TS* occurring at the minimum time after AACK* is asserted. Also the two numbers shown in the 1st beat column are for page miss/page hit.

2. In some cases, the numbers shown are averages and specific instances may be longer or shorter.

Page 59

Flash Memory

The MVME230x base board has provision for up to 5 MB of Flash memory.

Bank B consists of 1 MB of 8-bit Flash memory in two 32-pin PLCC 8-bit sockets.

The onboard monitor/debugger, PPCBug, resides in the Flash chips. PPCBug provides functionality for:

Functional Description

❏ Booting the system ❏ Initializing after a reset ❏ Displaying and modifying configuration variables ❏ Running self-tests and diagnostics ❏ Updating firmware ROM

Under normal operation, the Flash devices are in Òread-onlyÓ mode, their contents are pre-defined, and they are protected against inadvertent writes due to loss of power conditions. However, for programming purposes, programming voltage is always supplied to the devices and the Flash contents may be modified by executing the proper program command sequence. Refer to the PFLASH command in the PPCbug Debugging Package UserÕs Manual for further device-specific information on modifying Flash contents.

3-11

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Block Diagram

Flash Latency

There is one 16-bit port bank of Flash on the MVME230x. The access times for this bank are shown in the following table.

Table 3-7.PowerPC 60x Bus to FLASH Access Timing for Bank B (16-bit Port)

Clock Periods Required for:

Access type

4-Beat Read 68 64 64 64 260

4-Beat Write N/A N/A N/A N/A N/A

1-Beat Read (2 bytes to 8 bytes) 68 ---68

1-Beat Read (1 byte) 20 ---20

1-Beat Write 19 ---19

1st

Beat

2nd

Beat

3rd

Beat

4th

Beat

Total

Clocks

Ethernet Interface

The MVME230x module uses Digital EquipmentÕs DECchip 21140/21143 PCI Fast Ethernet LAN controller to implement an Ethernet interface that supports 10Base-T/100Base-TX connections, via an RJ45 connector on the front panel. The balanced differential transceiver lines are coupled via on-board transformers.

Every MVME230x is assigned an Ethernet station address. The address is $08003E2xxxxx, where xxxxx is the unique 5-nibble number assigned to the board (i.e., every board has a different value for xxxxx).

Each MVME230x displays its Ethernet station address on a label attached to the base board in the PMC connector keepout area just behind the front panel. In addition, the six bytes including the Ethernet station address are stored in the NVRAM (BBRAM) configuration area specified by boot ROM. That is, the value

3-12

Page 61

Functional Description

08003E2xxxxx is stored in NVRAM. The MVME230x debugger, PPCBug, has the capability to retrieve the Ethernet station address via the CNFG command.

Note The unique Ethernet address is set at the factory and

should not be changed. Any attempt to change this address may create node or bus contention and thereby render the board inoperable.

If the data in NVRAM is lost, use the number on the label in the PMC connector keepout area to restore it.

For the pin assignments of the 10Base-T/100Base-TX connector, refer to Appendix C.

At the physical layer, the Ethernet interface bandwidth is 10Mbit/second for 10Base T. For the 100Base TX, it is 100Mbit/second. Refer to the BBRAM/TOD Clock memory map description in the MVME2300-Series VME Processor Module Programmer's Reference Guide for detailed programming information.

PCI Mezzanine Card (PMC) Interface

A key feature of the MVME230x family is the PCI bus. In addition to the on-board local bus devices (Ethernet, etc.), the PCI bus supports an industry-standard mezzanine interface, IEEE P1386.1 PCI Mezzanine Card (PMC).

PMC modules offer a variety of possibilities for I/O expansion such as FDDI (Fiber Distributed Data Interface), ATM (Asynchronous Transfer Mode), graphics, Ethernet, or SCSI ports. For a complete listing of available PMCs, go to the GroupIPC WorldWideWeb site at URL PMC front panel and rear P2 I/O. There is also provision for stacking one or two PMC carrier boards, or PMCspan PCI expansion modules, on the MVME230x for additional expansion.

http://www.groupipc.com/ . The MVME230x supports

3-13

Page 62

Block Diagram

The MVME230x supports two PMC slots. Two sets of four 64-pin connectors on the base board (J11 - J14, and J21 - J24) interface with 32-bit/64-bit IEEE P1386.1 PMC-compatible mezzanines to add any

desirable function.

Refer to Appendix C for the pin assignments of the PMC connectors. For detailed programming information, refer to the PCI bus descriptions in the MVME2300-Series VME Processor Module Programmer's Reference Guide and to the user documentation for the PMC modules you intend to use.

PMC Slot 1 (Single-Width PMC)

PMC slot 1 has the following characteristics:

Mezzanine Type PCI Mezzanine Card (PMC)

Mezzanine Size

PMC Connectors J11 to J14 (32/64-Bit PCI with front and rear I/O)

Signaling Voltage Vio = 5.0Vdc

S1B: Single width, standard depth (75mm x 150mm) with front panel

For P2 I/O configurations, all I/O pins of PMC slot 1 are routed to the 5-row power adapter card. Pins 1 through 64 of J14 are routed to row C and row A of P2.

PMC Slot 2 (Single-Width PMC)

PMC slot 2 has the following characteristics:

Mezzanine Type PCI Mezzanine Card (PMC)

Mezzanine Size

PMC Connectors J21 to J24 (32/64-Bit PCI with front and rear I/O)

Signaling Voltage Vio = 5.0Vdc

3-14

S1B: Single width, standard depth (75mm x 150mm) with front panel

Page 63

Functional Description

For P2 I/O configurations, 46 I/O pins of PMC slot 2 are routed to the 5-row power adapter card. Pins 1 through 46 of J24 are routed to row D and row Z of P2.

PMC Slots 1 and 2 (Double-Width PMC)

PMC slots 1 and 2 with a double-width PMC have the following characteristics:

Mezzanine Type PCI Mezzanine Card (PMC)

Mezzanine Size

PMC Connectors

Signaling Voltage Vio = 5.0Vdc

Double width, standard depth (150mm x 150 mm) with front panel

J11 to J14 and J21 to J24 (32/64-Bit PCI) with front and rear I/O

PCI Expansion

The PMCspan expansion module connector, J4, is a 114-pin Mictor connector. It is located near P2 on the primary side of the MVME230x. Its interrupt lines are routed to the Raven MPIC.

VMEbus Interface

The VMEbus interface is implemented with the CA91C042 Universe ASIC. The Universe chip interfaces the 32/64-bit PCI local bus to the VMEbus.

The Universe ASIC provides:

❏ The PCI-bus-to-VMEbus interface

❏ The VMEbus-to-PCI-bus interface

❏ The DMA controller functions of the local VMEbus

The Universe chip includes Universe Control and Status Registers (UCSRs) for interprocessor communications. It can provide the VMEbus system controller functions as well. For detailed

3-15

Page 64

Block Diagram

programming information, refer to the Universe UserÕs Manual and to the discussions in the MVME2300-Series VME Processor Module Programmer's Reference Guide.

Maximum performance is achieved with D64 Multiplexed Block Transfers (MBLT). The on-chip DMA channel should be used to move large blocks of data to/from the VMEbus. The Universe should be able to reach 50MB/second in 64-bit MBLT mode.)

The MVME2300 interfaces to the VMEbus via the P1 and P2 connectors, which use the new 5-row 160-pin connectors as specified in the VME64 extension standard. It also draws +5V, +12V, and -12V power from the VMEbus backplane through these two connectors. 3.3V and 2.5V supplies are regulated onboard from the +5 power.

Asynchronous Debug Port

A National Semiconductor PC16550 Universal Asynchronous Receiver/Transmitter (UART) provides the asynchronous debug port. TTL-level signals for the port are routed through appropriate EIA-232-D drivers and receivers to an RJ45 connector on the front panel. The external signals are ESD protected.

This serial port can support 19.2 KBaud I/O. For detailed programming information, refer to the MVME2300-Series VME Processor Module Programmer's Reference Guide and to the vendor documentation for the UART device.

PCI-ISA Bridge (PIB) Controller

The MVME230x uses a Winbond W83C553 PCI/ISA Bridge (PIB) Controller to supply the interface between the PCI local bus and the ISA system I/O bus (diagrammed in Figure 3-1).

The PIB controller provides the following functions:

❏ PCI bus arbitration for:

3-16

Page 65

Functional Description

Ð ISA (Industry Standard Architecture) bus DMA (not

functional on MVME230x)

Ð The PHB (PCI Host Bridge) MPU/local bus interface

function, implemented by the Raven ASIC Ð All on-board PCI devices Ð The PMC slot

❏ ISA bus arbitration for DMA devices

❏ ISA interrupt mapping for four PCI interrupts

❏ Interrupt controller functionality to support 14 ISA interrupts

❏ Edge/level control for ISA interrupts

❏ Seven independently programmable DMA channels

❏ One 16-bit timer

❏ Three interval counters/timers

Accesses to the configuration space for the PIB controller are performed by way of the CONADD and CONDAT (Configuration Address and Data) registers in the Raven bridge controller ASIC. The registers are located at offsets $CF8 and $CFC, respectively, from the PCI I/O base address.

Real-Time Clock/NVRAM/Timer Function

The MVME230x employs an SGS-Thomson surface-mount M48T59/T559 RAM and clock chip to provide 8KB of non-volatile static RAM, a real-time clock, and a watchdog timer function. This chip supplies a clock, oscillator, crystal, power failure detection, memory write protection, 8KB of NVRAM, and a battery in a package consisting of two parts:

❏ A 28-pin 330mil SO device containing the real-time clock, the

oscillator, power failure detection circuitry, timer logic, 8KB of static RAM, and gold-plated sockets for a battery

❏ A SNAPHAT battery housing a crystal along with the battery

3-17

Page 66

Block Diagram

The SNAPHAT battery package is mounted on top of the M48T59/T559 device. The battery housing is keyed to prevent reverse insertion.

The clock furnishes seconds, minutes, hours, day, date, month, and year in BCD 24-hour format. Corrections for 28-, 29- (leap year), and 30-day months are made automatically. The clock generates no interrupts. Although the M48T59/T559 is an 8-bit device, 8-, 16-, and 32-bit accesses from the ISA bus to the M48T59/T559 are supported. Refer to the MVME2300-Series VME Processor Module Programmer's Reference Guide and to the M48T59/T559 data sheet for detailed programming and battery life information.

PCI Host Bridge

The Raven ASIC provides the bridge function between the MPC60x bus and the PCI Local Bus. It provides 32 bit addressing and 64 bit data. 64 bit addressing (dual address cycle) is not supported. The Raven supports various PowerPC processor external bus frequencies up to 66MHz and PCI frequencies up to 33MHz.

There are four programmable map decoders for each direction to provide flexible address mappings between the MPC and the PCI Local Bus. Refer to the MVME2300-Series VME Processor Module ProgrammerÕs Reference Guide for additional information and programming details.

Interrupt Controller (MPIC)

The Raven ASIC provides an MPIC Interrupt Controller to handle various interrupt sources. The interrupt sources are:

❏ Four MPIC timer interrupts

❏ Processor 0 self interrupt

❏ Memory Error interrupt from the Falcon chipset

❏ Interrupts from all PCI devices

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Page 67

❏ Two software interrupts

❏ ISA interrupts (actually handles as a single 8259 interrupt at

INT0)

Programmable Timers

Among the resources available to the local processor are a number of programmable timers. Timers are incorporated into the PCI/ISA Bridge (PIB) controller and the Raven device (diagrammed in Figure 3-1). They can be programmed to generate periodic interrupts to the processor.

Interval Timers

The PIB controller has three built-in counters that are equivalent to those found in an 82C54 programmable interval timer. The counters are grouped into one timer unit, Timer 1, in the PIB controller. Each counter output has a specific function:

❏ Counter 0 is associated with interrupt request line IRQ0. It

can be used for system timing functions, such as a timer interrupt for a time-of-day function.

Functional Description

The interval timers use the OSC clock input as their clock source. The MVME230x drives the OSC pin with a 14.31818MHz clock source.

16/32-Bit Timers

There is one 16-bit timer and four 32-bit timers on the MVME230x. The 16-bit timer is provided by the PIB. Raven device provides the four 32-bit timers that may be used for system timing or to generate

❏ Counter 1 generates a refresh request signal for ISA memory.

This timer is not used in the MVME230x.

❏ Counter 2 provides the tone for the speaker output function

on the PIB controller (the

SPEAKER_OUT signal which can be

cabled to an external speaker via the remote reset connector). This function is not used on the MVME230x.

3-19

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Block Diagram

periodic interrupts. For information on programming these timers, refer to the data sheet for the W83C553 PIB controller and to the

MVME2300-Series VMe P:rocessor Module ProgrammerÕs Reference

Guide.

3-20

Page 69

4Programming the MVME230x

Introduction

This chapter provides basic information useful in programming the MVME230x. This includes a description of memory maps, control and status registers, PCI arbitration, interrupt handling, sources of reset, and big/little endian issues.

For additional programming information about the MVME230x, refer to the MVME2300-Series VME Processor Module ProgrammerÕs Reference Guide.

For programming information about the PMCs, refer to the applicable userÕs manual furnished with the PMCs.

Memory Maps

There are multiple buses on the MVME230x and each bus domain has its own view of the memory map. The following sections describe the MVME230x memory organization from the following three points of view:

❏ The mapping of all resources as viewed by the MPU

(processor bus memory map)

❏ The mapping of onboard resources as viewed by PCI local

bus masters (PCI bus memory map)

❏ The mapping of onboard resources as viewed by VMEbus

masters (VMEbus memory map)

Additional, more detailed memory maps can be found in the

MVME2300-Series VME Processor Module ProgrammerÕs Reference Guide.

4-1

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Programming the MVME230x

Processor Bus Memory Map

The processor memory map configuration is under the control of the Raven bridge controller ASIC and the Falcon memory controller chip set. The Raven and Falcon devices adjust system mapping to suit a given application via programmable map decoder registers.

Default Processor Memory Map

At system power-up or reset, a default processor memory map takes over.

The default processor memory map that is valid at power-up or reset remains in effect until reprogrammed for specific applications. Table 4-1 defines the entire default map ($00000000 to $FFFFFFFF).

Table 4-1. Processor Default View of the Memory Map

4-2

Processor Address

Start End

00000000 7FFFFFFF 2GB Not Mapped

80000000 8001FFFF 128KB PCI/ISA I/O Space

80020000 FEF7FFFF 2GB-16MB-640KB Not Mapped

FEF80000 FEF8FFFF 64KB Falcon Registers

FEF90000 FEFEFFFF 384KB Not Mapped

FEFF0000 FEFFFFFF 64KB Raven Registers

FF000000 FFEFFFFF 15MB Not Mapped

FFF00000 FFFFFFFF 1MB Flash Bank A or Bank B (See Note)

Notes

The first 1MB of Flash bank A (soldered 2MB or 4MB

Size DeÞnition

Flash) appears in this range after a reset if the rom_b_rv control bit in the FalconÕs ROM B Base/Size register is cleared. If the rom_b_rv control bit is set, this address range maps to Flash bank B (socketed 1MB Flash).

Page 71

For detailed processor memory maps, including suggested CHRPand PREP-compatible memory maps, refer to the MVME2300-Series VME Processor Module ProgrammerÕs Reference Guide.

PCI Local Bus Memory Map

Memory Maps

The PCI memory map is controlled by the Raven MPU/PCI bus bridge controller ASIC and by the Universe PCI/VME bus bridge ASIC. The Raven and Universe devices adjust system mapping to suit a given application via programmable map decoder registers.

No default PCI memory map exists. Resetting the system turns the PCI map decoders off, and they must be reprogrammed in software for the intended application.

For detailed PCI memory maps, including suggested CHRP- and PREP-compatible memory maps, refer to the MVME2300-Series VME Processor Module ProgrammerÕs Reference Guide.

VMEbus Memory Map

The VMEbus is programmable. Like other parts of the MVME230x memory map, the mapping of local resources as viewed by VMEbus masters varies among applications.

The Universe PCI/VME bus bridge ASIC includes a userprogrammable map decoder for the VMEbus-to-local-bus interface. The address translation capabilities of the Universe enable the processor to access any range of addresses on the VMEbus.

Recommendations for VMEbus mapping, including suggested CHRP- and PREP-compatible memory maps, can be found in the

MVME2300-Series VME Processor Module ProgrammerÕs Reference Guide. Figure 4-1 shows the overall mapping approach from the

standpoint of a VMEbus master.

4-3

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Programming the MVME230x

Programming Considerations

Good programming practice dictates that only one MPU at a time have control of the MVME230x control registers. Of particular note are:

❏ Registers that modify the address map

❏ Registers that require two cycles to access

❏ VMEbus interrupt request registers

PCI Arbitration

There are seven potential PCI bus masters on the MVME230x :

❏ Raven ASIC (MPU/PCI bus bridge controller)

❏ Winbond W83C553 PIB (PCI/ISA bus bridge controller)

❏ DECchip 21140 Ethernet controller

❏ Universe ASIC (PCI/VME bus bridge controller)

❏ PMC Slot 1 (PCI mezzanine card)

❏ PMC Slot 2 (PCI mezzanine card)

❏ PCI Expansion Slot

The Winbond W83C553 PIB device supplies the PCI arbitration support for these seven types of devices. The PIB supports flexible arbitration modes of fixed priority, rotating priority, and mixed priority, as appropriate in a given application. Details on PCI arbitration can be found in the MVME2300-Series VME Processor Module ProgrammerÕs Reference Guide.

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Programming Considerations

ONBOARD

MEMORY

PCI MEMORY

SPACE

PCI/ISA

MEMORY SPACE

PCI

I/O SPACE

NOTE 1

PCI MEMORYPROCESSOR

VMEBUS

PROGRAMMABLE

SPACE

NOTE 2

VME A24

VME A16

NOTE 3

VME A24

VME A16

VME A24

VME A16

VME A24

VME A16

MPC

RESOURCES

1. Programmable mapping done by Raven ASIC.

NOTES:

2. Programmable mapping performed via PCI Slave images in Universe ASIC.

3. Programmable mapping performed via Special Slave image (SLSI) in Universe ASIC.

Figure 4-1. VMEbus Master Mapping

11553.00 9609

4-5

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Programming the MVME230x

The arbitration assignments for the MVME230x are shown in Table 4-2.

Table 4-2. PCI Arbitration Assignments

PCI Bus Request PCI Master(s)

PIB (Internal) PIB CPU Raven ASIC Request 0 PMC Slot 2 Request 1 PMC Slot 1 Request 2 PCI Expansion Slot Request 3 Ethernet Request 4 Universe ASIC (VMEbus)

Interrupt Handling

The Raven ASIC, which controls PHB (PCI Host Bridge) MPU/local bus interface functions on the MVME230x, performs interrupt handling as well. Sources of interrupts may be any of the following:

4-6

❏ The Raven ASIC itself (timer interrupts or transfer error

interrupts)

❏ The processor (processor self-interrupts)

❏ The Falcon chip set (memory error interrupts)

❏ The PCI bus (interrupts from PCI devices)

❏ The ISA bus (interrupts from ISA devices)

Figure 4-2 illustrates interrupt architecture on the MVME230x. For details on interrupt handling, refer to the MVME2300-Series VME Processor Module ProgrammerÕs Reference Guide.

Page 75

INT

Programming Considerations

INT_

PIB

(8529 Pair)

Processor

MCP_

RavenMPIC

SERR_& PERR_

PCI Interrupts

ISA Interrupts

11559.00 9609

Figure 4-2. MVME230x Interrupt Architecture

The MVME230x routes the interrupts from the PMCs and PCI expansion slots as follows:

4-7

Page 76

Programming the MVME230x

INTA#

PMC Slot 1

INTB# INTC#

INTD#

INTA#

PMC Slot 2

INTB# INTC#

INTD#

INTA#

PCIX Slot

INTB# INTC#

INTD#

IRQ10

IRQ9

RavenMPIC

IRQ11 IRQ12

DMA Channels

The PIB supports seven DMA channels. They are not functional on the MVME230x.

Sources of Reset

The MVME230x has nine potential sources of reset:

1. Power-on reset

4-8

RST switch (resets the VMEbus when the MVME230x is

2. system controller)

3. Watchdog timer Reset function controlled by the SGSThomson MK48T59 timekeeper device (resets the VMEbus when the MVME230x is system controller)

ALT_RST∗ function controlled by the Port 92 register in the

PIB (resets the VMEbus when the MVME230x is system controller)

5. PCI/ISA I/O Reset function controlled by the Clock Divisor register in the PIB

Page 77

Programming Considerations

6. The VMEbus SYSRESET∗ signal

7. VMEbus Reset sources from the Universe ASIC (PCI/VME bus bridge controller): the System Software reset, Local Software Reset, and VME CSR Reset functions

Table 4-3 shows which devices are affected by the various types of resets. For details on using resets, refer to the MVME2300-Series VME Processor Module ProgrammerÕs Reference Guide.

Table 4-3. Classes of Reset and Effectiveness

Device Affected

Processor

Reset Source

Power-On reset √√√√√ √ Reset switch √√√√√ √ Watchdog reset √√√√√ √ VME SYSRESET∗signal √√√√√ √ VME System SW reset √√√√√ √ VME Local SW reset √√√√√ VME CSR reset √√√√√ Hot reset (Port 92) √√√√√ PCI/ISA reset √√

Raven

ASIC

Falcon

Chip Set

PCI

Devices

ISA

Devices

VMEbus

(as system

controller

4-9

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Programming the MVME230x

Endian Issues

The MVME230x supports both little-endian (e.g., Windows NT) and big-endian (e.g., AIX) software. The PowerPC processor and the VMEbus are inherently big-endian, while the PCI bus is inherently little-endian. The following sections summarize how the

Processor/Memory Domain

MVME230x handles software and hardware differences in big- and little-endian operations. For further details on endian considerations, refer to the MVME2300-Series VME Processor Module ProgrammerÕs Reference Guide.

The MPC603/604 processor can operate in both big-endian and little-endian mode. However, it always treats the external processor/memory bus as big-endian by performing address rearrangement and reordering when running in little-endian mode. The MPC registers in the Raven MPU/PCI bus bridge controller ASIC and the Falcon memory controller chip set, as well as DRAM, Flash, and system registers, always appear as big-endian.

PCI Domain

4-10

Role of the Raven ASIC

Because the PCI bus is little-endian, the Raven performs byte swapping in both directions (from PCI to memory and from the processor to PCI) to maintain address invariance while programmed to operate in big-endian mode with the processor and the memory subsystem.

In little-endian mode, the Raven reverse-rearranges the address for PCI-bound accesses and rearranges the address for memory-bound accesses (from PCI). In this case, no byte swapping is done.

The PCI bus is inherently little-endian. All devices connected directly to the PCI bus operate in little-endian mode, regardless of the mode of operation in the processorÕs domain.

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PCI and Ethernet

Ethernet is byte-stream-oriented; the byte having the lowest address in memory is the first one to be transferred regardless of the endian mode. Since the Raven maintains address invariance in both little-endian and big-endian mode, no endian issues should arise for Ethernet data. Big-endian software must still take the byteswapping effect into account when accessing the registers of the PCI/Ethernet device, however.

Role of the Universe ASIC

Because the PCI bus is little-endian while the VMEbus is bigendian, the Universe PCI/VME bus bridge ASIC performs byte swapping in both directions (from PCI to VMEbus and from VMEbus to PCI) to maintain address invariance, regardless of the mode of operation in the processorÕs domain.

VMEbus Domain

The VMEbus is inherently big-endian. All devices connected directly to the VMEbus must operate in big-endian mode, regardless of the mode of operation in the processorÕs domain.

Programming Considerations

In big-endian mode, byte-swapping is performed first by the Universe ASIC and then by the Raven. The result is transparent to big-endian software (a desirable effect).

In little-endian mode, however, software must take the byteswapping effect of the Universe ASIC and the address reverse- rearranging effect of the Raven into account.

For further details on endian considerations, refer to the

MVME2300-Series VME Processor Module ProgrammerÕs Reference Guide.

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Programming the MVME230x

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PPCBug Overview

The PPCBug firmware is the layer of software just above the hardware. The firmware provides the proper initialization for the devices on the MVME230x module upon power-up or reset.

This chapter describes the basics of PPCBug and its architecture, describes the monitor (interactive command portion of the firmware) in detail, and gives information on actually using the PPCBug debugger and the special commands. A complete list of PPCBug commands appears at the end of the chapter.

Chapter 6 contains information about the CNFG and ENV commands, system calls, and other advanced user topics.

For full user information about PPCbug, refer to the PPCBug Firmware Package UserÕs Manual and the PPCBug Diagnostics Manual, listed in the Related Documentation appendix.

5PPCBug

PPCBug Basics

The PowerPC debug firmware, PPCBug, is a powerful evaluation and debugging tool for systems built around the Motorola PowerPC microcomputers. Facilities are available for loading and executing user programs under complete operator control for system evaluation.

PPCBug provides a high degree of functionality, user friendliness, portability, and ease of maintenance.

It achieves good portability and comprehensibility because it was written entirely in the C programming language, except where necessary to use assembler functions.

PPCBug includes commands for:

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PPCBug Basics

❏ Display and modification of memory

❏ Breakpoint and tracing capabilities

❏ A powerful assembler and disassembler useful for patching

programs

❏ A self-test at power-up feature which verifies the integrity of

the system

PPCBug consists of three parts:

❏ A command-driven, user-interactive software debugger,

described in the PPCBug Firmware Package UserÕs Manual. It is hereafter referred to as Òthe debuggerÓ or ÒPPCBugÓ.

❏ A command-driven diagnostics package for the MVME230x

hardware, hereafter referred to as Òthe diagnostics.Ó The diagnostics package is described in the PPCBug Diagnostics

Manual.

❏ A user interface or debug/diagnostics monitor that accepts

commands from the system console terminal.

When using PPCBug, you operate out of either the debugger directory or the diagnostic directory.

❏ If you are in the debugger directory, the debugger prompt

PPC1-Bug> is displayed and you have all of the debugger

commands at your disposal.

❏ If you are in the diagnostic directory, the diagnostic prompt

PPC1-Diag>

is displayed and you have all of the diagnostic commands at your disposal as well as all of the debugger commands.

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Because PPCBug is command-driven, it performs its various operations in response to user commands entered at the keyboard. When you enter a command, PPCBug executes the command and the prompt reappears. However, if you enter a command that causes execution of user target code (e.g., GO), then control may or may not return to PPCBug, depending on the outcome of the user program.

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Memory Requirements

PPCBug requires a maximum of512KB of read/write memory (i.e., DRAM). The debugger allocates this space from the top of memory. For example, a system containing 64MB ($04000000) of read/write memory will place the PPCBug memory page at locations $03F80000 to $03FFFFFF.

PPCBug

PPCBug Implementation

PPCBug is written largely in the C programming language, providing benefits of portability and maintainability. Where necessary, assembly language has been used in the form of separately compiled program modules containing only assembler code. No mixed-language modules are used.

Physically, PPCBug is contained in two socketed 32-pin PLCC Flash devices that together provide 1MB of storage. The executable code is checksummed at every power-on or reset firmware entry, and the result (which includes a precalculated checksum contained in the Flash devices), is verified against the expected checksum.

MPU, Hardware, and Firmware Initialization

The debugger performs the MPU, hardware, and firmware initialization process. This process occurs each time the MVME230x is reset or powered up. The steps below are a high-level outline; not all of the detailed steps are listed.

1. Sets MPU.MSR to known value.

2. Invalidates the MPU's data/instruction caches.

3. Clears all segment registers of the MPU.

4. Clears all block address translation registers of the MPU.

5. Initializes the MPU-bus-to-PCI-bus bridge device.

6. Initializes the PCI-bus-to-ISA-bus bridge device.

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MPU, Hardware, and Firmware Initialization

7. Calculates the external bus clock speed of the MPU.

8. Delays for 750 milliseconds.

9. Determines the CPU base board type.

10. Sizes the local read/write memory (i.e., DRAM).

11. Initializes the read/write memory controller. Sets base address of memory to $00000000.

12. Retrieves the speed of read/write memory from NVRAM.

13. Initializes the read/write memory controller with the speed of read/write memory.

14. Retrieves the speed of read only memory (i.e., Flash) from NVRAM.

15. Initializes the read only memory controller with the speed of read only memory.

16. Enables the MPU's instruction cache.

17. Copies the MPU's exception vector table from $FFF00000 to $00000000.

18. Verifies MPU type.

19. Enables the super-scalar feature of the MPU (boards with MPC604-type chips only).

20. Verifies the external bus clock speed of the MPU.

21. Determines the debugger's console/host ports, and initializes the PC16550A.

22. Displays the debugger's copyright message.

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23. Displays any hardware initialization errors that may have occurred.

24. Checksums the debugger object, and displays a warning message if the checksum failed to verify.

25. Displays the amount of local read/write memory found.

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PPCBug

26. Verifies the configuration data that is resident in NVRAM, and displays a warning message if the verification failed.

27. Calculates and displays the MPU clock speed, verifies that the MPU clock speed matches the configuration data, and displays a warning message if the verification fails.

28. Displays the BUS clock speed, verifies that the BUS clock speed matches the configuration data, and displays a warning message if the verification fails.

29. Probes PCI bus for supported network devices.

30. Probes PCI bus for supported mass storage devices.

31. Initializes the memory/IO addresses for the supported PCI bus devices.

32. Executes Self-Test, if so configured. (Default is no Self-Test.)

33. Extinguishes the board fail LED, if Self-Test passed, and outputs any warning messages.

34. Executes boot program, if so configured. (Default is no boot.)

35. Executes the debugger monitor (i.e., issues the prompt).

Using PPCBug

PPCBug is command-driven; it performs its various operations in response to commands that you enter at the keyboard. When the PPC1-Bug prompt appears on the screen, the debugger is ready to accept debugger commands. When the PPC1-Diag prompt appears on the screen, the debugger is ready to accept diagnostics commands. To switch from one mode to the other, enter SD.

What you key in is stored in an internal buffer. Execution begins only after you press the Return or Enter key. This allows you to correct entry errors, if necessary, with the control characters described in the PPCBug Firmware Package UserÕs Manual, Chapter 1.

PPC1-Bug>

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Using PPCBug

After the debugger executes the command, the prompt reappears. However, if the command causes execution of user target code (for example GO) then control may or may not return to the debugger, depending on what the user program does. For example, if a breakpoint has been specified, then control returns to the debugger when the breakpoint is encountered during execution of the user program. Alternately, the user program could return to the debugger by means of the System Call Handler routine RETURN (described in the PPCBug Firmware Package UserÕs Manual, Chapter

5). For more about this, refer to the GD, GO, and GT command descriptions in the PPCBug Firmware Package UserÕs Manual, Chapter 3.

A debugger command is made up of the following parts:

❏ The command name, either uppercase or lowercase (e.g., MD

or md).

❏ Any required arguments, as specified by command.

❏ At least one space before the first argument. Precede all other

arguments with either a space or comma.

❏ One or more options. Precede an option or a string of options

with a semicolon (;). If no option is entered, the commandÕs default option conditions are used.

Debugger Commands

The individual debugger commands are listed in the following table. The commands are described in detail in the PPCBug Firmware Package UserÕs Manual, Chapter 3

Note You can list all the available debugger commands by

entering the Help (HE) command alone. You can view the syntax for a particular command by entering HE and the command mnemonic, as listed below.

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Table 5-1. Debugger Commands

Command Description

AS One Line Assembler BC Block of Memory Compare BF Block of Memory Fill BI Block of Memory Initialize BM Block of Memory Move BR Breakpoint Insert NOBR Breakpoint Delete BS Block of Memory Search BV Block of Memory Verify CM Concurrent Mode NOCM No Concurrent Mode CNFG ConÞgure Board Information Block CS Checksum CSAR PCI ConÞguration Space READ Access CSAW PCI ConÞguration Space WRITE Access DC Data Conversion DMA Block of Memory Move DS One Line Disassembler DU Dump S-Records ECHO Echo String ENV Set Environment FORK Fork Idle MPU at Address FORKWR Fork Idle MPU with Registers GD Go Direct (Ignore Breakpoints) GEVBOOT Global Environment Variable Boot GEVDEL Global Environment Variable Delete GEVDUMP Global Environment Variable(s) Dump GEVEDIT Global Environment Variable Edit GEVINIT Global Environment Variable Initialization GEVSHOW Global Environment Variable(s) Display GN Go to Next Instruction GO Go Execute User Program GT Go to Temporary Breakpoint

PPCBug

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Using PPCBug

Table 5-1. Debugger Commands (Continued)

Command Description

HE Help IDLE Idle Master MPU IOC I/O Control for Disk IOI I/O Inquiry IOP I/O Physical (Direct Disk Access) IOT I/O Teach for ConÞguring Disk Controller

IRD Idle MPU Register Display IRM Idle MPU Register Modify IRS Idle MPU Register Set LO Load S-Records from Host MA Macro DeÞne/Display NOMA Macro Delete MAE Macro Edit MAL Enable Macro Listing NOMAL Disable Macro Listing MAR Load Macros MAW Save Macros MD, MDS Memory Display MENU System Menu MM Memory Modify MMD Memory Map Diagnostic MS Memory Set MW Memory Write NAB Automatic Network Boot NAP Nap MPU NBH Network Boot Operating System, Halt NBO Network Boot Operating System NIOC Network I/O Control NIOP Network I/O Physical NIOT Network I/O Teach (ConÞguration) NPING Network Ping OF Offset Registers Display/Modify PA Printer Attach

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Table 5-1. Debugger Commands (Continued)

Command Description

NOPA Printer Detach PBOOT Bootstrap Operating System PF Port Format NOPF Port Detach PFLASH Program FLASH Memory PS Put RTC into Power Save Mode RB ROMboot Enable NORB ROMboot Disable RD Register Display REMOTE Remote RESET Cold/Warm Reset RL Read Loop RM Register Modify RS Register Set RUN MPU Execution/Status SD Switch Directories SET Set Time and Date SROM SROM Examine/Modify SYM Symbol Table Attach NOSYM Symbol Table Detach SYMS Symbol Table Display/Search T Trace TA Terminal Attach TIME Display Time and Date TM Transparent Mode TT Trace to Temporary Breakpoint VE Verify S-Records Against Memory VER Revision/Version Display WL Write Loop

PPCBug

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Using PPCBug

Although a command to allow the erasing and

Caution

reprogramming of Flash memory is available to you, keep in mind that reprogramming any portion of Flash memory will erase everything currently contained in Flash, including the PPCBug debugger.

Note, however, that both banks A and B of Flash contain the PPCBug debugger.

Diagnostic T ests

The PPCBug hardware diagnostics are intended for testing and troubleshooting the MVME230x module.

In order to use the diagnostics, you must switch to the diagnostic directory. You may switch between directories by using the SD (Switch Directories) command. You may view a list of the commands in the directory that you are currently in by using the HE (Help) command.

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If you are in the debugger directory, the debugger prompt

PPC1-Bug> displays, and all of the debugger commands are

available. Diagnostics commands cannot be entered at the

PPC1-Bug> prompt.

If you are in the diagnostic directory, the diagnostic prompt

PPC1-Diag> displays, and all of the debugger and diagnostic

commands are available.

PPCBugÕs diagnostic test groups are listed in the Table 5-2. Note that not all tests are performed on the MVME230x. Using the HE command, you can list the diagnostic routines available in each test group. Refer to the PPCBug Diagnostics Manual for complete descriptions of the diagnostic routines and instructions on how to invoke them.

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Table 5-2. Diagnostic Test Groups

Test Group Description

CL1283 Parallel Interface (CL1283) Tests* DEC DEC21x40 Ethernet Controller Tests ISABRDGE PCI/ISA Bridge Tests KBD8730x PC8730x Keyboard/Mouse Tests* L2CACHE Level 2 Cache Tests* NCR NCR 53C8xx SCSI-2 I/O Processor Tests* PAR8730x Parallel Interface (PC8730x) Test UART Serial Input/Output Tests PCIBUS PCI/PMC Generic Tests RAM Local RAM Tests RTC MK48Txx Timekeeping Tests SCC Serial Communications

Controller (Z85C230) Tests* VGA543x Video Diagnostics Tests* VME2 VMEchip2 VME Interface ASIC Tests* Z8536 Z8536 Counter/Timer Tests*

PPCBug

Notes You may enter command names in either uppercase or

lowercase.

Some diagnostics depend on restart defaults that are set up only in a particular restart mode. Refer to the documentation on a particular diagnostic for the correct mode.

Test Sets marked with an asterisk (*) are not available on the MVME230x.

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Using PPCBug

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6Modifying the Environment

Overview

You can use the factory-installed debug monitor, PPCBug, to modify certain parameters contained in the MVME230x's NonVolatile RAM (NVRAM), also known as Battery Backed-up RAM (BBRAM).

❏ The Board Information Block in NVRAM contains various

elements concerning operating parameters of the hardware. Use the PPCBug command CNFG to change those parameters.

❏ Use the PPCBug command ENV to change configurable

PPCBug parameters in NVRAM.

The CNFG and ENV commands are both described in the PPCBug Firmware Package User's Manual. Refer to that manual for general information about their use and capabilities.

The following paragraphs present additional information about CNFG and ENV that is specific to the PPCBug debugger, along with the parameters that can be configured with the ENV command.

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CNFG - Configure Board Information Block

CNFG - Conﬁgure Board Information Block

Use this command to display and configure the Board Information Block, which is resident within the NVRAM. The board information block contains various elements detailing specific operational parameters of the MVME230x. The board structure for the MVME230x is as shown in the following example:

Board (PWA) Serial Number = “MOT00 Board Identifier = “MVME2300 ” Artwork (PWA) Identifier = “01-w3260F

MPU Clock Speed = “200 ” Bus Clock Speed = “067 ” Ethernet Address = 08003E20C983 Local SCSI Identifier = “07” System Serial Number = “ System Identifier = “Motorola MVME2300” License Identifier = “

xxxxxxx

nnnnnnn

nnnnnnnn

B”

“

”

The parameters that are quoted are left-justified character (ASCII) strings padded with space characters, and the quotes (Ò) are displayed to indicate the size of the string. Parameters that are not quoted are considered data strings, and data strings are rightjustified. The data strings are padded with zeroes if the length is not met.

The Board Information Block is factory-configured before shipment. There is no need to modify block parameters unless the NVRAM is corrupted.

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Refer to the MVME2300-Series VME Processor Module ProgrammerÕs Reference Guide for the actual location and other information about the Board Information Block.

Refer to the PPCBug Firmware Package User's Manual for a description of CNFG and examples.

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ENV - Set Environment

Use the ENV command to view and/or configure interactively all PPCBug operational parameters that are kept in Non-Volatile RAM (NVRAM).

Refer to the PPCBug Firmware Package User's Manual for a description of the use of ENV. Additional information on registers in the Universe ASIC that affect these parameters is contained in your MVME2300-Series VME Processor Module ProgrammerÕs Reference Guide.

Modifying the Environment

Listed and described below are the parameters that you can configure using ENV. The default values shown were those in effect when this publication went to print.

Conﬁguring the PPCBug Parameters

The parameters that can be configured using ENV are:

Bug or System environment [B/S] = B?

Field Service Menu Enable [Y/N] = N?

Y N

Bug is the mode where no system type of support is displayed. However, system-related items are still available. (Default)

System is the standard mode of operation, and is the default mode if NVRAM should fail. System mode is deÞned in the PPCBug Firmware Package User's Manual.

Display the Þeld service menu.

Do not display the Þeld service menu. (Default)

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ENV - Set Environment

Remote Start Method Switch [G/M/B/N] = B?

The Remote Start Method Switch is used when the MVME2300 is cross-loaded from another VME-based CPU, to start execution of the cross-loaded program.

Use the Global Control and Status Register to pass and start execution of the cross-loaded program. This selection is not applicable to the

MVME2300 boards.

Use the Multiprocessor Control Register (MPCR) in shared RAM to pass and start execution of the cross-loaded program.

Use both the GCSR and the MPCR methods to pass and start execution of the cross-loaded program. (Default)

Probe System for Supported I/O Controllers [Y/N] = Y?

Do not use any Remote Start Method.

Accesses will be made to the appropriate system buses (e.g., VMEbus, local MPU bus) to determine the presence of supported controllers. (Default)

Accesses will not be made to the VMEbus to determine the presence of supported controllers.

Auto-Initialize of NVRAM Header Enable [Y/N] = Y?

NVRAM (PReP partition) header space will be initialized automatically during board initialization, but only if the PReP partition fails a sanity check. (Default)

NVRAM header space will not be initialized automatically during board initialization.

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Network PReP-Boot Mode Enable [Y/N] = N?

Modifying the Environment

Enable PReP-style network booting (same boot image from a network interface as from a mass storage device).

Do not enable PReP-style network booting. (Default)

Negate VMEbus SYSFAIL* Always [Y/N] = N?

Negate the VMEbus SYSFAIL∗ signal during board initialization.

Negate the VMEbus SYSFAIL∗ signal after successful completion or entrance into the bug command monitor. (Default)

SCSI Bus Reset on Debugger Startup [Y/N] = N?

Y N

Local SCSI bus is reset on debugger setup.

Local SCSI bus is not reset on debugger setup. (Default)

Primary SCSI Bus Negotiations Type [A/S/N] = A?

A S N

Asynchronous SCSI bus negotiation. (Default)

Synchronous SCSI bus negotiation.

None.

Primary SCSI Data Bus Width [W/N] = N?

W N

Secondary SCSI identifier = 07?

Wide SCSI (16-bit bus).

Narrow SCSI (8-bit bus). (Default)

Select the identiÞer. (Default = 07.)

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ENV - Set Environment

NVRAM Bootlist (GEV.fw-boot-path) Boot Enable [Y/N] = N?

Give boot priority to devices deÞned in the fwboot-path global environment variable (GEV).

Do not give boot priority to devices listed in the fw-boot-path GEV. (Default)

Note When enabled, the GEV (Global Environment

Variable) boot takes priority over all other boots, including Autoboot and Network Boot.

NVRAM Bootlist (GEV.fw-boot-path) Boot at power-up only [Y/N] = N?

Give boot priority to devices deÞned in the fwboot-path GEV at power-up reset only.

Give power-up boot priority to devices listed in the fw-boot-path GEV at any reset. (Default)

NVRAM Bootlist (GEV.fw-boot-path) Boot Abort Delay = 5?

The time in seconds that a boot from the NVRAM boot list will delay before starting the boot. The purpose for the delay is to allow you the option of stopping the boot by use of the

BREAK

key. The time value is from 0-255 seconds. (Default = 5 seconds)

Auto Boot Enable [Y/N] = N?

Y N

The Autoboot function is enabled.

The Autoboot function is disabled. (Default)

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Auto Boot at power-up only [Y/N] = N?

Y N

Autoboot is attempted at power-up reset only.

Autoboot is attempted at any reset. (Default)

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Auto Boot Scan Enable [Y/N] = Y?

Modifying the Environment

Auto Boot Scan Device Type List = FDISK/CDROM/TAPE/HDISK?

If Autoboot is enabled, the Autoboot process attempts to boot from devices speciÞed in the scan list (e.g., FDISK/CDROM/TAPE/HDISK). (Default)

If Autoboot is enabled, the Autoboot process uses the Controller LUN and Device LUN to boot.

This is the listing of boot devices displayed if the Autoboot Scan option is enabled. If you modify the list, follow the format shown above (uppercase letters, using forward slash as separator).

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ENV - Set Environment

Auto Boot Controller LUN = 00?

Refer to the PPCBug Firmware Package User's Manual for a listing of disk/tape controller modules currently supported by PPCBug. (Default = $00)

Auto Boot Device LUN = 00?

Refer to the PPCBug Firmware Package User's Manual for a listing of disk/tape devices currently supported by PPCBug. (Default = $00)

Auto Boot Partition Number = 00?

Which disk ÒpartitionÓ is to be booted, as speciÞed in the PowerPC Reference Platform (PRP) speciÞcation. If set to zero, the Þrmware will search the partitions in order (1, 2, 3, 4) until it Þnds the Þrst ÒbootableÓ partition. That is then the partition that will be booted. Other acceptable values are 1, 2, 3, or 4. In these four cases, the partition speciÞed will be booted without searching.

Auto Boot Abort Delay = 7?

The time in seconds that the Autoboot sequence will delay before starting the boot. The purpose for the delay is to allow you the option of stopping the boot by use of the

BREAK key. The

time value is from 0-255 seconds. (Default = 7 seconds)

Auto Boot Default String [NULL for an empty string] = ?

You may specify a string (Þlename) which is passed on to the code being booted. The maximum length of this string is 16 characters. (Default = null string)

ROM Boot Enable [Y/N] = N?

Y N

The ROMboot function is enabled.

The ROMboot function is disabled. (Default)

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