Motorola MVME2300 User Manual

MVME2300 Series

VME Processor Module

Programmer’s Reference

Guide

V2300A/PG5

Edition of June 2001

Printed in the United States of America.

Motorola

PowerPC

and the Motorola logo are registered t r ademarks of Motorola, Inc.

is a registered trademark of International Business Machines Corporation and

is used by Motorola with permission. All other products ment io ned i n this document are trademarks or registered trade ma rk s of

their respective holders.

Safety Summary

The following general safety precautions must be observed during all phases of operation, service, and repair of this equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual could result in personal injury or damage to the equipment.

The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You, as the user of the product, shoul d foll ow these warni ngs and al l other sa fety pr ecauti ons nece ssary fo r the safe ope ration of the equipment in your operating environment.

Ground the Instrument.

To minimize shock hazard, the equipment chassis and enclosure must be connected to an electrical ground. If the equipment is su pplied wi th a three-c onductor A C power ca ble, the po wer cable m ust be plug ged into an a pproved three-contact electrical outlet, with the grounding wire (green/yellow) reliably connected to an electrical ground (safety ground) at the power outlet. The power jack and mating plug of the power cable meet International Electrotechnical Commission (IEC) safety standards and local electrical regulatory codes.

Do Not Operate in an Explosive Atmosphere.

Do not operate the equipment in any explosive atmosphere such as in the presence of flammable gases or fumes. Operation of any electrical equipment in such an environment could result in an explosion and cause injury or damage.

Keep Away From Live Circuits Inside the Equipment.

Operating personnel must not remove equipment covers. Only Factory Authorized Service Personnel or other qualified service personnel may remove equipment covers for internal subassembly or component replacement or any internal adjust ment. Service pe rsonnel should n ot replace compon ents with power c able connected. Under certain conditions, dangero us voltages may exist even with the power cable remo ved. T o avoid inju ries, such pers onnel should always disconnect power and discharge circuits before touching components.

Use Caution When Exposing or Handling a CRT.

Breakage of a Cathode-Ray Tube (CRT) causes a high-velocity scattering of glass fragments (implosion). To prevent CRT implosion, do not handl e the CRT and avoid rough handling o r jarring of t he equipment . Handling o f a CRT should be done only by qualified service personnel using approved safety mask and gloves.

Do Not Substitute Parts or Modify Equipment.

Do not install substitute parts or perform any unauthorized modification of the equipment. Contact your local Motorola representative for service and repair to ensure that all safety features are maintained.

Observe Warnings in Manual.

W arn ings , such as th e exa mple be low, preced e pote ntia lly da nger ous pro cedure s thro ugh out th is manual . In struc tion s contained in the warnings m ust be follow ed. You should also employ all ot her safety precautions w hich you dee m necessary for the operation of the equi pment in your operating environment.

To prevent serious injury or death from dangerous voltages, use extreme caution when handling, testing, and adjusting this equipment and its

Warning

components.

Flammability

All Motorola PWBs (printed wiring boards) are manufactured with a flammability rating of 94V-0 by UL-recognized manufacturers.

EMI Caution

This equipment ge ner ates, uses a nd can radi ate el ectro magne tic energy . It

Caution

This product contains a lithium battery to power the clock and calendar circuitry.

Caution

may cause or be susceptible to electromagnetic interference (EMI) if not installed and used with adequate EMI protection.

Lithium Battery Caution

Danger of explosion if battery is re placed incorrect ly. Replace battery only with the same or equivalent type recommended by the equipment

manufacturer. Dispose of used batteries according to the manufacturer’s instructions.

Attention

Vorsicht

Il y a danger d’explosion s’il y a remplacement incorrect de la batterie. Remplacer uniquement avec une batterie du même type ou d’un type équivalent recommandé par le constructeur. Mettre au rebut les batteries usagées conformément aux instructions du fabricant.

Explosionsgefahr bei unsachgemäßem Austausch der Ba tt erie. Ersatz nur durch denselben ode r einen vom Herstel ler empfohle nen Typ. Entsorgu ng gebrauchter Batterien nach Angaben des Herstellers.

CE Notice (European Community)

Motorola Compute r Group pro ducts wi th the CE mar king co mply with the EMC Dir ective (89/336/EEC). Compliance with this directive implies conformity to the following European Norms:

EN55022 “Limits and Methods of Meas urement of Radio Int erferen ce Chara cteri stic s of Information Technology Equipment”; this product tested to Equipment Class B

EN50082-1:1997 “Electromag netic Compatibi lit y—Gener ic Im munity St andard , Part

1. Residential, Commercial and Light Industry”

System products al so fulf ill EN60950 ( product saf ety) which i s essenti ally the r equirement for the Low Voltage Directive (73/23/EEC).

Board products are tested in a representative system to show compliance with the above mentioned requirements. A proper installation in a CE-marked system will maintain the required EMC /safety performance.

In accordance with European Community directives, a “Declaration of Conformity” has been made and is on file within the European Union. The “Declaration of Conformity” is available on request. Please contact your sales representative.

Notice

While reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. a ssumes n o lia bility r esulti ng from any omissio ns in this docu ment, or from the use of the information obtained therein. Motorola reserves the right to revise this document and to ma ke c hanges from time to ti me in t h e cont ent hereof without obligation of Motorola to notify any person of such revision or changes.

Electronic versions of this material may be read online, downloaded for personal use, or referenced in another document as a URL to the Motorola Computer Group website. The text itself may not b e published commerci ally in print o r electronic for m, edited, transla ted, or otherwise altered without the permission of Motorola, Inc.

It is possible th at t hi s publication may contain r ef erence to or information about Motorola products (machines and pr ograms), progra mming, or services that are not av ailable in your country. Such references or information must not be construed to mean that Motorola intends to announce such Motorola products, programming, or services in your country.

Limited and Restricted Rights Legend

If the documentation contained herein is supplied, directly or indirectly, to the U.S. Government, the following notice shall apply unless otherwise agreed to in writing by Motorola, Inc.

Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (b)(3) of t he Rig hts i n Technical Data clause at DFARS 252.227-7013 (Nov .

1995) and of the Rights in Noncommerc ial Computer Software and Docume ntation c lause at DFARS 252.227-7014 (Jun. 1995).

Motorola, Inc. Computer Group 2900 South Diablo Way Tempe, Arizona 85282

About This Manual

Summary of Changes..................................................................................................xx

Overview of Contents................................................................................................xxi

Comments and Suggestions.......................................................................................xxi

Conventions Used in This Manual............................................................................xxii

CHAPTER 1 Board Description and Memory Maps

Introduction................................................................................................................1-1

Overview....................................................................................................................1-1

Summary of Features.................................................................................................1-2

System Block Diagram..............................................................................................1-3

Functional Description ...............................................................................................1-6

VMEbus Interface............................................................. ..................................1-6

Front Panel..........................................................................................................1-6

PCI interface.......................................................................................................1-7

P2 I/O...........................................................................................................1-7

Programming Model..................................................................................................1-7

Processor Memory Maps................................. ...... ...... .......................................1-7

Default Processor Memory Map..................................................................1-8

Processor CHRP Memory Map...................................................................1-9

Processor PREP Memory Map......................................................... .........1-11

PCI Configuration Access.........................................................................1-12

PCI Memory Maps............................................................................................1-13

Default PCI Memory Map.........................................................................1-13

PCI CHRP Memory Map ..........................................................................1-13

PCI PREP Memory Map ...........................................................................1-16

VMEbus Mapping................................. ...... ..... ........................................ .........1-20

VMEbus Master Map ...................................................... ...... ..... ...............1-20

VMEbus Slave Map.......................................................................... .........1-21

Falcon-Controlled System Registers ................................................................1-24

System Configuration Register (SYSCR).................................................1-25

Memory Configuration Register (MEMCR).............................................1-27

System External Cache Control Register (SXCCR)..................................1-29

Processor 0 External Cache Control Register (P0XCCR).........................1-30

Processor 1 External Cache Control Register (P1XCCR).........................1-30

vii

CPU Control Register ...............................................................................1-30

ISA Local Resource Bus..........................................................................................1-31

W83C553 PIB Registers ..................................................................................1-31

16550 UART ....................................................................................................1-31

General-Purpose Readable Jumpers.................................................................1-32

NVRAM/RTC and Watchdog Timer Registers................................................1-32

Module Configuration and Status Registers.....................................................1-33

CPU Configuration Register.....................................................................1-34

Base Module Feature Register..................................................................1-35

Base Module Status Register (BMSR)......................................................1-36

Seven-Segment Display Register........................................ ...... ..... ...........1-37

VME Registers.................................................................................................1-37

LM/SIG Control Register..........................................................................1-38

LM/SIG Status Register............................................................................1-39

Location Monitor Upper Base Address Register ......................................1-41

Location Monitor Lower Base Address Register......................................1-41

Semaphore Register 1 ............................. ..... ...... .......................................1-42

Semaphore Register 2 ............................. ..... ...... .......................................1-42

VME Geographical Address Register (VGAR) ........................................1-43

Emulated Z8536 CIO Registers and Port Pins.................................................1-43

Emulated Z8536 Registers........................................................................1-43

Z8536 CIO Port Pins.................................................................................1-44

ISA DMA Channels .........................................................................................1-45

CHAPTER 2 Raven PCI Bridge ASIC

Introduction ...............................................................................................................2-1

Features......................................................................................................................2-1

Block Diagram...........................................................................................................2-2

Functional Description ..............................................................................................2 -4

MPC Bus Interface.............................................................................................2-4

MPC Address Mapping...............................................................................2-4

MPC Slave ..................................................................................................2-6

MPC Write Posting .....................................................................................2-8

MPC Master ................................................................................................2-8

MPC Arbiter..............................................................................................2-10

MPC Bus Timer ........................................................................................ 2-10

PCI Interface.....................................................................................................2-10

PCI Address Mapping...............................................................................2-11

PCI Slave...................................................................................................2-14

PCI Write Posting .....................................................................................2-17

viii

PCI Master.................................................................................................2-17

Generating PCI Cycles..............................................................................2-21

Endian Conversion............................................................................................2-25

When MPC Devices are Big-Endian.........................................................2-25

When MPC Devices are Little-Endian......................................................2-27

Raven Registers and Endian Mode............................................. ...... ...... ...2-27

Error Handling............................................................................................... ...2-28

Transaction Ordering........................................................................................2-29

Raven Registers ................................ ..... ...... ........................................ ....................2-30

MPC Registers..................................................................................................2-30

Vendor ID/Device ID Registers ................................................................2-32

Revision ID Register .................................................................................2-33

General Control-Status/Feature Registers.................................................2-33

MPC Arbiter Control Register...................................................................2-36

Prescaler Adjust Register...........................................................................2-36

MPC Error Enable Register.......................................................................2-37

MPC Error Status Register........................................................................2-39

MPC Error Address Register.....................................................................2-40

MPC Error Attribute Register - MERAT..................................................2-41

PCI Interrupt Acknowledge Register ........................................................2-43

MPC Slave Address (0,1 and 2) Registers................................................2-43

MPC Slave Address (3) Register...............................................................2-44

MPC Slave Offset/Attribute (0,1 and 2) Registers....................................2-45

MPC Slave Offset/Attribute (3) Registers.................................................2-46

General-Purpose Registers ........................................................................2-47

PCI Registers....................................................................................................2-47

Vendor ID/ Device ID Registers ...............................................................2-49

PCI Command/ Status Registers................................................................2-50

Revision ID/ Class Code Registers............................................................2-52

I/O Base Register.......................................................................................2-52

Memory Base Register ......................................... ..... ................................2-53

PCI Slave Address (0,1,2 and 3) Registers................................................2-54

PCI Slave Attribute/ Offset (0,1,2 and 3) Registers..................................2-55

CONFIG_ADDRESS Register..................................................................2-56

CONFIG_DATA Register.........................................................................2-58

Raven Interrupt Controller.............................................................................. .........2-60

Features...................................... ....................................... ................................2-60

Architecture ........................................................... ...... ..... ................................2-60

Readability of CSR....................................................................................2-61

Interrupt Source Priority............................................................................2-61

Processor’s Current Task Priority..............................................................2-61

Nesting of Interrupt Events.......................................................................2-62

Spurious Vector Generation...................................................................... 2-62

Interprocessor Interrupts (IPI)...................................................................2-62

8259 Compatibility....................................................................................2-62

Raven-Detected Errors..............................................................................2-63

Timers .......................................................................................................2-63

Interrupt Delivery Modes..........................................................................2-64

Block Diagram Description..............................................................................2-65

Program-Visible Registers........................................................................2-66

Interrupt Pending Register (IPR) ..............................................................2-66

Interrupt Selector (IS) ...............................................................................2-66

Interrupt Request Register (IRR).............................................................. 2-67

In-Service Register (ISR)..........................................................................2-67

Interrupt Router.........................................................................................2-67

MPIC Registers ................................................................................................2-69

RavenMPIC Registers...............................................................................2-69

Feature Reporting Register ................................ .......................................2-73

Global Configuration Register..................................................................2-74

Vendor Identification Register................................. ..... ...... ......................2-75

Processor Init Register ........................................................ ......................2-75

IPI Vector/Priority Registers........................ ........................................ .....2-76

Spurious Vector Register..........................................................................2-77

Timer Frequency Register.........................................................................2-77

Timer Current Count Registers.................................................................2-78

Timer Base Count Registers......................................................................2-78

Timer Vector/Priority Registers................................................................2-79

Timer Destination Registers......................................................................2-80

External Source Vector/Priority Registers................................................2-81

External Source Destination Registers......................................................2-82

Raven-Detected Errors Vector/Priority Register ......................................2-83

Raven-Detected Errors Destination Register............................................2-84

Interprocessor Interrupt Dispatch Registers..............................................2-84

Interrupt Task Priority Registers...............................................................2-85

Interrupt Acknowledge Registers..............................................................2-86

End-of-Interrupt Registers ........................................................................2-86

Programming Notes..........................................................................................2-87

External Interrupt Service.........................................................................2-87

Reset State.................................................................................................2-88

Interprocessor Interrupts...........................................................................2-89

Dynamically Changing I/O Interrupt Configuration.................................2-89

EOI Register.................................................................. ............................2-90

Interrupt Acknowledge Register...............................................................2-90

8259 Mode.................................................................................................2-90

Current Task Priority Level.......................................................................2-90

Architectural Notes...........................................................................................2-91

CHAPTER 3 Falcon ECC Memory Controller Chip Set

Introduction................................................................................................................3-1

Features......................................................................................................................3-1

Block Diagrams .........................................................................................................3-2

Functional Description ...............................................................................................3-5

Bit Ordering Convention ........................................................ ............................3-5

Performance.................................................................................. ......................3-5

Four-beat Reads/Writes...............................................................................3-5

Single-beat Reads/Writes ............................................................................3-6

DRAM Speeds.......................................... ........................................ ...........3-6

ROM/Flash Speeds....................................................................................3-10

PowerPC 60x Bus Interface..............................................................................3-11

Responding to Address Transfers..............................................................3-11

Completing Data Transfers........................................................................3-11

Cache Coherency.......................................................................................3-11

Cache Coherency Restrictions...................................................................3-12

L2 Cache Support......................................................................................3-12

ECC...................................................................................................................3-12

Cycle Types...............................................................................................3-12

Error Reporting....................................................................................... ...3-13

Error Logging................................ ........................................ ....................3-14

DRAM Test er....................... ...... ..... ........................................ ..........................3-14

ROM/Flash Interface ........................................................................................3-14

Refresh/Scrub....................................................................................................3-18

Blocks A and/or B Present, Blocks C and D Not Present .........................3-18

Blocks A and/or B Present, Blocks C and/or D Present............................3-19

DRAM Arbitration................................................. ...... ..... ................................3-20

Chip Defaults....................................................................................................3-20

External Register Set ........................................................................................3-21

CSR Accesses...................................................................................................3-21

Programming Model................................................................................................3-21

CSR Architecture..............................................................................................3-21

Detailed Register Bit Descriptions ...................................................................3-27

Vendor/Device Register ............................................................................3-30

Revision ID/ General Control Register .....................................................3-31

DRAM Attributes Register ...................................... ..... ...... ......................3-33

DRAM Base Register.................................................... ............................3-35

CLK Frequency Register...........................................................................3-35

ECC Control Register ...............................................................................3-36

Error Logger Register ......................................................... ...... ................3-39

Error Address Register......................................................................... .....3-42

Scrub/Refresh Register..............................................................................3-43

Refresh/Scrub Address Register ...............................................................3-44

ROM A Base/Size Register.......................................................................3-45

ROM B Base/Size Register....................................................................... 3-48

DRAM Tester Control Registers............................................... ..... ...... .....3-50

32-Bit Counter...........................................................................................3-50

Test SRAM................................................................................................3-50

Power-Up Reset Status Register 1 ............................................................3-51

Power-Up Reset Status Register 2 ............................................................3-51

External Register Set.................................................................................3-52

Software Considerations..........................................................................................3-53

Parity Checking on the PowerPC Bus..............................................................3-53

Programming ROM/Flash Devices..................................................................3-53

Writing to the Control Registers.......................................................................3-53

Sizing DRAM...................................................................................................3-54

ECC Codes.......................................................................................................3-57

Data Paths.........................................................................................................3-60

CHAPTER 4 Universe (VMEbus to PCI) Chip

Introduction ...............................................................................................................4-1

Features......................................................................................................................4-1

Block Diagram...........................................................................................................4-3

Functional Description ..............................................................................................4 -3

VMEbus Interface ............................................... ........................................ .......4-4

Universe as VMEbus Slave.........................................................................4-4

Universe as VMEbus Master ......................................................................4-5

PCI Bus Interface ...............................................................................................4-5

Universe as PCI Slave.................................................................................4-6

Universe as PCI Master...............................................................................4-6

Interrupter...........................................................................................................4-6

VMEbus Interrupt Handling .............................. ........................................ .4-7

DMA Controller.................................................................................................4-7

Universe Control and Status Registers (UCSR).................................................4-8

Universe Register Map................................................................................4-9

xii

Universe Chip Problems after PCI Reset..........................................................4-14

Description.................................................................................................4-14

Workarounds .............................................................................................4-15

Examples...........................................................................................................4-16

Example 1: MVME2600 Series Board Exhibits PCI Reset Problem........4-16

Example 2: MVME3600 Series Board Acts Differently...........................4-17

Example 3: Universe Chip is Checked at Tundra......................................4-19

CHAPTER 5 Programming Details

Introduction................................................................................................................5-1

PCI Arbitration...........................................................................................................5-1

Interrupt Handling......................................................................................................5-2

RavenMPIC ........................................................................................................5-3

8259 Interrupts....................................................................................................5-4

ISA DMA Channels...................................................................................................5-7

Exceptions ..................................................................................................................5-8

Sources of Reset..................................................................................................5-8

Soft Reset............................. ...... ....................................... ..................................5-9

Universe Chip Problems after PCI Reset............................................................5-9

Error Notification and Handling.......................................................................5-10

Endian Issues ........................................................................................................... 5-11

Processor/Memory Domain.................................................... ...... ..... ...............5-13

Role of the Raven ASIC...................................................................................5-13

PCI Domain ......................................................................................................5-13

PCI-SCSI...................................................................................................5-13

PCI/Ethernet ..............................................................................................5-13

PCI-Graphics.............................................................................................5-14

Role of the Universe ASIC...............................................................................5-14

VMEbus Domain.............................................................. ...... ...... ....................5-14

ROM/Flash Initialization .........................................................................................5-15

APPENDIX A Related Documentation

Motorola Computer Group Documents....................................................................A-1

Manufacturers’ Documents.......................................................................................A-2

Related Specifications...............................................................................................A-4

xiii

List of Figures

Figure 1-1. MVME2300 Series System Block Diagram ...........................................1-5

Figure 1-2. VMEbus Master Mapping.....................................................................1-20

Figure 1-3. VMEbus Slave Mapping.......................................................................1-22

Figure 1-4. General-Purpose Software-Readable Header........................................1-32

Figure 2-1. Raven Block Diagram.............................................................................2-3

Figure 2-2. MPC-to-PCI Address Decoding..............................................................2-5

Figure 2-3. MPC to PCI Address Translation............................................................2-6

Figure 2-4. PCI to MPC Address Decoding............................................................2-12

Figure 2-5. PCI to MPC Address Translation..........................................................2-13

Figure 2-6. PCI Spread I/O Address Translation.....................................................2-22

Figure 2-7. Big- to Little-Endian Data Swap...........................................................2-26

Figure 2-8. RavenMPIC Block Diagram.................................................................2-65

Figure 3-1. Falcon Pair Used with DRAM in a System ............................................3-2

Figure 3-2. Falcon Internal Data Paths (Simplified)..................................................3-3

Figure 3-3. Overall DRAM Connections...................................................................3-4

Figure 3-4. Data Path for Reads from the Falcon Internal CSRs.............................3-22

Figure 3-5. Data Path for Writes to the Falcon Internal CSRs.................................3-23

Figure 3-6. Memory Map for Byte Reads to CSR...................................................3-24

Figure 3-7. Memory Map for Byte Writes to Internal Register Set

and Test SRAM........................................................................................................3-25

Figure 3-8. Memory Map for 4-Byte Reads to CSR................................................3-26

Figure 3-9. Memory Map for 4-Byte Writes to Internal Register Set

and Test SRAM........................................................................................................3-26

Figure 3-10. PowerPC Data to DRAM Data Correspondence.................................3-60

Figure 4-1. Architectural Diagram for the Universe..................................................4-4

Figure 4-2. UCSR Access Mechanisms.....................................................................4-9

Figure 5-1. MVME2300 Series Interrupt Architecture..............................................5-2

Figure 5-2. PIB Interrupt Handler Block Diagram....................................................5-5

Figure 5-3. Big-Endian Mode..................................................................................5-11

Figure 5-4. Little-Endian Mode...............................................................................5-12

List of T ables

Table 1-1. Features: MVME2300 Series....................................................................1-2

T ab le 1-2. Default Processor Memory Map...............................................................1-8

T ab le 1-3. CHRP Memory Map Example................................ ...... ...... ......................1-9

Table 1-4. Raven MPC Register Values for CHRP Memory Map...........................1-10

Table 1-5. PREP Memory Map Example.................................................................1-11

Table 1-6. Raven MPC Register Values for PREP Memory Map ...........................1-12

Table 1-7. PCI CHRP Memory Map........................................................................1-13

Table 1-8. Raven PCI Register Values for CHRP Memory Map.............................1-15

Table 1-9. Universe PCI Register Values for CHRP Memory Map.........................1-15

Table 1-10. PCI PREP Memory Map.......................................................................1-16

Table 1-11. Raven PCI Register Values for PREP Memory Map............................1-18

Table 1-12. Universe PCI Register Values for PREP Memory Map........................1-19

Table 1-13. Universe PCI Register Values for VMEbus Slave Map Example ........1-23

Table 1-14. VMEbus Slave Map Example...............................................................1-24

Table 1-15. System Register Summary....................................................................1-24

Table 1-16. 16550 Access Registers ........................................................................1-31

Table 1-17. M48T59/559 Access Registers.............................................................1-33

Table 1-18. Module Configuration and Status Registers.........................................1-33

Table 1-19. VME Registers......................................................................................1-38

Table 1-20. Emulated Z8536 Access Registers .......................................................1-43

Table 1-21. Z8536 CIO Port Pin Assignments........................................................1-44

Table 2-1. Features of the Raven ASIC.....................................................................2-1

Table 2-2. Command Types — MPC Slave Response...............................................2-7

Table 2-3. MPC Transfer Types .................................................................................2-9

Table 2-4. Command Types — PCI Slave Response...............................................2-15

Table 2-5. PCI Master Command Codes .................................................................2-18

Table 2-6. Address Modification for Little-Endian Transfers .................................2-27

T ab le 2-7. Raven MPC Register Map......................................................................2-31

Table 2-8. Raven PCI Configuration Register Map.................................................2-48

Table 2-9. Raven PCI I/O Register Map..................................................................2-49

Table 2-10. RavenMPIC Register Map....................................................................2-69

Table 3-1. Features of the Falcon Chip Set................................................................3-1

Table 3-2. PowerPC 60x Bus to DRAM Access Timing — 70ns Page Devices.......3-7

Table 3-3. PowerPC 60x Bus to DRAM Access Timing — 60ns Page Devices.......3-8

xvii

Table 3-4. PowerPC Bus to DRAM Access Timing — 50ns Hyper Devices...........3 -9

Table 3-5. PowerPC 60x Bus to ROM/Flash Access Timing — 64 Bits

(32 Bits per Falcon).................................................................................................3-10

Table 3-6. PowerPC 60x Bus to ROM/Flash Access Timing — 16 Bits (8 Bits

per Falcon)...............................................................................................................3-10

T ab le 3-7. Error Reporting...................................................... .................................3-13

Table 3-8. PowerPC 60x to ROM/Flash Address Mapping — ROM/Flash

16 Bits Wide (8 Bits per Falcon).............................................................................3-16

Table 3-9. PowerPC 60x to ROM/ Flash Address Mapping — ROM/Flash

64 Bits Wide (32 Bits per Falcon)...........................................................................3-17

Table 3-10. Register Summary................................................................................3-28

Table 3-11. ram spd1,ram spd0 and DRAM Type...................................................3-32

Table 3-12. Block_A/B/C/D Configurations...........................................................3-34

Table 3-13. rtest Encodings.....................................................................................3-43

Table 3-14. ROM Block A Size Encoding..............................................................3-46

Table 3-15. rom_a_rv and rom_b_rv Encoding.......................................................3-46

Table 3-16. Read/Write to ROM/Flash....................................................................3-47

Table 3-17. ROM Block B Size Encoding ..............................................................3-49

T ab le 3-18. Sizing Addresses....................................................................... ...........3-56

Table 3-19. PowerPC 60x Address to DRAM Address Mappings..........................3-56

Table 3-20. Syndrome Codes Ordered by Bit in Error............................................3-57

Table 3-21. Single-Bit Errors Ordered by Syndrome Code.....................................3-59

Table 3-22. PowerPC Data to DRAM Data Mapping.............................................3-61

Table 4-1. Features of the Universe ASIC.................................................................4-2

Table 4-2. Universe Register Map...........................................................................4-10

T ab le 5-1. PCI Arbitration Assignments................................ ..... ..............................5-1

T ab le 5-2. RavenMPIC Interrupt Assignmen ts........................... ...... ...... ..................5-3

Table 5-3. PIB PCI/ISA Interrupt Assignments........................................................5-6

Table 5-4. Reset Sources and Devices Affected........................................................5-9

Table 5-5. Error Notification and Handling.............................................................5-10

Table 5-6. ROM/Flash Bank Default......................................................................5-15

xviii

About This Manual

The MVME2300 Series VME Processor Module Programmer’s Referenc e Guide provides board-level information and detailed ASIC information,

including register bit descriptions, for the MVME2300 and MVME2300SC series of VME processor modules.

The MVME2300 series VME processor module is based on an MPC603 or MPC604 PowerPC microprocessor, and features dual PCI Mezzanine Card (PMC) slots with front panel and/or P2 I/O. In addition, the MVME2300SC versions of the board give both PMC slot s access (via P2) to an SCSA (Signal Computing System Arch itecture) backplane bus , if the system supports one.

The MVME2300 series VME processor module is compatible with optional double-width or si ngle- width PMCs, and wit h the PMCspan PCI expansion mezzanine modul e. By utilizing the two onboard PMC slots an d stacking PMCspan(s), the MVME2300SC can provide support for up to six PMCs.

As of the publication date , the information presented in t his manual applies to the following MVME2300 and MVME2300SC models:

Model Memory Processor

MVME2301 16MB ECC DRAM MVME2302 32MB ECC DRAM MVME2303 64MB ECC DRAM MVME2304 128MB ECC DRAM MVME2304-0111, -0113, MVME2305* 16MB ECC DRAM MVME2304-0121, -0121SC, -0123, MVME2306* 32MB ECC DRAM MVME2304-0131, -0131SC, -0133, MVME2307* 64MB ECC DRAM MVME2304-0141, -0141SC, -0143, MVME2308* 128MB ECC DRAM MVME2306SC-1 32MB ECC DRAM MVME2307SC-1 64MB ECC DRAM

MPC603

@ 200 MHz

MPC604

@ 300*/333

MHz

MPC604

@ 300 MHz

xix

This manual is intended for anyone who designs OEM systems, adds capability to an existing compatible system, or works in a lab environment for experimental purposes. A basic knowledge of computers and digital logic is assumed. To use this manual, you may also wish to become familiar with the publications listed in Appendix A, Related

Documentation.

Summary of Changes

This is the fifth edition of the Programmer’s Reference Guide. It supersedes the Mar ch 2001 edition a nd incorporate s the follo wing updates.

Date Description of Change

January 2001 A caution about DRAM component requirements was added to the DRAM

Attributes Register and Sizing DRAM sections of Chapter 3.

January 2001 In descriptio ns of the gen eral-purpo se software-readab le header (J 10/J17), s uch

as Figure 1-4 in Chapter 1, information on bit 1 (SRH1) was updated to correctly reflect the functionality of that bit.

March 2001 At various locations in the manual, such as P2 I/O on page 1-7, information has

been added to accommodate the The contents of the manual have also been reorganized somewhat to conform

with present Computer Group practice for board manuals.

June 2001 All data referring to the VME CSR Bit Set Register (VCSR_SET) and VME

CSR Bit Clear Register (VCSR_CLR) has been deleted. These registers of the Universe II are unavailable for implementation as intended by the MVME materials and the Universe II User Manual.

MVME2300SC variants of the board.

Overview of Contents

Chapter 1, Board Description and Memory Maps, describes the board-

level hardware features of MVME2300 se ries VME processor modules. It includes memory maps and a discussion of some general software considerations such as cache coherency, interrupts, and bus errors.

Chapter 2, Raven PCI Bridge ASIC, describes the Raven ASIC, the PCI

local bus/PowerPC processor bus interface chip used on MVME2300 series boards.

Chapter 3, Falcon ECC Memory Contr oller Chip Set, descr ibes the Falcon

memory controller chip set, w hich provides the interface between the PowerPC processor bus and memory systems on MVME2300 series boards.

Chapter 4, Universe (VMEbus to PCI) Chip, describes the Universe ASIC,

the VMEbus/PCI local bus interface chip used on MVME2300 series boards.

Chapter 5, Programming Details, examines aspects of several

programming functions that are not tied to any specific ASIC on MVME2300 series boards.

Appendix A, Related Documentat ion, lists all documentation rel ated to the

MVME2300 and MVME2300SC series boards.

Comments and Suggestions

Motorola welcomes and appreciates your comments on its doc umentation. We want to know what y ou think about our manuals and how we can make them better. Mail comments to:

Motorola Computer Group Reader Comments DW164 2900 S. Diablo Way Tempe, Arizona 85282

You can also submit comments to the following e-mail address:

reader-comments@mcg.mot.com

xxi

In all your corres pondence , plea se li st your name, po si tion, a nd compan y. Be sure to include the title and par t number of the manual and tell how you used it. Then tell us your feelings about its strengths and weaknesses and any recommendations for improvements.

Conventions Used in This Manual

The following typographical conventions are used in this document:

bold

is used for user inpu t that you t ype just as i t appears ; it is al so used for commands, options and arguments to commands, and names of programs, directories and files.

italic

is used for names of variables to which you assign values. Italic is also used for comments in screen dis plays and examples, and to intr odu ce new terms.

courier

is used for system output (for example, screen displays, reports), examples, and system prompts.

xxii

<CR> represents the carriage return or Enter key.

CTRL

represents the Control key. Execute control characters by pressing the Ctrl key and the letter simultaneously, for example, Ctrl-d.

Data and address parameters are preceded by a character identifying the numeric format as follows:

$ % &

dollar percent ampersand

specifies a hexadecimal character specifies a binary number specifies a decimal number

For example, “12” is t he decimal numbe r twelve, and “$12” is the decimal number eighteen.

Unless otherwise specified, all address references are in hexadecimal. In descriptions of the VMEbus interface, an asterisk (∗) following the

signal name for signals which are level significant denotes that the signal is true or valid when the s ignal is low. An aste risk (∗) following the signal name for signals which are edge significant denotes that the actions initiated by that signal occur on high to low transition.

In references to other bus signals (such as PCI) found on MVME2300 series boards, an underscore (_) or pound sign (#) following the signal name denotes an active low signal.

In this manual, assertion and negation signify the forcing of a signal to a particular state. In particular, assertion and assert refer to a signal that is active or true; neg ation and negate indica te a signal that is ina ctive or false. These terms are used ind ependen tly of t he vol tag e level (high or low) t hat they represent.

Data and address sizes for MPC60x chips are defined as follows:

❏ A byte i s eight bits, numb ered 0 through 7, wit h bit 0 being the leas t

significant.

❏ A half-word is 16 b its, number ed 0 thr oug h 15, with bit 0 b eing th e

least significant.

❏ A word or single wor d is 32 bits , numbered 0 t hrough 31, wit h bit 0

being the least significant.

❏ A double word is 64 bits, numbered 0 through 63, with bit 0 being

the least significant.

Refer to Endian Issues in Chapter 5 for a discussion of which elements on MVME2300 series boards use big-endian byte ordering, and which use small-endian byte ordering.

The terms control bit and status bit are used extensively in this document. The term control b it is used to d escribe a bit in a register that can be set and cleared under softwar e c ont rol . The te rm tr ue is used to indicate that a bit is in the state that enables the function it controls. The term false is used to

xxiii

indicate that the bit is in the state that disables the function it controls. In all tables, th e terms 0 and 1 are used to describe the actual va lue that should be written to the bit, or the value that it yields when read. The term status bit is used to describe a bit in a register that reflects a specific condition. The status bit can be read by software to determine operational or exception conditions.

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1Board Description and Memory

Introduction

This manual provides programming information for MVME2300 and MVME2300SC VME processor modules. Extensive programming information is pr ovided for several Appl ication-Specific I ntegrated Circuit (ASIC) devices used on the boards. Reference information is included in Appendix A for the Large Scale Integration (LSI) devices used on the boards and sources for additional information are listed.

This chapter briefly describes the board level hardware features of the MVME2300-series VME processor modules. The chapter begins with a board level overvi ew and feat ures lis t. Memo ry maps are n ext, and are the major feature of this chapte r.

Programmable register s that reside i n ASICs in the M VME2300 series are covered in the chapters on those ASICs. Chapter 2, Raven PCI Bridge

ASIC covers the Raven chip, Chapter 3, Falcon ECC Memory Controller Chip Set covers the F alcon chip se t, Chapter 4, Universe (VMEbus to PCI) Chip covers the U niverse chip, and Chapter 5, Programming Details

covers certain programming features, such as interrupts and exceptions.

Appendix A, Related Documentation lists all related do cumentation.

Maps

Overview

The MVME2300-series VME Processor Module family, hereafter sometimes referred to simply as the MVME230x or the MVME2300 series, provides many standard features required by a computer system: Ethernet interfac e, async s erial port , boot Flash, and up to 128MB of ECC DRAM.

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Board Description and Memory Maps

Summary of Features

There are many models based on t he MVME2300 ser ies archite cture. The following table summarizes the major features of the MVME2300 series:

Table 1-1. Features: MVME2300 Series

Feature MVME2300 MVME2300SC

200 MHZ MPC603 PowerPC processor

Microprocessor

Form factor 6U VMEbus

ECC DRAM

Flash memory

Real-time clock

Switches Reset

Status LEDs

Timers

Interrupts VME I/O VMEbus P2 connector

(MVME2301 - 2304 models) 300 MHZ MPC604 PowerPC

processor (MVME2305 - 2308 models)

Two-way interleaved, ECCprotected 16MB, 32MB, 64MB, or 128MB

Bank B: T w o 32-pin PLCC socket s that can be populated with 1MB 8- bit Flash devices

Bank A: Four 16-bit Smart Voltage SMT devices that can be populated with 8Mbit Flash devices (4MB) or 4Mbit devices (2MB)

8KB NVRAM with RTC, battery backup, and watchdog function (SGS-Thomson M48T59/T559)

Four: Board fail (one for PMC slot 2, one for slot 1)

One 16-bit timer in W83C553 PCI/ISA bridge; four 32-bit timers in Raven (MPIC) device

Watchdog timer provided in SGS-Thomson M48T59/T559 Software interr upt handling via Raven (PCI/MPU bridge) and Winbond

(PCI/ISA bridge) controllers

(BFL), CPU, PMC

(RST) and Abort (ABT)

300 MHZ MPC604 PowerPC processor (All models)

Two-way interleaved, ECCprotected 32MB or 64MB

Bank A: Four 16-bit Smart Voltage SMT devices populated with 8Mbit Flash devices (4MB)

8KB NVRAM with RTC, battery backup, and watchdog function (SGS-Thomson M48T559)

Four: Board Fail (BFL), CPU, System Controller (

FUS)

(

SCON), Fuses

1-2 Computer Group Literature Center Web Site

Table 1-1. Features: MVME2300 Series (Continued)

Feature MVME2300 MVME2300SC

One asynchronous debug port via

Serial I/O

Ethernet I/O

PCI interface

SCSA I/O Not available

VMEbus interface

RJ45 connector on front panel

10BaseT/100BaseTX connections via RJ45 connector on front panel

Two IEEE P1386.1 PCI Mezzanine Card (PMC) slots for one doublewidth or two single-width PMCs

Front panel and/or VMEbus P2 I/O on both PMC slots One 114-pin Mictor connector for optional PMCspan expansion module

VMEbus system controller functions VME64 extension VMEbus-to-local-bus interface (A24/A32, D8/D16/D32/block transfer

[D8/D16/D32/D64]) Local-bus-to-VMEbus interface (A16/A24/A32, D8/D16/D32) VMEbus interrupter VMEbus interrupt handler Global Control/Status Register (GCSR) for in terprocessor

communications DMA for fast local memory/VMEbus transfers (A16/A24/A32,

D16/D32/D64)

One asynchronous debug port via DB9 connector on front panel, also via P2 and transition module

10BaseT/100BaseTX connections via RJ45 connector on front panel; AUI connections via P2 and transition module

Connections from both PMC slots to SCSA backplane TDM bus (if present in system) via

on P2

connector

System Block Diagram

shared pins

System Block Diagram

The MVME2300 series does not provide any look-aside external cache option. The Falcon chip set controls the boot Flash and the ECC DRAM. The Raven ASIC functions as the 64-bit PCI host bridge and the MPIC interrupt controller. PCI devices include: VME, Ethernet, and two PMC

http://www.motorola.com/computer/literature 1-3

Board Description and Memory Maps

slots. Standard I/O functions are provided by the UART device which resides on the ISA bus. The NVRAM/RTC also resides on the ISA bus. The general system blo ck diagra m for MVME2300 s eries i s shown belo w:

1-4 Computer Group Literature Center Web Site

System Block Diagram

CLOCK

GENERATOR

PHB & MPIC

RAVEN ASIC

64-BIT PMC SLOT

PROCESSOR

MPC603/604

10BT/100BTX

PORT

SERIAL

DEBUG CONNECTOR

66MHz MPC604 PROCESSOR BUS

33MHz 32/64-BIT PCI LOCAL BUS

W83C553

ETHERNET

DEC21140

PC16550

UART

PIB

ISA BUS

MEMORY CONTROLLER

FALCON CHIP SET

RTC/NVRAM/WD

MK48T59/559

ISA

REGISTERS

DRAM

16/32/64/128MB

Flash

3MB or 5MB

SYSTEM

REGISTERS

VME BRIDGE

UNIVERSE

BUFFERS

PCI EXPANSION

PMC FRONT I/O SLOT

FRONT PA N EL

VME P2 VME P1

2067 9708

Figure 1-1. MVME2300 Series System Block Diagram

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Board Description and Memory Maps

Functional Description

The MVME2300 series is a fa mily of single- slot VME processor modules. It consists of the MPC603/604 processor, the Raven PCI Bridge and Interrupt Controller, the Falcon ECC Memory Controller chip set, 3MB or 5MB of Flash memory, 16MB to 128MB of ECC-prot ected DRAM, and a rich set of I/O features.

I/O peripheral devices on the PCI bus are: Ethernet chip, Universe VMEbus interface ASIC, and two PMC sl ots. Functions provid ed from the ISA bus are: one asynchronous serial port, a real-time clock, counters/timers, and a software-readable header.

VMEbus Interface

MVME2300 series boards interface to the VMEbus via the P1 and P2 backplane connectors. MVME2300SC boards use the three-row 96-pin connectors specified in the original VMEbus standard; non-SCbus MVME2300 boards use the 5-row 160-pin connectors specified in the VME64 Extension standard.

Both types of boards draw +5V, +12V, a nd –12V power from the VMEbus backplane through these two connectors. 3.3V and 2.5V supplies are regulated onboard from the +5 power.

Front Panel

Front panel connectors on the non-SCbus MVME2300 series boards include an RJ45 connector for the Ethernet 10BaseT/100BaseTX interface, and a second RJ45 conne ctor for the async hronous serial debug port.

Front panel connector s o n the MVME2300SC include an RJ45 connector for the Ethernet 10BaseT/100BaseTX interface, and a 9-pin DB9 connector for the asynchronous serial debug port.

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