Motorola MVME2100 Installation And Use Manual

MVME2100

Single Boar d Computer

Installation and Use

V2100A/IH2

July 2001 Edition

© Copyright 2001 Motorola, Inc.

All rights reserved.

Printed in the United States of America.
Motorola and the Motorola symbol are registered trademarks of Motorola, Inc.
PowerPC and the PowerPC logo are registered trademarks of International Business

Machines Corporation and are used by Motorola, Inc. under license from International
Business Machines Corporation.

PC•MIP is a trademark of SBS GreenSpring Modular I/O, Inc.

2

C is a registered trademark of Philips Semiconductors

I
All other products ment io ned i n this document are trademarks or registered trade ma rk s of

their respective holders.

Safety Summary

The following general safety precautions must be observed during all phases of operation, service, and repair of this
equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual could result
in personal injury or damage to the equipment.

The safety precaut ions listed be low represent warnings of ce rtain danger s of which Mot orola is awar e. You, as the
user of the product, should follow these warnings and all other safety precautions necessary for the safe operation of
the equipment in your operating environment.

Ground the Instrument.

To minimize shock hazard, the equipment chassis and enclosure must be connected to an electrical ground. If the
equipment is su pplied wi th a three-c onductor A C power ca ble, the po wer cable m ust be plug ged into an a pproved
three-contact electrical outlet, with the grounding wire (green/yellow) reliably connected to an electrical ground
(safety ground) at the power outlet. The power jack and mating plug of the power cable meet International
Electrotechnical Commission (IEC) safety standards and local electrical regulatory codes.

Do Not Operate in an Explosive Atmosphere.

Do not operate the equipment in any explosive atmosphere such as in the presence of flammable gases or fumes.
Operation of any electrical equipment in such an environment could result in an explosion and cause injury or damage.

Keep Away From Live Circuits Inside the Equipment.

Operating personnel must not remove equipment covers. Only Factory Authorized Service Personnel or other
qualified service personnel may remove equipment covers for internal subassembly or component replacement or any
internal adjust ment. Service pe rsonnel should n ot replace compon ents with power c able connected. Under certain
conditions, dangerous voltages may exist even with the power cable removed. To avoid injuries, such personnel
should always disconnect power and discharge circuits before touching compon ent s.

Use Caution When Exposing or Handling a CRT.

Breakage of a Cathode-Ray Tube (CRT) causes a high-velocity scattering of glass fragments (implosion). To prevent
CRT implosion, do not handl e the CRT and avoid rough handling o r jarring of t he equipment . Handling o f a CRT
should be done only by qualified service personnel using approved safety mask and gloves.

Do Not Substitute Parts or Modify Equipment.

Do not install substitute parts or perform any unauthorized modification of the equipment. Contact your local
Motorola representative for service and repair to ensure that all safety features are maintained.

Observe Warnings in Manual.

W arn ings , such as th e exa mple be low, preced e pote ntia lly da nger ous pro cedure s thro ugh out th is manual . In struc tion s
contained in the warnings m ust be follow ed. You should also employ all ot her safety precautions w hich you dee m
necessary for the operation of the equipment in your operat in g environment.

To prevent serious injury or death from dangerous voltages, use extreme
caution when handling, testing, and adjusting this equipment and its

Warning

components.

Flammability

All Motorola PWBs (printed w iring boards) are manufactu red with a flammability rating
of 94V-0 by UL-recognized manufacturers.

EMI Caution

This equipment ge ner ates, uses a nd can radi ate el ectro magne tic energy . It

!

Caution

This product contains a lithium battery to power the clock and calendar circuitry.

!

Caution

may cause or be susceptible to electromagnetic interference (EMI) if not
installed and used with adequate EMI protection.

Lithium Battery Caution

Danger of explosion if battery is re placed incorrect ly. Replace battery only
with the same or equivalent type recommended by the equipment

manufacturer. Dispose of used batteries according to the manufacturer’s
instructions.

!

Attention

!

Vorsicht

Il y a danger d’explosion s’il y a remplacement incorrect de la batterie.
Remplacer uniquement avec une batterie du même type ou d’un type
équivalent recommandé par le constructeur. Mettre au rebut les batteries
usagées conformément aux instructions du fabricant.

Explosionsgefahr bei unsachgemäßem Austausch der Ba tterie. Ersatz nur
durch denselben ode r einen vom Herstel ler empfohle nen Typ. Entsorgu ng
gebrauchter Batterien nach Angaben des Herstellers.

CE Notice (European Community)

Motorola Compute r Group pro ducts wi th the CE mar king co mply with the EMC Dir ective
(89/336/EEC). Compliance with this directive implies conformity to the following
European Norms:

EN55022 “Limits and Methods of Meas urement of Radio Int erferen ce Chara cteri stic s
of Information Technology Equipment”; this product tested to Equipment Class B

EN55024 “Information te chnology equipment—Immunity char acteristics—Limits and
methods of measurement”

Board products are tested in a representative system to show compliance with the above
mentioned requirements. A proper installation in a CE-marked system will maintain the
required EMC /safety performance.

In accordance with European Community directives, a “Declaration of Conformity” has
been made and is available on request. Please contact your sales representative.

Notice

While reasonable efforts have been made to assure the accuracy of this document,
Motorola, Inc. a ssumes n o lia bility r esulti ng from any omissio ns in this docu ment, or from
the use of the information obtained there in. Motorola re serves the right to revise this
document and to ma ke c hanges from time to ti me in the content hereof wi thout obligation
of Motorola to notify any person of such revision or changes.

Electronic versions of this material may be read online, downloaded for personal use, or
referenced in another document as a URL to the Motorola Computer Group website. The
text itself may not b e published commerci ally in print o r electronic for m, edited, transla ted,
or otherwise altered withou t the permission of Motorola, Inc.

It is possible th at t hi s publication may contain r eference to or information about Motorola
products (machines and pr ograms), progra mming, or services that are not av ailable in your
country. Such references or information must not be construed to mean that Motorola
intends to announce such Motorola products, programming, or services in your country.

Limited and Restricted Rights Legend

If the documentation contained herein is supplied, directly or indirectly, to the U.S.
Government, the following notice shall apply unless otherwise agreed to in writing by
Motorola, Inc.

Use, duplication, or disclosure by the Government is subject to restrictions as set forth in
subparagraph (b)(3) of t he Rig hts i n Tech nical Data clause at DFARS 252.227-7013 (Nov.

1995) and of the Rights in Noncommerc ial Computer Software and Docume ntation c lause
at DFARS 252.227-7014 (Jun. 1995).

Motorola, Inc.
Computer Group
2900 South Diablo Way
Tempe, Arizona 85282

Contents

About This Manual

Summary of Changes.................................................................................................xvi

Overview of Contents................................................................................................xvi

Comments and Suggestions......................................................................................xvii

Conventions Used in This Manual...........................................................................xviii

Terminology ......................................................................................................xviii

CHAPTER 1 Preparation and Installation

Introduction................................................................................................................1-1

PMCspan Expansion Mezzanine........................................................................1-2

PCI Mezzanine Cards (PMCs)............................................................................1-2

PC•MIP Expansion.............................................................................................1-2

VME System Enclosure......................................................................................1-3

System Console Terminal ...................................................................................1-3

Unpacking the MVME2100 Hardware......................................................................1-4

Preparing the MVME2100 Hardware........................................................................1-4

MVME2100 Configuration Settings...................................................................1-4

Setting Flash Memory Bank A/Bank B Header (J9) (Pins 1 and 2)............1-5

Setting System Controller Selection Header (J2)........................................1-5

PMCs ..................................................................................................................1-6

PMCspan.............................................................................................................1-6

System Console Terminal ...................................................................................1-6

Installing the MVME2100 Hardware ........................................................................1-7

ESD Precautions.................................................................................................1-8

PMCs & PC•MIPs ..............................................................................................1-8

Primary PMCspan.............................................................................................1-11

Secondary PMCspan.........................................................................................1-14

MVME2100 System Installation......................................................................1-17

Installation Considerations ............................................... ...... ..........................1-19

CHAPTER 2 Operating Instructions

Introduction................................................................................................................2-1

Applying Power.........................................................................................................2-1

MVME2100 User Interface Devices..........................................................................2-3

vii

Switches..............................................................................................................2-3

ABT (S1).....................................................................................................2-3

RST (S2)............................................ ...... ..... ........................................ ...... .2-4

BFL (DS1).................................................... ...... ...... ...................................2-4

SYS (DS2)............................................................................................ ...... .2-4

RUN (DS3)........................................ ...... ..... ........................................ .......2-4

10/100 BASE T Port...........................................................................................2-4

DEBUG Port............................................. ........................................ ..... .............2-4

Jumper Settings ..................................................................................................2-6

I/O Expansion Cards ..........................................................................................2-7

PCI Mezzanine Card...................................................................................2-7

TYPE II PC-MIP.........................................................................................2-7

CHAPTER 3 Functional Description

Introduction ...............................................................................................................3-1

Functional Description ..............................................................................................3-4

Processor ............................................................................................................3-4

PCI Host Bridge/Memory Controller.................................................................3-4

PCI Bus Arbitration............................................................................................3-4

PCI Local Bus ....................................................................................................3-5

Interrupt Controller.............................................................................................3-5

T wo-Wire Serial Interface.................. ...... ...... ....................................... .............3-6

I2O Message Unit...............................................................................................3-6

Direct Memory Access (DMA)..........................................................................3-6

Timers.................................................................................................................3-6

System Clock Generator.....................................................................................3-7

Flash Memory.....................................................................................................3-7

System Memory .................................................................................................3-7

Ethernet Interface...............................................................................................3-8

Asynchronous Serial Port...................................................................................3-8

VMEbus Interface ............................................... ........................................ .......3-9

PCI Mezzanine Card Slot...................................................................................3-9

PC•MIP Type I Mezzanine Card Slots...............................................................3-9

PC•MIP Type II Mezzanine Card Slots..............................................................3-9

PCI/PMC Expansion Capability.......................................................................3-10

Real-Time Clock & NVRAM ..........................................................................3-10

CHAPTER 4 PPCBug Firmware

PPCBug Overview.....................................................................................................4-1

viii

PPCBug Basics ..........................................................................................................4-1

Memory Requirements ..................................................... ...... ............................4-3

PPCBug Implementation....................................................................................4-3

MPU, Hardware, and Firmware Initialization ...........................................................4-3

Using PPCBug ...........................................................................................................4-5

Debugger Commands .........................................................................................4-6

Diagnostic Tests................................................................................................4-11

CHAPTER 5 Modifying the Environment

Overview....................................................................................................................5-1

CNFG - Configure Board Information Block............................................................5-2

ENV - Set Environment.............................................................................................5-3

Configuring the PPCBug Parameters.................................................................5-3

LED/Serial Startup Diagnostic Codes.......................................................5-11

Configuring the VMEbus Interface..................................................................5-12

Firmware Command Buffer.................................................................... ...5-16

APPENDIX A Related Documentation

Motorola Computer Group Documents.................................................................... A-1

Manufacturers’ Documents.......................................................................................A-2

Related Specifications...............................................................................................A-5

APPENDIX B Specifications

Specifications............................................................................................................B-1

Mechanical Characteristics................................................................................B-1

Electrical Characteristics ...................................................................................B-1

Environmental Characteristics...........................................................................B-2

EMC Compliance......................................................................................................B-3

Thermal Validation....................................................................................................B-4

Thermally Significant Components...................................................................B-4

Component Temperature Measurement................................... .................................B-8

Preparation.................................................. ..... ........................................ ..........B-8

Measuring Junction Temperature.......................................................................B-8

Measuring Case Temperature ............................................................................ B-8

Measuring Local Air Temperature...................................................................B-11

ix

APPENDIX C Connector Pin Assignments

Introduction .............................................................................................................. C-1

VMEbus Connectors ................................................. ...... ..................................C-1

PC•MIP PCI Interface Connectors....................................................................C-3

PC•MIP User Defined I/O Connectors..............................................................C-5

PCI Mezzanine Card (PMC) PCI Interface Connectors.................................... C-6

PMC User Defined I/O Connector.................................................................... C-8

PCI Expansion Connector........................................................................C-10

10BaseT/100BaseTx Connector............................................................... C-13

Asynchronous Serial Port Connector....................................................... C-13

Two-Wire Serial Interface Header........................................................... C-14

APPENDIX D Troubleshooting

Solving Startup Problems.........................................................................................D-1

x

List of Figures

Figure 1-1. MVME2100 Layout................................................................................1-7

Figure 1-2. MVME2100 Installation and Removal From a VMEbus Chassis..........1-9

Figure 1-3. Typical Single-width PMC Module Placement on an MVME2100 .....1-10

Figure 1-4. Typical Type II PC•MIP Placement on an MVME2100.......................1-11

Figure 1-5. PMCspan-001 Installation on an MVME2100 .....................................1-13

Figure 1-6. PMCspan-010 Installation on a PMCspan-001/MVME2100...............1-15

Figure 2-1. System Boot-up Sequence.......................................................................2-2

Figure 3-1. MVME2100 Block Diagram...................................................................3-3

Figure 3-2. Asynchronous Serial Port Connections...................................................3-8

Figure B-1. Thermally Significant Components (Primary Side) .............................B-6

Figure B-2. Thermally Significant Components (Secondary Side) .........................B-7

Figure B-3. Mounting a Thermocouple Under a Heatsink ....................................B-10

Figure B-4. Measuring Local Air Temperature .....................................................B-11

xi

List of T ables

T ab le 1-1. PMCspan Models.................................................... ...... ...... ......................1-2

Table 2-1. Jumper Switches and Settings...................................................................2-6

T ab le 3-1. MVME2100 Features ...............................................................................3-1

T ab le 4-1. Debugger Command s........................................ .......................................4-7

Table 4-2. Diagnostic Test Groups...........................................................................4-12

T ab le A-1. Motorola Computer Gr oup Documents..................................................A-1

Table A-2. Manufacturers’ Documents ...................................................................A-2

Table A-3. Related Specifications ...........................................................................A-5

Table B-1. Power Requirements for the MVME2100 .............................................B-1

Table B-2. MVME2100 Environmental Specifications ...........................................B-2

Table B-3. Thermally Significant Components .......................................................B-5

Table C-1. P2 Connector Pin Assignment ...............................................................C-1

Table C-2. PC•MIP P1/P2 Pin Assignments ............................................................C-3

Table C-3. PC•MIP Slot 2 User Defined I/O Connector P3

Pin Assignments .......................................................................................................C-5

Table C-4. PMC Connector J11/J12 Pin Assignments ............................................C-6

Table C-5. PMC User Defined I/O Connecto r J14

Pin Assignments .......................................................................................................C-8

Table C-6. PCI Expansion Connector Pin Assignments ........................................C-10

Table C-7. 10BaseT/100BaseTx Connector Pin Assignments ..............................C-13

Table C-8. Asynchronous Serial Connector Pin Assignments ..............................C-13

Table C-9. Two-Wire Serial Interface Header Pin Assignments ...........................C-14

Table D-1. Troubleshooting Problems .....................................................................D-1

xiii

About This Manual

The MVME2100 Single Board Computer Installation and Use provides
the information you will need to install and configure your MVME2100
Single Board Computer.
information and data applicable to the board.

As of the printing date of th is man ual , the MVME2100 i s ava il abl e in the
configurations shown below.

It provides specific preparation and installation

Model MPC

MVME2101-1 MPC8240

@200MHz

MVME2101-3

MVME2112-1 MPC8240

@250MHz

MVME2112-3

Memory

32MB SDRAM
5 MB Flash Memory

32MB SDRAM
5 MB Flash Memory

64MB SDRAM
9 MB Flash Memory

64MB SDRAM
9 MB Flash Memory

Handles

VME Scanbe

IEEE 1101

(Injector/Ejector)

VME Scanbe

IEEE 1101

(Injector/Ejector)

Related Products

Part Number Description

Primary PCI expansion, mates directly to the

PMCSPAN-001

PMCSPAN1-001 PMCSPAN-001 with original VME Scanbe front panel

PMCSPAN-010 Secondary PCI expansion; plugs directly into

PMCSPAN1-010 PMCSPAN-010 with original VME Scanbe front panel

MPMCxxxx Motorola’s family of PMC modules; ask your sales

MVME2100 providing slots for either two single-wide
or one double-wide IEEE P1386.1 compatible front
panel with injector/ejector handles.

and handles.

PMCSPAN-001 providing two additional PMC slots.

and handles.

representative for details.

xv

Summary of Changes

The following changes were made for the 2nd revision of this manual.

Date Doc. Rev Changes

07/2001 V2100A/IH2 A correction was made on page 1-5 to change the

explanation of the jumper settings for Flash Bank A
and B. Flash Bank B (0) is the factory setting.
Appendix B, Specifications, was also updated.
Other corrections were made throughout the
manual. This section titled "About this Manual"
was also added.

Overview of Contents

The following paragraphs briefly describe the contents of each chapter.

Chapter 1, Preparation and Installation, provides a description of the

MVME2100 and its main integrated PMC and PC•MIP boards. The
remainder of the chapter inc ludes an explanation of the installation
procedure, including preparation and jumper setting information.

Chapter 2, Operating Instructions, provides a description of the

operational functions of the MVME2100 including tips on applying
power, a description of the switch settings, the status indicators, standard
jumper settings, I/O expansion and PMCspan slots.

xvi

Chapter 3, Functional Description, provides an explanation of the

functional components on the MVME2100. T he chapter inc ludes a listing
of the MVME2100 features and a block diagram. The remainder of the
chapter includes specific descriptions of each functional element on the
board and a description of its functional characteristics.

Chapter 4, PPCBug Firmware, describes the PPCBug debugger and

diagnostics firmware including a listing of the initialization sequence, a
brief explanation of how to use PPCBug an d a description of the standard
list of debugger and diagnostic commands.

Chapter 5, Modifying the Environment, describes how to change certain

parameters of the MVME2100 board by using the CNFG and ENV
commands of the PPCBug firmware.

Appendix A, Related Documenta tion, provides a listing of other Mot orola

documents related to the MVME2100, as well as manufacturer’s
documents dealing with specif ic components on the boar d. It also provides
a section on related industry specifications.

Appendix B, Specifications, provides the standard specifications for the

MVME2100.

Appendix C, Connector Pin Assignments, provides the connector pin

assignments for all related connectors associated with the MVME2100.

Appendix D, Troubleshoo ting, provides a brie f explanation of the possible

resolutions for basic error conditions.

Comments and Suggestions

Motorola welcomes and appreciates your comments on its doc umentation.
We want to know what y ou think about our manuals and how we can make
them better. Mail comments to:

Motorola Computer Group
Reader Comments DW164
2900 S. Diablo Way
Tempe, Arizona 85282

You can also submit comments to the following e-mail address:

[e-mail]

In all your corres pondence , plea se li st your name, po siti on, and c ompan y.
Be sure to include the title and par t number of the manual and tell how you
used it. Then tell us your feelings about its strengths and weaknesses and
any recommendations for improvements.

xvii

Conventions Used in This Manual

The following typographical conventions are used in this document:

bold

is used for user inpu t that you t ype just as i t appears ; it is al so used for
commands, options and arguments to commands, and names of
programs, directories and files.

italic

is used for names of variables to which you assign values. Italic is also
used for comments in screen dis plays and examples, and to intr odu ce
new terms.

courier

is used for system output (for example, screen displays, reports),
examples, and system prompts.

<Enter>, <Return> or <CR>

<CR> represents the carriage return or Enter key.

CTRL

Terminology

A character precedes a data or address parameter to specify the numeric
format, as follows (if not specified, the format is hexadecimal):

An asterisk (*) f ollowing a signal name for signals th at are l evel significant
denotes that the signal is true or valid when the signal is low.

xviii

represents the Control key. Execute control characters by pr essing the
Ctrl key and the letter simultaneously, for example, Ctrl-d.

0x Specifies a hexadecimal number
% Specifies a binary number
& Specifies a decimal number

An asterisk (*) f ollowing a signal name for signals th at are e dge significant
denotes that the actions initiated by that signal occur on high to low
transition.

In this manual, assertion and negation are used to specify forcing a signal
to a particular stat e. In parti cular, a ssertion and asser t refe r to a signal tha t
is active or true; negation and negate indicate a signal that is inactive or
false. These terms ar e used independently of the vo ltage level (high or l ow)
that they represent.

Data and address sizes are defined as follows:

Byte 8 bits, numbered 0 through 7, with bit 0 being the least significant.
Half word 16 bits, numbered 0 through 15, with bit 0 being th e least significant.
Word 32 bits, numbered 0 through 31, with bit 0 being th e least significant.
Double word 64 bits, numbered 0 through 63, with bit 0 being the least significant.

xix

1Preparation and Installation

Introduction

This chapter provides general product information along with hardware
preparation, installation, and operating instructions for the MVME2100
Single Board Computer (SBC).

Note Unless otherwise specified, the designati on “MVME2100” refers

The MVME2100 SBC is installed in a standard VME chassis and uses
injector/ejector handles for easy installation and removal. A combination
of PCI mezzanine cards (PMC) and PC Mezza ine Industry Pack (PC•MIP)
I/O cards can be installed on the MVME2100. Additi onal ca pacit y can be
provided by adding primary and secondary PMCspan modules to the
MVME2100 SBC.

Instructions for installing the PMC and PC•MIP boards are included in this
chapter, as are instructions for installing the PMCspan modules and the
MVME2100 into a VME chassis.

1

to all models of the MVME2100-series single board computers.

The following list of equipment may be used in an MVME2100 system:

❏ PMCspan PCI expansion mezzanine module
❏ Type I or II PC•MIP cards
❏ Peripheral Component Inte rconnect (PCI ) Mezzanine Cards

(PMC)s

❏ VME system enclosure
❏ System console terminal
❏ Disk drives (and/or other I/O) and controllers
❏ Operating system (and/or application software)

The following subsections describe some of these interconnecting
modules.

1-1

1

Preparation and Installation

PMCspan Expansion Mezzanine

An optional PCI expansion mezzanine module or PMC carrier board,
PMCspan, provides the capability of adding two additional PMCs. Two
PMCspans can be stacked on an MVME2100, providing four additional
PMC slots, for a total of five slots including the one onboard the
MVME2100. The following table lists the PMCspan models that are
available for use with the MVME2100.

Table 1-1. PMCspan Models

Expansion Module D escript ion

PMCSPAN-001 Primary PCI expansion mezzanine module. Allows two PMC

modules for the MVME2100. Includes 32-bit PCI bridge.

PMCSPAN-010 Secondary PCI expansion mezzanine module. Allows two

additional PMC modules for the MVME2100. Does not include
32-bit PCI bridge; requires a PMCSPAN-001.

PCI Mezzanine Cards (PMCs)

The PMC slot on the MVME2100 is IEEE P1386.1 compliant. P2 I/O­based PMCs that follow the PMC committee recommendation for PCI I/O
when using the 5-row VME64 extension connector will be pin-out
compatible with the MVME2100.

PC•MIP Expansion

To maximize I/O expansion flexibili ty, the MVME2100 provides a

combination of Type I and Type II PC•MIP slot s for added capability. The
MVME2100 provides one Type I PC•MIP slot with rear I/O via the P2
connector and two Type II PC•MIP slots with front panel I/O. The two
Type II slots can accept either one double-wide or two single-wide
PC•MIP cards.

1-2 Computer Group Literature Center Web Site

VME System Enclosure

Your MVME2100 board must be installed in a VME sys te m chass is with
both P1 and P2 backplane connections. It requires a single slot, except
when PMCspan carrier boards are used. Allow one extra slot for each
PMCspan.

System Console Terminal

In normal operation, connection of a debug console terminal is required

only if you intend to use the MVME2100’s debug firmware, PPCbug,
interactively. An RJ45 connector is provided on the front panel of the
board for this purpose.

Introduction

1

http://www.motorola.com/computer/literature 1-3

1

Preparation and Installation

Unpacking the MVME2100 Hardware

Avoid touching areas of integrated circuitry; static discharge can damage

!

Caution

these circuits.

Note

Unpack the equipment from the shipping carton. Refer to the packing
list(s) and verify that all items are present. Save the packing material f or
storing and reshipping of equipment.

If the shipping carton is damaged upon receipt, request that the
carrier’s agent be present during the unpa cking and inspe ction of
the equipment.

Preparing the MVME2100 Hardware

To produce the desired configuration and ensure proper operation of the
board, it may be necessary to perform certain modifications before and
after installing it . The fol lowing parag raphs di scuss th e pre parat ion of the
MVME2100 hardware components prior to installing them into a chassis
and connecting them.

MVME2100 Configuration Settings

The MVME2100 provides software control over most options by setting
bits in contro l registers. A fter installing it in a system, you can modify its

configuration. For ad diti onal i nformat ion on t he boar d’s c ontrol regi sters ,
refer to the MVME2100 Single Board Compu ter Programme r’s Reference
Guide listed in Appendix

Some options, however, are not sof tware-programmabl e. Such options are
controlled thro ugh manual instal lation or removal of jumpers or additional
interface modules on the MVME2100.

Manually configured jumpers on the MVME2100 include:

❏ Memory usage (soldered or socketed Flash memory) (J9)
❏ System Control (J2)

1-4 Computer Group Literature Center Web Site

Preparing the MVME2100 Hardware

Setting Flash Memory Bank A/Bank B Header (J9) (Pins 1 and 2)

Bank A (soldered memory) consists of four 16-bit devices that are
populated with 8-Mbit flash devices (4MB). Jumper header J9 (pins 1 and

2) provides selection between the Bank A (Bank 1) or Bank B (Bank 0)
configuration (for PPCBug use only).

Bank B consists of 1MB of 8-bit Flash memory in two 32-pin PLCC 8-bit
sockets.

A jumper must be installed either between J9 pins 1 and 2 for Bank A, or
left off for Bank B (factory default).

1

21

Bank B Configuration

(factory default)

21

Bank A Configuration

Setting System Controller Selection Header (J2)

The MVME2100 is factory-configured in automatic system controller
mode (jumper is inst alled acr oss pins 2 and 3 of he ader J2). This means th at
the MVME2100 determines if it is the system controller at system power­up or reset by its pos ition on th e bus; if i t is in sl ot 1 on the VME sys tem, it
configures itself as the system controller.

Remove the jumper from J2 if you intend to operate the MVME2100 as
system controller in all cases.

Install the jumper across pins 1 and 2 to prevent the MVME2100 from
operating as the system controller under any circumstances.

J2

1
2

3

Automatic System Controller mode
(factory default)

System Controller Always Disable as

J2

1
2

3

J2

1
2

3

System Controller

http://www.motorola.com/computer/literature 1-5

1

Preparation and Installation

PMCs

For a discussion of any configurable it ems on the PMCs, refer to the user’s
manual for the particular PMCs.

PMCspan

You will need to use an additional slot in the VME chassis for each
PMCspan expansion module you plan to us e. Before installing a PMCspan
on the MVME2100, you must install t he selecte d PMCs on the PMCspan.
Refer to the PMCspan PMC Adapter Carrier Board Installation and Use
manual for instructions. Referenced in Appendix

System Console Terminal

Ensure that the appr opria te jum per(s ) are s et in t he c orrec t posit ion on t he
MVME2100 board. This is nece ssary when the PPCBug firmware is used.
Connect the terminal vi a a ca bl e to the RJ45 DEBUG connector. Refer t o
Appendix C for pin signal assignments. Set up the terminal as follows:

❏ Eight bits per character
❏ One stop bit per character
❏ Parity disabled (no parity)
❏ Baud rate = 9600 baud (default baud rate of the port at power-up);

after power-up, you can reconfigure the baud rate with PPCbug’s PF
command

1-6 Computer Group Literature Center Web Site

Installing the MVME2100 Hardware

Installing the MVME2100 Hardware

The following section discusses installing PMCs and PMCspan modules
onto the MVME2100, installin g the MVME2100 into a VME chassis, and
connecting an optional system console terminal.

1

TYPE I
IPC•MIP

SLOTS

TYPE II PC•MIP
SLOTS

J2

PMCspan
INTERFACE

PMC SLOTS

J9

Figure 1-1. MVME2100 Layout

http://www.motorola.com/computer/literature 1-7

1

Preparation and Installation

ESD Precautions

Use ESD

Wrist Strap

Motorola strongly recommends that you use an a ntistatic wrist stra p and a
conductive foam pad when installing or upgrading a system. Electronic
components, such as d isk dr ives, c omputer boards , and memor y modules ,
can be extremely sensitive to electrostatic discharge (ESD). After
removing the component fr om th e system or its protectiv e wrapper, place
the component on a groun ded and st atic- free surfac e (and, i n the case of a
board, component side up). Do not slide the component over any surface.

If an ESD station is not available, you can avoid damage resulting from
ESD by wearing an antistatic wrist strap (available at electronics stores)
that is attached to an active electrical ground. Note that a system chassis
may not be grounded if it is unplugged.

PMCs & PC•MIPs

PMC modules and PC•MIP cards mount on top of the MVME2100 SBC.
Perform the following steps to install a PMC module and/or a PC•MIP card
on your MVME2100.

Dangerous voltages, capable of causing death, are present in
this equipment. Use extreme caution when handling, testing,

Warning

and adjusting.
Inserting or removin g modules with power applied may re sult

in damage to module components .

Avoid touching areas of integrated circuitry; static discharge
can damage these circuits.

Caution

Note This procedure assumes that you h ave read the user’s manual

that came with your PMCs.

1. Attach an ESD strap to your wri st. Att ach the o ther en d of the ESD
strap to the chassis as a ground. The ESD strap must be secured to
your wrist and to ground throughout the procedure.

1-8 Computer Group Literature Center Web Site

Installing the MVME2100 Hardware

2. Perform an operating system shutdown. Turn the AC or DC power
off and remove the AC cord or DC power lines from the system.
Remove chassis or system cover(s) as necessary for access to the
VME modules.

3. If the MVME2100 has alread y been installed in a VMEbus card slot,
carefully remove it as shown in the figure below and place it with
connectors P1 and P2 facing you.

1

Figure 1-2. MVME2100 Installation and Removal From a VMEbus Chassis

4. Remove the filler plate( s) fro m the fr ont panel of the MVME2100.

If installing both PMC and PC•MIP(s), remove both filler plates.

http://www.motorola.com/computer/literature 1-9

1

Preparation and Installation

5. If installing a PMC module, position the module’s mating

connectors on top of the MVME2100’s mating connectors
(J11/J12/J14), o r if installing a PC•MIP, position the card’s mating
connectors on top of the MVME2100’s Type II PC•MIP con nectors
(P41/P42 or P31/P32 for Type II; or P21/P22/P23 for Type I PC­MIP).

Note As a reminder, Type I PC-MIP cards without I/O can also be

installed on the MVME2100’s Type II PC-MIP connectors.

Figure 1-3. Typical Single-width PMC Module Placement on an MVME2100

1-10 Computer Group Literature Center Web Site

Installing the MVME2100 Hardware

1

Figure 1-4. Typical Type II PC•MIP Placement on an MVME2100

6. Insert the appropriate number of Phillips head screws (typically 2)

through the holes of the PMC module or PC•MIP card(s), into the
mating standoffs on the MVME2100 and tighten the screws.

Primary PMCspan

To install a PMCspan-001 PCI expansion module on your MVME2100,
refer to the PM Cspan PMC Adapter Carrier Board Installation and Use
manual, listed in Related Documentation on page A-1, refer to Figure 1-5

on page 1-13, and perform the following steps:

Dangerous voltages, capable of causing death, are present in
this equipment. Use extreme caution when handling, testing,

Warning

http://www.motorola.com/computer/literature 1-11

and adjusting.

1

Preparation and Installation

Inserting or removin g modules with power applied may re sult
in damage to module components .

Avoid touching areas of integrated circuitry; static discharge
can damage these circuits.

Caution

Note This procedure assumes that you h ave read the user’s manual

that was furnished with the PMCspan, and that you have
installed the s elected PMCs on the PMCs pan according to the
instructions given in the PMCspan and PMC manuals.

1. Attach an ESD strap to your wri st. Att ach the o ther en d of the ESD
strap to the chassis as a ground. The ESD strap must be secured to
your wrist and to ground while you are performing the installation
procedure.

2. Perform an operating system shutdown. Turn the AC or DC power
off and remove the AC cord or DC power lines from the system.
Remove chassis or system cover(s) as necessary for access to the
VME module card cage.

3. If the MVME2100 has already been installed in the chassis,
carefully remove i t fr om t he VMEbus card slot and position it with
connectors P1 and P2 facing you.

1-12 Computer Group Literature Center Web Site

PMCspan

Installing the MVME2100 Hardware

1

MVME2100

2081 9708

Figure 1-5. PMCspan-001 Installation on an MVME2100

http://www.motorola.com/computer/literature 1-13

1

Preparation and Installation

4. Attach the four standoffs to the MVME2100 module. For each
standoff:

– Insert the threaded end into the standoff hole at each corner of

the VME processor module.
– Thread the locking nuts onto the standoff tips.
– Tighten the nuts with a box- end wrenc h or a pair of needl e nose

pliers.

5. Place the PMCspan on top of the MVME21 00. Align the mount ing
holes to the stan doffs i n each co rner, and align PM Cspan conn ector
P4 with MVME2100 connector J4.

6. Gently press the PMCspan an d MVME210 0 tog et her , ma kin g sur e
that P4 is fully seated in J4.

7. Insert the four short Phi llips s crews thr ough the hol es at the corn ers
of the PMCspan and into the st andoffs on th e MVME2100. Tighten
the screws.

Secondary

1-14 Computer Group Literature Center Web Site

PMCspan

The PMCspan-010 PCI expansion module mounts on top of a PMCspan­001 PCI expansion module. To install a PMCspan-010 on your
MVME2100, refer to Figure 1-6 on page 1-15 and perform the following
steps:

Note

This procedure assumes that you have read the user’s manual that
was furnished with the PMCspan, and that you have installed the
selected PMCs on the PMCspan according to the instructions given
in the PMCspan and PM C man ua l s.

1. Attach an ESD strap to your wri st. Att ach the o ther en d of the ESD
strap to the chassis as a ground. The ESD strap must be secured to
your wrist and to ground while you are performing the installation
procedure.

2. Perform an operating system shutdown. Turn the AC or DC power
off and remove the AC cord or DC power lines from the system.

Installing the MVME2100 Hardware

P3

1

J3

2065 9708

Figure 1-6. PMCspan-010 Installation on a PMCspan-001/MVME2100

http://www.motorola.com/computer/literature 1-15

1

Preparation and Installation

Remove chassis or system cover(s) as necessary for access to the
VME module card cage.

Dangerous voltages, capable of causing death, are present in
this equipment. Use extreme caution when handling, testing,

Warning

Caution

and adjusting.
Inserting or removin g modules with power applied may re sult

in damage to module components .

Avoid touching areas of integrated circuitry; static discharge
can damage these circuits.

3. If the Primary PMC Carrier Module/MVME2100 assembly is
already installed in the VME chassis, carefully remove the two­board assembly fr om the VMEbus card sl ots and positi on it with the
P1 and P2 connectors facing you.

4. Remove th e four short Phillips head screws from the standoffs in
each corner of the primary PCI expansion module, PMCspan-001.

5. Attach the four standoffs to the PMCspan-001.

6. Place the PMCspan-010 on top of the PMCspan-001. Align the
mounting holes to the standoffs in each corner, and align
PMCspan-010 connector P3 with PMCspan-001 connector J3.

7. Gently press the two PMCspan modules togethe r, making sure th at
P3 is fully seated in J3.

8. Insert the four short Phi llips s crews thr ough the hol es at the corn ers
of PMCspan-010 and into the standoffs on the primary PMCspan-

001. Tighten the screws.

Note The screws have two different head diameters. Use the screws

with the smaller heads on the standoffs next to VMEbus
connectors P1 and P2.

1-16 Computer Group Literature Center Web Site

MVME2100 System Installation

Before installing the MVME2100 in to you r VME ch ass is, ensure that the
jumpers on J2 and J9 are confi gured properly. This proce dure assumes that
you have already instal led the PMCspan(s) if desired, and a ny PMCs tha t
you have selected.

Proceed as follows to install the MVME2100 in the VME chassis:

Dangerous voltages, capable of causing death, are present in

!

Warning

!

Caution

this equipment. Use extreme caution when handling, testing,
and adjusting.

Inserting or removin g modules with power app lied may result
in damage to module components .

Avoid touching areas of integrated circuitry; static discharge can damage
these circuits

1. Attach an ESD strap to your wri st. Att ach the o ther en d of the ESD
strap to the chassis as a ground. The ESD strap must be secured to
your wrist and to ground throughout the procedure.

Installing the MVME2100 Hardware

1

2. Perform an operating system shutdown:
a. Turn the AC or DC power off and remove the AC cord or DC

power lines from the system.

b. Remove cha ssis or system cover(s) as necessary for access to t he

VMEmodules.

3. Remove the filler panel from the card slot where you are going to
install the MVME2100. If you have install ed one or more PMCspan
PCI expansion modules onto your MVME2100, you will need to
remove filler panels from one additional card slot for each
PMCspan, above the card slot for the MVME2100.

– If you intend to use the MVME2100 as the sy stem controller, it

must occupy the left-most card slot (slot 1). The system
controller must be in slot 1 to correctly initiate the bus-grant
daisy-chain and to ensure proper operation of the IACK daisy­chain driver.

http://www.motorola.com/computer/literature 1-17

1

Preparation and Installation

– If you do not intend to use the MVME2100 as the system

controller, it can occupy any unused card slot.

4. Slide the MVME2100 (and PMCspans if used) into the selected
card slot(s). Be sure the module or modules is/are seated properly in
the P1 and P2 connectors on t he backpla ne. Do not damage o r bend
connector pins.

5. Secure the MVME2100 (and PMCspans if us ed) in the chass is with
the screws provided, making good contact with the transverse
mounting rails to minimize RF emissions.

Note

Some VME backplanes (e.g., those used in Motorola “Modular
Chassis” systems) ha ve a n aut o - jumpe ri ng feature for automa ti c
propagation of the IACK and BG signals. Step 6 does not apply
to such backplane designs.

6. On the chassis backplane, remove the
(IACK) and

BUS GRANT (BG) jumpers from the header for t he card

INTERRUPT ACKNOWLEDGE

slot occupied by the MVME2100.

7. If you intend to use PPCBug interactivel y, connect the terminal that
is to be used as the PPCBug system console to the

DEBUG port on

the front panel of the MVME2100.

Note In normal operation the host CPU controls MVME2100

operation via the VMEbus Universe registers.

8. Replace the chassis or system cover(s), cable peripherals to the
panel connectors as a ppr opriate, reconnect t he s yst em to the AC or
DC power source, and turn the equipment power on.

9. The MVME2100 green
confidence tests is run, and the debugger prompt

RUN LED indicates activity as a set of

PPC5-Bug>

appears on the system console.

1-18 Computer Group Literature Center Web Site

Installation Considerations

The MVME2100 draws power from the VMEbus backplane connectors P1
and P2. Connector P2 is also used for the upper 16 bits of data in 32-bit
transfers, and for the upper 8 address lines in extended addressing mode.
The MVME2100 may not function properly if the main board is not
properly connected to connectors P1 and P2 on the VMEbus backplane.

Regardless of whether the MVME2100 operates as a VMEbus master or
as a VMEbus slave, it is configured for 32 bits of address and 32 bits of
data (A32/D32). However, it handles A16 or A24 devices in the
appropriate address r ang es. D8 an d/o r D16 de vic es i n the system must be
handled by the processor software.

If the MVME2100 tries to access off-board resources that do not respond
to its cycle, and the MVME2100 is not the system controller, and the
system does not have a global bus time-out, the MVME2100 waits
indefinately for t he VMEbus cycle to comple te. This will cause t he system
to lock up. There is o nly one situa tion i n which the s ystem mig ht lac k thi s
global bus time-out : when the MVME2100 is not the system c ontroller and
there is no global bus time-out elsewhere in the system.

Installing the MVME2100 Hardware

1

Multiple MVME2100 boards may be installed in a single VME chassis.
Each must have a unique Universe address. Other MPUs on the VMEbus
can interrupt, disable, communicate with, and determine the operational
status of the processor(s). One register of the Universe set includes four
bits that funct ion as locati on monitors to allow o ne MVME2100 process or
to broadcast a signal to any other MVME2100 processor. All eight
registers are accessible from any local processor as well as from the
VMEbus.

http://www.motorola.com/computer/literature 1-19

2Operating Instructions

Introduction

This chapter provides operating instructions for the MVME2100 Single
Board Computer. This inc ludes information about p owering up the system,
and functionality of the switches, status indicators, and I/O ports on the
front panel of the board.

Applying Power

After you have verified that all necessary hardware preparation has been
done, that all connections have been made correctly, and that the
installation is complete, you can power up the system. The MPU,
hardware, and firm ware initializa tion process is perf ormed by the PPCBug
firmware power-up or system reset. The fi rmware initializes t he devices on
the MVME2100 module in preparation for booting the operating system.

2

The firmware is shipped from the factory with an appropriate set of
defaults. In most cases there is no need to modify the firmware
configuration before you boot the operating system. Refer to Chapter 5,

Modifying the Environment for further information about modifying

defaults.
The following flowchart shows the basic initialization process that takes

place during MVME2100 system start-ups.
For further information on PPCBug, refer to the following:

❏ Chapter 4, PPCBug Firmware
❏ Chapter 5, Modifying the Environment
❏ Appendix A, Related Documentation
❏ Appendix D, Troubleshooting

2-1

Operating Instructions

2

STARTUP

INITIALIZATION

POST

BOOTING

MONITOR

Power-up/reset initialization

Initialize devices on the MVME2100

Power-On Self-Test diagnostics

Firmware configured boot mechanism,
if so configured. Default is no boot.

Interactive, command-driven on-line PowerPC
debugger, when terminal connected

Figure 2-1. System Boot-up Sequence

2-2 Computer Group Literature Center Web Site

MVME2100 User Interface Devices

MVME2100 User Interface Devices

The following subsection s describe various sw itches, status indi cators and
connectors that a user should be familiar with prior to using the
MVME2100. These devices include MVME2100 switches and their
settings, status indicators, the MVME2100 Debug port, the jumper
settings, the MVME2100 I/O Expansion card op eni ngs an d t he PMCspan
openings. Front pane ls are depic ted on severa l of the foll owing pages as an
aid in identifying the location of status ind icators and switche s, and for the
purpose of showing t he difference betwee n the standard MVME2100 front
panel and the PMCspan front panel.

Switches

There are two switches (ABT and RST) and three LED (light-emitting
diode) status indica tors (
panel.

ABT (S1)

When activated by firmware, the Abort switch,
interrupt signal from the base board to the processor at a user­programmable level. The interrupt is normally used to abort program
execution and return control to the debugger firmware located in the
MVME2100 Flash memory.

BFL, SYS, RUN) located on the MVME2100 front

ABT, can generate an

2

The interrupt signal reaches the processor module via serial interrupt 14.
The signal is al so avail able fr om the general p urpose I/O port, whic h allo w s
software to poll the Abort switch after receiving serial interrupt 14 and verify that it
has been pressed.

The interrupter connect ed to the
filtered to remove switch bounce.

http://www.motorola.com/computer/literature 2-3

ABT switch is an edge-sensitive circuit,

Operating Instructions

2

RST (S2)

The Reset switch,

RST, resets all onboard devices and cau ses HRESET* to

be asserted in the MPC8240. It also drives a

SYSRESET* signal if the

MVME2100 VME processor module is the system controller. The Status
Indicators

There are three LED ( light-emit ting diode) s tatus indic ators locat ed on the
MVME2100 front panel:

BFL, SYS, and RUN. Refer to Figure 1-1 on page

1-7.

BFL (DS1)

The yellow BFL LED indicates b oar d fai lure; this i ndicat or is ill umina ted
during a hard reset. The LED can be turned on or off by writing to Bit 0
BD_FAIL in the System Status Register 2.

SYS (DS2)

The green

SYS LED indicates CPU activity; when illuminated, this

indicator signifies that the MVME2100 is functioning as the VMEbus
System Con troller.

RUN (DS3)

The green

PCI

RUN LED illuminates when either ROM/FLASH, SDRAM, or

accesses are occurring.

10/100 BASE T Port

The RJ45 port on the front p ane l of the MVME2100 labeled 10/100 BASE

T

supplies the Ethernet LAN 10BaseT/100BaseTx interface.

DEBUG Port

The RJ45 port labeled DEBUG on the front panel of the MVME2100
supplies the MVME2100 serial communications interface, implemented
via a TL16C550 Universal Asynchronous Receiver/Transmitter (UART)
controller chip manufactured by Texas Instruments. It is asynchronous
only. For configuration information, refer to the section Asynchronous

Serial Port found in Chapter 3, Functional Description.

2-4 Computer Group Literature Center Web Site

MVME2100 User Interface Devices

Universe ASIC includes both a global and a local reset driver.
When the Universe operates as the VMEbus system controller, the reset

driver provides a global system reset by asserting the VMEbus signal
SYSRESET*.

A SYSRESET* signal may be generated by the RESET switch, a power­up reset, a watchdog timeout, or by a control bit in the Miscellaneous
Control Register (MISC_CTL) in the Universe ASIC. SYSRESET*
remains asserted for at least 200 ms, as required by the VMEbus
specification.

DEBUG port may be used for connect ing a terminal to the MVME2 100

The
to serve as the firmware c onsole for th e factory installed debugger,
PPCBug. The port is configured as follows:

❏ 8 bits per character
❏ 1 stop bit per character
❏ Parity disabled (no parity)
❏ Baud rate = 9600 baud (default baud rate at power-up)

After power-up, the baud rate of the

DEBUG port can be reconfigured by

using the debugger’s Port Format (PF) command . Refer to Chapters 5 and
6 for information about the PPCBug.

2

http://www.motorola.com/computer/literature 2-5

Operating Instructions

2

Jumper Settings

The following table describes the MVME2100 jumper configuration.

Table 2-1. Jumper Switches and Settings

Jumper Description Setting Default

J1 Factory T est Header Reserved N/A
J2 VMEbus System

Controller
Functionality Select

J6 Factory T est Header

(I2C Signals)

J7 Programming Header

(ISPLI)
J8 RiscWatch JTAG Reserved N/A
J9 Software Readable

Header (Support for

Processor Emulation)

Pins 1 & 2 For

PPCBug use only.

Pins 1 & 2 Shorted: Disables the System
Controller Function

Pins 2 & 3 Shorted: Enables Auto-Sence
Function

No Shunt on Pins Forces the System
Controller On

Reserved N/A

Reserved N/A

Pins 1 & 2:
ON = Use Soldered On Flash Memory

Devices
OFF = Use Memory in Sockets U1, U8, U13,

U15
Note: PPCBug uses Bit 7 while booting to

determine whether to continue executing
from socketed Flash or jump to soldered-on
Flash.

Pins 3 - 16 are User Definable
Pins 3 and 4 = Bit 1,
Pins 5 and 6 = Bit 2,
Pins 7 and 8 = Bit 3
Pins 9 and 10 = Bit 4,
Pins 11 and 12 = Bit 0,
Pins 13 and 14 = Bit 6,
Pins 15 and 16 = Bit 7
Refer to the Configuration Header Register

section in the V2100 Programmer’s Guide.

.

No

Shunt on

Pins

Pins 1&2

OFF

2-6 Computer Group Literature Center Web Site

MVME2100 User Interface Devices

I/O Expansion Cards

Two openings are located on the fr ont panel of the MVME2100 to provi de
I/O expansion by allowi ng access t o a PCI Mezzan ine Card (PMC) or two

Type II PC•MIP cards. Ref er t o Appendix C, Connector Pin Assi gnmen ts
for additional information on pin assignments.

Do not attempt to instal l any PMC boards without performing

!

Warning

PCI Mezzanine Card

TYPE II PC-MIP

an operating system shutdown and following the procedures
given in the user’s manual for the particular PMC.

The right-most (lower) opening labeled
MVME2100 front panel provides front panel I/O access to a PMC that is
connected to the 64-pin conne ctors J11, J12, and J1 4 on the MVME2100.
Connector J14 allows rear panel P2 I/O. Refer to Appen dix C, Connector

Pin Assignmentsfor additional info rmation on pin assignments.

The left-most opening labeled
panel provides front panel I/O access to two Type II PC•MIP cards
connected to the 64-pi n connector s P31/P32, and P41/P42 resp ectivel y on
the MVME2100. Refer to Appendix C, Connector Pin Assignments for
additional information on pin assignments.

2

PCI MEZZANINE CARD on the

TYPE II PC-MIP on the MVME2100 front

http://www.motorola.com/computer/literature 2-7

3Functional Description

Introduction

This chapter prov ides addi tional pr oduct informati on along wi th a gene ral
functional description for the MVME2100 single board computer.

The MVME2100 is a VME based single-slot sing le board computer ba sed
on the MPC8240 Integrated Processor.

Key features of the MVME2100 include one 32-bit PMC expansion slot,

one Type I and two Type II PC•MIP expansion slots, 32 or 64MB of
synchronous DRAM memory, 1MB boo t Flash ROM, 4 or 8MB expansion
Flash ROM, one 10BaseT/100BaseTx Ethernet port, and one front panel
accessible asynchronous serial port.

The following table lists the key features of the MVME2100.

3

Table 3-1. MVME2100 Features

Feature Description

Processor • MPC8240

• Bus clock frequencies of 66.67/83.33 MHz

Flash Memory

System Memory • 32 or 64MB Synchronous DRAM
LAN • DEC21143 10BaseT/100BaseTx Ethernet

Interrupt Controller • P

DMA • Two independent DMA channels
Timers • Four Independent T i mers

• Sockets for 1MB (8-bit) plus 4MB or 8MB (64-bit)
of expansion Flash memory

Controller

• LXT970 Fast Ethernet Transceiver

owerPC Embedded Programmable Interrupt Con-

troller (EPIC)

3-1

Functional Descr iption

I2C •Integrated I2C port with full master support

Table 3-1. MVME2100 Features (Continued)

3

I2O•I
NVRAM • 8KB (MK48T59Y)
RTC &

Watchdog Timer
Serial Interface • One 16550-compatible async serial port
PCI Mezzanine Card • One 32-bit PMC slot

PC•MIP • One 32-bit Type I PC•MIP slots (MVME2300

PCI Expansion • Genesis II PCI expansion compatibility
Miscellaneous • RESET switch

Form Factor • Standard 6U VME

O compliant messaging Interface

2

• MK48T59 device

• Front panel I/O

• MVME2300 compatible P2 I/O

compatible P2 I/O)

• Two 32-bit Type II PC•MIP slots (front panel

I/O)

•ABORT switch

• Front panel status indicators

3-2 Computer Group Literature Center Web Site

Introduction

The block diagram in Figure 3-1 illustrates the architecture of the
MVME2100 Single Board Computer.

RTC/NVRAM

M48T59

Debug Connector

Clock

Generator

DRAM

32/64MB

Flash

5/9MB

SCC

16550

RJ45

3

PCI
Expansion
Connector

MPC8240

CPU

ETHERNET

DEC21143

PC•MIP
TYPE II

Slot 2

PC•MIP
TYPE II

Slot 1

Local Bus

PMC

Slot

32-bit PCI

PC•MIP

TYPE I

Slot 2

LXT970

PHY

EEPROM

Front Panel

RJ45

I/OI/OI/O

P2

Universe II

VME

P1

Figure 3-1. MVME2100 Block Diagram

http://www.motorola.com/computer/literature 3-3

Functional Descr iption

Functional Description

This section provides a description of the primary components on the

3

Processor

PCI Host Bridge/Memory Controller

MVME2100 and in some cases the corresponding functions associated
with those components.

The MVME2100 is designed to support the MPC8 240 pr oces sor in a 352
pin TBGA package. It is also designed to support memory bus speeds of
50, 60, 66.67, and 83.33 MHz.

The MPC8240 contains an integrated PCI host bridge and memory
controller which provides the bridge function between the internal
MPC60x bus and the external PCI local bus.

The processor supports a 32-bit PCI interface that is compliant with the
PCI Local Bus Specification, Revision 2.1. Additional features of the
processor include:

❏ PReP or CHRP compatible memory maps
❏ DRAM control/refresh
❏ 3.3/5.0V compatible I/O
❏ power management support
❏ Boot ROM interface

PCI Bus Arbitration

PCI arbitration for the MVME2100 board is provided by the integrated
PCI arbiter internal to the processor in conjunction with an external sub­arbiter. The processor provides support for itself and up to five external
PCI masters.

3-4 Computer Group Literature Center Web Site

Since the MVME2100 could have as many as seven poten tial PCI masters
in addition to the processor, an onboard sub-arbiter is provided. The sub-

arbiter is designed t o multiple x the PMC slot and t hree PC•MIP slots ont o
one set of the processor’s PCI bus request/grant pins.

PCI Local Bus

In addition to the processor, there may be as many as 7 additional PCI
devices located on the local PCI bus. The potential PCI devices on the
board are: one PMC board, one PC•MIP Type I board, t wo PC•MIP Type
II boards, one DEC21143 Ethernet controller, one PCI-VMEbus bridge,
and one DEC21150 PCI-to-PCI Bridge.

Interrupt Controller

The MVME2100 uses the Embedded Programmable Interrupt Controller
(EPIC) integrated into the processor to manage locally generated
interrupts. The interrupt controller will operate in the serial interrupt mode.

Currently defined external interrupting devices include:

Functional Description

3

❏ DEC21143 Ethernet controller
❏ One PC•MIP Type I Expansion slot
❏ Two PC•MIP Type II Expansion slots
❏ Universe II VME-PCI bridge
❏ 16550 UART
❏ Watchdog timer
❏ Front panel Abort switch
❏ Four PCI expansion interrupts (INTA* - INTD*)

For additional inf orm ation on th e oper ation of t he pro ces sor’s EPI C, ref er
to the MPC8240 User’s Manual, listed in Appendix A, Related

Documentation.

http://www.motorola.com/computer/literature 3-5

Functional Descr iption

Two-Wire Serial Interface

A two-wire serial interface for the MVME2100 is provided by an I2C

3

compatible serial controller integrated into the proces sor’s peripheral
device. The processo r’s s erial con trol ler is used by the sys te m softwar e to
read the contents of the configuration EEPROM contained on the board.

I2O Message Unit

I2O compliant messaging for the MVME2100 is provided by an I2O
compliant messaging unit integrated into the processor’s peripheral
device. The processor’s message unit can operate with either generic
messages and door bell registers, or as an I

O compliant interface.

2

Direct Memory Access (DMA)

The MVME2100 provides DMA capability through a two-channel DMA
controller integrated into the processor’s peripheral device. Each DMA
channel is capable of performing local memory to local memory, PCI
memory to local memory , local memo ry to PCI memory and PCI memory
to PCI memory data transfers.

Both DMA channels can be accessed by the local CPU as well as external PCI
bus masters an d su p po rt un al igned transfers, da t a c haining, and scat t e r ga t he r .

Timers

Timing functions for the MVME2100 are provided by four independent
31-bit timers integrated into the processor . The four timers are clocked at
1/8 of the proces sor clock ra te. Each ti mer contains four regist ers enablin g
the system software to set the count values, enable or disable the timer,
enable or disable interrupt generation, set the interrupt priority level, and
to generate an interrupt ve ctor.

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System Clock Generator

The system clock generator function generates and distributes all of the
clocks required for normal system operation. The clock generator for the
processor, memory, and PCI devices is designed in such a manner as to
maintain the strict e dge to edge ji tter and low clock to cloc k skew required
by these devices.

Additional clocks that may be required should be generated near the
individual devices requiring clocks to minimize onboard trace lengths.

Flash Memory

The MVME2100 contains two banks of Flash memory accessed via the
integrated memory controller contained within the processor. Bank B
consists of two 32-pin PLCC sockets that can be populated with up to
1024KB of Flash memory, and resides at address 0xFFF00000, and is
restricted to 8 bits in width.

Bank A may be populated with four 512Kx16 Flash de vices to obtain 4MB
of 64-bit wide expansion Flash memory or four 1Mx16 Flash devices to
obtain 8MB of 64-bit wide Flash memory. The expansion Flash memory
starts at address 0xFF000000.

Functional Description

3

System Memory

System memory for the MVME2100 is provided by 2 banks of
synchronous DRAM. Each ba nk cons ists of f ive 4 Mx16 SDRAM devi ces
providing a 32MB bank organized in a 4Mx72 conf igura tion. Thi s allows
memory configurations of 32 or 64MB that can be s upported by the board.

During syst em initializati on, the firmware determines the presence, and
configuration o f each memory ban k installed by r eading the con tents of the
serial presence detect ROM located on the board. The system firmware
then initializes the MPC8240 memory controller for proper operation
based on the contents of the serial presence detection ROM.

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Functional Descr iption

Ethernet Interface

The MVME2100 provides a 10BaseT/100BaseTx Ethernet transceiver

3

interface using a DEC21143 Ethernet controller and a LXT970 Fast
Ethernet transceiver. The Ethernet interface is accessed via an industry
standard front panel mounted RJ45 connector.

The DEC21143 will be assi gned an Ether net Station Address. The addr ess
will be 0x0001AFxxxxx wher e xxxxx is the unique number assi gned to the
Ethernet con troller.

The Ethernet statio n address is display ed on a label affixed t o the board. In
addition, the Ethernet address is stored in the configuration ROM
interfaced to the Ethernet controller.

Asynchronous Serial Port

The MVME2100 uses a TL16C550 or compatible Universal
Asynchronous Receiver/Transmitter (UART) with a 1.8432 MHz input
clock to provide an asynchronous serial interface. EIA232 drivers and
receivers reside onboard and are routed to an industry standard RJ45
connector accessible from the front panel.

TL16C550

DCD#

RTS#

SOUT

SIN

CTS#

DTR#

DSR#

RI#

+5V

DCD

RTS

TXD

RXD

CTS

DTR

GND

1

2

4

5

7

8

3
6

Figure 3-2. Asynchronous Serial Port Connections

3-8 Computer Group Literature Center Web Site

VMEbus Interface

The VMEbus interface for the MVME2100 i s provided by the Unive rse II
ASIC. Refer to the Universe II User’s Manual, listed in Appendix A

Related Documentation for additional information.

PCI Mezzanine Card Slot

The MVME2100 provides one PMC slot. Three EIA E700 AAAB
connectors interface to a single 32-bit IEEE P1386.1 PMC to add any
desirable function.

PMC slot support specifications are:

❏ Mezzanine Type: PMC = PCI Mezzanine Card
❏ Mezzanine Size: S1B = Single width & standard depth (75mm x

150mm) with front panel

❏ PMC Connectors: J11, J12, J14 (32-Bit PCI with front panel and

user defined I/O)

Functional Description

3

❏ Signalling Voltage: V

= 5.0V

io

PC•MIP Type I Mezzanine Card Slots

The MVME2100 provides one dedicated Type I PC•MIP slot.
User defined I/O, as defined in the PC•MIP specification, is provided for

the Type I PC•MIP card slot via the VMEbus P2 connector.

PC•MIP Type II Mezzanine Card Slots

The MVME2100 provides two Type II PC•MIP slot s wi th ac ces s to front
panel I/O. These slots accommodate either one double width Type II
PC•MIP board or two single width Type II PC•MIP boards.

Note User defined I/O using P3 of the Type II PC•MIP boards is

not supported by the board.

http://www.motorola.com/computer/literature 3-9

Functional Descr iption

PCI/PMC Expansion Capability

The MVME2100 provides additional PCI capability through the use of a

3

114-pin Mictor connector that is compatible with the Genesis II series of
VMEbus processor boards. By using exi sting PMCspan carrier boards, u p
to four additional PMC boards can be used.

Real-Time Clock & NVRAM

The ST-Thomson M48T59 is used by th e MVME2100 to provide 8KB of
non-volatile static RAM and a real-time clock. It consists of two parts:

❏ A 28-pin 330mil SO device which cont ains the RTC, t he oscillato r,

8KB of SRAM, and gold-plated sockets fo r the SNAPHAT batt ery.

❏ A SNAPHAT battery that houses the crystal and the battery.

Note Refer to the MK48T59 data sheets listed in Appendix A

Related Documentation for programming information.

3-10 Computer Group Literature Center Web Site

4PPCBug Firmware

PPCBug Overview

The PPCBug firmware is the layer of so ftware just a bove the hardware.
The firmware provides the proper initialization for the devices on the
MVME2100 module upon power-up or reset.

This chapter desc ribes the basics o f PPCBug and its architecture, des cribes
the monitor (interactive command portion of the firmware) in detail, and
gives informatio n on ac tua lly us ing t he P PCBug de bugger and th e s pecial
commands . A complete list of PPCBug commands ap pears at the end of
the chapter.

For full user information about PPCBug, refer to the PPCBug Firmware
Package User’s Manual and the PPCBug Diagnostics Manual, listed in
Appendix A, Related Documentation.

4

PPCBug Basics

The PowerPC debug firmware (known as the “PPCBug”) is a powerful
evaluation and debugging tool for systems built around the Motorola
PowerPC microcomputers. Facilities are available for loading and
executing user programs under complete operator control for system
evaluation. The PPCBug provides a high degree of functionality, user
friendliness, portabilit y, and ease of maintenance.

4-1

PPCBug Firmware

PPCBug includes commands for:

❏ Display and modification of memory
❏ Breakpoint and tracing capabilities
❏ A powerful assembler and disassembler useful for patching

4

programs

❏ A self-test at power-up feature which verifies the integrity of the

system

PPCBug consists of three parts:

❏ A command-driven, user-interactive software debugger, described

in the PPCBug Firmware Package User’s Manual. It is hereafter

referred to as “the debugger” or “PPCBug.”

❏ A command-driven diagnostics package for the MVME2100

hardware, hereafter referred to as “the diagnostics.” The diagn ostics
package is described in the PPCBug Diagnostics Manual.

❏ A user interface or debug/diagnostics monitor that accepts

commands from the system console terminal.

When using PPCBug, you operate out of e it her the debugger directory or
the diagnostic directory.

❏ If you are in the debugger directory, the debugger prompt

PPC5-Bug> is displayed and you h ave all of the de bugger commands

at your disposal.

❏ If you are in the diagnostic directory, the diagnostic prompt

PPC5-Diag> is displayed and you have all of the diagnostic

commands at your disposal as well as all of the debugger
commands.

Because PPCBug is command-driv en, it performs it s various operatio ns in
response to user commands entered at the keyboard. When you enter a
command, PPCBug executes the command and the prompt reappears.
However, if you enter a command that causes executi on of user target code
(e.g., GO), then control may or may not return to PPCBug, depending on
the outcome of the user program.

4-2 Computer Group Literature Center Web Site

Memory Requirements

PPCBug requires a maximum of 768KB of read/write memory. The
debugger allocates this space from the top of memory. For example, a
system containing 64MB (0x04000000) of read/write memory will place
the PPCBug memory page at locations 0x03F40000 to 0x03FFFFFF.

PPCBug Implementation

PPCBug is written largely in the C programming language, providing
benefits of portability and maintainability. Where necessary, assembly
language has been used in the form of separately compiled program
modules containing only assembler code.

Physically, PPCBug is contained in two socketed 32-pin PLCC Flash
devices that together provide 1MB of storage. The executable code is
checksummed at every power-on or reset firmware entry. The result
(which includes a preca lculate d checksum cont ained in t he flash devic es),
is verified against the expected checksum.

MPU, Hardware, and Firmware Initialization

4

MPU, Hardware, and Firmware Initialization

The debugger performs the MPU, hardware, and firmware initialization
process. This process occurs each time the MVME2100 i s reset or powered
up. The steps below are a high-level outline; not all of the detailed steps
are listed.

1. Sets MPU.MSR to known value.

2. Invalidates the MPU’s data/instruction caches.

3. Clears all segment registers of the MPU.

4. Clears all block address translation registers of the MPU.

5. Initializes the MPU-bus-to-PCI-bus bridge device.

6. Initializes the PCI-bus-to-ISA-bus bridge device.

7. Calculates the external bus clock speed of the MPU.

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PPCBug Firmware

8. Delays for 750 milliseconds.

9. Determines the CPU base board type.

10. Sizes the local read/write memory (i.e., DRAM).

11. Initializes the read/write memory controller. Sets base address of
memory to 0x00000000.

4

12. Retrieve s the speed of read/write memory.

13. Initializes the read/wri te memory controller with the speed of
read/write memory .

14. Retrieves the speed of read only memory (i.e., Flash).

15. Initializes the read o nly memory contr oller with the speed of read
only memory .

16. Enables the MPU’s instruction cache.

17. Copies the MPU’s exception vector table from 0xFFF00000 to
0x00000000.

18. Verifies MPU type.

19. Enables the superscalar feature of the MPU (superscalar processor
boards only).

20. Verifies the external bus clock speed of the MPU.

21. Determines the debugger’s console/host ports and initializes the
UART.

22. Displays the debugger’s copyright message.

23. Displays any hardware initialization errors that may have occurred.

24. Checksums the debugger object and displays a warning message if
the checksum failed to verify.

25. Displays the amount of local read/write memory found.

26. Verifies the configuration data that is resident in NVRAM and
displays a warning message if the verification failed.

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Using PPCBug

27. Calculates and displ ays the MPU clock spee d, verifies that the MPU
clock speed matches the configura tion data , and displ ays a warni ng
message if the verification fails.

28. Displays the bus clock speed, verifies that the bus clock speed
matches the configuration data, and displays a warning message if
the verification fails.

29. Probes PCI bus for supported network devices.

30. Probes PCI bus for supported mass storage devices.

31. Initializes the memory/IO addresses for the supported PCI bus
devices.

32. Executes Self-Test, if so configured. (Default is no Self-Test.)

33. Extinguishes the board fail LED, if Self-Test passed, and outputs
any warning messages.

34. Executes boot program, if so configured. (Default is no boot.)

4

35. Executes the debugger moni tor (i .e., iss ues the

Using PPCBug

PPCBug is command-driven; it pe rforms its various operatio ns in response
to commands that you e nter at the key board. When the PPC5-B ug prompt
appears on the screen, the debugger is ready to accept debugger
commands. When the PPC5-Diag prompt appears on the screen, the
debugger is ready to accept diagnostics commands. To switch from one
mode to the other, enter SD.

What you enter is st ored i n an int ern al buf fer. Executi on begi ns o nly af ter
you press the <Retu rn> or < Enter > key. This allows you to cor rect entry
errors, if necessary, with the control characters described in the PPCBug
Firmware Package User’s Manual.

After the debugger executes the command, the prompt reappears.
However, depending on what the user program does, if the command
causes execution of a user t arget code ( i.e., GO), the n cont rol may or may
not return to the debugger.

PPC5-Bug> prompt).

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PPCBug Firmware

For example, if a bre akpoint has bee n specified, t hen contro l returns to t he
debugger when the br eakpoint is enc ountered during e xecution of the user
program. Alternately, the user program could return to the debugger by
means of the System Call Handler routine RETURN (described in the

PPCBug Firmware Package User’s Man ual, listed in Appendix A, Related

Documentation). For more about this, refer to the GD, GO, and GT

4

command descriptions in the PPCBug Firmware Packa ge User’s Manual ,
listed in Appendix A, Related Documentation.

A debugger command is made up of the following parts:

❏ The command name, either uppercase or lowercase (e.g., MD or

md).

❏ Any required arguments, as specified by command.
❏ At least one space before the first argument. Precede all other

arguments with either a space or comma.

❏ One or more options. Precede an option or a string of options with

a semicolon (;). If no option is entered, the command’s default
option conditions are used.

Debugger Commands

The individual debugger commands are listed in the following table. The
commands are described in detail in the PPCBug Firmware Package

User’s Manual, listed in Appendix A, Related Documentation

4-6 Computer Group Literature Center Web Site

.

Using PPCBug

Note You can list all the available debugger commands by

entering the Help (HE) command alone. You can view the
syntax for a particular command by entering HE and the
command mnemonic, as listed below.

Table 4-1. Debugger Commands

Command Description

AS Assembler

BC Block of Memory Compare

BF Block of Memory Fill

BI Block of Memory Initialize

BM Block of Memory Move

BS Block of Memory Search
BR Breakpoint Insert
BV Block of Memory Verify

CACHE Modify Cache State

CM Concurrent Mode

CNFG Configure Board Information Block

CS Checksum a Block of data

CSAR PCI Configuration Space READ Access

CSAW PCI Configuration Space WRITE Access

DC Data Conversion and Expression Evaluation

DS Disassembler
DU Dump S-Records

ECHO Echo String

ENV Set Environment to Bug/Operating System

FORK Fork Idle MPU at Address

FORKWR Fork Idle MPU with Registers

G “Alias” for “GO” Command

GD Go Direct (Ignore Breakpoints)

4

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PPCBug Firmware

Table 4-1. Debugger Commands (Continued)

Command Description

GEVBOOT Global Environment Variable Boot - Bootstrap

Operating System

GEVDEL Global Environment Variable Delete

4

GEVDUMP Global Environment Variable(s) Dump (NVRAM

Header + Data)

GEVEDIT Global Environment Variable Edit

GEVINIT Global Environment Variable Initialize (NVRAM

Header)

GEVSHOW Global Environment Variable Show

GN Go to Next Instruction
GO Go Execute User Program

GT Go to Temporary Breakpoint
HE Help on Command(s)

IBM Indirect Block Move

IDLE Idle Master MPU

IOC I/O Control for Disk

IOI I/O Inquiry
IOP I/O Physical to Disk
IOT I/O “Teach” for Configuring Disk Controller

IRD Idle MPU Register Display

IRM Idle MPU Register Modify

IRS Idle MPU Register Set

LO Load S-Records from Host

M “A lias” for “MM” Command

MA Macro Define/Display

MAE Macro Edit
MAL Enable Macro Expansion Listing
MAR Macro Load

MAW Macro Save

MD Memory Display

4-8 Computer Group Literature Center Web Site

Table 4-1. Debugger Commands (Continued)

Command Description

MDS Memory Display

MENU System Menu

MM Memory Modify

MMD Memory Map Diagnostic

MMGR Access Memory Manager

MS Memory Set

MW Memory Write

NAB Automatic Network Boots trap Op erat ing System

NAP Nap MPU
NBH Network Bootstrap Operating System and Halt
NBO Network Bootstrap Operating System

NIOC Network I/O Control

NIOP Network I/O Physical
NIOT I/O “Teach” for Configuring Network Controller

NOBR Breakpoint Delete
NOCM No Concurrent Mode
NOMA Macro Delete

NOMAL Disable Macro Expansion Listing

NOPA Printer Detach

NOPF Port Detach

NORB No ROM Boot

NOSYM Detach Symbol Table

NPING Network Ping

OF Offset Registers Display/Modify
PA Printer Attach

PBOOT Bootstrap Operating Sy stem

PF Port Format

PFLASH Program FLASH Memory

PS Put RTC into Power Save Mode

Using PPCBug

4

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PPCBug Firmware

Table 4-1. Debugger Commands (Continued)

Command Description

RB ROMboot Enable

RD Register Display

4

REMOTE Remote

RESET Cold/Warm Reset

RL Read Loop

RM Register Modify

RS R e gister Set

RUN MPU Execution/Status

SD Switch Directories

SET Set Time and Date

SROM SROM Examine/Modify

SYM Symbol Table Attach

SYMS Symbol Table Display/Search

T Trace

TA Terminal Attach

TIME Display Time and Date

TM Transparent Mode

TT Trace to Temporary Breakpoint
VE Verify S-Records Against Memory

VER Revision/Version Display

WL Write Loop

Although a command to allow the erasing and repr ogramming

!

Caution

of Flash memory is available to you, keep in mind that
reprogramming any portion of Flash memory will erase
everything currently contained in Flash, including the
PPCBug debugger.

4-10 Computer Group Literature Center Web Site

Diagnostic Tests

The PPCBug hardware diagnostics are intended for testing and
troubleshooting the MVME2100.

In order to use the diagno stics, you must switch to the di agnostic directory.
You may switch between directories by using the SD (Switch Directories)
command. You may view a list of the commands in the di recto ry that you
are currently in by using the HE (Help) command.

Using PPCBug

4

If you are in the debugger directory, the debugger prompt

PPC5-Bug> is

displayed, and all of the debugger commands are available. Diagnostics
commands cannot be entered at the

If you are in the di agnostic direc tory, the diagnosti c prompt

PPC5-Bug> prompt.

PPC5-Diag> is

displayed, and all of t he debugger and diagnos tic commands are availabl e.

PPCBug’s diagnostic test groups are listed in Table 4-2. Note that not all
tests are performed on the MVME2100. Usi ng the HE command, you ca n
list the diagnostic routines available in each test group. Refer to the

PPCBug Diagnostics Manual listed in Appendix A, Related

Documentationfor complete descriptions of the diagnostic routines and

instructions on how to invoke them.

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PPCBug Firmware

Table 4-2. Diagnostic Test Groups

Test Group Description

EPIC EPIC Timers Test

PHB PCI Bridge Revision Test

4

RAM RAM Tests (various)

HOSTDMA DMA Transfer Test

RTC MK48Txx Real Time Clock Tests

UART Serial Input/Output Tests (Register, IRQ, Baud, & Loopback)

Z8536 Z8536 Counter/Timer Tests*

SCC Serial Com munications Controller (Z85C230) Tests*

PAR8730x Parallel Interface (PC8730x) Test*

KBD8730x PC8730x Keyboard/Mouse Tests*

ISABRDGE P CI/ISA B r idge Tests (Register Access & IRQ)

VME3 VME3 Tests (Register Read & Register Walking Bit)

DEC DEC21x43 Ethernet Controller Tests

CL1283 Parallel Interface (CL1283) Tests*

Notes You may enter command names in either uppercase or

lowercase.
Some diagnostics depend on restart defaults that are set up

only in a particular rest art mode. Refer to the documentation
on a particular diagnostic for the correct mode.

Test Sets marked with an ast erisk (*) are not available on t he
MVME2100.

4-12 Computer Group Literature Center Web Site

5Modifying the Environment

Overview

You can use the factory-installed debug monitor, PPCBug, to modify
certain parameters contained in the MVME2100 Non-Volatile RAM
(NVRAM), also known as Battery Backed-up RAM (BBRAM).

The CNFG and ENV commands are both described in the PPCBug
Firmware Package User’s Manual. Refer to that manual for general
information about their use and capabilities.

The following para graphs present additi onal information abou t CNFG and
ENV. Some paragraphs may provide examples of MVME2100
information , but the majori ty of the information is specific to the generic
PPCBug commands and parameters being discussed. Also included, are
the parameters that can be co nfigured with the ENV command.

5

❏ The Board Information Block in NVRAM contains various

elements concerning operati ng parame ters of the ha rdware. Use the
PPCBug command CNFG to change those parameters.

❏ Use the PPCBug command ENV to change configurable PPCBug

parameters in NVRAM.

5-1

Modifying the Environment

CNFG - Configure Board Information Block

Use this command to displa y and config ure the Board I nformat ion Bloc k,
which is resident within the NVRAM. This data block contains various
elements detailing specific operational parameters of the MVME2100.
The structure for the board is shown in the following example:

Board (PWA) Serial Number = MOT00xxxxxxx
Board Identifier = MVME2100

5

Artwork (PWA) Identifier = 01-W3403FxxC
MPU Clock Speed = 250
Bus Clock Speed = 083
Ethernet Address = 0001AFA0A57
Primary SCSI Identifier = 07
System Serial Number = nnnnnnn
System Identifier = Motorola MVME2101
License Identifier = nnnnnnnn

The parameters that ar e quoted ar e left -just ifi ed chara cter ( ASCII) stri ngs

padded with space chara cters, and the quotes (“) ar e displayed to indicate
the size of the string. Parameters that are not quoted are considered data
strings, and data strings are right-justified. The data strings are padded
with zeroes if the length is not met.

The Board Information Block is factory-configured before shipment.
There is no need to modify block parameters unless the NVRAM is
corrupted.

Refer to the PPCBug Firmware Package User’s Manual for a description
of CNFG and examples.

5-2 Computer Group Literature Center Web Site

ENV - Set Environment

Use the ENV command to vi ew and/or confi gure interactiv ely all PPCBug
operational parameters that are kept in Non-Volatile RAM (NVRAM).

Refer to the PPCBug Firmware Package User’s Manual for a description
of the use of ENV. Additional information on registers in the Universe
ASIC that affect these parameters is contained in the MVME2100

Programmer’s Reference Guide listed in Appendix A, Related

Documentation.

Listed and described below are the parameters that you can configure
using ENV. The default values shown were those in effect when this
publication went to print.

Configuring the PPCBug Parameters

The parameters that can be configured using ENV are:

Bug or System environment [B/S] = B?

B Bug is the mode where no system type of support is

displayed. However, system-related items are still
available. (Default)

ENV - Set Environment

5

S System is the standard mode of operation, and is the

default mode if NVRAM should fail. System mode is
defined in the PPCBug Firmware Package User’s
Manual.

Maximum Memory Usage (Mb, 0=AUTO) = 1?

This parameter specifies the maximum number of meg abytes the bug is
allowed to use. Allocation begins at the top of physical memory and
expands downward as more memory is required until the max imum value
is reached.

If a value of zero is specified, memory will continue to be increased as
needed until half of the available memory is consumed (i.e. 32Mb in a
64Mb system). This mode is u seful for determining the full memory
required for a specific conf iguration. Once th is is determined, a hard value
may be given to th e paramete r and it is guar anteed that no memory wi ll be
used over this amount.

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Modifying the Environment

The default value for this parameter is one.

Note: The bug does not automatically acquire al l of th e me mory i t

is allowed. Rather, it accumulates memory as necessary in
one megabyte blocks.

5

Field Service Menu Enable [Y/N] = N?

Y
N

Remote Start Method Switch [G/M/B/N] = B?

Display the field service menu.
Do not display the field service menu. (Default)

The Remote Start Method Switch is used when the MVME2100 is
cross-loaded from a nother VME-based CPU in order to start execution
of the cross-loaded program.

G Use the Global Control and Status Register to pass

and start execution of the cross-loaded program.

M Use the Multiprocessor Control Register (MPCR) in

shared RAM to pass and start execution of the cross­loaded program.

B Use both the GCSR and the MPCR methods to pass

and start execution of the cross-loaded program.
(Default)

N Do not use any Remote Start Method.

Probe System for Supported I/O Controllers [Y/N] = Y?

Y

N

5-4 Computer Group Literature Center Web Site

Accesses will be made to the appropriate system
buses (e.g., VMEbus, local MPU bus) to determine
the presence of supported controllers. (Default)

Accesses will not be made to the VMEbus to
determine the presence of supported controllers.

ENV - Set Environment

Auto-Initialize of NVRAM Header Enable [Y/N] = Y?

Y

NVRAM (PReP partition) header space will be
initialized automatically during board initialization,
but only if the PReP partition fails a sanity check.
(Default)

N

NVRAM header space will not be initialized
automatically during board initialization.

Network PReP-Boot Mode Enable [Y/N] = N?

Y

Enable PReP-style network booting (same boot image
from a network interface as from a mass storage
device).

N

Negate VMEbus SYSFAIL* Always [Y/N] = N?

Y

Do not enable PReP-style network booting. (Default)

Negate the VMEbus SYSFAIL∗ signal during board
initialization.

N

Negate the VMEbus SYSFAIL∗ signal after
successful completion or entrance into the bug
command monitor. (Default)

SCSI Bus Reset on Debugger Startup [Y/N] = N?

5

Y
N

Local SCSI bus is reset on debugger setup.
Local SCSI bus is not reset on debugger setup.

(Default)

Primary SCSI Bus Negotiations Type [A/S/N] = A?

A
S
N

Asynchronous SCSI bus negotiation. (Default)
Synchronous SCSI bus negotiation.
None.

http://www.motorola.com/computer/literature 5-5

Modifying the Environment

Primary SCSI Data Bus Width [W/N] = N?

W
N

Secondary SCSI identifier = 07?

Wide SCSI (16-bit bus).
Narrow SCSI (8-bit bus). (Default)

Select the identifier. (Default = 07.)

NVRAM Bootlist (GEV.fw-boot-path) Boot Enable [Y/N] = N?

5

Y

Give boot priority to devices defined in the fw-boot­path globa l environment variable (GEV).

N

Do not give boot priority to devices listed in the fw­boot-path GEV. (Default)

Note When enabled, the GEV (Global Environment Variab le) boot

takes priority over all other boots, including Autoboot and
Network Boot.

NVRAM Bootlist (GEV.fw-boot-path) Boot at power-up only [Y/N] = N?

Y

N

Give boot priority to devices defined in the fw-boot­path GEV at power-up reset only.

Give power-up boot priority to devices list e d in the
fw-boot-path GEV at any reset. (Default)

NVRAM Bootlist (GEV.fw-boot-path) Boot Abort Delay = 5?

The time (in seconds) that a boot from the NVRAM boo t list will delay
before starting the boot . The pu rpos e for the delay is to allow you t he
option of stopping the boot by use of the

BREAK key. The time value

is from 0 - 255 seconds. (Default = 5 seconds)

Auto Boot Enable [Y/N] = N?

Y
N

5-6 Computer Group Literature Center Web Site

The Autoboot function is enabled.
The Autoboot function is disabled. (Default)

Auto Boot at power-up only [Y/N] = N?

ENV - Set Environment

Y
N

Auto Boot Scan Enable [Y/N] = Y?

Y

N

Auto Boot Scan Device Type List = FDISK/CDROM/TAPE/HDISK?

Autoboot is attempted at power-up reset only.
Autoboot is attempted at any reset. (Default)

If Autoboot is enabled, th e Autoboot process attem pts
to boot from devices specified in the scan list (e.g.,

FDISK/CDROM/TAPE/HDISK). (Default)

If Autoboot is enabled, the Autoboot process uses the
Controller LUN and Device LUN to boot.

This is the listing of boot devices displayed if the Autoboot Scan
option is enabled. If you modify the list, follow the format shown
above (uppercase letters, using forward slash as separator).

Auto Boot Controller LUN = 00?

Refer to the PPCBug Firmware Package User’s Manual for a listing
of disk/tape controller modules currently supported by PPCBug.
(Default = 0x00)

Auto Boot Device LUN = 00?

Refer to the PPCBug Firmware Package User’s Manual for a listing
of disk/tape devices currently supported by PPCBug.
(Default = 0x00)

5

Auto Boot Partition Number = 00?

Which disk “p artition” is to be booted, as specified in the PowerPC
Reference Platform (PReP) specification. If set to zero, the firmware
will search the partitions in order (1, 2, 3, 4) until it finds the first
“bootable” partition. That is then the partition that will be booted.
Other acceptable values are 1, 2, 3, or 4. In these four cases, the
partition specified will be booted without searching.

http://www.motorola.com/computer/literature 5-7

Modifying the Environment

Auto Boot Abort Delay = 7?

The time in seconds that the Autoboot sequence will delay before
starting the boot. The pu rpo se f or t he delay is to allow you the opti on
of stopping the boot by use of th e

BREAK key. The time valu e is from

0 - 255 seconds. (Default = 7 seconds)

Auto Boot Default String [NULL for an empty string] = ?

You may specify a string (filename) which is passed on to the code

5

being booted. The maximum length of this string is 16 characters.
(Default = n ull string)

ROM Boot Enable [Y/N] = N?

Y
N

ROM Boot at power-up only [Y/N] = Y?

Y
N

ROM Boot Enable search of VMEbus [Y/N] = N?

Y

N

ROM Boot Abort Delay = 5?

The ROMboot function is enabled.
The ROMboot function is disabled. (Default)

ROMboot is attempted at power-up only. (Default)
ROMboot is attempted at any reset.

VMEbus address space, in addition to the usual areas
of memory, will be searched for a ROMboot module.

VMEbus address space will not be accessed by
ROMboot. (Default)

The time (in seconds) that the ROMboot sequence will delay before
starting the boot. The pu rpo se f or t he delay is to allow you the opti on
of stopping the boot by use of th e

BREAK key. The time valu e is from

0 - 255 seconds. (Default = 5 seconds)

ROM Boot Direct Starting Address = FFF00000?

The first location tested when PPCBug searches for a ROMboot
module. (Default = 0xFFF00000)

5-8 Computer Group Literature Center Web Site

ENV - Set Environment

ROM Boot Direct Ending Address = FFFFFFFC?

The last location tested when PPCBug searches for a ROMboot
module. (Default = 0xFFFFFFFC)

Network Auto Boot Enable [Y/N] = N?

Y

N

Network Auto Boot at power-up only [Y/N] = N?

Y
N

Network Auto Boot Controller LUN = 00?

The Network Auto Boot (NETboot) function is
enabled.

The NETboot function is disabled. (Default)

NETboot is attempted at power-up reset only.
NETboot is attempted at any reset. (Default)

Refer to the PPCBug Firmware Package User’s Manual for a listing
of network controller modules currently supported by PPCBug.
(Default = 0x00)

Network Auto Boot Device LUN = 00?

Refer to the PPCBug Firmware Package User’s Manual for a listing
of network controller modules currently supported by PPCBug.
(Default = 0x00)

Network Auto Boot Abort Delay = 5?

The time in seconds that the NETboot sequence will delay before
starting the boot. The pu rpo se f or t he delay is to allow you the opti on
of stopping the boot by use of th e

BREAK key. The time valu e is from

0 - 255 seconds. (Default = 5 seconds)

5

Network Auto Boot Configuration Parameters Offset (NVRAM) =
00001000?

The address where th e network inte rface conf iguration p arameters ar e
to be saved/retained in NVRAM; these parameters are the necessary
parameters to perform an unattended network boot. A typical offset
might be 0x1000, but this value is application-specific.
Default = 0x00001000.

http://www.motorola.com/computer/literature 5-9

Modifying the Environment

If you use the NIOT debugger command, thes e parameters need

!

Caution

to be saved somewhere in the offset range 0x0000100 0 through
0x000016F7. The NIOT parameters do not exc eed 128 byt es in
size. The setting of this ENV pointer determines th eir location.
If you have used the same space for your own program
information or commands, they will be overwritten and lost.

You can relocate the network interface configuration parameters
in this space b y using the ENV command to change the Network

5

Auto Boot Configuration Parameters Offset from its def ault of
0x00001000 to the value you need to be clear o f yo ur d at a wit hi n
NVRAM.

Memory Size Enable [Y/N] = Y?

Y

N

Memory Size Starting Address = 00000000?

Memory will be sized for Self-Test diagnostics.
(Default)

Memory will not be sized for Self-Test diagnostics.

The default Starting Address is 0x00000000.

Memory Size Ending Address = 02000000?

The default Ending Address is the calculated size of loc al memor y. If
the memory start is changed from 0x00000000, this value will also
need to be adjusted.

DRAM Speed in NANO Seconds = 15?

The default setting fo r this parameter will vary depending on th e speed
of the DRAM memory parts installed on the board. The default is set
to the slowest speed found on the available banks of DRAM memory.

5-10 Computer Group Literature Center Web Site

ENV - Set Environment

ROM Bank A Access Speed (ns) = 80?

This defines the min imum access speed for the Bank A Flash device( s)
in nanoseconds.

ROM Bank B Access Speed (ns) = 70?

This defines the minimum acce ss speed for the Bank B Flas h device(s)
in nanoseconds.

DRAM Parity Enable [On-Detection/Always/Never - O/A/N] = O?

5

O
A
N

DRAM parity is enabled upon detection. (Default)
DRAM parity is always enabled.
DRAM parity is never enabled.

Note This DRAM Parity Enable parameter also applies t o enabling

ECC for DRAM.

L2 Cache Parity Enable [On-Detection/Always/Never - O/A/N] = O?

O
A
N

PCI Interrupts Route Control Registers (PIRQ0/1/2/3) = 0A0B0E0F?

L2 Cache parity is enabled upon detection. (Default)
L2 Cache parity is always enabled.
L2 Cache parity is never enabled.

Initializes the PIRQx (P CI Interrupts) route control registers in the
PIBC (PCI/ISA bus bridge co ntroller). The ENV parame ter is a 32- bit
value that is di vided by 4 to yiel d the v alues for route c ontrol r egisters
PIRQ0/1/2/3. The default is determined by system type.

LED/Serial Startup Diagnostic Codes

These codes can be displayed at key points in the initialization of the
hardware devices . If the debug ger fails to come up to a prompt, the last
code displayed will indicate how far the initialization sequence had
progressed before stalling. The codes are enabled by an ENV
parameter similar to the following:

http://www.motorola.com/computer/literature 5-11

Modifying the Environment

Serial Startup Code Master Enable [Y/N]=N?

A line feed can be inserted after each code is displayed to prevent it
from being overwritten by the next code. This is also enabled by an
ENV parameter:

Serial Startup Code LF Enable [Y/N]=N?

The list of LED/serial codes is included in the section on MPU,
Hardware, and Firmware Initialization in the PPCBug Firmware

Package User’s Manual, as listed in Appendix A, Related

5

Documentation.

Configuring the VMEbus Interface

ENV asks the following serie s of questions to set up the VMEbus interface
for the MVME2100. To perform this configuration, you should have a
working knowledge of the Universe ASIC as described in your
MVME2100 Programmer’s Reference Guide.

VME3PCI Master Master Enable [Y/N] = Y?

Y
N

PCI Slave Image 0 Control = 00000000?

Set up and enable the VMEbus Interface. (Default)
Do not set up or enable the VMEbus Interface.

The configured value is written into the LSI0_CTL register of the
Universe chip.

PCI Slave Image 0 Base Address Register = 00000000?

The configured value is written into the LSI0_BS register of the
Universe chip.

PCI Slave Image 0 Bound Address Register = 00000000?

The configured value is written into the LSI0_BD register of the
Universe chip.

PCI Slave Image 0 Translation Offset = 00000000?

The configured value is written into the LSI0_TO register of the
Universe chip.

5-12 Computer Group Literature Center Web Site

ENV - Set Environment

PCI Slave Image 1 Control = C0820000?

The configured value is written into the LSI1_CTL register of the
Universe chip.

PCI Slave Image 1 Base Address Register = 81000000?

The configured value is written into the LSI1_BS register of the
Universe chip.

PCI Slave Image 1 Bound Address Register = A0000000?

The configured value is written into the LSI1_BD register of the
Universe chip.

PCI Slave Image 1 Translation Offset = 80000000?

The configured value is written into the LSI1_TO register of the
Universe chip.

PCI Slave Image 2 Control = C0410000?

The configured value is written into the LSI2_CTL register of the
Universe chip.

PCI Slave Image 2 Base Address Register = A0000000?

The configured value is written into the LSI2_BS register of the
Universe chip.

PCI Slave Image 2 Bound Address Register = A2000000?

The configured value is written into the LSI2_BD register of the
Universe chip.

PCI Slave Image 2 Translation Offset = 500000000?

The configured value is written into the LSI2_TO register of the
Universe chip.

PCI Slave Image 3 Control = C0400000?

The configured value is written into the LSI3_CTL register of the
Universe chip.

PCI Slave Image 3 Base Address Register = AFFF0000?

5

The configured value is written into the LSI3_BS register of the
Universe chip.

http://www.motorola.com/computer/literature 5-13

Modifying the Environment

PCI Slave Image 3 Bound Address Register = B0000000?

The configured value is written into the LSI3_BD register of the
Universe chip.

PCI Slave Image 3 Translation Offset = 50000000?

The configured value is written into the LSI3_TO register of the
Universe chip.

VMEbus Slave Image 0 Control = E0F20000?

5

The configured value is written into the VSI0_CTL register of the
Universe chip.

VMEbus Slave Image 0 Base Address Register = 00000000?

The configured value is written into the VSI0_BS register of the
Universe chip.

VMEbus Slave Image 0 Bound Address Register = (Local DRAM Size)?

The configured value is written into the VSI0_BD register of the
Universe chip. The value is the same as the Local Memory Found
number already displayed.

VMEbus Slave Image 0 Translation Offset = 00000000?

The configured value is written into the VSI0_TO register of the
Universe chip.

VMEbus Slave Image 1 Control = 00000000?

The configured value is written into the VSI1_CTL register of the
Universe chip.

VMEbus Slave Image 1 Base Address Register = 00000000?

The configured value is written into the VSI1_BS register of the
Universe chip.

VMEbus Slave Image 1 Bound Address Register = 00000000?

The configured value is written into the VSI1_BD register of the
Universe chip.

VMEbus Slave Image 1 Translation Offset = 00000000?

The configured value is written into the VSI1_TO register of the
Universe chip.

5-14 Computer Group Literature Center Web Site

ENV - Set Environment

VMEbus Slave Image 2 Control = 00000000?

The configured value is written into the VSI2_CTL register of the
Universe chip.

VMEbus Slave Image 2 Base Address Register = 00000000?

The configured value is written into the VSI2_BS register of the
Universe chip.

VMEbus Slave Image 2 Bound Address Register = 00000000?

The configured value is written into the VSI2_BD register of the
Universe chip.

VMEbus Slave Image 2 Translation Offset = 00000000?

The configured value is written into the VSI2_TO register of the
Universe chip.

VMEbus Slave Image 3 Control = 00000000?

The configured value is written into the VSI3_CTL register of the
Universe chip.

VMEbus Slave Image 3 Base Address Register = 00000000?

The configured value is written into the VSI3_BS register of the
Universe chip.

VMEbus Slave Image 3 Bound Address Register = 00000000?

The configured value is written into the VSI3_BD register of the
Universe chip.

VMEbus Slave Image 3 Translation Offset = 00000000?

The configured value is written into the VSI3_TO register of the
Universe chip.

PCI Miscellaneous Register = 10000000?

The configured value is written into the LMISC register of the
Universe chip.

Special PCI Slave Image Register = 00000000?

5

The configured value is writte n into the SLSI re giste r of the Uni verse
chip.

Master Control Register = 80C00000?

The configured value is written into the MAST_CTL register of the
Universe chip.

http://www.motorola.com/computer/literature 5-15

Modifying the Environment

Miscellaneous Control Register = 52060000?

The configured value is written into the MISC_CTL register of the
Universe chip.

User AM Codes = 00000000?

The configured value is written into the USER_AM register of the
Universe chip.

Firmware Command Buffer

5

Firmware Command Buffer Enable = N?

Y

N

Enables Firmware Command Buffer execution.
Disables Firmware Command Buffer execution

(Default).

Firmware Command Buffer Delay = 5?

Defines the number of seconds to wait before firmware begins
executing the startup commands in the startup command buffer.
During this delay, you may press any key to prevent the execution of
the startup command buffer.

The default value of this parameter causes a sta rtup delay of 5 seconds.

Firmware Command Buffer:
[’NULL’ terminates entry]?

The Firmware Command Buffer content s contain the BUG commands
which are executed upon firmware startup.

BUG commands you will place into the command buffer should be
typed just as you enter the commands from the command line.

The string ’NULL’ on a new line terminates the command line entr ies.
All BUG commands except for the following may be used within the

command buffer: DU, ECHO, LO, TA, VE.

Note Interactive editing of the startup command buffer is not

supported. If cha nges a re nee ded to an exist ing s et of st artu p
commands, a new set of commands with changes must be
reentered.

5-16 Computer Group Literature Center Web Site

ARelated Documentation

Motorola Computer Group Documents

The Motorola publicat ions listed be low are referen ced in this manual. You
can obtain paper or electronic copies of Motorola Computer Group
publications by:

❏ Contacting your local Motorola sales office
❏ Visiting MCG’s World Wide Web literature site

http://www.motorola.com/computer/literature

Table A-1. Motorola Computer Group Documents

A

Document Title

MVME2100 Single Board Computer Programmer’s
Reference Manual

PPCBug User’s Manual, Part 1
PPCBug User’s Manual, Part 2
PPCBug Diagnostics Users Manual PPCDIAA/UM
PMCspan PMC Adapter Carrier Board Ins tallation

and Use

Motorola

Publication Number

V2100A/PG

PPCBUGA1/UM
PPCBUGA2/UM

PMCSPANA/IH

A-1

A

Manufacturers’ Documents

Manufacturers’ Documents

For additional information, refer to the following table for manufacturers’
data sheets or user’s manua ls. For your convenience, a sour ce for the listed
document is also provided.

Note In many cases, the information is preliminary and the

revision levels of the documents are subject to change
without notice.

Table A-2. Manufacturers’ Documents

Document Title

MPC8240 Integrated Processor User’s Manual
Motorola Literature Distribution Center
Telephone: [phone] or [phone]

WebSite: http://e-www.motorola.com/webapp/DesignCenter/
E-mail: [e-mail]

PowerPC 603 RISC Microprocessor User’s Manual
Motorola Literature Distribution Center
Telephone: [phone] or [phone]

WebSite: http://e-www.motorola.com/webapp/DesignCenter/
E-mail: [e-mail]

OR
IBM Microelectronics

PowerPC603/EM603e User Manual
PowerPC604e User Manual
Web S ite:

http://www.chips.ibm.com/techlib/products/powerpc/manuals

Universe II User Manual
Tundra Semiconductor Corporation
603 March Road, Kanata, ON, Canada K2K 2M5
1-800-267-7231, [phone]
Fax: [phone]

http://www.tundra.com/page.cfm?tree_id=100008#Universe II
(CA91C142)

Publication

Number

MPC8240UM/D

MPC603EUM/AD

G522-0297-00
G522-0330-00

8091142_MD300_01.pdf

A-2 Computer Group Literature Center Web Site

Related Documentation

Table A-2. Manufacturers’ Documents (Continued)

A

Document Title

TL16C550C Universal Asynchronous
Receiver/Transmitter (UART)
Texas Instruments
Dallas, Texas

http://www.ti.com

LXT970 Fast Ethernet Transceiver
Intel Corporation
(previously, Level One Communications, Inc.)
9760 Goethe Road
Sacramento, CA 95827

http://developer.intel.com/design/network/prod­ucts/lan/docs/LXT970A_docs.htm

AT24C01A/02/04/08/16
2-Wire Serial CMOS E
Atmel Corporation
2325 Orchard Parkway San Jose, CA 95131
[phone]

http://www.atmel.com/atmel/support/

M48T59Y CMOS 8Kx8 Timekeeper SRAM
ST Microelectronics
(formerly, SGS Thomson Microelectronics)
1000 East Bell Road
Phoenix, AZ 85022

http://eu.st.com/stonline/index.shtml

2

PROM

Publication

Number

SLLS177C

N/A

AT24C04

M48T59Y

Intel Corporation
(previously, DIGITAL Semicond uctor 21143)
PCI/CardBus 10/100-Mb/s Ethernet
LAN Controller, Hardware Reference Manual

http://developer.intel.com/design/network/manuals/278074.htm

http://www.motorola.com/computer/literature A-3

27807401.pdf

A

Manufacturers’ Documents

Table A-2. Manufacturers’ Documents (Continued)

Document Title

Intel Corporation
(previously, DIGITAL Semicond uctor 21143)
PCI/CardBus 10/100-Mb/s Ethernet
LAN Controller Data Sheet

http://developer.intel.com/design/network/datashts/278074.htm

Publication

Number

N/A

A-4 Computer Group Literature Center Web Site

Related Specifications

For additional information, refer to the following table for related
specifications. For your convenience, a source for the listed document is
also provided.

Note In many cases, the information is preliminary and the

revision levels of the documents are subject to change
without notice.

Table A-3. Related Specifications

Related Documentation

A

Document Title and Source

IEEE - PCI Mezzanine Card Specification (PMC)
Institute of Electrical and Electronics Engineers, Inc.

Publication and Sa les Department
345 East 47th Street
New York, New York 10017-21633
T e le ph one: 1-80 0-6 78 -433 3

http://standards.ieee.org/catalog/

Peripheral Component Interconnect (PCI) Local Bus
Specification, Revision 2.0, 2.1, 2.2
PCI Special Interest Group
P.O. Box 14070
Portland, Oregon 97214-4070
Marketing/Help Line
T e le ph one: (503 ) 696- 6111
Document/Specification Ordering
Telephone: [phone]or [phone]
FAX: [phone]

http://www.pcisig.com/

Intelligent I/O (I2O) Architecture Specification
Version 1.5 March 199 7

O Special Interest Group

I

2

404 Balboa Street
San Francisco, CA 94118
Voice: 415-750-8352

Fax: [phone]

Publication

Number

P1386.1 Draft 2.0

PCI Local Bus

Specification

N/A

http://www.motorola.com/computer/literature A-5

A

Related Specifications

Table A-3. Related Specifications (Continued) (Conti nued)

Document Title and Source

PC•MIP Specification
VITA Standards Organization
7825 East Gelding Drive,
Suite 104, Scottsdale AZ

85260

http://www.vita.com/

PCI Mezzanine Card Specification
IEEE Standards Department
445 Hoes Lane
P.O Box 1331

Piscataway, NJ 08855-1331

http://standards.ieee.org/catalog/

Common Mezzanine Card Specification
IEEE Standards Department
445 Hoes Lane
P.O Box 1331

Piscataway, NJ 08855-1331

http://standards.ieee.org/catalog/

PCI Interface Specification Rev 2.1
PCI Special Interest Group

503-696-2000

http://www.pcisig.com/

Publication

Number

VITA 29 Draft 0.9a

P1386.1

Draft 2.0

P1386

Draft 2.0

PCI Rev 2.1

A-6 Computer Group Literature Center Web Site

Specifications

This appendix provides general board specifications for the MVME2100
including mechanical, electrical and environmental specifications. It also
provides a section on EMC compliance, and a section on Thermal
Validation, including a listing of thermally significant components.

Mechanical Characteristics

The mechanical outline of the MVME2100 SBC conforms to the
dimensions of a standard 6U VMEbus form factor.

Electrical Characteristics

The estimated power requirements for the MVME2100 are as follows:

Table B-1. Power Requirements for the MVME2100

BSpecifications

B

Configuration +5V Power + 12V Power -12V Power

250 MHz Processor 2.5A typical N/A N/A

83.33 MHz Memory bus 3.5A maximum N/A N/A

Notes The power requirement listed for the MVME2100 does not

include the power requirements for the PMC or PC•MIP
slots. The PMC specification allows for 7.5 watts per PMC
slot. The PC•MIP specification does not limit maximum
power per slot. A total of 15 watts can be drawn from any
combination of the four voltage sources provided by the
MVME2100: +3.3V, +5V, +12V, and -12V.

B-1

Specifications

B

Environmental Characteristics

Table B-2. MVME2100 Environmental Specifications

Characteristics Specifications

Temperature Operating

Nonoperating

Relative Humidity Operat ing

Nonoperating

Vibration Operating

Nonoperating

0° C to 55°C (32° F to 131° F) (Inlet air temperature
with 250 LFM minimum airflow)

−40°

5% to 90% (noncondensing)
5% to 95% (noncondensing

1.0 G sine sweep; 5.0 - 200 Hz; 0.25 octaves/min

0.5 G sine sweep; 5 - 50 Hz; 0.1 octa ves/min

3.0 G sine sweep; 50 - 500 Hz; 0.25 octaves/min

C to 70°C (32° F to 148° F)

B-2 Computer Group Literature Center Web Site

Specifications

EMC Compliance

The MVME2100 was tested in an EMC compliant chassis and meets the
requirements for Class B equipmen t. Complianc e was achiev ed under the
following conditions:

❏ Shielded cables on all external I/O ports.
❏ Cable shields connected to chassis ground via metal shell

connectors bonded to a conductive module front panel.

❏ Conductive chassis r ails connected t o chassis grou nd. This provides

the path for connecting shields to earth ground.

❏ Front panel screws properly tightened.
❏ All peripherals were EMC-compliant

For minimum RF emissions, it is essential that the conditions above be
implemented. Failure to do so could compromise the EMC compliance of
the equipment containing the module.

The MVME2100 is a board level product and meant to be use d in standard
VME applications. As such, it is the respons ibility of the OEM to me et the
regulatory guidelines as determined by its application.

B

All external I/O connect ors are shield ed to aid in meet ing EMC emissions
standards. MVME2100 boards are tested in an MCG chassis for EMC
compliance.

http://www.motorola.com/computer/literature B-3

Thermal Validation

B

Thermal Validation

Board component temperatures are affected by ambient temperature, air
flow, board electrical operation, and software operation. In order to
evaluate the thermal performance of a circuit board asse mbly, it is
necessary to test the board under actual operating conditions. These
operating conditions vary depending on system design.

While Motorol a C omputer Group performs thermal analysis in a
representative system to verify operation within specified ranges (see

Table B-3 on page B-5), you should evaluate the thermal performance of

the board in your application.
This appendix provides sys tems integrators with inf ormation which can be

used to conduct thermal evaluations of the board in their specific system
configuration. It identifies thermally significant components and lists the
corresponding maximum allowa ble component oper ating temperat ures. It
also provides example procedures for component-level temperature
measurements.

Thermally Significant Components

Table B-3 on page B-5 summarizes components that exhibit significant

temperature rises. These are the components that should be monitored in
order to assess thermal performance. The table also supplies the
component reference designator and the maximum allowable operating
temperature.

You can find components on the board by their reference designators as
shown in Figure B-1 and Figure B-2. Versions of the board tha t are not
fully populated may not contain some of these components.

The preferred measurement location for a component may be junction,
case, or air as specified in the table. Junction temp erature refers to the
temperature measured by an on-chip thermal device. Case temperature
refers to the temperature at the top, center surface of the component. Air
temperature refers to the ambient temperature near the component.

B-4 Computer Group Literature Center Web Site

Specifications

Table B-3. Thermally Significant Components

Maximum

Component

Location

General Description

Allowable

Temperature

(Degrees C)

U9 PPC8240, 250MHz 105 Junction
U20 Intel 21143 70 Ambient
U19 Level One LXT970ATC 110 Case
U22 Tundra Universe 2 125 Junction

U3 DRAM NEC D4564 70 Ambient
U25 Lattice isp2032V 70 Ambient

U1 AMD L160BT80VC 70 Ambient

U6 P15C 16245A 80 Ambient
U57 Lattice 2064V 100LT100 70 Ambient

Measurement

(Junction, Case

B

Location

or Air)

http://www.motorola.com/computer/literature B-5

B

Thermal Validation

U1

U19

U3

U6

U20

U9

U22

U25

Figure B-1. Thermally Significant Components (Primary Side )

B-6 Computer Group Literature Center Web Site

Specifications

B

U57

Figure B-2. Thermally Significant Components (Secondary Side)

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Component Temperature Measurement

B

Component Temperature Measurement

The following secti ons outline general t emperature measurement methods.
For the specific typ es of me asure ments requir ed for t her mal eval uatio n of
this board, see Table B-3.

Preparation

We recommend 40 AWG (American Wire Gauge) thermocouples for all
thermal measurements. Larger gauge thermocouples can wick heat away
from the components and disturb air flowing past the board.

Allow the board to reach thermal equ ilibrium before ta king measurements.
Most circuit boards will reach thermal equilibrium within 30 minutes.
After the warm up period, monitor a small number of components over
time to assure that equilibrium has been reached.

Measuring Junction Temperature

Some components have an on-chip thermal measuring device such as a
thermal diode. For instructions on measuring temperatures using the on­board device, refer to th e MVME2100 Programmer’s Reference Guide and

to the component manufacturer’s documentation listed in Appendix A,

Related Documentation.

Measuring Case Temperature

Measure the case temperature at the center of the top of the component.
Make sure there is good thermal contact between the thermocouple
junction and the component. We recommend you use a thermally
conductive adhesive such as Loctite 384.

If components are covered by mecha nical parts such as heats inks, you will
need to machine these par ts to route the the rmocouple wire. Make sure tha t
the thermocouple junction contacts only the electrical component. Also
make sure that heatsink s la y fla t on el ectrical components . The fol lo wi ng
figure shows one method of machining a heatsink base to provide a
thermocouple routing path.

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