Motorola MVME197LE User Manual

MVME197LE

Single Board Computer

User’s Manual

(MVME197LE/D2)

Notice

While reasonable efforts have been made to assure the accuracy of this document,
Motorola, Inc. assumes no liability resulting from any omissions in this document, or
from the use of the information obtained therein. Motor ola rese rves the right to revise
this document and to make changes from time to time in the content hereof without
obligation of Motorola to notify any person of such revision or changes.

No part of this material may be reproduced or copied in any tangible medium, or
stored in a retrieval system, or transmitted in any form, or by any means, radio,
electronic, mechanical, photocopying, recording or facsimile, or otherwise, without the
prior written permission of Motorola, Inc.

It is possible that this publication may contain reference to, or information about
Motorola products (machines and programs), programming, or services that are not
announced in your country. Such references or information must not be construed to
mean that Motorola intends to announce such Motorola products, programming, or
services in your country.

Restricted Rights Legend

If the documentation contained herein is supplied, directly or indirectly, to the U.S.
Government, the following notice shall apply unless otherwise agreed to in writing by
Motorola, Inc.

Use, duplication, or disclosure by the Governm ent is subject to r estrictions as set forth
in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software
clause at DFARS 252.227-7013.

Motorola, Inc.

Computer Group

2900 South Diablo Way

Tempe, Arizona 85282-9602

Preface

This document provides general information, hardware preparation and installation
instructions, operating instructions, and a functional description for the MVME197LE
Single Board Computer.

This document is intended for anyone who wants to design OEM systems, supply
additional capability to an existing compatible system, or work in a lab environment
for experimental purposes.

A basic knowledge of computers and digital logic is assumed.
T o use this document, you may wish to become familiar with the publications listed in

the Related Documentation section found in the following pages.

Document Terminology

Throughout this document, a convention has been maintained whereby data and
address parameters are pr eceded by a cha racter which specifies the numeric format, as
follows:

$ dollar specifies a hexadecimal number
% percent specifies a binary number
& ampersand specifies a decimal number

For example, “12” is the decimal number twelve, and “$12” is the decimal number
eighteen. Unless otherwise specified, all address references are in hexadecimal
throughout this document.

An asterisk (*) following the signal name for signals which are level significant denotes
that the signal is true or valid when the signa l is low.

An asterisk (*) following the signal name for signals which are edge significant denotes
that the actions initiated by that signal occur on high to low transition.

In this document, assertion and negation are used to specify forcing a signal to a
particular state. In particular, assert ion and assert refer to a signal that is active or true;
negation and negate indicate a signal that is inactive or false. These terms are used
independently of the voltage level (high or low) that they represent.

Data and address sizes are defined as follows:

❏ A byte is eight bits, numbered 0 through 7, with bit 0 being the least

significant.

❏ A two-byte is 16 bits, numbered 0 through 15, with bit 0 being the least

significant. For the MVME197series and other RISC modules, this is called
a half-word.

❏ A four-byte is 32 bits, numbered 0 through 31, with bit 0 being the least

significant. For the MVME197 series and other RISC modules, this is called
a word.

❏ An eight-byte is 64 bits, numbered 0 through 63, with bit 0 being the least

significant. For the MVME197 series and other RISC modules, this is called
a double-word.

Throughout this document, it is assumed that the MPU on the MVME197 module
series is always programmed with big-endian byte orde r ing, as shown below. Any
attempt to use small-endian byte ordering will immediately render the MVME197Bug
debugger unusable.

BIT BIT
63 56 55 48 47 40 39 32

ADRO ADR1 ADR2 ADR3

31 24 23 16 15 08 07 00

ADR4 ADR5 ADR6 ADR7

The terms control bit and status bit are used extensively in this document. The term
control bit is used to describe a bit in a register that can be set and cleared under
software control. The term true is used to indicate that a bit is in the state that enables
the function it controls. The term false is used to indicate th at the bit is in the state th at
disables the function it controls. In all tables, the terms 0 and 1 are used to describe the
actual value that should be written to the bit, or the value that it yields when read. The
term status bit is used to describe a bit in a register that r eflects a specific condition. The
status bit can be read by software to determine operational or exception conditions.

Related Documentation

The following publications are applicable to the MVME197LE module a nd m ay
provide additional helpful information. If not shipped with this product, they may be
purchased by contacting your Motorola sales office.

Document Title

MVME197LE, MVME197DP, and MVME197SP Single

Board Computers Programmer’s Reference Guide
MVME197BUG 197Bug Debugging Package User’s Ma nual
MVME197BUG 197Bug Diagnostic Firmware User’s Ma nual
MVME712M Transition Module and P2 A dapter Board

User’s Manual
MVME712-12, MVME712-13, MVME 712A, MVME712A M,

and MVME712B Transition Module and LCP2 Adapter Board

User’s Manual
MC88110 Second Generation RISC Microp rocessor User ’s

Manual
MC68040 Microprocessor User’s Manual

Note

Although not shown in the above list, each Motorola
Computer Group manual publication number is suffixed
with characters which represent the revision level of the

document, such as “/D2” (the second revision of a manual);
a supplement bears the same number as the ma nual but has
a suffix such as “/A1” (the first supplement to the manual).

Motorola

Publication Number

MVME197PG

MVME197BUG
MVME197DIAG
MVME712M

MVME712A

MC88110UM

MC68040UM

To further assist your development effort, Motorola has collected user’s manuals for
each of the peripheral controllers used on the MVME197 module series and other
boards from the suppliers. This bundle includes manuals for the following:

68-1X7DS for use with the MVME197 series of Single Board Computers.

NCR 53C710 SCSI Controller Data Manual and Programmer’s Guide
Intel i82596 Ethernet Controller User’s Manual
Cirrus Logic CD2401 Serial Controller User’s Manual
SGS-Thompson MK48T08 NVRAM/TOD Clock Data Sheet

The following non-Motorola publications may also be of interest and may be obtained
from the sources indicated. The VMEbus Specification is contained in ANSI/IEEE
Standard 1014-1987 .

ANSI/IEEE Std 1014-1987 The Institute of Electrical and Electronics
Versatile Backplane Bus: VMEbus Engineers, Incorporated

Publication and Sales Department
345 East 47th Street
New York, New York 10017-2633
Telephone: [phone]

ANSI Small Computer System Interface-2 Global Engineering Documents
(SCSI-2), Draft Document X3.131-198X, P.O. Box 19539
Revision 10c Irvine, California 92713-9539

Telephone [phone]

The computer programs stored in the Read Only Memory of this device contain
material copyrighted by Motorola Inc., first published 1991, and may be used only
under license such as the License for Computer Programs (Article 14) contained in

Motorola’s Terms and Conditions of Sale, Rev. 1/79.

®

Motorola

Delta Series, M88000, SYSTEM V/88, VMEmodule, VMEsystem, and 197bug are
trademarks of Motorola, Inc.

Timekeeper and Zeropower are trademarks of Thompson Components.
All other products mentioned in this document are trademarks or registered

trademarks of their respective holders

and the Motorola symbol are registered trademarks of Motorola, Inc.

© Copyright Motorola 1993

All Rights Reserved

Printed in the United States of America

December 1993

!

WARNING

This equipment generates, uses, and can radiate radio
frequency energy and if not installed and used in
accordance with the documentation for this product, may
cause interference to radio communications. It has been
tested and found to comply with the limits for a Class A
Computing Device pursuant to Subpart J of Part 15 of FCC
rules, which are designed to provide reasonable protection
against such interference when operated in a commercial
environment. Operation of this equipment in a residential
area is likely to cause interference in w hich ca se the user, at

the user’s own expense, will be required to take whatever
measures necessary to correct the interference.

SAFETY SUMMARY

SAFETY DEPENDS ON YOU

The following general safety precautions must be observed during all phases of operation, service, and repair
of this equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual
violates safety standards of design, manufacture, and intended use of the equipment. Motorola Inc. assumes

no liability for the customer’s failure to comply with these requirements. The safety precautions listed below
represent warnings of certain dangers of which we are aware. You, as the user of the product, should follow
these warnings and all other saf ety precautio ns necessary for the safe oper ation of the e quipment in you r
operating environment.

GROUND THE INSTRUMENT.

To minimize shock h azard, the equipm ent chassis and e nclosure must be co nnected to an ele ctrical ground. T he
equipment is supplied w ith a three-conduct or ac power cable. The power cable must either be plugged in to an
approved three-contact electrical ou tlet or used w ith a three- contact to two- contact adap ter, with the gr ounding w ire
(green) firmly connected to an electrical ground (safety ground) at the power outlet. The power jack and mating plug
of the power cable meet international Electrotechnical Commission (IEC) safety standards.

DO NOT OPERATE IN AN EXPLOSIVE ATMOSPHERE.

Do not operate the equipment in the presence of flammable gases or fumes. Operation of any electrical equipment in
such an environment constitutes a definite safety hazard.

KEEP AWAY FROM LIVE CIRCUITS.

Operating personnel must not remove equipment covers. Only Factory Authorized Service Personnel or other qualified
maintenance person nel may remove equ ipment covers for internal sub assembly or comp onent replacem ent or any
internal adjustment. D o not replace comp onents with power cab le connected. Unde r certain conditio ns, dangerous
voltages may exist even with th e power cable remo ved. To avoid injuries, alw ays disconnect power and disc harge
circuits before touching them.

DO NOT SERVICE OR ADJUST ALONE.

Do not attempt internal service or adjustment unless another person, capable of rendering first aid and resuscitation,
is present.

USE CAUTION WHEN EXPOSING OR HANDLING THE CRT.

Breakage of the Cathode-Ray Tube (CRT) causes a high-velocity scattering of glass fragments (implosion). To prevent
CRT implosion, avoid rough handling or jarring of the equipment. Handling of the CRT should be done only by qualified
maintenance personnel using approved safety mask and gloves.

DO NOT SUBSTITUTE PARTS OR MODIFY EQUIPMENT.

Because of the danger of introduc ing additional hazards, do not install subs titute par ts or perform an y unauthor ized
modification of the equipment. Contact your local Motorola representative for service and repair to ensure that safety
features are maintained.

DANGEROUS PROCEDURE WARNINGS.

Warnings, such as the example below, precede potentially dangerous procedures throughout this manual. Instructions
contained in the war nings must be fo llowed. You shou ld also employ a ll other safety precautions which you deem
necessary for the operation of the equipment in your operating environment.

!

WARNING

Dangerous voltages, capab le of causing de ath, are present in
this equipment. Use extreme caution when handling,
testing, and adjusting.

SPD 15163 R-2 (9/93)

Contents

CHAPTER 1 GENERAL INFORMATION

Introduction.............................................................................................................1-1

General Description................................................................................................1-1

Features.....................................................................................................................1-2

Specifications...........................................................................................................1-3

Cooling Requirements.....................................................................................1-4

FCC Compliance..............................................................................................1-5

Equipment Required...............................................................................................1-5

Support Information...............................................................................................1-6

CHAPTER 2 HARDWARE PREPARATION AND INSTALLATION

Introduction.............................................................................................................2-1

Unpacking Instructions..........................................................................................2-1

Hardware Preparation............................................................................................2-1

Configuration Switches...................................................................................2-3

Configuration Switch S1: General Information....................................2-3

Configuration Switch S1: General Purpose Functions

(S1-1 to S1-8)...................................................................................2-4

Configuration Switch S1: System Controller Enable

Function (S1-9)...............................................................................2-4

Configuration Switch S6: Serial Port 4 Clock Select

(S6-1, S6-2)......................................................................................2-5

Connectors ........................................................................................................2-5

Installation Instructions..........................................................................................2-5

MVME197LE Module Installation.................................................................2-6

System Considerations....................................................................................2-7

CHAPTER 3 OPERATING INSTRUCTIONS

Introduction.............................................................................................................3-1

Controls and Indicators..........................................................................................3-1

ABORT Switch S2..................................... ..... ...................................................3-1

RESET Switch S3..............................................................................................3-1

Front Panel Indicators (DS1-DS6)..................................................................3-2

Memory Maps .........................................................................................................3-2

ix

Processor Bus Memory Map..........................................................................3-2

Detailed I/O Memory Maps.......................................................................3-5

BBRAM, TOD Clock Memory Map.........................................................3-19

VMEbus Memory Map.....................................................................................3-20

VMEbus Accesses to the Local Peripheral Bus......................................3-20

VMEbus Short I/O Memory Map............................................................3-20

Software Initialization ..............................................................................................3-21

Multi-MPU Programming Considerations....................................................3-21

Local Reset Operation.......................................................................................3-21

CHAPTER 4 FUNCTIONAL DESCRIPTION

Introduction.................................................................................................................4-1

MVME197LE Functional Description......................................................................4-1

Data Bus Structure...............................................................................................4-1

MC88110 MPU .....................................................................................................4-1

BOOT ROM ..........................................................................................................4-3

FLASH Memory...................................................................................................4-3

Onboard DRAM...................................................................................................4-3

Battery Backup RAM and Clock .......................................................................4-3

VMEbus Interface................................................................................................4-4

I/O Interfaces.......................................................................................................4-4

Serial Port Interface ......................................................................................4-4

Printer Interface..................................................... ..... ...... ............................4-5

Ethernet Interface.........................................................................................4-5

SCSI Interface................................................................................................4-6

SCSI Termination .........................................................................................4-6

Peripheral Resources...........................................................................................4-6

Programmable Tick Timers ........................................................................4-6

Watchdog Timer...........................................................................................4-7

Software-Programmable Hardware Interrupts.......................................4-7

Processor Bus Timeout................................................................................4-7

Local Peripheral Bus Timeout....................................................................4-7

Interrupt Sources.................................................................................................4-7

APPENDIX A EIA-232-D INTERCONNECTIONS...............................................A-1

x

List of Figures

Figure 2-1. MVME197LE Switches, Connectors, and LED Indicators

Location Diagram...................................................................2-2

Figure 4-1. MVME197LE Block Diagram.............................................................4-2

Figure A-1. Middle-of-the-Road EIA-232-D Configuration.............................A-5

Figure A-2. Minimum EIA-232-D Connection...................................................A-6

xi

xii

List of Tables

Table 1-1. MVME197LE Specifications.................................................................1-3

Table 3-1. Processor Bus Memory Map................................................................3-3

Table 3-2. Local Devices Memory Map...............................................................3-4

Table 3-3. BusSwitch Register Memory Map .....................................................3-6

Table 3-4. ECDM CSR Register Memory Map ....................................................3-7

Table 3-5. DCAM (I

Table 3-6. VMEchip2 Memory Map......................................................................3-9

Table 3-7. PCCchip2 Memory Map.....................................................................3-13

Table 3-8. Printer Memory Map ..........................................................................3-14

Table 3-9. Cirrus Logic CD2401 Serial Port Memory Map..............................3-15

Table 3-10. 82596CA Ethernet LAN Memory Map...........................................3-16

Table 3-11. 53C710 SCSI Memory Map ..............................................................3-17

Table 3-12. MK48T08 BBRAM, TOD Clock Memory Map..............................3-17

Table 3-13. BBRAM Configuration Area Memory Map ..................................3-18

Table 3-14. TOD Clock Memory Map.................................................................3-18

Table A-1. EIA-232-D Interconnections...............................................................A-2

2

C) Register Memory Map...................................................3-8

xiii

xiv

GENERAL INFORMATION

Introduction

This user’s manual provides general information, preparation for use and
installation instructions, operating instructions, and a functional description
for the MVME197LE version of the MVME197 series of single board
computers.

General Description

The MVME197LE module is a double-high VMEmodule based on the
MC88110 RISC microprocessor. The MVME197LE has 32/64MB of DRAM,
1MB of FLASH memory, 8KB of static RAM (with battery backup), a time of
day clock (with battery backup), an Ethernet transceiver interface, four serial
ports with EIA-232-D interface, six tick timers, a watchdog timer, 128/256KB
of BOOT ROM, a SCSI bus interface with DMA (Direct Memory Access), a
Centronics printer port, an A16/A24/A32/D8/D16/D32 VMEbus
master/slave interface, and a VMEbus system controller.

Input/Output (I/O) signals are routed through the MVME197LE’s backplane
connector P2. A P2 Adapter Board or LCP2 Adapter board routes the signals
and grounds from connector P2 to an MVME712 series tra nsition module. The
MVME197LE supports the MVME712M, MVME712A, MVME712AM, and
MVME712B transition boards (referred to here as the MVME712X, unless
separately specified). The MVME197LE also supports the MVME712-12 and
MVME712-13 (referred to as the MVME712-XX, unless separately specified).
These transition boards provide configuration headers, seria l port drivers, and
industry standard connectors for the I/O devices.

1

The MVME197LE modules have eight ASICs (Application-Specific Integrated
Circuits) described in the following order: BusSwitch, DCAM, ECDM, PCC2,
and VME2.

The BusSwitch ASIC provides an interface between the processor bus
(MC88110 bus) and the local peripheral bus (MC68040 com patible bu s). Refer
to the MVME197LE block diagram ( Figure 1-1). It provides bus arbitration for
the MC88110 bus and serves as a seven level interrupt handler. It has
programmable map decoders for both busses, as well as write post buffers on
each, two tick timers, and four 32-bit general purpose registers.

MVME197LE/D21-1

1

General Information

Note

For the MVME197 series, the term Local Bus, as used in
other MVME1xx Single Board Computer series, is referred
to as the Local Peripheral Bus.

The DCAM (DRAM Controller and Address Multiplexer) ASIC provides the
address multiplexers and RAS/CAS/WRITE control for the DRAM as well as
data control for the ECDM.

The ECDM (Error Correction and Data Multiplexer) ASIC multiplexes
between four data paths on the DRAM array. Since the device handles 16 bits,
four such devices are required on the MVME197LE to accommodate the 64-bit
data bus of the MC88110 microprocessor. Single-bit error correction and
double-bit detection is performed in the ECDM.

The PCCchip2 (Peripheral Channel Controller) ASIC provides two tick timers
and the interface to the LAN chip, the SCSI chip, the serial port chip, the
printer port, and the BBRAM (Battery Backup RAM).

The VMEchip2 ASIC provides a VMEbus interface. The VMEchip2 includes
two tick timers, a watchdog timer, programmable map decoders for the master
and slave interfaces, and a VMEbus to/from the local peripheral bus DMA
controller, a VMEbus to/from the local peripheral bus non-DMA
programmed access interface, a VMEbus interrupter, a VMEbus system
controller, a VMEbus interrupt handler, and a VMEbus requester.

Local peripheral bus to VMEbus transfers can be D8, D16, or D32. VMEchip2
DMA transfers to the VMEbus, however, can be 64 bits wide as Block Transfer
(BLT).

Features

These are some of the major features of the MVME197LE single board
computer:

❏ MC88110 RISC Microprocessor
❏ 32 or 64 megabytes of 64-bit Dynamic Random Access Memory (DRAM)

with error correction

❏ 1 megabyte of FLASH memory
❏ Six status LEDs (FAIL, RUN, SCON, LAN, SCSI, and VME)
❏ 8 kilobytes of Static Random Access Memory (SRAM) and Time of Day

(TOD) clock with Battery Backup RAM (BBRAM)

❏ Two push-button switches (ABORT and RESET)

1-2 User’s Manual

Specifications

❏ 128 or 256 kilobytes of BOOT ROM
❏ Six 32-bit tick timers for periodic interrupts
❏ Watchdog timer
❏ Eight software interrupts
❏ I/O

– SCSI Bus interface with Direct Memory Access (DMA)
– Four serial ports with EIA-232-D buffers
– Centronics printer port
– Ethernet transceiver interface

❏ VMEbus interface

– VMEbus system controller functions
– VMEbus interface to local peripheral bus (A24/A32, D8/D16/D32

BLT (D8/D16/D32/D64))(BLT = Block Transfer)

– Local peripheral bus to VMEbus interface (A24/A32, D8/D16/D32

BLT (D16/D32/D64))
– VMEbus interrupter
– VMEbus interrupt handler
– Global CSR for inter-processor communications
– DMA for fast local memory - VMEbus transfers (A16/A24/A32,

D16/D32 BLT (D16/D32/D64))

1

Specifications

The specifications for the MVME197LE are listed in Table 1-1.

Table 1-1. MVME197LE Specifications

Characteristics Specifications

Power requirements

Operating temperature

(refer to the Cooling

Requirements section)
Storage temperature
Relative humidity

MVME197LE/D2 1-3

+5 Vdc (± 2.5% ), 4 A (typical), 5 A (maxim um )
+12 Vdc (± 2.5%), 100 mA (maximum)

-12 Vdc (± 2.5%), 100 mA ( ma ximum)

0° to 55° C at point of entry of forced air
(approximately 490 LFM)

-40° to 85° C
5% to 90% (non-condensing)

1

General Information

Table 1-1. MVME197LE Specifications (Continued)

Characteristics Specifications

Physical dimensions:

PC board

Height
Width
Thickness

PC board with connectors
and front panel

Height
Width
Thickness

Board connectors:

P1 connector

P2 connector

J1 connector

J2 connector

Cooling Requirements

Double-high VMEboard

9.187 inches (233.35 mm)

6.299 inches (160.00 mm)

0.063 inch (1.60 mm )

10.309 inches (261.85 mm)

7.4 inches (188.00 mm)

0.80 inch (20.32 mm)

A 96-pin connector which provides the interface to the
VMEbus signals.

A 96-pin connector which provides the interface to the
extended VMEbus signals and other I/O signals.

A 20-pin connector which provides the interface to the
remote reset, abort, the LEDs, and thr ee gen era l purpos e I/O
signals.

A 249-pin connector which provides the interface to the
MC88110 address, data, and control signals to and from the
mezzanine expansion.

The Motorola MVME197LE VMEmodule is specified, designed, an d tested to

operate reliably with an incoming air temp erature range from 0 ° to 55° C (3 2°
to 131° F) with forced air cooling at a velocity typically achievable by using a
100 CFM axial fan. Temperature qualification is performed in a standard
Motorola VMEsystem 3000 chassis. Twenty-five watt load boards are inserted
in two card slots, one on each side, adjacent to the board under test, to simulate
a high power density system configuration. An assembly of three axial fans,
rated at 100 CFM per fan, is placed directly under the VME card cage. The
incoming air temperature is measured between the fan assembly and the card
cage, where the incoming airstream first encounters the module under test.
Test software is executed as the module is subjected to ambient temperature
variations. Case temperatures of critical, high power density integrated
circuits are monitored to ensure component vendors specifications are not
exceeded.

1-4 User’s Manual

While the exact amount of airflow required for cooling depends on the
ambient air temperature and the type, number, and location of boards and
other heat sources, adequate cooling can usually be achieved with 10 CFM and
490 LFM flowing over the module. Less airflow is required to cool th e module
in environments having lower maximum ambients. Under more favorable
thermal conditions, it may be possible to operate the module reliably at higher

than 55° C with increased airflow. It is important to note that there are several
factors, in addition to the rated CFM of the air mover, which determine the
actual volume and speed of air flowing over a module.

FCC Compliance

The MVME197LE was tested in an FCC-compliant chassis, and meets the
requirements for Class A equipment. FCC compliance was achieved under the
following conditions:

1. Shielded cables on all external I/O ports.

2. Cable shields are connected to earth ground via metal shell connectors
bonded to a conductive module front panel.

3. Conductive chassis rails connected to earth ground. This provides the path
for connecting shields to earth ground.

4. All chassis and MVME197LE front panel attachment screws are properly
tightened.

Equipment Required

1

For minimum RF emissions , it is essential that the conditions above be
implemented; failure to do so could compromise the FCC compliance of the
equipment containing the module.

Equipment Required

The following equipment is required to make a complete system using the
MVME197LE:

System console terminal
Disk drives and controllers
MVME712 series transition modules (MVME712-12, MVME712-13,

MVME712A, MVME712AM, MVME712B, or MVME712M); P2 or LCP2
Adapter Boards

Operating system

The MVME197Bug debug monitor firmware (197Bug) is provided in the
FLASH memory on the MVME197LE module. It provides over 50 debug,
up/down line load, and disk bootstrap load commands, as well as a set of
onboard diagnostics and a one-line assembler/disassembler. 197Bug includes

MVME197LE/D2 1-5

1

General Information

a user interface which accepts commands from the system console terminal.
197Bug can also operate in a System Mode, which includes choices from a
service menu. Refer to the MVME197BUG 197Bug Debugging Package User’s
Manual for more details.

The MVME712 series transition modules provide an interface between the
MVME197LE module and peripheral devices. They connect the MVME197 LE
to EIA-232-D serial devices, Centronics-compatible parallel devices, SCSI
devices, and Ethernet devices. A P2 Adapter Board or LCP2 Adapter Board
and cable is required with the MVME712 series transition modules. Refer to
the MVME712-12, MVME712-13, MVME712A, MVME712AM, and

MVME712B Transition Modules and LCP2 Adapter Board User’s Manual or the
MVME712M Transition Module and P2 Adapter Board User’s Manual for more

details.
Software available for the MVME197LE includes SYSTEM V/88 and real-time

operating systems, programming languages, and other tools and applications.
Contact your local Motorola sales office for more details.

Support Information

Detailed support information such as connector signal decriptions, the module
parts list, and the schematic diagram for the MVME197LE is contained in the
SIMVME197LE Single Board Computer Support Information manual.

This manual may be obtained free of charge by contactin g your local Motorola
sales office.

1-6 User’s Manual

HARDWARE PREPARATION

Introduction

This chapter provides unpacking instructions, hardware preparation, and
installation instructions for the MVME197LE VMEmodule. The MVME712X
transition module hardware preparation is provided in separate manuals,
refer to the Related Documentation section found in the preface part of this

User’s Manual.

Unpacking Instructions

Note

Carefully unpack the equipment from the shipping carton. Refer to the
packing list and verify that all items are present. Save the shipping carton and
packing materials for storing or reshipping of the equipment.

Caution

If shipping carton is damaged upon receipt, request that the

carrier’s agent be present during unpacking and inspection
of equipment.

Avoid touching areas of integrated circuit s. Sta tic discha rge
can damage these components.

AND INSTALLATION

2

Inspect the equipment for any shipping damage. If no damage exists, then the
module can be prepared for operation according to the following sections of
this chapter.

Hardware Preparation

To select the desired configuration and ensure proper operation of the
MVME197LE module, certain modifications may be necessary before
installation. These modifications are made through switch settings as
described in the following sections. Many other modifications are done by
setting bits in control registers after the MVME 197LE has been installed in a
system. (The MVME197LE registers are described in the MVME197LE,

MVME197DP, and MVME197SP S ingle Board Computers Programm er’s Reference
Guide as listed in the Related Documentation section of this manual).

MVME197LE/D22-1

Hardware Preparation and Installation

2

2-2 User’s Manual

MVME197LE/D2 2-3

VMEbus CONNECTOR P1

VMEbus CONNECTOR P2

P1 P2

A1
B1
C1

A32
B32
C32

A1
B1
C1

1A17

1A1

1A1

2A17

3A1

A32
B32
C32

3A17

12345678

O
N

CONFIGURATION SWITCH S1

GENERAL PURPOSE/SCON

MODULE CONNECTOR J1

REMOTE RESET/ABORT/LEDS

20

19

DS1

FAIL

MVME197LE

S1

DS2

SCON

1E1

1E17

1E1

2E17

3E1

3E17

MEZZANINE CONNECTOR J2

12

O
N

S6

9

2

J1

1

DS4

DS3

LAN

RUN

ABORT

RESET

SWITCH

SWITCH

S2

DS6

DS5

SCSI

VME

S3

S2 S3

CONFIGURATION SWITCH S6

SERIAL PORT 4 CLOCK SELECT

Hardware Preparation

Figure 2-1. MVME197LE Switches, Connectors, and LED Indicators Location Diagram

2

Hardware Preparation and Installation

2

Configuration Switches

The location of the switches, connectors, and LED indicators on the
MVME197LE is illustrated in Figure 2-1. The MVME197LE has been factory
tested and is shipped with factory switch settings that are described in the
following sections. The MVME197LE operates with its required and factory­installed Debug Monitor, MVME197Bug (197Bug), with these factory switch
setting.

Configuration Switch S1: General Information

Switch S1 is a bank of nine two-way switch segments. The following
illustration shows the factory configuration of switch S1. The bit values are
read as a one when the switch is OFF (open), and as a zero when the switch is

ON (closed). The default value for switch S1 is shown below.

Switch S1

1

O
N

2 3 4 5 6 7 8 9

CLOSED
OPEN

System Controller (SCON)
General Purpose Input 7 (GPI7)
General Purpose Input 6 (GPI6)
General Purpose Input 5 (GPI5)
General Purpose Input 4 (GPI4)
General Purpose Input 3 (GPI3)
General Purpose Input 2 (GPI2)
General Purpose Input 1 (GPI1)
General Purpose Input 0 (GPI0)

(FACTORY CONFIGURATION)

2-4 User’s Manual

Hardware Preparation

Configuration Switch S1: General Purpose Functions (S1-1 to S1-8)

The eight General Purpose Input lines (GPI0-GPI7) on the MVME197LE may
be configured with selectable switch segments S1-1 through S1-8. These
switches can be read as a register (at $FFF40088) in the VMEchip2 LCSR. Refer
to the VMEchip2 chapter in the MVME197LE, MVME197DP, an d MVME197SP
Single Board Computers Programmer’s Reference Guide for the status of lines GPI0
through GPI7. Factory configuration is with the general purposes input lines
disabled (open).

Switch S1

1

O

O
N

N

S1-1 to S1-8: OFF -- All Ones (FACTORY CON FIGU RATION )

Configuration Switch S1: System Controller Enable Function (S1-9)

The MVME197LE can be the system controller. The system controller
function is enabled or disabled by configuring selectable switch segment
S1-9. When the MVME197LE is the system controller, the SCON LED is
turned ON. T he VMEchi p2 may b e configu red as a system controller as
illustrated below. Factory configuration is with the system controller
switch enabled (closed).

2 3 4 5 6 7 8 9

CLOSED
OPEN

2

Switch S1

O

O
N

N

S1-9: ON -- MVME197 IS the System Controller

(FACTORY CONF IG URAT ION )

91 2 3 4 5 6 7 8

CLOSED
OPEN

Switch S1

O
N

S1-9: OFF -- MVME197 IS NOT the System Controller

MVME197LE/D2 2-5

91 2 3 4 5 6 7 8

CLOSED
OPEN

Hardware Preparation and Installation

2

Configuration Switch S6: Serial Port 4 Clock Select (S6-1, S6-2)

Serial port 4 can be configured to use clock signals provided by the RTXC4 and
TRXC4 signal lines. Switch segments S6-1 and S6-2 on the MVME197LE
configures serial port 4 to drive or receive TRXC4 and RTXC4, respectively.
Factory configuration is with serial port 4 set to receive both signals (open).
The remaining configuration of the clock lines is accomplished by using the
Serial Port 4 Clock Configuration Select header on the MVME712M transition
module. Refer to the MVME712M Transition Module and P2 Adapter Board
User’s Manual for configuration of that header.

Switch S6

1 2

O
N

Receive TRXC4 Receive RTXC4

(FACTORY CONFIGURATION)

Switch S6

1 2

O
N

Drive TRXC4 Drive RTXCC4

CLOSED
OPEN

CLOSED
OPEN

Connectors

The MVME197LE has two 64-position DIN connectors: P1 and P2. Connec tor
P1 rows A, B, C, and connector P2 row B provide the VMEbus interconnection.
Connector P2 rows A and C provide the interconnect to the SCSI bus, the serial
ports, the Ethernet interface, and the Centronics printer. There is a 249-pin
mezzanine connector (J2) with the MC88110 bus interface. This mezzanine
connector is for MVME197LE module expansion. There is also a 20-pin
general purpose connector (J1) which provides the interconnect to the LEDs
and the reset and abort signals. Refer to the SIMVME197LE Single Board
Computer Support Information manual for detailed signal descriptions.

Installation Instructions

The following sections discuss i nsta llation of the MVME197LE into a VME
chassis, and system considerations. Ensure that the BOOT ROM device is
installed. Ensure that all switches are configured as desired.

2-6 User’s Manual

Installation Instructions

MVME197LE Module Installation

Now that the MVME197LE module is ready for installation, proceed as
follows:

a. Turn all equipment power OFF and disconnect the power cable from the

power source.

Caution

!

WARNING

b. Remove the chassis cover as instructed in the equipment user’s manual.
c. Remove the filler panel(s) from the appropriate card slot(s) at the front and

Inserting or removing modules while power is applied
could result in damage to module components.

DANGEROUS VOLTAGES, CAPABLE OF CAUSING
DEATH, ARE PRESENT IN THIS EQUIPMENT. USE
EXTREME CAUTION WHEN HANDLING, TESTING,
AND ADJUSTING.

rear of the chassis (if the chassis has a rear card cage). The MVME197LE
module requires power from both P1 and P2. It may be installed in any
double-height unused card slot, if it is not configured as the system
controller. If the MVME197LE is configured as the system controller, it
must be installed in the left-most card slot (slot 1) to correctly initiate the
bus-grant daisy-chain and to have proper operation of the IACK-daisy­chain driver. The MVME197LE is to be installed in the front of the chassis
and the MVME712X trans ition board whi ch has a double- wide front panel
is to be installed in the rear of the chassis.

2

d. Carefully slide the MVME197LE module in to the card slot. Be sure the

module is seated properly into the P1 and P2 connectors on the backplane.
Do not damage or bend connector pins. Fasten the modu le in the chassis
with screws provided, making good contact with the transverse mounting
rails to minimize RFI emiss ions.

e. Remove the IACK and BG jumpers from the header on the chassis

backplane for the card slot in which the MVME197LE is installed.

f. Connect the P2 Adapter Board and specified cable(s) to the MVME197LE

at P2 on the backplane at the MVME197LE slot, to mate with (optional)
terminals or other peripherals at the EIA-232-D serial ports, parallel port,
SCSI ports, and LAN Ethernet port. Refer to the manuals listed in the
Related Documentati on section for information on installing the P2 Adapter
Board and the MVME712X transition module. (S ome connection diagrams

MVME197LE/D2 2-7

Hardware Preparation and Installation

2

are provided in the MVME197LE, MVME197DP, and MVME197SP Single
Board Computers Prog rammer’s Reference Gui de). Some cable(s) are not
provided with the MVME712X module and therefore, are made or
provided by the user. (Motorola recommends using shielded cables for all
connections to peripherals to minimize radiation). Connect the
peripherals to the cable(s). Detailed information on the EIA-232-D signals

supported is found in Appendix A.
g. Install any other required VMEmodules in the system.
h. Replace the chassis cover.
i. Connect the power cable to the ac power source and turn the equipment

power ON.

System Considerations

The MVME197LE needs to draw power from both connectors P1 an d P2 of the
VMEbus backplane. Connector P2 is also used for the upper 16 bits of data for
32-bit transfers, and for the upper 8 address lines for the extend ed addr essing
mode. The MVME197LE may not operate properly without its main board
connected to connectors P1 and P2 of the VMEbus backplane.

Whether the MVME197LE operates as a VMEbus master or as a VMEbus slave,
it is configured for 32 bits of address and for 32 bits of data (A32/D32).
However, it handles A16 or A24 devices in ce rtain address ran ges. D8 an d/or
D16 devices in the system must be handled by software. Refer to the memory
maps in the MVME197LE, MVME197DP, and MVME197SP Single Board
Computers Programmer ’s Reference Guide.

The MVME197LE contains shared onboard DRAM whose base address is
software-selectable. Both the onboard processor and off-board VMEbus
devices see this local DRAM at base physical address $00000000, as
programmed by the MVME197Bug firmware. This may be changed, by
software, to any other base address. Refer to the MVME197LE, MVME197DP,
and MVME197SP Single Board Computers Programmer’s Reference Guide for
details.

If the MVME197LE tries to access off-board resources in a non-existent
location, and is not the system controller, and if the system does not have a
global bus timeout, the MVME197LE waits forever for the VMEbus cycle to
complete. This would cause the system to hang up. There is only one situation
in which the system might lack this global bus timeout: when the
MVME197LE is not the system controller and there is no global bus timeout
elsewhere in the system.

2-8 User’s Manual

Installation Instructions

Multiple MVME197LE modules may be configured into a single VME card
cage. In general, hardware multiprocessor features are supported.

Other MPUs on the VMEbus can interrupt, disable, communicate with and
determine the operational status of the RISC processor(s). One register of the
GCSR set includes four bits which function as location monitors to allow one
MVME197LE processor to broadcast a signal to other MVME197LE
processors, if any. All eight registers are accessible from any local processor as
well as from the VMEbus.

The MVME197LE provides +12 Vdc power to the Ethernet LAN transceiver
interface through a 1 amp fuse (F2) located on the MVME197LE module. If the
Ethernet transceiver fails to operate, check the fuse. When using the
MVME712M transition module, the yellow LED (DS1) on the MVME712M
front panel lights when LAN power is available, indicating that the fuse is
good.

2

MVME197LE/D2 2-9

Hardware Preparation and Installation

2

2-10 User’s Manual

OPERATING

Introduction

This chapter provides the necessary information to use the MVME197LE
VMEmodule in a system configuration. This includes controls and indicators,
memory maps, and software initialization of the module.

Controls and Indicators

The MVME197LE Single Board Computer has two push-botton switches
(ABORT and RESET) and six LED indicators (FAIL, SCON, RUN, LAN, VME,
and SCSI), all located on the front panel of the module.

ABORT Switch S2

When enabled by software, the front panel ABORT switch (S2) generates an
NMI (Non-Maskable Interrupt) type interrupt at a user-programmable level.
It is normally used to abort program execution and return to the 197Bug
debugger. Refer to the VMEchip2 chapter of the MVME197LE, MVME197D P,
and MVME197SP Single Board Computers Programmer’s Reference Guide for more
information.

INSTRUCTIONS

3

RESET Switch S3

The RESET switch (S3) will reset all the onboard devices and drive the
SYSRESET* signal if the MVME197LE module is the system controller. The
RESET switch (S3) will reset all the onboard devices, with the exception of the
DCAM and ECDM, if the MVME197LE module is not the system controller.
The VMEchip2 generates the SYSREST* signal. The BusSwitch combines the
local reset and the reset switch to generate a loca l board reset. Refer to the Reset

Driver section in the VMEchip2 chapter of the MVME197LE, M VME197DP, and
MVME197SP Single Board Computers Programmer’s Reference Guide for more

information.
The BusSwitch receives the reset switch signal, debounces it and combines

with the reset signal from the VMEchip2 to generate a board reset signal.
The VMEchip2 includes both a global and a local reset driver. When the chip

operates as the VMEbus system controller, the reset driver provides a global
system reset by asserting the VMEbus signal SYSRESET*. A SYSRESET* may
be generated by the RESET switch, a power up reset, a watchdog timeout, or

MVME197LE/D23-1

Operating Instructions

by a control bit in the LCSR. SYSRESET* remains asserted for a t least 200 msec,
as required by the VMEbus specification.

Similarly, the VMEchip2 provides an input signal and a control bit to initiate

3

a local reset operation. By setting a cont rol bit, software can maintain a board
in a reset state, disabling a faulty board from participating in normal system
operation.

The local reset driver is enabled even when the VMEchip2 is not the system
controller. A local reset may be generated by the RESET switch, a power up
reset, a watchdog timeout, a VMEbus SYSRESET*, or a contro l bit in the GCSR.

Front Panel Indicators (DS1-DS6)

The six LEDs on the MVME197LE front panel are: FAIL, SCON, RUN, LAN,
VME, and SCSI.

1. The yellow FAIL LED (DS1) is lit when the BRDFAIL signal line is active.

2. The green SCON LED (DS2) is lit when the VMEchip2 is the VMEbus

system controller.

3. The green RUN LED (DS3) is lit when the MC88110 bus MC* pin is low.

4. The green LAN LED (DS4) lights when the LAN chip is the local

peripheral bus master.

5. The green VME LED (DS5) lights when the board is using the VMEbus or

when the board is accessed by the VMEbus.

6. The green SCSI LED (DS6) lights when the SCSI chip is the local peripheral

bus master.

Memory Maps

There are three points of view for the memory maps: 1) the mapping of all
resources as viewed by the Processor Bus (MC88110 bus), 2) the mapping of
onboard/off-board resources as viewed from the Local Peripheral Bus
(MC68040 compatible bus), and 3) the mapping of onboard resources as
viewed by VMEbus Masters (VMEbus memory map).

Processor Bus Memory Map

Care should be taken, since all three maps are programmable. It is
recommended that direct mapping from the Processor Bus to the Local
Peripheral Bus be used.

3-2 User’s Manual

Memory Maps

The memory maps of MVME197LE devices are provided in the following
tables. Table 3-1 is the entire map from $00000000 to $FFFFFFFF. Many areas
of the map are user-programmable, and suggested uses are shown in the table.
This is assuming no address translation is used between the processor and
local peripheral bus and between the local peripheral bus and VMEbus. The
cache inhibit function is programmable in the MC88110. The onboard I/O
space must be marked cache inhibit and serialized in its page table. Table 3-2
further defines the map for the local devices.

Table 3-1. Processor Bus Memory Map

3

Address

Range

$00000000 - (DRAMSIZE -1) User Programmable

DRAMSIZE - $FF7FFFFF User Programmable

$FF800000 - $FFBFFFFF Flash M em or y D32 4MB N 5
$FFC00000 - $FFEFFFFF reserved --- 3MB --- 4
$FFF00000 - $FFFEFFFF Local Devices

$FFFF0000 - $FFFFFFFF User Programmable

Notes

1. This area is user-programmable. The suggested use is
shown in the table. The DRAM decoder i s programmed
in the DCAM through the ECDM I

Devices

Accessed

(Onboard DRAM)

(VMEbus)

(Refer to next table)

(VMEbus A16)

Port
Size

D64 DRAMSIZE N 1

D32/D16 3GB ? 2,3

D32-D8 1MB Y ---

D32/D16 64KB ? 1,3

Size

2

CBus interface. The

Software

Cache

Inhibit

Processor Bus to Local Peripheral Bus and the Local
Peripheral Bus to Processor Bus decoders are
programmed in the BusSwitch. The Local Peripheral to
VMEbus (master) and VMEbus to Local Peripheral Bus
(slave) decoders are programmed in the VMEchip2.

2. Size is approximate.

3. Cache inhibit depends on devices in area mapped.

4. This area is not decoded. If these locations are accessed
and the local peripheral bus timer is enabled, the cycle
times out and is terminated by a TEA signal.

5. This area is user programmable via the BusSwitch.
Default size is 4 megabytes.

Notes

MVME197LE/D2 3-3

Operating Instructions

The following table focuses on the Local Devices portion of the Memory Map.

Table 3-2. Local Devices Memory Map

3

Address Range Devices Accessed Port Size Size Notes

$FFF00000 - $FFF00FFF BusSwitch D64-D8 4KB 1
$FFF01000 - $FFF01FFF ECDM (DCAM access) --- 4KB 1
$FFF02000 - $FFF02FFF reserved --- 4KB 4
$FFF03000 - $FFF03FFF reserved --- 4KB 4
$FFF04000 - $FFF04FFF reserved --- 4KB 4
$FFF05000 - $FFF05FFF reserved --- 4KB 4
$FFF06000 - $FFF06FFF reserved --- 4KB 4
$FFF07000 - $FFF07FFF User defined --- 4KB 4
$FFF08000 - $FFF3FFFF reserved --- 224KB 4
$FFF40000 - $FFF400FF VMEchip2 (LCSR) D32 256B 1,2,3
$FFF40100 - $FFF401FF VMEchip2 (GCSR) D32-D8 256B 1,2,3
$FFF40200 - $FFF40FFF reserved --- 3.5KB 4,5
$FFF41000 - $FFF41FFF reserved --- 4KB 4
$FFF42000 - $FFF42FFF PCCchip2 D32-D8 4KB 1,2
$FFF43000 - $FFF43FFF reserved --- 4KB 4
$FFF44000 - $FFF44FFF reserved --- 4KB 3
$FFF45000 - $FFF45FFF CD2401 (Serial Comm. Cont.) D16-D8 4KB 1,2
$FFF46000 - $FFF46FFF 82596CA (LAN) D32 4KB 1,2,6
$FFF47000 - $FFF47FFF 53C710 (SCSI) D32/D8 4KB 1,2
$FFF48000 - $FFF4FFFF reserved --- 32KB 4
$FFF50000 - $FFF6FFFF reserved --- 128KB 4
$FFF70000 - $FFF77FFF reserved --- 32KB 4
$FFF78000 - $FFF7FFFF reserved --- 288KB 4
$FFF80000 - $FFFBFFFF DROM (BOOT ROM) --- 256KB 7
$FFFC0000 - $FFFCFFFF MK48T08 (BBRAM,TOD Clk) D32-D8 64KB 1,2
$FFFD0000- $FFFEFFFF reserved --- 128KB 4

Notes

1. For a complete description of the register bits, refer to
the appropriate data sheet for the specific chip. For a
more detailed memory map refer to the detailed
peripheral device memory maps in the MVME197LE,

MVME197DP, and MV ME197SP Sing le Board Comp uters

Programmer’s Reference Guide.

2. Address is the physical address going to the device. It is
after the BusSwitch translation from the MC88110
address to the device seen address.

3-4 User’s Manual

3. Writes to the LCSR in the VMEchip2 must be 32 bits.
LCSR writes of 8 o r 16 bits terminate with a TEA signal.
Writes to the GCSR may be 8, 16, or 32 bits. Reads t o the
LCSR and GCSR may be 8, 16, or 32 bits.

4. This area does not return an acknowledge signal. If the
processor bus timeout timer is enabled, the access times
out and is terminated by a TEA signal.

5. Size is approximate.

6. Port commands to the 82596CA must be written as two
16-bit writes: upper word first and lower word second.

7. DROM (BOOT ROM) appears at $0 following a local
peripheral bus reset. Th e D RO M appears at 0 until the
DR0 bit is cleared in the PCCchip2. In additi on, the
ROM0 bit in the BusSwitch must be cleared before
the DRAM is ac cess ed .

Detailed I/O Memory Maps

Memory Maps

3

Tables 3-3 through 3-14 give the detailed memory maps for the BusSwitch
register, the ECDM CSR register, the DCAM (I
register, the PCCchip2 register, the printer register, the CD2401 Serial Port
register, the Ethernet LAN register, the SCSI Controller register, and the
BBRAM/TOD Clock register.

2

C) register, the VMEchip2

MVME197LE/D2 3-5

Operating Instructions

Table 3-3. BusSwitch Register Memory Map

BusSwitch Base Address = $FFF00000
Offset

3

63 56 55 48 47 32 31 16 15 0

CHIPID CHIPREV GCSR IODATA IODIR

0

8
10
18
20
28
30
38
40
48
50
58
60
68
70
78
80
88
90

PSAR1 PEAR1 PSAR2 PEAR2
PSAR3 PEAR3 PSAR4 PEAR4

PTR1 PTSR1 PTR2 PTSR2

PTR3 PTSR3 PTR4 PTSR4
SSAR1 SEAR1 SSAR2 SEAR2
SSAR3 SEAR3 SSAR4 SEAR4

STR1 STSR1 STR2 STSR2

STR3 STSR3 STR4 STSR4

PAR1 PAR2 PAR3 PAR4 SAR1 SAR2 SAR3 SAR4

BTIMER PADJUST PCOUNT PAL

WPPA WPTPA WPPAT

ROMCR TCTRL1 TCTRL2 LEVEL MASK ISEL0 ISEL1

ABORT CPINT TINT1 TINT2 WPINT PALINT XINT VBASE

TCOMP1 TCOUNT1
TCOMP2 TCOUNT2

GPR1 GPR2
GPR3 GPR4

XCTAGS

100
108
110
118

3-6 User’s Manual

XCCR VECTOR1
VECTOR2 VECTOR3
VECTOR4 VECTOR5
VECTOR6 VECTOR7

Memory Maps

3

MVME197LE/D2 3-7

3

3-8 User’s Manual

Operating Instructions

Table 3-4. ECDM CSR Register Memory Map

Sub-System Me mory C SR Base Address = $FF F01000
Offset/Register:

ECDM0 ECDM1 ECDM2 ECDM3

ADDR/REGISTER ADDR/REGISTER ADDR/REGISTER ADDR/REGISTER ADDR/REGISTER ADDR/REGISTER ADDR/REGISTER ADDR/REGISTER

00 / MEMCON0 01 / ECDMID0 02 / MEMCON1 03 / ECDMID1 04 / MEMCON2 05 / ECDMID2 06 / MEMCON3 07 / ECDMID3

08 / SYNSTAT0 0 9 / E R STAT0 0A / SYNS TAT1 0 B / E R STAT1 0C / SYNSTAT2 0D / ERSTAT2 0E / SYNSTAT3 0F / ER STAT3

10 / I2CON0 11 / I2STAT0 12 / I2CON1 13 / I2STAT1 14 / I2CON2 15 / I2STAT2 16 / I2CON3 17 / I2STAT3

18 / I2DATA0 19 / I2ADDR0 1A / I2DATA1 1B / I2ADDR1 1C / I2DATA2 1 D / I2ADDR2 1E / I2DATA3 1F / I2ADDR3

D64 D56 D55 D48 D47 D40 D39 D32 D31 D24 D23 D16 D15 D8 D7 D0

ECDM register ma p of four ECDM device s in a 64-bit sy stem. The byte offset add ress is shown next to each reg ister.

Memory Maps

Table 3-5. DCAM (I2C) Register Memory Map

DCAM (I2C) Base Address = $C0 (default)
Offset

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

00 00 ID Register
01 01 Version Register
02 02 SL31 SL30 SL29 SL28 SL27 SL26 SL25 DISRAM
03 03 SH31 SH30 SH29 S H28 SH27 SH26 SH25 SCRUB1TIME
04 04 CASCLKSL CASCLK2 CASCLK1 PGMODE ONEBANK DRAMSIZ3 DRAMSIZ2 DRAMSIZ1
05 05 REF7 REF6 REF5 REF4 REF3 REF2 REF1 REF0
06 06 REFTAIL4 REFTAIL3 REFTAIL2 REFTAIL1 REF11 REF10 REF9 REF8
07 07 NOT USED NOT USED RDTAIL5 RDTAIL4 RDTAIL3 RDTAIL2 RDTAIL1 RTCLKSL
08 08 READACK7 READACK6 READACK5 READACK4 READACK3 READACK2 READACK1 INTRRUPT
09 09 NOT USED READOE 6 READOE5 READOE4 READOE3 READOE2 READOE1 NOT USED
0A 10 FECCKSL BREADOE6 BREADOE5 BREADOE4 BREADOE3 BREADOE2 BREADOE1 PCGCLKSL
0B 11 PCHG7 PCHG6 PCHG5 PCHG4 PCHG3 PCHG2 PCHG1 PCHG0
0C 12 SL ECDM5 SLECDM4 SLECDM3 SLECDM2 FLECDM4 FLECDM3 FLECDM2 FLECDM1
0D 13 NOT USED ERAMOE6 ERAMOE5 ERAMOE4 ERAMOE3 ERAMOE2 ERAMOE1 ROECLKSL
0D 14 NOT USED RMWRMOE6 RMWRMOE5 RMWRMOE4 RMWRMOE3 RMWRMOE2 RMWRMOE1 RMWOE5
0F 15 CSRTAIL7 CSRTAIL6 CSRTAIL5 CSRTAIL4 CSRTAIL3 CSRTAIL2 CSRTAIL1 NOT USED
10 16 BWRTTL4 BWRTTL3 BWRTTL2 BWRTTL1 RMWOE4 RMWOE3 RMWOE2 RMWOE1
11 17 SECCLKSL RMWOCKSL BWRITE5 BWRITE4 BWRITE3 BWRITE2 BWRITE1 WRCLKSEL
12 18 NOT USED NOT USED RMW5 RMW4 RMW3 RMW2 RMW1 NOT USED
13 19 RMWTAIL7 RMWTAIL6 RMWTAIL5 RMWTAIL4 RMWTAIL3 RMWTAIL2 RMWTAIL1 RMWTLCSL
14 20 CBRDOE3 CBRDOE2 CBRDOE1 NOT USED C R EADOE3 CREADOE2 CREADOE1 BWRTCSL
15 21 SC9 SC8 SC7 SC6 SC5 SC4 SC3 SC2
16 22 SC17 SC16 SC15 SC14 SC13 S C12 SC11 SC10
17 23 SC25 SC24 SC23 SC22 SC21 S C20 SC19 SC18
18 24 NOT USED SC32 SC31 SC30 SC29 SC28 SC27 SC26
19 25 NOT USED NOT USED NOT USED CBTAIL4 CBTAIL3 CBTAIL2 CBTAIL1 CBTLCKSL
1A 26 CSR7 CSR6 CSR5 CSR4 NOT USED NOT USED NOT USED NOT USED
1B 27 CSR15 CSR14 CSR13 CSR12 CSR11 CSR10 CSR9 CSR8
1C 28 CSR23 CSR22 CSR21 CSR20 CSR19 CSR18 CSR17 CSR16
1D 29 CSR31 CSR30 CSR29 CSR28 CSR27 CSR26 CSR25 CSR24
1E 30 NOT USED NOT USED BRDTAIL5 BRDTAIL4 BRDTAIL3 BRDTAIL2 BRDTAIL1 NOT USED
1F 31

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

3

DCAM registers are only accessible/addressable on the DRAM sub-system I2Cbus through
the ECDM I

2

C interface.

MVME197LE/D2 3-9

Operating Instructions

3

3-10 User’s Manual

MVME197LE/D2 3-11

Table 3-6. VMEchip2 Memory Map

(Sheet 1 of 4)

VMEchip2 LCSR Base Address = $FFF40000
OFFSET:

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

00

04

08 VMEbus SLAVE ADDRESS TRANSLATION ADDRESS 1 VMEbus SLAVE ADDRESS TRANSLATION SELECT 1

0C

10

14

18 LOCAL BUS SLAVE ENDING ADDRESS 2 LOCAL BUS SLAVE STARTING ADDRESS 2

1C

20 LOCAL BUS SLAVE ENDING ADDRESS 4 LOCAL BUS SLAVE STARTING ADDRESS 4

24

(LB)

(LB)

D16

WP

28

EN

EN

2C

(VB) GCSR GROUP ADDRESS

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

LB = Local Bus
(LB) = Local Bus Slave
LV = Local Bus to VMEbus

VMEbus SLAVE ENDING ADDRESS 1 VMEbus SLAVE STARTING ADDRESS 1

VMEbus SLAVE ENDING ADDRESS 2 VMEbus SLAVE STARTING ADDRESS 2

VMEbus SLAVE ADDRESS TRANSLATION ADDRESS 2 VMEbus SLAVE ADDRESS TRANSLATION SELECT 2

(VB)

(VB)

(VB)

(VB)

(VB)

(VB)

(VB)

(VB)

(VB)

SNP

WP

SUP

USR

A32

A24

2

2

2

2

LOCAL BUS SLAVE ENDING ADDRESS 1 LOCAL BUS SLAVE STARTING ADDRESS 1

LOCAL BUS SLAVE ENDING ADDRESS 3 LOCAL BUS SLAVE STARTING ADDRESS 3

LOCAL BUS SLAVE ADDRESS TRANSLAT ION ADDRESS 4 LOCAL BUS SLAVE ADDRESS TRANSLAT ION SELECT 4

(LB)

(LB) AM 4

D16

EN

(LB)

WP
EN

(VB) GCSR

BOARD

ADDRESS

D64

2

2

2

(LB) AM 3

LB

EN4LBEN3LBEN2LBEN1LBI2

BLK

(VB)

PGM

DAT

2

2

2

(LB)

(LB)

D16

WP

EN

EN
LB

LB

I2

EN

WP

LB

I2

I2

SU

PD

(LB) AM 2

LB
I1
EN

D16

(VB)

(VB)

(VB)

(VB)

(VB)

WP
EN

1

A32

1

ROM BANK B

SPEED

(VB)
A24

(XX)

SNP

WP

SUP

1

LB

LB

I1

I1

WP

USR

1

1

(LB)

(LB)

D16

EN

LB

ROM

I1

SIZE

SU

(XX)

VB = VMEbus
(VB) = VMEbus Slave
(XX) = Not Used on the MVME197 Series

(VB)

(VB)

D64

BLK

1

1

1

(LB) AM 1

ROM BANK A

(VB)
PGM

1

SPEED

(XX)

(VB)
DAT

1

Memory Maps

3

Operating Instructions

3

3-12 User’s Manual

MVME197LE/D2 3-13

Table 3-6. VMEchip2 Memory Map (Continued)

(Sheet 2 of 4)

VMEchip2 LCSR Base Address = $FFF40000
OFFSET:

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

30

34

38

3C

40 DMAC BYTE COUNTER

44

INTERRUPT

48

1

SIGNAL

IRQ
CLR

4C

IRQ

STAT

VMEbus

INTERRUPT

LEVEL

VB

DMAC

TO

TIME OFF

50 TICK TIMER 1 COMPARE

54

58 TICK TIMER 2 COMPARE

5C

SCON SYS

60

FAIL

BRD
FAIL

STAT

PURS
STAT

CLR

PURS

STAT

BRD
FAIL
OUT

RST

SW
EN

SYS
RSTWDCLR

64

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

LB = Local Bus
(LB) = Local Bus Slave
LV = Local Bus to VMEbus

ROM0

(XX)

VMEbus INTERRUPT VECTOR

TIME ON

WD

WD
CLR
CNT

TO

STAT

STAT

DMAC TB

SNP MODE

DMAC

WD

BDF

EN

SPRAM
SPEED

(XX)

DMAC LOCAL BUS ADDRESS COUNTER

DMAC VMEbus ADDRESS COUNTER

DMAC TABLE ADDRESS COUNTER

WD

SYS

LRST

ROBN

(XX)

MODE
DMAC

VMEbus
GLOBAL

TIMEOUT

TICK TIMER 1 COUNTER

TICK TIMER 2 COUNTER

WD

WD

RST

EN

EN

PRESCALER COUNTER

VB = VMEbus
(VB) = VMEbus Slave
(XX) = Not Used on the MVME197 Series

LV

INTE

VMEbus
ACCESS
TIMEOUT

LV

DHBLVDWB

DMAC LB

SNP

MODE

DMAC

INTERRUPT

COUNTER

TIMEOUT

OVERFLOW
COUNTER 2

LV

FAIRLVRWDLVREQUEST

DMAC

DMAC

DMAC

VME

LB

TVME

INC

INC

MPU

MPU

CLR

LB
EN

LOCAL

BUS

PERR

WATCHDOG TIMEOUT PRESCALER ADJUST

CLR
OVF

2

LEVEL

DMAC

D16

MPU

MPU

LB

OB

COC2CNT

EN

DMAC

DMACENDMAC

HALT

DMAC

DMAC

BLK

TR

MPU

DMAC

LB

LB
TO

2

DMAC

FAIR

DMAC

LB
OB

DMAC

LB
TO

DMAC
RELM

DMAC

LB

ERR

CLR
OVF

1

TBL

DMACAMDMACAMDMACAMDMACAMDMACAMDMAC

BLK

TR

DMAC

LB

LB

EN

PERR

OVERFLOW
COUNTER 1

DMAC

REQUEST

LEVEL

DMAC

VME
ERR

COC1CNT

AM

DMAC
DONE

EN

1

Memory Maps

3

Operating Instructions

3

3-14 User’s Manual

MVME197LE/D2 3-15

Table 3-6. VMEchip2 Memory Map (Continued)

(Sheet 3 of 4)

VMEchip2 LCSR Base Address = $FFF40000
OFFSET:

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

AC

AB

SYS

MWP

PE

IRQ1

TIC

TIC

VME

DMAC

GCSR

GCSR

GCSR

GCSR

GCSR

GCSR

LB

LB

LB

LB

LB

LB

LB

LB

FAIL

SW

FAIL

ERR

IRQ

EDGE

TIM2

TIM1

IACK

IRQ

SIG3

SIG2

SIG1

SIG0

LM1

LM0

SW7

SW6

SW5

SW4

SW3

68

IRQ

IRQ

IRQ

EN

IRQ

IRQ

6C

31

IRQ

EN

EN

IRQ

IRQ

30

29

70

CLR

CLR

CLR

IRQ

30

29

ACFAIL

IRQ LEVEL

VMEbus

ACKNOWLEDGE

IRQ LEVEL

SW7

IRQ LEVEL

SPARE

IRQ LEVEL

CLR
IRQ

7C

74

78

80

84

88

IRQ

31

VECTOR BASE

IRQ

REGISTER 0

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

LB = Local Bus
(LB) = Local Bus Slave
LV = Local Bus to VMEbus

IRQ

IRQ

IRQ

EN

EN

EN

IRQ

IRQ

27

CLR

27

VECTOR BASE

REGISTER 1

26

IRQ

26

IRQ LEVEL

IRQ LEVEL

IRQ LEVEL

IRQ LEVEL

IRQ

CLR

IRQ

ABORT

DMAC

SW6

VMEbus

IRQ7

28

CLR
IRQ

28

IRQ

EN

EN

IRQ

IRQ

25

24

CLR

CLR

IRQ

IRQ

25

24

MST
IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

EN

EN

EN

EN

EN

EN

EN

IRQ

IRQ

IRQ

IRQ

23

22

21

CLR

CLR

22

SYSFAIL

IRQ LEVEL

IRQ LEVEL

IRQ LEVEL

VMEbus

IRQ LEVEL

IRQ

21

GCSR

SIG 3

SW5

IRQ6

AC

FAIL

LEVEL

CLR
IRQ

ABORT
LEVEL

IRQ

23

SYS
FAIL

EN

LEVEL

IRQ

20

19

CLR

CLR

IRQ

IRQ

20

19

GENERAL
PURPOSE

I/O ENABLE

IRQ

18

17

CLR
IRQ

18

17

MASTER WRITE

POST ERROR

IRQ LEVEL

GCSR

SIG 2

IRQ LEVEL

SW4

IRQ LEVEL

VMEbus

IRQ5

IRQ LEVEL

CLR

IRQ

IRQ

EN

IRQ

16

SET

IRQ

CLR

IRQ

16

EN
15

15

15

IRQ

EN

EN

IRQ

IRQ

14

13

SET

SET

IRQ

IRQ

14

13

CLR

CLR

IRQ

IRQ

14

13

PARITY ERROR

IRQ LEVEL

GCSR
SIG 1

IRQ LEVEL

SW3

IRQ LEVEL

VMEbus

IRQ4

IRQ LEVEL

GENERAL

PURPOSE

I/O OUTPUT

SET
IRQ

CLR

IRQ

VB = VMEbus
(VB) = VMEbus Slave
(XX) = Not Used on the MVME197 Series

SW2

IRQ

IRQ

12

12

12

IRQ

SET
IRQ

CLR
IRQ

EN

11

11

11

IRQ

EN

IRQ

10

SET

IRQ

10

CLR

IRQ

10

EDGE-SENSITIVE

IRQ LEVEL

GCSR

IRQ LEVEL

IRQ LEVEL

VMEbus

IRQ LEVEL

GENERAL

PURPOSE

I/O INPUT

EN
IRQ

SW1

IRQ

EN

IRQ

SET
IRQ

CLR
IRQ

IRQ1

SIG 0

SW2

IRQ3

SPARE VME

SW0

IRQ

EN

IRQ

9

8

SET
IRQ

9

8

CLR
IRQ

9

8

IRQ

EN

7

IRQ7

IRQ

EN

IRQ

6

TICK TIMER 2

IRQ LEVEL

IRQ LEVEL

IRQ LEVEL

IRQ LEVEL

VME

VME

VME

IRQ6

IRQ5

IRQ

EN

IRQ

5

GCSR

LM 1

SW1

VMEbus

IRQ2

GENERAL PURPOSE INPUT

VME

IRQ4

IRQ3

IRQ

IRQ

IRQ

EN

EN

IRQ

IRQ

IRQ

4

3

EN

2

TICK TIMER 1

VME
IRQ2

IRQ

EN

IRQ

1

IRQ LEVEL

GCSR

LM 0

IRQ LEVEL

SW0

IRQ LEVEL

VMEbus

IRQ1

IRQ LEVEL

VME
IRQ1

IRQ

EN

IRQ

0

Memory Maps

3

Operating Instructions

3

3-16 User’s Manual

MVME197LE/D2 3-17

Table 3-6. VMEchip2 Memory Map (Continued)

(Sheet 4 of 4)

VMEchip2 GCSR Base Address = $FFF40100

L V D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

00

LM3 LM2 LM1 LM0 SIG3 SIG2 SIG1 SIG0 RST ISF BF SCON

42

84

C6

10 8

14 A

18 C

1C E

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

NOTES: L = Local Bus Offset.

CHIP REVISION CHIP ID

GENERAL PURPOSE CONTROL AND STAT US REGISTER 0

GENERAL PURPOSE CONTROL AND STAT US REGISTER 1

GENERAL PURPOSE CONTROL AND STAT US REGISTER 2

GENERAL PURPOSE CONTROL AND STAT US REGISTER 3

GENERAL PURPOSE CONTROL AND STAT US REGISTER 4

GENERAL PURPOSE CONTROL AND STAT US REGISTER 5

V = VMEbus Offset.

SYS

FL

Memory Maps

3

Operating Instructions

3

3-18 User’s Manual

MVME197LE/D2 3-19

Table 3-7. PCCchip2 Memory Map

PCCchip2 LCSR Base Address = $FFF42000
OFFSET:

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

00

04

08

0C

10

14

GPI

GPI

PLTY

E/L*

18

1C

CHIP ID CHIP REVISION DR0

PRESCALER COUNT PRESCALER CLOCK ADJUST

GPI

GPI

GPI

INT

IEN

ICLR

SCC

SCC

RTRY

PAR

ERR

ERR

GPI

IRQ LEVEL GPI GIOE GPO

SCC

SCC

EXT

ERR

LTO

ERR

SCC

SCLR

SCC

MDM

SCC

MDM

SCC

MDM

SCC MODEM

IRQ LEVEL

TIC TIMER 1 COMPARE

TIC TIMER 1 COUNTER

TIC TIMER 2 COMPARE

TIC TIMER 2 COUNTER

OVERFLOW
COUNTER 2

TIC2

INT

SCC

TX

IRQ

20

24 SCC TRANSMIT PIACK SCC RECEIVE PIACK

LAN

LAN

LAN

LAN

LAN

28

2C

PRTR

PRTR

PRTR

ACK

30

ACK

E/L*

PRTR

BSY
E/L*

ACK

PRTR

BSY

PLTY

PRTR

BSY

34

PLTY

PAR
ERR

ERR

SCSI

SCSI
PAR
ERR

ACK

IEN

BSY

IEN

PRTR

ACK
ICLR

PRTR

BSY
ICLR

ERR

PRTR

INT

PRTR

INT

EXT

EXT

IRQ LEVEL

IRQ LEVEL

LTO

ERR
SCSI

LTO

ERR

PRTR ACK

PRTR BSY

LAN

SCLR

SCSI

SCLR

PRTR

FLT

PLTY

PRTR

FLT

E/L*

PRTR

FLT
INT

PRTR

FLT
IEN

PRTR

FLT

ICLR

PRTR FAULT

IRQ LEVEL

PLTY

PRTR

SEL

PLTY

PRTR

ANY

LAN

E/L*

INT

PRTR

PRTR

PRTR

SEL

SEL

E/L*

INT

INT

PRTR

38 CHIP SPEED PRINTER DATA

3C

D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

TIC2

IEN

SCC

TX

IEN

LAN

IEN

SEL
IEN

ACK

TIC2
ICLR

SCC

TX

AVEC

LAN
ICLR

PRTR

SEL

ICLR

PRTR

FLT

CPU

MSTR

040

INT
EN

CLR

COUN

OVF

EN

2

TIC TIMER 2

IRQ LEVEL

SCC TRANSMIT

IRQ LEVEL

LAN

IRQ LEVEL

PRTR SEL

IRQ LEVEL

PRTR

PRTRPEPRTR

SEL

INTERRUPT

IPL LEVEL

FAST

BRAM VECTOR BASE

COUN

2

EN

BSY

OVERFLOW
COUNTER 1

2

SCC
SC1

LAN
SC1

PRTR

PLTY

TIC1

TIC1

INT

SCC

SCC
IRQ

LAN
ERR

INT

SCSI

IRQ

PRTR

PE

PE
INT

SCC

SCC MODEM PIACK

LAN
ERR

SCSI

PRTR

PRTR

DAT

ENBL

SC2

LAN
SC2

PRTR

PE

E/L*

CLR
OVF

1

TIC1

ICLR

SCC

AVEC

LAN
ERR

ICLR

PRTR

PE

ICLR
PRTR

INP

TIC TIMER 1

SCC RECEIVE

PRTR

STB

INTERRUPT

MASK LEVEL

IEN

IEN

IEN

IEN

PE
IEN

COUN

EN

1

IRQ LEVEL

IRQ LEVEL

LAN ERR

IRQ LEVEL

SCSI INT

IRQ LEVEL

PRTR PE

IRQ LEVEL

PRTR

FAST
ASTB

COUN

EN

PRTR

MAN
STB

1

Memory Maps

3

Operating Instructions

Table 3-8. Printer Memory Map

Printer ACK Interrupt Control Register $FFF42030

3

BIT 31 30 29 28 27 26 25 24

NAME PLTY E/L* INT IEN ICLR IL2 IL1 IL0

Printer FAULT Interrupt Control Register $FFF42031

BIT 23 22 21 20 19 18 17 16

NAME PLTY E/L* INT IEN ICLR IL2 IL1 IL0

Printer SEL Interrupt Control Register $FFF42032

BIT 15 14 13 12 11 10 9 8

NAME PLTY E/L* INT IEN ICLR IL2 IL1 IL0

Printer PE Interrupt Control Register $FFF42033

BIT 76543210

NAME PLTY E/L* INT IEN ICLR IL2 IL1 IL0

Printer BUSY Interrupt Control Register $FFF42034

BIT 31 30 29 28 27 26 25 24

NAME PLTY E/L* INT IEN ICLR IL2 IL1 IL0

Printer Input Status Register $FFF42036

BIT 15 14 13 12 11 10 9 8

NAME PINT ACK FLT SEL PE BSY

Printer Port Control Register $FFF42037

BIT 76543210

NAME DOEN INP STB FAST MAN

Printer Data Register (16 bits) $FFF4203A

BIT 15-0

NAME PD15-PD0

Printer memory map is part of the PCCchip2 (refer to PCCchip2 Memory Map).

3-20 User’s Manual

Memory Maps

Table 3-9. Cirrus Logic CD2401 Serial Port Memory Map

Base Address Is $FFF45000

Cirrus Logic CD2400 Memory Map Offsets Size Access

Global Firmware Revision Code Register (GFRCR) 8 1 B R
Transmit FIFO Transfer Count (TFTC) 8 0 B R
Modem End Of Interrupt Register (MEOIR) 86 B R/W
Transmit End Of Interrupt Register (TEOIR) 85 B R/W
Receive End Of Interru pt Register (REOIR) 84 B R/W

Modem (/Timer) Interrupt Status Register (MISR) 8B B R
Transmit Interrupt Status Register (TISR) 8A B R
Receive Interrupt Status Register (RISR) 88 W R

(NOTE)
Receive Interrupt Status Register low (RISRl) 89 B R
Receive Interrupt Status Register high (RISRh) 88 B R
Timer Period Register (TPR) DA B R/W
Priority Interrupt level Register 1 (PILR1) E3 B R/W
Priority Interrupt level Register 2 (PILR2) E0 B R/W
Priority Interrupt level Register 3 (PILR3) E1 B R/W
Channel Access Register (CAR) EE B R/W
Receive Data Register (RDR) F8 B R
Transmit Data Register (TDR) F8 B W

3

Local Interrupting Channel Register (LICR) 26 B R/W
Local Interrupt Vector Register (LIVR) 09 B R/W
Channel Command Register (CRR) 13 B R/W
Special Transmit Command Register (STCR) 12 B R/W
Interrupt Enable Register (IER) 11 B R/W
Channel Option Register 1 (COR1) 10 B R/W
Channel Option Register 2 (COR2) 17 B R/W
Channel Option Register 3 (COR3) 16 B R/W
Channel Option Register 4 (COR4) 15 B R/W
Channel Option Register 5 (COR5) 14 B R/W
Channel Mode Register (CMR) 1B B R/W

This is a 16-bit register.

MVME197LE/D2 3-21

Operating Instructions

Table 3-10. 82596CA Ethernet LAN Memory Map

82596CA Ethernet LAN

Directly Accessible Registers

3

Data Bits

Address D31 D16 D15 D0

$FFF46000 Upper Command Word Lower Command Word
$FFF46004 MPU Channel Attention (CA)

Notes

1. Refer to the MPU Port and MPU Channel Attention
registers in the PCCchip2 chapter of the MVME197LE,
MVME197DP, and MVME197SP Single Board

Computers Programmer’s Reference Guide.

2. After reset you must write the System Configuration
Pointer to the command registers prior to writing to the
CPU Channel Attention register. Writes to the System
Configuration Pointer must be upper word first, lower
word second.

3-22 User’s Manual

Memory Maps

Table 3-11. 53C710 SCSI Memory Map

53C710 Register Address Map Base Address is $FFF47000

Big SCRIPTs Mode

Endian and Little

Mode Endian Mode

00 SIEN SDID SCNTL1 SCNTL0 00
04 SOCL SODL SXFER SCID 04
08 SBCL SBDL SIDL SFBR 08

0C SSTAT2 SSTAT1 SSTAT0 DSTAT 0C

10 DSA 10
14 CTEST3 CTEST2 CTEST1 CTEST0 14
18 CTEST7 CTEST6 CTEST5 CTEST4 18

1C TEMP 1C

20 LCRC CTEST8 ISTAT DFIFO 20
24 DCMD DBC 24
28 DNAD 28

2C DSP 2C

30 DSPS 30
34 SCRATCH 34
38 DCNTL DWT DIEN DMODE 38

3C ADDER 3C

3

Note

Accesses may be 8-bit or 32-bit, but not 16-bit.

Table 3-12. MK48T08 BBRAM, TOD Clock Memory Map

Address Range Description Size (Bytes)

$FFFC0000 - $FFFC0 FFF User Area 4096
$FFFC1000 - $FFFC10FF Networking Area 256
$FFFC1100 - $FFFC16F7 Operating System Area 1528
$FFFC16F8 - $FFFC1EF7 Debugger Area 2048
$FFFC1EF8 - $FFFC1FF7 Configuration Area 256
$FFFC1FF8 - $FFFC1FFF TOD Clock 8

MVME197LE/D2 3-23

Operating Instructions

Table 3-13. BBRAM Configuration Area Memory Map

Address Range Description Size (Bytes)

3

$FFFC1EF8 - $FFFC1EFB Version 4
$FFFC1EFC - $FFFC1F07 Serial Number 12
$FFFC1F08 - $FFFC1F17 Board ID 16
$FFFC1F18 - $FFFC1F27 PWA 16
$FFFC1F28 - $FFFC1F2B Speed 4
$FFFC1F2C - $FFFC1F33 Ethernet Address 8
$FFFC1F34 - $FFFC1FF6 Reserved 195
$FFFC1FF7 Checksum 1

Table 3-14. TOD Clock Memory Map

Data Bits

Address D7 D6 D5 D4 D3 D2 D1 D0 Function

$FFFC1FF8 WRS----------CONTROL
$FFFC1FF9 ST -- -- -- -- -- -- -- SECONDS 00

$FFFC1FFA x--------------MINUTES00

$FFFC1FFB xx------------HOUR 00
$FFFC1FFC x x x x x -- -- -- DAY 01
$FFFC1FFD x x FT -- -- -- -- -- DATE 01

$FFFC1FFE x x x -- -- -- -- -- MONTH 01

$FFFC1FFF ----------------YEAR 00

Notes

ST = Stop Bit S = Sign Bit
W = Write Bit FT = Frequency Test
R = R ead Bit x = Unused

-- = Data Bit

3-24 User’s Manual

BBRAM, TOD Clock Memory Map

The MK48T08 BBRAM (also called Non-Volatile RAM or NVRAM) is divided
into six areas as shown in Table 3-12. The first five areas are defined by
software, while the sixth area, the time-of-day (TOD) clock, is defined by the
chip hardware. The first area is reserved for user data. The second area is used
by Motorola networking software. The third area is used by the SYSTEM V/88
operating system. The fourth area is used by the MVME197 board debugger.
The fifth area, detailed in Table 3-13, is the configuration area. The sixth area,
the TOD clock, detailed in Table 3-14, is defined by the chip hardware.

The data structure of the configuration bytes starts at $FFFC1EF8 and is as
follows.

struct config_rom {

char version[4];
char serial[12];
char id[16];
char pwa[16];
char speed[4];
char ethernet_adr[8];
char reserved[195];
char cksum[1];

}

Memory Maps

3

The fields are defined as follows:

1. Four bytes are reserved for the revision or version of this structure. This
revision is stored in ASCII format, with the first two bytes being the major
version numbers and the last two bytes being the minor version numbers.
For example, if the version of a structure is 4.6, this field contains:

0460

2. Twelve bytes are reserved for the serial number of the board in ASCII
format. For example, this field could contain:

000000470476

3. Sixteen bytes are reserved for the board ID in ASCII format. For example,
for a MVME197LE module, this field contains:

MVME197LE

(The nine characters are f ollowed by seven blank s.)

MVME197LE/D2 3-25

Operating Instructions

4. Sixteen bytes are reserved for the printed wiring assembly (PW A) n umber
assigned to this board in ASCII format. This includes the 01-W prefix. This
is for the main logic board if more than one board is required for a set.

3

Additional boards in a set are defined by a structure for that set. For
example, for a 32 megabyte, 50 MHz MVME197LE boar d at revi sion A, the
PWA field contains:

01-W3869B03A

(The 12 characters are followe d by four blanks.)

5. Four bytes contain the speed of the board in MHz. The first two bytes are
the whole number of MHz and the second two bytes ar e fractions of MHz .
For example, for a 50 MHz board, this field contains:

5000

6. Eight bytes are reserved for the Ethernet address. The a ddre ss is stored in
hexadecimal format, with the last two bytes not used. (Refer to the Ethernet
Interface section for a more detailed description). If the board does not
support Ethernet, this field is filled with zeros.

7. Growth space (195 bytes) is reserved. This pads the structure to an even
256 bytes. Board-specific items, such as mezzanine board PWA numbers,
may go here.

8. The final one byte of the area is reserved for a checksum (as defined in the
MVME197BUG 197Bug Debugg ing Package Us er’ s M anual ) f or security and
data integrity of the configuration area of the NVRAM. This data is stored
in hexadecimal format.

VMEbus Memory Map

This section describes the mapping of local resources as viewed by VMEbus
masters.

VMEbus Accesses to the Local Peripheral Bus

The VMEchip2 includes a user-programmable map decoder for the VMEbus
to local peripheral bus interface. The map decoder allows the user to program
the starting and ending address and the modifiers the MVM E197 re sponds to.

VMEbus Short I/O Memory Map

The VMEchip2 includes a user-programmable map decoder for the GCSR
(Global Control and Status Registers). The GCSR map decoder allows the user
to program the starting address of the GCSR in the VMEbus short I/O space.

3-26 User’s Manual

Software Initiali za tion

Most functions that have been done with switches or jumpers on other
modules are done by setting control registers on the MVME197LE. At power­up or reset, the FLASH memory that contains the 197Bug debugging package
sets up the default values of many of these registers.

Specific programming details may be determined by study of the MC88110
Second Generation RISC Microprocessor User’s Manual. Then check the details of
all the MVME197LE onboard registers as given in the MVME197LE,

MVME197DP, and MVME197S P Single Board Computer s Programmer’s Refe rence
Guide.

Multi-MPU Programming Considerations

Good programming practice dictates that only one MPU at a time have control
of the MVME197LE control registers.Of particular note are:

registers that modify the address map;
registers that require two cycles to access; and
VMEbus interrupt request registers.

Local Reset Operation

Software Initialization

3

Local reset (LRST) is a subset of system reset (SRST). Local reset can be
generated five ways: by expiration of the watchdog timer, by pressing the
front panel RESET switch (if the system controller function is disabled), by
asserting a bit in the board control register in the GS CR, by SY SRES ET*, or by
power-up reset.

Note

MVME197LE/D2 3-27

The GCSR allows a VMEbus master to reset the local bus.
This feature is very dangerous and should be used with
caution. The local reset feature is a partial system reset, not
a complete system reset such as power-up reset or
SYSRESET*. When the local bus reset signal is asserted, a
local bus cycle may be aborted. The VMEchip2 is connect ed
to both the local peripheral bus and the VMEbus and if the
aborted cycle is bound for the VMEbus, erratic operation
may result. Communications between the local processor
and a VMEbus master should use interrupts or mailbox
locations; reset should not be used in normal
communications. Reset should be used only when the local
processor is halted or the local peripheral bus is hung and
reset is the last resort.

Operating Instructions

Any VMEbus access to the MVME197LE while it is in the reset state is ignored.
If a global bus timer is enabled, a bus error is generated.

3

3-28 User’s Manual

FUNCTIONAL

DESCRIPTION

Introduction

This chapter provides a block diagram level description of the MVME197LE
Single Board Computer. The functional description provides an overview of
the module, followed by a detailed description of several blocks of the module.
The block diagram for the MVME197LE is illustrated in Figure 4- 1.

Descriptions of the other blocks of the MVME197LE module, including
programmable registers in the ASICs and peripheral chips, are given in the

MVME197LE, MVME197DP, and MVME197SP Single Board Computers

Programmer’s Reference Guide. Refer to it for the rest of the functional
description of the MVME197LE module.

MVME197LE Functional Description

The MVME197LE module is a high functionality VMEbus single board
computer based on the MC88110 second generation RISC microprocessor. The
MVME197LE has 32/64MB of DRAM, 1MB of F LASH memory, 128/ 256KB of
BOOT ROM, 8KB of static RAM (with battery backup), a time of day clock
(with battery backup), an Ethernet transceiver interface, fo ur serial ports with
EIA-232-D interface, six tick timers, a watchdog timer, a SCSI bus interface
with DMA (Direct Memory Access), a Centronics printer port, an A16/A24/
A32/D8/D16/D32 VMEbus master/slave interface, and a VMEbus system
controller.

4

Data Bus Structure

The local data bus on the MVME197LE module is designed to accommodate
the various 8-bit, 16-bit, and 32-bit devices that reside on the module. Refer to
the MVME197LE, MVME197DP, and MVME197SP Single Board Computers

Programmer’s Reference Guide and to the specific sections of this user’s manual
for each device to determine its port size, the da ta bus connection, and any
restrictions that apply when accessing the specific device.

MC88110 MPU

The MVME197LE is based on the MC88000 family and uses one MC88110
RISC microprocessor unit. Refer to the MC88110 Second Generation RISC

Microprocessor User’s Manual for more information.

MVME197LE/D24-1

Functional Description

4

4-2 User’s Manual

MVME197LE/D2 4-3

MC88110

MUX Address

Mezzanine

Port

Address 32

Address Bus

PROCESSOR

BUS

Data Bus

Data 64

DCAM

ECDM

(X4)

RAS, CAS

Data

Bus

256

Memory Array

32/64 MB

Address Bus

Data Bus

VMEbus

(VMEchip2)

Address 32

LAN

82596CA

BusSwitch

I2CBus

Data 32

LOCAL PERIPHERAL

Flash

Memory

SCSI -II

NCR53710

Figure 4-1. MVME197LE Block Diagram

PCCchip2

I2C EEPROM

MVME197LE Functional Description

BUS

NVRAM/RTC

BOOT

ROM

4 Serial Ports

CL-CD2401

4

Functional Description

BOOT ROM

Currently a socket (socket will be removed from module in later board
revisions) for a 32-pin PLCC/CLCC ROM/EPROM referred to as BOOT ROM
or DROM (Download ROM) is provided. It is organized as a 128K x 8 device,
but as viewed from the processor it looks like a 16K x 64 memory. This
memory is mapped starting at location $FFF80000, but after a local reset it is

4

also mapped at location 0, providing a reset vector and bootstrap code for the
processor. The DR0 bit in the General Control Register (GCR) of the PCCchip2
must be cleared to disable the BOOT ROM memory map at 0.

FLASH Memory

Up to 1MB of FLASH memory is available on the board. FLASH memory
works like EPROM, but can be erased and reprogrammed by software. It is
organized as 32 bits wide, but to the processor it looks as 64 bits wide. It is
mapped at location $FF800000. Reads can be of any size, including burst
transfers, but writes are always 32 bits wide, regardless of the size specified for
the transfer. For this reason, software should only use 32-bit write transfers.
This memory is controlled by the BusSwitch, and the memory size, access
time, and write enable capability can be programmed via the ROM Control
Register (ROMCR) in the BusSwitch. The FLASH memory can be accessed
from the processor bus only. It is not accessible from the local peripheral bus
or VMEbus.

Onboard DRAM

The MVME197LE onboard DRAM (2 banks of 32MB memory, one optionally
installed) is sized at 32MB using 1M x 4 devices and configured as 256 bits
wide. The DRAM is four-way interleaved to efficiently support cache burst
cycles. The DRAM is controlled by the DCAM and ECDM, and the map
decoders in the DCAM can be programmed through the I
ECDM to accommodate different base address(es) and sizes. The onboard
DRAM is not reset by a local peripheral bus reset. Refer to the DCAM and
ECDM chapters in the MVME197LE, MVME197DP, and MVME197SP Single
Board Computers Programmer’s Reference Guide for detailed programming
information.

2

Cbus interface in the

Battery Backup RAM and Clock

The MK48T08 RAM and clock chip is used on the MVME197LE. This chip
provides a time of day clock, oscillator, crystal, power fail detection, memory
write protection, 8KB of RAM, an d a battery in one 28-pin package. The clock
provides seconds, minutes, hours, day, date, month, and year in BCD 24-hour

4-4 User’s Manual

format. Corrections for 28-, 29-, (leap year) and 30-day months are
automatically made. No interrupts are generated by the clock. The MK48T08
is an 8-bit device; however the interface provided by the PCCchip2 supports
8-, 16-, and 32-bit accesses to the MK48T08. Refer to the PCCchip2 chapter in
the MVME197LE, MVME197DP, and MVME197SP Single Board Computers
Programmer’s Reference Guide and to the MK48T08 data sheet for detailed
programming information.

VMEbus Inte rface

The local peripheral bus to VMEbus interface, the VMEbus to local peripheral
bus interface, and the local-VMEbus DMA controller functions on the
MVME197LE are provided by the VMEchip2. The VMEchip2 can also provide
the VMEbus system controller functions. Refer to the VMEchip2 chapter in the

MVME197LE, MVME197DP, and MVME197SP Single Board Computers
Programmer’s Reference Guide for detailed programming information.

I/O Interfaces

The MVME197LE provides onboard I/O for many system applications. The
I/O functions include serial ports, a printer port, an Ethernet transceiver
interface, and a SCSI mass storage interface.

MVME197LE Functional Description

4

Serial Port Interface

The CD2401 serial controller chip (SCC) is used to implement the four serial
ports. The serial ports support the standard baud rates (110 to 38.4K baud).
Serial port 4 also supports synchronous modes of operation.

The four serial ports are different functionally because of the limited number
of pins on the I/O connector.

Serial port 1 is a minimum function asynchronous port. It uses RXD, CTS,
TXD, and RTS.

Serial ports 2 and 3 are full function asynchronous ports. They use RXD,
CTS, DCD, TXD, RTS, and DTR.

Serial port 4 is a full function asynchronous or synchronous port. It can
operate at synchronous bit rates up to 64k bits per second. It uses RXD,
CTS, DCD, RTS, and DTR. It also interfaces to the synchronous clock
signal lines.

Refer to the MVME197LE, MVME197DP, and MVME197SP Single Board
Computers Prog rammer’s Refe rence Guide for drawings of the se rial port interface
connections.

MVME197LE/D2 4-5

Functional Description

All four serial ports use EIA-232-D drivers and receivers located on the main
board, and all the signal lines are routed to the I/O connector. The
configuration headers are located on the MVME712X transition board. An
external I/O transition board such as the MVME712X should be used to
convert the I/O connector pinout to industry-standard connectors.

The interface provided by the PCCchip2 allows the 16-bit CD2401 to appear at

4

Printer Interface

contiguous addresses; however, accesses to the CD2401 must be 8 or 16 bits.
32-bit accesses are not permitted. Refer to the CD2401 data sheet and to the
PCCchip2 chapter in the MVME197L E, MV ME197DP, and MV ME197S P Sing le
Board Computers Programmer’s Reference Guide for detailed programming
information.

The CD2401 supports DMA operations to local memory. Because the CD2401
does not support a retry operation necessary to break VMEbus lo ck conditions,
the CD2401 DMA controllers should not be programmed to access the
VMEbus. The hardware does not restrict the CD2401 to onboard DRAM.

The MVME197LE has a Centronics-compatible printer interface. The printer
interface is provided by the PCCchip2. Refer to the PCCchip2 chapter in the

MVME197LE, MVME197DP, and MVME197SP Single Board Computers
Programmer’s Reference Guide for detailed programming information and for

drawings of the printer port interface connections.

Ethernet Interface

The 82596CA is used to implement the Ethernet transceiver interface. The
82596CA accesses local RAM using DMA operations to perform its norm al
functions. Because the 82596CA has small internal buffers and the VMEbus
has an undefined latency period, buffer overrun may occur if the DMA is
programmed to access the VMEbus. Therefore, the 82596CA should not be
programmed to access the VMEbus.

Every MVME197LE module is assigned an Ethernet Station Address. This
address is $08003E2XXXXX, where XXXXX is the unique 5-nibble number
assigned to the board (i.e., every MVME197LE has a different value for
XXXXX).

The Ethernet Station Address is displayed on a label attached to the VMEbus
P2 connector. In addition, the eight bytes including the Ethernet address are
stored in the configuration area of the BBRAM, with the two lower bytes of
those set to 0. That is, 08003E2XXXXX0000 is stored in the BBRAM. At an
address of $FFFC1F2C, the upper four bytes (08003E2X) can be read. At an
address of $FFFC1F30, the lower four bytes (XXXX0000) can be read. Refer to

4-6 User’s Manual

the BBRAM, TOD Clock memory map description in the Operating Instructio ns
chapter of this manual. The MVME197LE debugger has the capability to
retrieve or set the Ethernet address.

If the data in the BBRAM is lost, the user should use the number on the
VMEbus P2 connector label to restore it. Refer to the MVME197BUG 197Bug
Debugging Package User’s Manual.

The Ethernet transceiver interface is located on the MVME197LE main
module, and the industry standard connector is located on the MVME712X
transition module.

Support functions for the 82596CA are provided by the PCCchip2. Refer to the

82596CA LAN Coprocessor User’s Manual and to the PCCchip2 chapter in the
MVME197LE, MVME197DP, and MVME197SP Single Board Computers
Programmer’s Reference Guide for detailed programming information.

SCSI Interface

The MVME197LE provides for mass storage subsystems through the industry­standard SCSI bus. These subsystems may include hard and floppy disk
drives, streaming tape drives, and other mass storage devices. The SCSI
interface is implemented using the NCR 53C710 SCSI I/O controller.

Support functions for the 53C710 are provided by the PCCchip2. Refer to the

NCR 53C710 SCSI I/O Processor Data Manual and to the PCCchip2 chapter in the
MVME197LE, MVME197DP, and MVME197SP Single Board Computers
Programmer’s Reference Guide for detailed programming information.

MVME197LE Functional Description

4

SCSI Termination

The system configurer must ensure that the SCSI bus is terminated properly.
On the MVME197LE, the terminators are located on the P2 transition board.
The +5V power to the SCSI bus termination resistors is provided by the P2
transition board.

Peripheral Resources

The MVME197LE includes many resources for the local processor. These
include tick timers, software programmable hardware interrupts, watchdog
timer, and local peripheral bus timeout.

Programmable Tick Timers

Six 32-bit programmable tick timers with 1 µsec resolution are provided, two
in the BusSwitch, two in the VMEchip2, and two in the PCCchip2. The tick
timers can be programmed to generate periodic interrupts to the processor.

MVME197LE/D2 4-7

Functional Description

Refer to the VMEchip2, PCCchip2, and BusSwitch chapters in the MVM E197LE,

MVME197DP, and MVME197S P Single Board Computer s Programmer’s Refe rence
Guide for detailed programming information.

Watchdog Timer

A watchdog timer function is provided in the VMEchip2. When the watchdog

4

Software-Programmable Hardware Interrupts

Processor Bus Timeout

timer is enabled, it must be reset by software within the programmed time or
it times out. The watchdog can be programmed to generate a SYSRESET*
signal, local reset signal, or board fail if it times out. Refer to the VMEchip2
chapter in the MVME197LE, MVME197DP, and MVME197SP Single Board
Computers Programmer ’s Reference Guide for detailed programming
information.

Eight software-programmable hardware interrupts are provided by the
VMEchip2. These interrupts allow software to create a hardware interrupt.
Refer to the VMEchip2 chapter in the MVME197LE, MVME197DP, and
MVME197SP Single Board Computers Programmer’s Reference Guide for detailed
programming information.

The BusSwitch provides a bus timeout circuit for the processor bus. When
enabled by the BTIMER register in the BusSwitch, the timer starts counting
when DBB* is asserted, and if the cycle is not terminated (TA*, TEA*, or
TRTRY* asserted) before the programmed timeout period, TEA* is asserted.
This timer is disabled if the access goes to the local peripheral bus.

Local Peripheral Bus Timeout

The MVME197LE provides a timeout function for th e processor bus (MC88110
bus) and for the local peripheral bus (MC68040 compatible bus). When the
timer is enabled and a bus access times out, a Transfer Error Acknowledge
(TEA) signal is generated. The timeout value is selectable by software for 8
µsec, 64 µsec, 256 µs ec, or infinite for the local peripheral bus. The local
peripheral bus timer does not operate during VMEbus bound cycles. VMEbus
bound cycles are timed by the VMEbus access timer and the VMEbus global
timer.

Interrupt Sources

MVME197LE MPU interrupts are channeled through the BusSwitch. They
may come from internal BusSwitch sources as well as from the PCCchip2 (IPL
inputs to the BusSwitch), the VMEchip2 (XIPL inputs to the BusSwitch), and

4-8 User’s Manual

MVME197LE Functional Description

other external sources (PALINT and IRQ). The BusSwitch may also generate
the non-maskable interrupt (NMI) signal to the MPU from the ABORT push­button switch. Refer to the BusSwitch, PCCchip2, and VMEchip2 chapters in the

MVME197LE, MVME197DP, and MVME197SP Single Board Computers

Programmer’s Reference Guide for more detailed information.

4

MVME197LE/D2 4-9

Functional Description

4

4-10 User’s Manual

EIA-232-D

INTERCONNECTIONS

The EIA-232-D Standard is the most widely used interface between terminals
and computers or modems, and yet it is not fully understood. This is because
all the lines are not clearly defined, and many users do not see the need to
conform for their applications. A system should easily connect to any other.
Many times designers think only of their own equipment, but the state-of-the­art is computer-to-computer or computer-to-modem operation.

The DIA-232-D Standard was originally developed by the Bell System to
connect terminals via modems. Therefore, several handshaking lines were
included. In many applications these are not needed, but since they permit
diagnosis of problems, they are included in many applications.

Table A-1 lists the standard DIA-232-D interconnections. To interpret this
information correctly it is necessary to know that EIA-232-D is intended to
connect a terminal to a modem. When computers are connected to computers
without modems, one of them must be conf igured a s a terminal and the o ther
as a modem. Because computers are normally configured to work with
terminals, they are said to be configured as a modem. Also, the signal levels
must be between +3 and +15 volts for a high level, and between -3 and -15 volts
for a low level. Any attempt to connect units in parallel may result in out of
range voltages and is not allowed by the EIA-232-D specifications.

A

MVME197LE/D2A-1

A

EIA-232-D Interconnections

Table A-1. EIA-232-D Interconnections

Pin

Number

1 --- Not used.
2 TXD TRANSMIT DATA - data to be transmitted is furnished on

3 RCD RECEIVE DATA - data which is demodulated from the

4 RTS REQUEST TO SEND - RTS is supplied by the termin al to the

5 CTS CLEAR TO SEND - CTS is a function supplied to the

6 DSR DATA SET READY - data set ready is a function supplied

7 SIG-GND SIGNAL GROUND - common return line for all signals at

8 DCD DATA CARRIER DETECT - sent by the modem to the

Signal

Mnemonic

Signal Name and Description

this line to the modem from the terminal.

receive line is presented to the terminal by the modem.

modem when required to transmit a message. With RTS off,
the modem carrier remains off. When RTS is turned on, the
modem immediately turns on the carrier.

terminal by the modem wh ich indica tes that it is permi ssible
to begin transmission of a message. When using a modem,
CTS follows the off-to-on transition of RTS after a time
delay.

by the modem to the termi nal to indicate that the modem is
ready to transm it data.

the modem interface.

terminal to indicate that a valid carrier is being received.

9-14 --- Not used.

15 TXC TRANSMIT CLOCK - this line clocks output data to the

modem from the terminal.
16 --- Not used.
17 RXC RECEIVE CLOCK - this line clocks input data from a

terminal to a modem.

18,19 --- Not used.

20 DTR DATA TERMINAL READY - a signal from the terminal to

the modem indicating that the terminal is ready to send or

receive data.
21 --- Not used.

A-2 User’s Manual

EIA-232-D Interconnections

Table A-1. EIA-232-D Interconnections (Continued)

A

Pin

Number

22 RI RING INDICATOR - RI is sent by the modem to the

23 --- Not used.
24 TXC TRANSMIT CLOCK - Same as TXC on pin 15.
25 BSY BUSY - a positive EIA signal applied to this pin causes the

Notes

There are several levels of conformance that are appropriate for typical EIA­232-D interconnections. The bare minimum requirement is the two data lines
and a ground. The full version of EIA-232-D requires 12 lines and
accommodates automatic dialing, automatic answering, and synchro nous
transmission. A middle-of- the- road approach is illustrated in Figure A-1.

Signal

Mnemonic

terminal. This line i ndicates to the termin al that an incoming
call is present. The terminal causes the modem to answer the
phone by carrying DTR true while RI is active.

modem to go off-hook and make the associated phone busy.

1. High level = +3 to +15 volts. Low level = -3 to -15 volts.

2. EIA-232-D is intended to connect a terminal to a modem.
When computers are connected to computers without
modems, one of the computers must be configured as a
modem and the other as a terminal.

Signal Name and Description

One set of handshaking signals frequently implemented are RTS and CTS. CTS
is used in many systems to inhibit transmission until the signal is high. In the
modem applications, TRS is turned around and returned as TRS after 150
microseconds. RTS is programmable in some systems to work with the older
type 202 modem (half duplex). CTS is used in some systems to provide flow
control to avoid buffer overflow. This is not po ssible if modems are used. It is
usually necessary to make CTS high by connecting it to RTS or to some source
of +12 volts such as the resistors shown in Figure A - 1. It is also frequently
jumpered to an MC1488 gate which has its inputs grounded (the gate is
provided for this purpose). Another signal used in many systems is DCD. The
original purpose of this signal was to tell the system that the carrier tone from
the distant modem was being received. This signal is frequently used by the
software to display a message like CARRIER NOT PRESENT to help the user
to diagnose failure to communicate. Obviously, if the system is designed
properly to use this signal, and it is not connected to a modem, the signal must

MVME197LE/D2 A-3

A

EIA-232-D Interconnections

be provided by a pull-up resistor or gate as described before (see Figure A-1).
Many modems expect a DTR high signal and issue a DSR. These signals are
used by software to help prompt the operator about possible causes of trouble.
The DTR signal is used sometimes to disconnect the phone circuit in
preparation for another automatic call. It is necessary to provide these signals
in order to talk to all possible modems (see Figure A-1). Figure A-1 is a good
minimum confi guration that al most always work s. If the CTS and DCD s ignals
are not received from the modem, the jumpers can be moved to artificially
provide the needed signal. Figure A-2 shows a way that an EIA-232-D
connector can be wired to enable a computer to connect to a basic terminal
with only three wires. This is because most terminals have a DTR signal that is
ON and can be used to pull-up the CTS, DCD and DSR signals. Two of these
connectors wired back-to-back can be used. It must be realized that all the
handshaking has been bypassed an d possible diagnostic messages do not
occur. Also, the TX and RX lines may have to be crossed since TX from a
terminal is outgoing but the TX line on a modem is an incoming signal.

A-4 User’s Manual

6850

TXD

EIA-232-D Interconnections

RXD

3

A

RXD

RTS

CTS

DCD

TXC

RXC

6850

RXD

TXC

RXC

TXD

RTS

CTS

DCD

-12V

+12V

-12V

LS08

OPTIONAL

HARDWARE

TRANSPARENT

MODE

LS08

39kΩ

470Ω

39kΩ

+12V

-12V

470Ω

39kΩ

-12V

+12V

LOGIC

GND

+12V

39kΩ

470Ω

470Ω

470Ω

470Ω

SIG GND

SIG GND

MODULE

TXD

NC

CTS

DSR

DCD

NC

DTR

TXD

RXD

RTS

CTS

DCD

2

1

5

6

8

7

7

1

20

2

3

4

5

6

CONNECTOR

TO

TERMINAL

CHASSIS GND

CONNECTOR

TO

MODEM

OR

HOST

SYSTEM

Figure A-1. Middle-of-the-Road EIA-232-D Configuration

MVME197LE/D2 A-5

A

EIA-232-D Interconnections

Another subject that needs to be considered is the use of ground pins. There
are two pins labeled GND. Pin 7 is the SIGNAL GROUND and must be
connected to the distant device to complete the circuit. Pin 1 is the CHASSIS
GROUND, but it must be used with care. The chassis is connected to the
power ground through the green wire in the power cord and must be
connected to the chassis to be in compliance with the electrical code. The
problem is that when units are connected to different electrical outlets, there
may be several volts difference in ground potential. If pin 1 of the devices are
interconnected with a cable, several amperes of current could result. This not
only may be dangerous for the small wires in a typical cable, but could result
in electrical noise that could cause errors. That is the reason that Figure A-1
shows no connection for pin 1. Normally, pin 7 should only be connected to
the CHASSIS GROUND at one point and, if several terminals are used with
one computer, the logical place for that point is at the computer. The terminal
should not have a connection between the logic ground return and the chassis.

EIA-232-D

CONNECTOR

GND 1 O

TXD 2 O

RXD 3 O

RTS 4 O
CTS 5 O

DSR 6 O

GND 7 O

DCD 8 O

DTR 20 O

Figure A-2. Minimum EIA-232-D Connection

A-6 User’s Manual

•

•

•

•

•

Index

When using this index, keep in mind that a page number indicates only where
referenced material begins. It may extend to the page or pages following the page
referenced.

Numerics

197Bug 2-3
53C710 SCSI Memory Map 3-17
82596CA Ethernet LAN Memory Map

3-16

A

ABORT Switch S2 3-1
address, ethernet station 4-5

B

Battery Backup RAM and Clock 4-3
BBRAM Configuration Area Memory

Map 3-18
BBRAM, TOD Clock Memory Map 3-19
BOOT ROM 2-5, 4-3
bus terminators, SCSI 4-6
BusSwitch ASIC 1-1
BusSwitch Register Memory Map 3-6

C

Cirrus Logic CD2401 Serial Port Memory

Map 3-15
Configuration Switch S1 2-3, 2-4
Configuration Switch S6 2-5
Connector P2 2-7
Connectors 1-4, 2-5
connectors, P1 and P2 2-5
Controls and Indicators 3-1
Cooling Requirements 1-4

DCAM (I2C) Register Memory Map 3-8
DCAM ASIC 1-2
Detailed I/O Memory Maps 3-5
diagram(s)

MVME197LE Block 4-2
MVME197LE Switches, Connectors,

and LED Indicators Location
2-2

DROM (Downloa d ROM) 4-3

E

ECDM ASIC 1-2
ECDM CSR Register Memory Map 3-7
Equipment Required 1-5
Ethernet Interface 4-5
Ethernet Station Address 4-5

F

FCC-compliant chassis 1-5
Features, MVME197LE 1-2
FFC Compliance 1-5
FLASH Memory 4-3
forced air cooling 1-4
Front Panel Indicators (DS1-DS6) 3-2
fuse (F2) 2-8

G

General Description, MVME197LE

module 1-1

General Information, Switch 2-3

D

Data Bus Structure 4-1

MVME197LE/D2IN-1

H

hardware interrupt, VMEchip2 4-7

Index

I

I/O Interfaces 4-4
Installation Instructions 2-5
installation, MVME197LE 2-6
interfaces

ethernet 4-5
I/O 4-4
printer 4-5
SCSI 4-6
serial port 4-4
VMEbus 4-4

introduction(s)

Functional Description 4-1
General Information 1-1
Hardware Preparation and

Installation 2- 1

Operating Instructions 3-1

L

LEDs, front panel 3-2
Local Devices Memory Map 3-4
local peripheral bus (MC68040

compatible bus) 1-1

Local Peripheral Bus Timeout 4-7

PCCchip2 3-13
printer 3-14
Processor Bus 3-3
SCSI 3-17

VMEchip2 3-9
mezzanine connector 2-5
MK48T08 BBRAM Memory 3-19
MK48T08 BBRAM, TOD Clock Memory

Map 3-17
module expansion 2-5
MVME197BUG 197Bug Debugging

Package User’s Manual 1-6, 3-20
MVME197Bug debug monitor firmware

(197Bug) 1-5
MVME197LE Block Diagram 4-2
MVME197LE Functional Description 4-1
MVME197LE Module Installation 2-6
MVME197LE registers 2-1
MVME197LE Specifications 1-3
MVME712M Transition Module and P2

Adapter Board User’s Manual

2-5
MVME712X 1-1
MVME712-XX 1-1

N
D
E
X

M

mapping

Local Peripheral Bus (MC68040

compatible bus) 3-2
Processor Bus (MC88110 bus) 3-2
VMEbus Masters 3-2

MC88110 MPU 4-1
MC88110 RISC microprocessor 1-1, 4-1
memory map(s)

BBRAM Configuration Area 3-18

I

BBRAM/TOC Clock 3-17
BusSwitch Register 3-6
CD2401 Serial Port 3-15
DCAM (I2C) 3-8
ECDM CSR Register 3-7
Ethernet LAN 3-16
Local Devices 3-4

IN-2 User’s Manual

N

Non-Volatile RAM Memory (NVRAM)

3-19

O

Onboard DRAM 4-3
Operating temperature 1-3

P

P1 and P2 connectors 2-6
PCCchip2 ASIC 1-2
PCCchip2 Memory Map 3-13
Peripheral Resources 4-6
Physical dimensions, board 1-4
Power requirements 1-3
Printer Interface 4-5
Printer Memory Map 3-14

processor bus (MC88110 bus) 1-1
Processor Bus Memory Map 3-2, 3-3
Processor Bus Timeout 4-7
Programmable Tick Timers 4-6

R

Relative humidity 1-3
RESET switch (S3) 3-1

U

Unpacking Instructions 2-1

V

VMEbus Interface 4-4
VMEchip2 ASIC 1-2
VMEchip2 Memory Map 3-9
VMEsystem 3000 chassis 1-4

S

SCSI Interface 4-6
SCSI Termination 4-6
Serial Port Interface 4-4
Software-Programmable Hardware

Interrupts 4-7
specifications, MVME197LE 1-3
Storage temperature 1-3
Support Information 1-6
switch settings 2-1
switch(es)

ABORT (S2) 3-1
Configuration S1 2-3
Configuration S6 2-5
front panel 3-1
general purpose functions 2-4
LED 3-2
RESET (S3) 3-1
serial port 4 clock select 2-5
system controller enable function 2-4

Switches, Connectors, and LED

Indicators Location Diagram 2-2
System Considerations 2-7
system controller 2-4, 2-6
SYSTEM V/88 operating system 3-19

W

Watchdog Timer 4-7

T

terminal to modem interface A-1
tick timer, programmable 4-6
time-of-day (TOD) clock 3-19
TOD Clock Memory 3-19
transition boards 1-1

MVME197LE/D2 IN-3

I
N
D
E
X

Index

N
D
E
X

I

IN-4 User’s Manual