Motorola MVME197LE User Manual 2

MVME197LE

Single Board Computer

Installation Guide

(MVME197LEIG/D1)

Notice

While reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Motor ola rese rves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes.

No part of this material may be reproduced or copied in any tangible medium, or stored in a retrieval system, or transmitted in any form, or by any means, radio, electronic, mechanical, photocopying, recording or facsimile, or otherwise, without the prior written permission of Motorola, Inc.

It is possible that this publication may contain reference to, or information about Motorola products (machines and programs), programming, or services that are not announced in your country. Such references or information must not be construed to mean that Motorola intends to announce such Motorola products, programming, or services in your country.

Restricted Rights Legend

If the documentation contained herein is supplied, directly or indirectly, to the U.S. Government, the following notice shall apply unless otherwise agreed to in writing by Motorola, Inc.

Use, duplication, or disclosure by the Governm ent is subject to r estrictions as set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227-7013.

Motorola, Inc.

Computer Group

2900 South Diablo Way

Tempe, Arizona 85282-9602

Preface

This document provides a general board level hardware description, hardware preparation and installation instructions, debugger general information, and instructions on using the debugger for the MVME197LE Single Board Computer.

This document is intended for anyone who wants to design OEM systems, supply additional capability to an existing compatible system, or work in a lab environment for experimental purposes.

A basic knowledge of computers and digital logic is assumed. T o use this document, you may wish to become familiar with the publications listed in

the Related Documentation section found in the following pages. This installation guide is based on these other documents.

Document Terminology

Throughout this document, a convention has been maintained whereby data and address parameters are pr eceded by a cha racter which specifies the numeric format, as follows:

$ dollar specifies a hexadecimal number % percent specifies a binary number & ampersand specifies a decimal number

For example, “12” is the decimal number twelve, and “$12” is the decimal number eighteen. Unless otherwise specified, all address references are in hexadecimal throughout this document.

An asterisk (*) following the signal name for signals which are level significant denotes that the signal is true or valid when the signa l is low.

An asterisk (*) following the signal name for signals which are edge significant denotes that the actions initiated by that signal occur on high to low transition.

In this document, assertion and negation are used to specify forcing a signal to a particular state. In particular, assert ion and assert refer to a signal that is active or true; negation and negate indicate a signal that is inactive or false. These terms are used independently of the voltage level (high or low) that they represent.

Data and address sizes are defined as follows:

❏ A byte is eight bits, numbered 0 through 7, with bit 0 being the least

significant.

❏ A two-byte is 16 bits, numbered 0 through 15, with bit 0 being the least

significant. For the MVME197series and other RISC modules, this is called a half-word.

❏ A four-byte is 32 bits, numbered 0 through 31, with bit 0 being the least

significant. For the MVME197 series and other RISC modules, this is called a word.

❏ An eight-byte is 64 bits, numbered 0 through 63, with bit 0 being the least

significant. For the MVME197 series and other RISC modules, this is called a double-word.

Throughout this document, it is assumed that the MPU on the MVME197 module series is always programmed with big-endian byte orde r ing, as shown below. Any attempt to use small-endian byte ordering will immediately render the MVME197Bug debugger unusable.

BIT BIT 63 56 55 48 47 40 39 32

ADRO ADR1 ADR2 ADR3

31 24 23 16 15 08 07 00

ADR4 ADR5 ADR6 ADR7

The terms control bit and status bit are used extensively in this document. The term control bit is used to describe a bit in a register that can be set and cleared under software control. The term true is used to indicate that a bit is in the state that enables the function it controls. The term false is used to indicate th at the bit is in the state th at disables the function it controls. In all tables, the terms 0 and 1 are used to describe the actual value that should be written to the bit, or the value that it yields when read. The term status bit is used to describe a bit in a register that r eflects a specific condition. The status bit can be read by software to determine operational or exception conditions.

Related Documentation

The following publications are applicable to the MVME197 module series and may provide additional helpful information. If not shipped with this product, they may be purchased by contacting your Motorola sales office.

Document Title

MVME197LE Single Board Computer User’s Ma nual MVME197LE Single Board Computer Support Infor mation MVME197DP and MVME197SP Single Board Computer

User’s Manual

MVME197DP and MVME197SP Single Board Computer

Support Information

MVME197LE, MVME197DP, and MVME197SP Single

Board Computers Programmer’s Reference Guide MVME197BUG 197Bug Debugging Package User’s Ma nual MVME197BUG 197Bug Diagnostic Firmware User’s Ma nual MVME712M Transition Module and P2 A dapter Board

User’s Manual MVME712-12, MVME712-13, MVME 712A, MVME712A M,

and MVME712B Transition Module and LCP2 Adapter Board

User’s Manual MC88110 Second Generation RISC Microp rocessor User ’s

Manual

Motorola

Publication Number

MVME197LE SIMVME197LE MVME197

SIMVME197

MVME197PG

MVME197BUG MVME197DIAG MVME712M

MVME712A

MC88110UM

MC68040 Microprocessor User’s Manual MC88410 Secondary Cache Co ntroller User’ s Manual

Notes

1. The support information manuals (SIMVME197LE and SIMVME197) contain: the connector intercon nect signal information, parts lists, and the schematics for the specific board(s) indicated.

MC68040UM MC88410UM

2. Although not shown in the above list, each Motorola Computer Group manual publication number is suffixed with characters which represent the revision

level of the document, such as “/D2” (the second revision of a manual); a supplement bears the same number as the manual but has a suffix such as “/A 1” (the first supplement to the manual).

To further assist your development effort, Motorola has collected user’s manuals for each of the peripheral controllers used on the MVME197 module series and other boards from the suppliers. This bundle includes manuals for the following:

68-1X7DS for use with the MVME197 series of Single Board Computers.

NCR 53C710 SCSI Controller Data Manual and Programmer’s Guide Intel i82596 Ethernet Controller User’s Manual Cirrus Logic CD2401 Serial Controller User’s Manual SGS-Thompson MK48T08 NVRAM/TOD Clock Data Sheet

The following non-Motorola publications may also be of interest and may be obtained from the sources indicated. The VMEbus Specification is contained in ANSI/IEEE Standard 1014-1987 .

ANSI/IEEE Std 1014-1987 The Institute of Electrical and Electronics Versatile Backplane Bus: VMEbus Engineers, Incorporated

Publication and Sales Department 345 East 47th Street New York, New York 10017-2633 Telephone: 1-800-678-4333

ANSI Small Computer System Interface-2 Global Engineering Documents (SCSI-2), Draft Document X3.131-198X, P.O. Box 19539 Revision 10c Irvine, California 92713-9539

Telephone (714) 979-8135

The computer programs stored in the Read Only Memory of this device contain material copyrighted by Motorola Inc., first published 1991, and may be used only under license such as the License for Computer Programs (Article 14) contained in

Motorola’s Terms and Conditions of Sale, Rev. 1/79.

Motorola

Delta Series, M88000, SYSTEM V/88, VMEmodule, VMEsystem, and197bug are trademarks of Motorola, Inc.

Timekeeper and Zeropower are trademarks of Thompson Components. All other products mentioned in this document are trademarks or registered

trademarks of their respective holders

and the Motorola symbol are registered trademarks of Motorola, Inc.

Printed in the United States of America

September 1993

WARNING

This equipment generates, uses, and can radiate radio frequency energy and if not installed and used in accordance with the documentation for this product, may cause interference to radio communications. It has been tested and found to comply with the limits for a Class A Computing Device pursuant to Subpart J of Part 15 of FCC rules, which are designed to provide reasonable protection against such interference when operated in a commercial environment. Operation of this equipment in a residential area is likely to cause interference in w hich ca se the user, at

the user’s own expense, will be required to take whatever measures necessary to correct the interference.

SAFETY SUMMARY

SAFETY DEPENDS ON YOU

The following general safety precautions must be observed during all phases of operation, service, and repair of this equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual violates safety standards of design, manufacture, and intended use of the equipment. Motorola Inc. assumes

no liability for the customer’s failure to comply with these requirements. The safety precautions listed below represent warnings of certain dangers of which we are aware. You, as the user of the product, should follow these warnings and all other saf ety precautio ns necessary for the safe oper ation of the e quipment in you r operating environment.

GROUND THE INSTRUMENT.

To minimize shock h azard, the equipm ent chassis and e nclosure must be co nnected to an ele ctrical ground. T he equipment is supplied w ith a three-conduct or ac power cable. The power cable must either be plugged in to an approved three-contact electrical ou tlet or used w ith a three- contact to two- contact adap ter, with the gr ounding w ire (green) firmly connected to an electrical ground (safety ground) at the power outlet. The power jack and mating plug of the power cable meet international Electrotechnical Commission (IEC) safety standards.

DO NOT OPERATE IN AN EXPLOSIVE ATMOSPHERE.

Do not operate the equipment in the presence of flammable gases or fumes. Operation of any electrical equipment in such an environment constitutes a definite safety hazard.

KEEP AWAY FROM LIVE CIRCUITS.

Operating personnel must not remove equipment covers. Only Factory Authorized Service Personnel or other qualified maintenance person nel may remove equ ipment covers for internal sub assembly or comp onent replacem ent or any internal adjustment. D o not replace comp onents with power cab le connected. Unde r certain conditio ns, dangerous voltages may exist even with th e power cable remo ved. To avoid injuries, alw ays disconnect power and disc harge circuits before touching them.

DO NOT SERVICE OR ADJUST ALONE.

Do not attempt internal service or adjustment unless another person, capable of rendering first aid and resuscitation, is present.

USE CAUTION WHEN EXPOSING OR HANDLING THE CRT.

Breakage of the Cathode-Ray Tube (CRT) causes a high-velocity scattering of glass fragments (implosion). To prevent CRT implosion, avoid rough handling or jarring of the equipment. Handling of the CRT should be done only by qualified maintenance personnel using approved safety mask and gloves.

DO NOT SUBSTITUTE PARTS OR MODIFY EQUIPMENT.

Because of the danger of introduc ing additional hazards, do not install subs titute par ts or perform an y unauthor ized modification of the equipment. Contact your local Motorola representative for service and repair to ensure that safety features are maintained.

DANGEROUS PROCEDURE WARNINGS.

Warnings, such as the example below, precede potentially dangerous procedures throughout this manual. Instructions contained in the war nings must be fo llowed. You shou ld also employ a ll other safety precautions which you deem necessary for the operation of the equipment in your operating environment.

WARNING

Dangerous voltages, capab le of causing de ath, are present in this equipment. Use extreme caution when handling, testing, and adjusting.

SPD 15163 R-2 (9/93)

Contents

CHAPTER 1 BOARD LEVEL HARDWARE DESCRIPTION

Introduction.............................................................................................................1-1

Overview..................................................................................................................1-1

Requirements...........................................................................................................1-2

Features.....................................................................................................................1-3

Block Diagram.........................................................................................................1-4

Functional Description...........................................................................................1-6

Front Panel Switches and Indicators.............................................................1-6

Data Bus Structure...........................................................................................1-7

MC88110 MPU..................................................................................................1-7

BOOT ROM.......................................................................................................1-7

Flash Memory...................................................................................................1-7

Onboard DRAM...............................................................................................1-7

Battery Backup RAM and Clock....................................................................1-8

VMEbus Interface ............................................................................................1-8

I/O Interfaces ...................................................................................................1-8

Serial Port Interface..................................................................................1-8

Printer Interface ...................................................... ...... ...... ......................1-9

Ethernet Interface.............................. ..... ...... .............................................1-9

SCSI Interface..........................................................................................1-10

SCSI Termination....................................................................................1-10

Peripheral Resources.....................................................................................1-11

Programmable Tick Timers...................................................................1-11

Watchdog Timer .....................................................................................1-11

Software-Programmable Hardware Interrupts..................................1-11

Processor Bus Timeout...........................................................................1-11

Local Peripheral Bus Timeout...............................................................1-11

Interrupt Sources............................................................................................1-12

Connectors ......................................................................................................1-12

Memory Maps .......................................................................................................1-12

Processor Bus Memory Map ........................................................................1-12

VMEbus Memory Map..................................................................................1-15

VMEbus Accesses to the Local Peripheral Bus...................................1-15

VMEbus Short I/O Memory Map........................................................1-15

CHAPTER 2 HARDWARE PREPARATION AND INSTALLATION

Introduction.................................................................................................................2-1

Unpacking Instructions..............................................................................................2-1

Hardware Preparation ...............................................................................................2-1

Configuration Switches ......................................................................................2-3

Configuration Switch S1: General Information.......................................2-3

Configuration Switch S1: General Purpose Functions

(S1-1 to S1-8)......................................................................................2-4

Configuration Switch S1: System Controller Enable

Function (S1-9)..................................................................................2-4

Configuration Switch S6: Serial Port 4 Clock Select

(S6-1, S6-2)..........................................................................................2-5

Installation Instructions.............................................................................................2-5

MVME197LE Module Installation....................................................................2-6

System Considerations .......................................................................................2-7

CHAPTER 3 DEBUGGER GENERAL INFORMATION

Overview of M88000 Firmware................................................................................3-1

Description of 197Bug................................................................................................3-1

Comparison With M68000-Based Firmware...........................................................3-2

197Bug Implementation.............................................................................................3-2

Installation and Start-up............................................................................................3-2

Autoboot ......................................................................................................................3-4

ROMboot......................................................................................................................3-5

Network Boot..............................................................................................................3-5

Restarting the System.................................................................................................3-6

Reset .................................. ..... .................................................................... ...... .....3-6

Abort............................................. ..... ....................................................................3-7

Break..................................................................................................... ...... ...... .....3-7

SYSFAIL* Assertion/Negation..........................................................................3-8

MPU Clock Speed Calculation ..........................................................................3-8

Memory Requirements ..............................................................................................3-8

Terminal Input/Output Control........................................................................3-9

Disk I/O Support......................................................................................................3-10

Blocks Versus Sectors ........................................................................................3-10

Device Probe Function......................................................................................3-10

Disk I/O via 197Bug Commands ....................................................................3-11

IOI (Input/Output Inquiry)......................................................................3-11

IOP (Physical Input/Output to Disk)......................................................3-11

IOT (Input/Output Teach).......................................................................3 -11

IOC (Input/Output Control) ...................................................................3-11

BO (Bootstrap Operating System)........................................................... 3-11

BH (Bootstrap and Halt)...........................................................................3-11

Disk I/O via 197Bug System Calls.......................................................... 3-12

Default 197Bug Controller and Device Parameters.....................................3-13

Disk I/O Error Codes.......................................................................................3-13

Network I/O Support......................................................................................3-13

Physical Layer Manager Ethernet Driver...............................................3-14

UDP/IP Protocol Modules.......................................................................3-14

RARP/ARP Protocol Modules................................................................ 3-14

BOOTP Protocol Module..........................................................................3-14

TFTP Protocol Module....................................................... ..... ...... ............ 3-14

Network Boot Control Module................................................................3-15

Network I/O Error Codes........................................................................3-15

Multiprocessor Support .......................................................................................... 3-15

Multiprocessor Control Register (MPCR) Method ......................................3-15

GCSR Method.................................................................................................... 3-17

Diagnostic Facilities.................................................................................................3-17

CHAPTER 4 USING THE 197Bug DEBUGGER

Entering Debugger Command Lines ...................................................................... 4-1

Syntactic Variables .............................................................................................. 4-2

Expression as a Parameter.......................................................................... 4-2

Address as a Parameter .............................................................................. 4-4

Address Formats..........................................................................................4-4

Offset Registers ............................................................................................4-4

Port Numbers ..................................... ...... ...........................................................4-5

Entering and Debugging Programs......................................................................... 4-5

Calling System Utilities From User Programs....................................................... 4-6

Preserving The Debugger Operating Environment..............................................4-6

197Bug Vector Table and Workspace................................................................ 4-6

Hardware Functions...........................................................................................4-6

Exception Vectors Used by 197Bug ..................................................................4-6

CPU/MPU Registers.......................................................................................... 4-7

Floating Point Support ................................... ..... ......................................................4-7

Single Precision Real...........................................................................................4-8

Double Precision Real......................................................................................... 4-8

Scientific Notation...............................................................................................4-8

197Bug Debugger Command Set............................................................................. 4-9

APPENDIX A CONFIGURE AND ENVIRONMENT COMMANDS

Configure Board Information Block........................................................................A-1

Set Environment to Bug/Operating System..........................................................A-2

APPENDIX B DISK/TAPE CONTROLLER DATA

Disk/Tape Controller Modules Supported............................................................B-1

Disk/Tape Controller Default Configurations......................................................B-2

IOT Command Parameters for Supported Floppy Types....................................B-5

APPENDIX C NETWORK CONTROLLER DATA

Network Controller Modules Supported...............................................................C-1

xii

List of Figures

FIGURES

Figure 1-1. MVME197LE Block Diagram.............................................................1-5

Figure 2-1. MVME197LE Switches, Connectors, and LED Indicators

Location Diagram......................................................... ..... ...... ...........2-2

xiii

xiv

List of Tables

TABLES

Table 1-1. MVME197LE Specifications.................................................................1-4

Table 1-2. Processor Bus Memory Map..............................................................1-13

Table 1-3. Local Devices Memory Map.............................................................1-14

Table 4-1. Debugger Commands...........................................................................4-9

Table A-1. ENV Command Parameters ..............................................................A-3

xvi

BOARD LEVEL

Introduction

This chapter describes the board level hardware features of the MVME197LE Single Board Computer. The chapter is organized with a board level overview and features listed in this introduction, followed by a more detailed ha rdware functional description. Front panel switches and indicators are included in the detailed hardware functional description. This chapter closes with some general memory maps.

All programmable registers in the MVME197LE module reside in ASICs (Application-Specific Integrated Circuits) that are covered in the

MVME197LE, MVME197DP, and MVME197SP Single Board Computers

Programmer’s Reference Guide.

Overview

The MVME197LE module is a double-high VMEmodule based on the MC88110 RISC microprocessor. The MVME197LE has 32/64MB of DRAM, 1MB of flash memory, 8KB of static RAM (with battery backup), a time of day clock (with battery backup), an Ethernet transceiver interface, four serial ports with EIA-232-D interface, six tick timers, a watchdog timer, 128KB of BOOT ROM, a SCSI bus interface with DMA (Direct Memory Access), a Centronics printer port, an A16/A24/A32/D8/D16/D32 VMEbus master/slave interface, and a VMEbus system controller.

HARDWARE DESCRIPTION

Input/Output (I/O) signals are routed through the MVME197LE’s backplane connector P2. A P2 Adapter Board or LCP2 Adapter board routes the signals and grounds from connector P2 to an MVME712 series tra nsition module. The MVME197LE supports the MVME712M, MVME712A, MVME712AM, and MVME712B transition boards (referred to here as the MVME712X, unless separately specified). The MVME197LE also supports the MVME712-12 and MVME712-13 (referred to as the MVME712-XX, unless separately specified). These transition boards provide configuration headers, seria l port drivers, and industry standard connectors for the I/O devices.

The MVME197LE modules have eight ASICs (described in the following order: BusSwitch, DCAM, ECDM, PCC2, and VME2).

MVME197LEIG/D11-1

Board Level Hardware Description

The BusSwitch ASIC provides an interface between the processor bus (MC88110 bus) and the local peripheral bus (MC68040 com patible bu s). Refer to the MVME197LE block diagram ( Figure 1-1). It provides bus arbitration for the MC88110 bus and serves as a seven level interrupt handler. It has programmable map decoders for both busses, as well as write post buffers on each, two tick timers, and four 32-bit general purpose registers.

The DCAM (DRAM Controller and Address Multiplexer) ASIC provides the address multiplexers and RAS/CAS/WRITE control for the DRAM as well as data control for the ECDM.

The ECDM (Error Correction and Data Multiplexer) ASIC multiplexes between four data paths on the DRAM array. Since the device handles 16 bits, four such devices are required on the MVME197LE to accommodate the 64-bit data bus of the MC88110 microprocessor. Single-bit error correction and double-bit detection is performed in the ECDM.

The PCCchip2 (Peripheral Channel Controller) ASIC provides two tick timers and the interface to the LAN chip, the SCSI chip, the serial port chip, the printer port, and the BBRAM (Battery Backup RAM).

A VMEbus interface chip with an MC68040 bus interface is one ASIC called th e VMEchip2. The VMEchip2 includes two tick timers, a watchdog timer, programmable map decoders for the master and slave interfaces, and a VMEbus to/from the local peripheral bus DMA controller, a VMEbus to/from the local peripheral bus non-DMA programmed access interface, a VMEbus interrupter, a VMEbus system controller, a VMEbus interrupt handler, and a VMEbus requester.

Local peripheral bus to VMEbus transfers can be D8, D16, or D32. VMEchip2 DMA transfers to the VMEbus, however, can be 64 bits wide as Block Transfer (BLT).

Requirements

These boards are designed to conform to the requirements of the following documents:

❏ VMEbus Specification (IEEE 1014-87) ❏ EIA-232-D Serial Interface Specification, EIA ❏ SCSI Specification, ANSI

1-2 Installation Guide

Features

These are some of the major features of the MVME197LE single board computer:

❏ MC88110 RISC Microprocessor ❏ 32 or 64 megabytes of 64-bit Dynamic Random Access Memory (DRAM)

❏ 1 megabyte of Flash memory ❏ Six status LEDs (FAIL, RUN, SCON, LAN, SCSI, and VME) ❏ 8 kilobytes of Static Random Access Memory (SRAM) and Time of Day

❏ Two push-button switches (ABORT and RESET) ❏ 128 kilobytes of BOOT ROM ❏ Six 32-bit tick timers for periodic interrupts ❏ Watchdog timer ❏ Eight software interrupts ❏ I/O

❏ VMEbus interface

Features

with error correction

(TOD) clock with Battery Backup RAM (BBRAM)

– SCSI Bus interface with Direct Memory Access (DMA) – Four serial ports with EIA-232-D buffers – Centronics printer port – Ethernet transceiver interface

– VMEbus system controller functions – VMEbus interface to local peripheral bus (A24/A32, D8/D16/D32

BLT (D8/D16/D32/D64))(BLT = Block Transfer)

– Local peripheral bus to VMEbus interface (A24/A32, D8/D16/D32

BLT (D16/D32/D64))

– VMEbus interrupter

MVME197LEIG/D1 1-3

Board Level Hardware Description

Specifications

The specifications for the MVME197LE are listed in Table 1-1.

Table 1-1. MVME197LE Specifications

Characteristics Specifications

Power requirements

Operating temperature

Storage temperature Relative humidity Physical dimensions:

PC board

Height Width Thickness

PC board with connectors and front panel

Height Width Thickness

Board connectors:

P1 connector

P2 connector

J1 connector

J2 connector

+5 Vdc (+/- 2.5%), 4 A (typical), 5 A (maximum) +12 Vdc (+/- 2.5% ), 10 0 m A ( ma ximum)

-12 Vdc (+/- 2.5%), 100 mA (maximum)

0° to 55° C at point of entry of forced air (approximately 490 LFM)

-40° to 85° C 5% to 90% (non-condensing) Double-high VMEboard

9.187 inches (233.35 mm)

6.299 inches (160.00 mm)

0.063 inch (1.60 mm )

10.309 inches (261.85 mm)

7.4 inches (188.00 mm)

0.80 inch (20.32 mm)

96-pin connector which provides the interface to the VMEbus signals.

96-pin connector which provides the interface to the extended VMEbus signals and other I/O signals.

20-pin connector which provides the interface to the remote reset, abort, the LEDs, and three general purpose I/O signals.

249-pin connector which provides the interface to the MC88110 address, data, and control signals to and from the mezzanine expansion.

Block Diagram

Figure 1-1 is a general block diagram of the MVME197LE.

1-4 Installation Guide

Block Diagram

MVME197LEIG/D1 1-5

1-6 Installation Guide

Mezzanine

Port

Address Bus

Address 32

Address Bus

Data Bus

Address 32

Data Bus

MC88110

Data 64

PROCESSOR

BUS

BusSwitch

Data 32

MUX Address

DCAM

ECDM

(X4)

I2CBus

RAS, CAS

Data

Bus

256

LOCAL PERIPHERAL

BUS

Board Level Hardware Description

Memory Array

32/64 MB

I2C EEPROM

NVRAM/RTC

VMEbus

(VMEchip2)

LAN

82596CA

Flash

Memory

SCSI -II

NCR53710

Figure 1-1. MVME197LE Block Diagram

PCCchip2

BOOT

ROM

4 Serial Ports

CL-CD2401

Functional Description

The following sections contain a functional description of the major blocks on the MVME197LE single board computer.

Front Panel Switches and Indicators

There are two push-button switches and six LEDs on the front panel of the MVME197LE module. The switches are RESET and ABORT. The RESET switch (S3) will reset all onboard devices and drive the SYSRESET* signal if the board is the system controller. The RESET switch (S3) will reset all onboard devices except the DCAM and ECDM if the board is not th e system controller. The VMEchip2 generates the SYSREST* signal. The BusSwitch combines the local reset and the reset switch to generate a loca l board reset. Refer to the Reset Driver section in the VMEchip2 chapter of the MVME197L E, MVME197DP, and MVME197SP Singl e Board Computers Programmer’s Refer ence Guide for more information.

When enabled by software, the ABORT switch (S2) generates an interrupt at a user-programmable level. It is normally used to abort program execution and return to the debugger. Refer to the VMEchip2 chapter of the MVME197LE,

MVME197DP, and MVME197S P Single Board Computer s Programmer’s Refe rence Guide for more information.

Functional Description

The six LEDs on the MVME197LE front panel are: FAIL, SCON, RUN, LAN, VME, and SCSI.

1. The yellow FAIL LED (DS1) is lit when the BRDFAIL signal line is active.

2. The green SCON LED (DS2) is lit when the VMEchip2 is the VMEbus system controller.

3. The green RUN LED (DS3) is lit when the MC88110 bus MC* pin is low.

4. The green LAN LED (DS4) lights when the LAN chip is the local peripheral bus master.

5. The green VME LED (DS5) lights when the board is using the VMEbus or when the board is accessed by the VMEbus.

6. The green SCSI LED (DS6) lights when the SCSI chip is the local peripheral bus master.

MVME197LEIG/D1 1-7

Board Level Hardware Description

Data Bus Structure

The data bus structure is arranged to accommodate the various 8-bit, 16-bit, 32-bit, and 64-bit devices that reside on the module. Refer to the MVME197LE,

MVME197DP, and MVME197S P Single Board Computer s Programmer’s Refe rence Guide and to the user’s guide for each device to determine its port size, data

bus connection, and any restrictions that apply when accessing the device.

MC88110 MPU

The MVME197LE is based on the MC88000 family and uses one MC88110 microprocessor unit. Refer to the MC88110 Second Generation RISC

Microprocessor User’s Manual for more information.

BOOT ROM

A socket for a 32-pin PLCC/CLCC ROM/EPROM referred to as BOOT ROM or DROM (Download ROM) is provided. It is organized as a 128K x 8 device, but as viewed from the processor it looks like a 16K x 64 memory. This memory is mapped starting at location $FFF80000, but after a local reset it is also mapped at location 0, providing a reset vector and bootstrap code for the processor. The DR0 bit in the General Control Register (GCR) of the PCCchip2 must be cleared to disable the BOOT ROM memory map at 0.

Flash Memory

Up to 1MB of flash memory is available on the board. Flash memory works like EPROM, but can be erased and reprogrammed by software. It is organized as 32 bits wide, but to the processor it looks as 64 bits wide. It is mapped at location $FF800000. Reads can be of any size, including burst transfers, but writes are always 32 bits wide, regardless of the size specified for the transfer. For this reason, software should only use 32-bit write transfers. This memory is controlled by the BusSwitch, and the memory size, access time, and write enable capability can be programmed via the ROM Control Register (ROMCR) in the BusSwitch. The flash memory can be accessed from the processor bus only. It is not accessible from the local peripheral bus or VMEbus.

Onboard DRAM

The MVME197LE onboard DRAM (2 banks of 32MB memory, one optionally installed) is sized at 32MB using 1M x 4 devices and configured as 256 bits wide. The DRAM is four-way interleaved to efficiently support cache burst cycles. The DRAM is controlled by the DCAM and ECDM, and the map decoders in the DCAM can be programmed through the I2Cbus interface in the ECDM to accommodate different base address(es) and sizes. The on board

1-8 Installation Guide

DRAM is not disabled by a local peripheral bus reset. Refer to the DCAM and ECDM chapters in the MVME197LE, MVME197DP, and MVME197SP Single Board Computers Programmer’s Reference Guide for detailed programming information.

Battery Backup RAM and Clock

The MK48T08 RAM and clock chip is used on the MVME197LE. This chip provides a time of day clock, oscillator, crystal, power fail detection, memory write protection, 8KB of RAM, an d a battery in one 28-pin package. The clock provides seconds, minutes, hours, day, date, month, and year in BCD 24-hour format. Corrections for 28-, 29-, (leap year) and 30-day months are automatically made. No interrupts are generated by the clock. The MK48T08 is an 8-bit device; however the interface provided by the PCCchip2 supports 8-, 16-, and 32-bit accesses to the MK48T08. Refer to the PCCchip2 chapter in the MVME197LE, MVME197DP, and MVME197SP Single Board Computers Programmer’s Reference Guide and to the MK48T08 data sheet for detailed programming information.

VMEbus Inte rface

The local peripheral bus to VMEbus interface, the VMEbus to local peripheral bus interface, and the local-VMEbus DMA controller functions on the MVME197LE are provided by the VMEchip2. The VMEchip2 can also provide the VMEbus system controller functions. Refer to the VMEchip2 chapter in the

MVME197LE, MVME197DP, and MVME197SP Single Board Computers Programmer’s Reference Guide for detailed programming information.

Functional Description

I/O Interfaces

The MVME197LE provides onboard I/O for many system applications. The I/O functions include serial ports, a printer port, an Ethernet transceiver interface, and a SCSI mass storage interface.

Serial Port Interface

The CD2401 serial controller chip (SCC) is used to implement the four serial ports. The serial ports support the standard baud rates (110 to 38.4K baud). Serial port 4 also supports synchronous modes of operation.

The four serial ports are different functionally because of the limited number of pins on the I/O connector. Serial port 1 is a minimum function asynchronous port. It uses RXD, CTS, TXD, and RTS. Serial ports 2 and 3 are full function asynchronous ports. They use RXD, CTS, DCD, TXD, RTS, and DTR. Serial port 4 is a full function asynchronous or synchronous port. It can

MVME197LEIG/D1 1-9

Board Level Hardware Description

operate at synchronous bit rates up to 64k bits per second. It uses RXD, CTS, DCD, RTS, and DTR. It also interfaces to the synchronous clock signal lines. Refer to the MVME197LE, MVME197DP, and MVME197SP Single Board Computers Prog rammer’s Refe rence Guide for drawings of the se rial port interface connections.

All four serial ports use EIA-232-D drivers and receivers located on the main board, and all the signal lines are routed to the I/O connector. The configuration headers are located on the MVME712X transition board. An external I/O transition board such as the MVME712X should be used to convert the I/O connector pinout to industry-standard connectors.

The interface provided by the PCCchip2 allows the 16-bit CD2401 to appear at contiguous addresses; however, accesses to the CD2401 must be 8 or 16 bits. 32-bit accesses are not permitted. Refer to the CD2401 data sheet and to the

PCCchip2 chapter in the MVME197L E, MV ME197DP, and MV ME197S P Sing le Board Computers Programmer’s Reference Guide for detailed programming

information. The CD2401 supports DMA operations to local memory. Because the CD2401

does not support a retry operation necessary to break VMEbus lo ck conditions, the CD2401 DMA controllers should not be programmed to access the VMEbus. The hardware does not restrict the CD2401 to onboard DRAM.

Printer Interface

The MVME197LE has a Centronics-compatible printer interface. The printer interface is provided by the PCCchip2. Refer to the PCCchip2 chapter in the

MVME197LE, MVME197DP, and MVME197SP Single Board Computers Programmer’s Reference Guide for detailed programming information and for

drawings of the printer port interface connections.

Ethernet Interface

The 82596CA is used to implement the Ethernet transceiver interface. The 82596CA accesses local RAM using DMA operations to perform its norm al functions. Because the 82596CA has small internal buffers and the VMEbus has an undefined latency period, buffer overrun may occur if the DMA is programmed to access the VMEbus. Therefore, the 82596CA should not be programmed to access the VMEbus.

Every MVME197LE module is assigned an Ethernet Station Address. This address is $08003E2XXXXX, where XXXXX is the unique 5-nibble number assigned to the board (i.e., every MVME197LE has a different value for XXXXX).

1-10 Installation Guide

The Ethernet Station Address is displayed on a label attached to the VMEbus P2 connector. In addition, the eight bytes including the Ethernet address are stored in the configuration area of the BBRAM, with the two lower bytes of those set to 0. That is, 08003E2XXXXX0000 is stored in the BBRAM. At an address of $FFFC1F2C, the upper four bytes (08003E2X) can be read. At an address of $FFFC1F30, the lower four bytes (XXXX0000) can be read. Refer to the BBRAM, TOD Clock memory map description later in this chapter. The MVME197LE debugger has the capability to retrieve or set the Ethernet address.

If the data in the BBRAM is lost, the user should use the number on the VMEbus P2 connector label to restore it. Refer to the MVME197BUG 197Bug Debugging Package User’s Manual.

The Ethernet transceiver interface is located on the MVME197LE main module, and the industry standard connector is located on the MVME712X transition module.

Support functions for the 82596CA are provided by the PCCchip2. Refer to the

82596CA LAN Coprocessor User’s Manual and to the PCCchip2 chapter in the MVME197LE, MVME197DP, and MVME197SP Single Board Computers Programmer’s Reference Guide for detailed programming information.

SCSI Interface

Functional Description

The MVME197LE provides for mass storage subsystems through the industrystandard SCSI bus. These subsystems may include hard and floppy disk drives, streaming tape drives, and other mass storage devices. The SCSI interface is implemented using the NCR 53C710 SCSI I/O controller.

Support functions for the 53C710 are provided by the PCCchip2. Refer to the

NCR 53C710 SCSI I/O Processor Data Manual and to the PCCchip2 chapter in the MVME197LE, MVME197DP, and MVME197SP Single Board Computers Programmer’s Reference Guide for detailed programming information.

SCSI Termination

The system configurer must ensure that the SCSI bus is terminated properly. On the MVME197LE, the terminators are located on the P2 transition board. The +5V power to the SCSI bus termination resistors is provided by the P2 transition board.

MVME197LEIG/D1 1-11

Board Level Hardware Description

Peripheral Resources

The MVME197LE includes many resources for the local processor. These include tick timers, software programmable hardware interrupts, watchdog timer, and local peripheral bus timeout.

Programmable Tick Timers

Six 32-bit programmable tick timers with 1 µsec resolution are provided, two in the BusSwitch, two in the VMEchip2, and two in the PCCchip2. The tick timers can be programmed to generate periodic interrupts to the processor. Refer to the VMEchip2, PCCchip2, and BusSwitch chapters in the MVM E197LE,

MVME197DP, and MVME197S P Single Board Computer s Programmer’s Refe rence Guide for detailed programming information.

Watchdog Timer

A watchdog timer function is provided in the VMEchip2. When the watchdog timer is enabled, it must be reset by software within the programmed time or it times out. The watchdog can be programmed to generate a SYSRESET* signal, local reset signal, or board fail if it times out. Refer to the VMEchip2 chapter in the MVME197LE, MVME197DP, and MVME197SP Single Board Computers Programmer ’s Reference Guide for detailed programming information.

Software-Programmable Hardware Interrupts

Eight software-programmable hardware interrupts are provided by the VMEchip2. These interrupts allow software to create a hardware interrupt. Refer to the VMEchip2 chapter in the MVME197LE, MVME197DP, and MVME197SP Single Board Computers Programmer’s Reference Guide for detailed programming information.

Processor Bus Timeout

The BusSwitch provides a bus timeout circuit for the processor bus. When enabled by the BTIMER register in the BusSwitch, the timer starts counting when DBB* is asserted, and if the cycle is not terminated (TA*, TEA*, or TRTRY* asserted) before the programmed timeout period, TEA* is asserted. This timer is disabled if the access goes to the local peripheral bus.

Local Peripheral Bus Timeout

The MVME197LE provides a timeout function for th e processor bus (MC88110 bus) and for the local peripheral bus (MC68040 compatible bus). When the timer is enabled and a bus access times out, a Transfer Error Acknowledge (TEA) signal is generated. The timeout value is selectable by software for 8

1-12 Installation Guide

µsec, 64 µsec, 256 µs ec, or infinite for the local peripheral bus. The local peripheral bus timer does not operate during VMEbus bound cycles. VMEbus bound cycles are timed by the VMEbus access timer and the VMEbus global timer.

Interrupt Sources

MVME197LE MPU interrupts are channeled through the BusSwitch. They may come from internal BusSwitch sources as well as from the PCCchip2 (IPL inputs to the BusSwitch), the VMEchip2 (XIPL inputs to the BusSwitch), and other external sources (PALINT and IRQ). The BusSwitch may also generate the non-maskable interrupt (NMI) signal to the MPU from the ABORT pushbutton switch. Refer to the BusSwitch, PCCchip2, and VMEchip2 chapters in the

MVME197LE, MVME197DP, and MVME197SP Single Board Computers

Programmer’s Reference Guide for more detailed information.

Connectors

The MVME197LE has two 64-position DIN connectors: P1 and P2. Connector P1 rows A, B, C, and connector P2 row B pro vide the VMEbus interconnection. Connector P2 rows A and C provide the interconnect to the SCSI bus, the serial ports, the Ethernet interface, and the Centronics printer. There is a 249-pin mezzanine connector (J2) with the MC88110 bus interface. This mezzanine connector is for other MVME197 module expansion. On the MVME197LE there is also a 20-pin general purpose connector (J1) which provides the interconnect to the LEDs and the reset and abort signals. This connector is different for the other modules in the MVME197 series. Refer to the board specific SIMVME197 Single Board Com puter Support Information manual for detailed connector signal descriptions.

Memory Maps

There are three points of view for the memory maps: 1) the mapping of all resources as viewed by the Processor Bus (MC88110 bus), 2) the mapping of onboard/off-board resources as viewed from the Local Peripheral Bus (MC68040 compatible bus), and 3) the mapping of onboard resources as viewed by VMEbus Masters (VMEbus memory map).

Processor Bus Memory Map

Care should be taken, since all three maps are programmable. It is recommended that direct mapping from the Processor Bus to the Local Peripheral Bus be used.

MVME197LEIG/D1 1-13

Board Level Hardware Description

The memory maps of MVME197LE devices are provided in the following tables. Table 1-2 is the entire map from $00000000 to $FFFFFFFF. Many areas of the map are user-programmable, and suggested uses are shown in the table. This is assuming no address translation is used between the processor and local peripheral bus and between the local peripheral bus and VMEbus. The cache inhibit function is programmable in the MC88110. The onboard I/O space must be marked cache inhibit and serialized in its page table. Table 1-3 further defines the map for the local devices.

Table 1-2. Processor Bus Memory Map

Address Devices Port Size Software Notes

Range Accessed Size Cache

Inhibit

$00000000 - DRAM S IZE User Programmable D64 DRAMSIZE N 1

(Onboard DRAM)

DRAMSIZE - $FF7FFFFF User Programmable D32/D16 3GB ? 2,3

(VMEbus)

$FF800000 - $FFBFFFFF Flash Memory D32 4MB N 5 $FFC00000 - $FFEFFFFF reserved --- 3MB --- 4 $FFF00000 - $FFFEFFFF Local Devices D32-D8 1MB Y

(Refer to next table)

$FFFF0000 - $FFFFFFFF User Programmable D32/D16 64KB ? 1,3

(VMEbus A16)

Notes

1-14 Installation Guide

1. This area is user-programmable. The suggested use is shown in the table. The DRAM decoder i s programmed in the DCAM through the ECDM I2CBus interface. The Processor Bus to Local Peripheral Bus and the Local Peripheral Bus to Processor Bus decoders are programmed in the BusSwitch. The Local Peripheral to VMEbus (master) and VMEbus to Local Peripheral Bus (slave) decoders are programmed in the VMEchip2.

2. Size is approximate.

3. Cache inhibit depends on devices in area mapped.

4. This area is not decoded. If these locations are accessed and the local peripheral bus timer is enabled, the cycle times out and is terminated by a TEA signal.

5. This area is user programmable via the BusSwitch. Default size is 4 megabytes.

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