Motorola MVME177 User Manual

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MVME177

Single Board Computer

Installation and Use Manual

VME177A/IH2

Notice

While reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes.

No part of this material may be reproduced or copied in any tangible medium, or stored in a retrieval system, or transmitted in any form, or by any means, radio, electronic, mechanical, photocopying, recording or facsimile, or otherwise, without the prior written permission of Motorola, Inc.

It is possible that this publication may contain reference to, or information about Motorola products (machines and programs), programming, or services that are not announced in your country. Such references or information must not be construed to mean that Motorola intends to announce such Motorola products, programming, or services in your country.

Restricted Rights Legend

If the documentation contained herein is supplied, directly or indirectly, to the U.S. Government, the following notice shall apply unless otherwise agreed to in writing by Motorola, Inc.

Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227-7013.

Motorola, Inc.

Computer Group

2900 South Diablo Way

Tempe, Arizona 85282

Preface

The

MVME177 UserÕs Manual

and installation instructions, operating instructions, and functional description for the MVME177 Single Board Computer (referred to as MVME177 throughout this manual). The information contained in this manual applies to the following MVME177 models:

This manual is intended for anyone who wants to design OEM systems, supply additional capability to an existing compatible system, or work in a lab environment for experimental purposes.

A basic knowledge of computers and digital logic is assumed.

To use this manual, you should be familiar with the publications listed in the

All Rights Reserved

Printed in the United States of America

June 1996

Safety Summary

Safety Depends On You

The following general safety precautions must be observed during all phases of operation, service, and repair of this equipment. Failure to comply with these precautions or with speciÞc warnings elsewhere in this manual violates safety standards of design, manufacture, and intended use of the equipment. Motorola, Inc. assumes no liability for the customer's failure to comply with these requirements.

The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You, as the user of the product, should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment.

Ground the Instrument.

To minimize shock hazard, the equipment chassis and enclosure must be connected to an electrical ground. The equipment is supplied with a three-conductor ac power cable. The power cable must be plugged into an approved three-contact electrical outlet. The power jack and mating plug of the power cable meet International Electrotechnical Commission (IEC) safety standards.

Do Not Operate in an Explosive Atmosphere.

Do not operate the equipment in the presence of ßammable gases or fumes. Operation of any electrical equipment in such an environment constitutes a deÞnite safety hazard.

Keep Away From Live Circuits.

Operating personnel must not remove equipment covers. Only Factory Authorized Service Personnel or other qualiÞed maintenance personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment. Do not replace components with power cable connected. Under certain conditions, dangerous voltages may exist even with the power cable removed. To avoid injuries, always disconnect power and discharge circuits before touching them.

Do Not Service or Adjust Alone.

Do not attempt internal service or adjustment unless another person capable of rendering Þrst aid and resuscitation is present.

Use Caution When Exposing or Handling the CRT.

Breakage of the Cathode-Ray Tube (CRT) causes a high-velocity scattering of glass fragments (implosion). To prevent CRT implosion, avoid rough handling or jarring of the equipment. Handling of the CRT should be done only by qualiÞed maintenance personnel using approved safety mask and gloves.

Do Not Substitute Parts or Modify Equipment.

Because of the danger of introducing additional hazards, do not install substitute parts or perform any unauthorized modiÞcation of the equipment. Contact your local Motorola representative for service and repair to ensure that safety features are maintained.

Dangerous Procedure Warnings.

Warnings, such as the example below, precede potentially dangerous procedures throughout this manual. Instructions contained in the warnings must be followed. You should also employ all other safety precautions which you deem necessary for the operation of the equipment in your operating environment.

Dangerous voltages, capable of causing death, are present in

WARNING

this equipment. Use extreme caution when handling, testing, and adjusting.

Introduction 1-1 Model Designations 1-1 Features 1-2 SpeciÞcations 1-3

Cooling Requirements 1-3 FCC Compliance 1-5

General Description 1-5 Equipment Required 1-8 Related Documentation 1-9 Support Information 1-11 Manual Terminology 1-12 Introduction 2-1 Unpacking Instructions 2-1 Overview of Start-up Procedure 2-2 Hardware Preparation 2-4

Setup Instructions 2-10

MVME177 Module Installation Instructions 2-12

System Considerations 2-15

Introduction 3-1 Controls and Indicators 3-1

ABORT Switch S1 3-1 RESET Switch S2 3-2 Front Panel Indicators (DS1 - DS4) 3-3

Memory Maps 3-4

Local Bus Memory Map 3-4 Normal Address Range 3-4

Software Initialization 3-8

Multi-MPU Programming Considerations 3-8 Local Reset Operation 3-8

Introduction 4-1 MVME177 Functional Description 4-1

Data Bus Structure 4-1 MC68060 MPU 4-4 Flash Memory and EPROM 4-4

Flash Memory 4-4 EPROM 4-6

Contents

SRAM 4-7 Onboard DRAM 4-9 Battery Backed Up RAM and Clock 4-10 VMEbus Interface 4-11 I/O Interfaces 4-11

Serial Port Interface 4-12 Parallel Port Interface 4-14 Ethernet Interface 4-15 SCSI Interface 4-16 SCSI Termination 4-16

Local Resources 4-16

Programmable Tick Timers 4-17 Watchdog Timer 4-17 Software-Programmable Hardware Interrupts 4-17

Local Bus Time-out 4-18 Module IdentiÞcation 4-18 Timing Performance 4-18

Local Bus to DRAM Cycle Times 4-18

ROM Cycle Times 4-19

SCSI Transfers 4-19

LAN DMA Transfers 4-20 Remote Status and Control 4-20

Introduction A-1 Levels of Implementation A-3

Signal Adaptations A-4 Sample ConÞgurations A-4 Proper Grounding A-7

Overview of M68000 Firmware B-1 Description of 177Bug B-1

177Bug Implementation B-3

Autoboot B-3 ROMboot B-5 Network Boot B-6 Restarting the System B-7

Reset B-8 Abort B-8 Break B-9 SYSFAIL* Assertion/Negation B-10 MPU Clock Speed Calculation B-10

Memory Requirements B-11 Terminal Input/Output Control B-12

Disk I/O Support B-13

Blocks Versus Sectors B-13 Device Probe Function B-15 Disk I/O via 177Bug Commands B-16 IOI (Input/Output Inquiry) B-16 IOP (Physical I/O to Disk) B-16 IOT (I/O Teach) B-17 IOC (I/O Control) B-17 BO (Bootstrap Operating System) B-17 BH (Bootstrap and Halt) B-17 Disk I/O via 177Bug System Calls B-17 Default 177Bug Controller and Device Parameters B-19 Disk I/O Error Codes B-19 Network I/O Support B-19 Intel 82596 LAN Coprocessor Ethernet Driver B-20 UDP/IP Protocol Modules B-20 RARP/ARP Protocol Modules B-21 BOOTP Protocol Module B-21 TFTP Protocol Module B-21 Network Boot Control Module B-22 Network I/O Error Codes B-22

Multiprocessor Support B-22

Multiprocessor Control Register (MPCR) Method B-22 GCSR Method B-24

Diagnostic Facilities B-25 Using the 177Bug Debugger B-27

Entering Debugger Command Lines B-27 Syntactic Variables B-28

Expression as a Parameter B-29 Address as a Parameter B-31 Address Formats B-31 Offset Registers B-32

Port Numbers B-34

Entering and Debugging Programs B-35 Calling System Utilities from User Programs B-36 Preserving the Debugger Operating Environment B-36

177Bug Vector Table and Workspace B-36 Hardware Functions B-37 Exception Vectors Used by 177Bug B-37

Using 177Bug Target Vector Table B-39 Creating a New Vector Table B-40

177Bug Generalized Exception Handler B-42

Floating Point Support B-44

Single Precision Real B-45 Double Precision Real B-46 Extended Precision Real B-46 Packed Decimal Real B-46 ScientiÞc Notation B-47

Additions to FLASH Commands B-47

Flash Test ConÞguration Acceptable Entries B-48 Erase Test B-48 Flash Fill Test B-48 Flash Patterns Test B-49 Default Flash Test ConÞguration B-50 SFLASH Command B-51

The 177Bug Debugger Command Set B-53 Disk/Tape Controller Modules Supported C-1 Disk/Tape Controller Default ConÞgurations C-2 IOT Command Parameters for Supported Floppy Types C-5 ConÞgure Board Information Block D-1 Set Environment to Bug/Operating System D-3 Network Controller Modules Supported E-1

List of Figures

MVME177 Switches, Headers, Connectors, Polyswitches, and LEDs 2-5

MVME177 Block Diagram 4-3

MVME177 Model Designations 1-1 MVME177 Features 1-2 MVME177 SpeciÞcations 1-4 Start-up Overview 2-2 ConÞguring MVME177 Headers 2-6 Local Bus Memory Map 3-5 Local I/O Devices Memory Map 3-6 EPROM and Flash Control and ConÞguration 4-5 Diagnostic Test Groups B-26

List of Tables

xii

1General Information

Introduction

This manual provides:

General information

❏

Preparation for use and installation instructions

❏

Operating instructions

❏

Functional description

❏

for the MVME177 series of Single Board Computers (referred to as the MVME177 throughout this manual).

Model Designations

The MVME177 is available in the models listed in Table 1 - 1.

Table 1-1. MVME177 Model Designations

Model Number Speed Major Differences

MVME177-001 50 MHz MC68060, 4MB Onboard ECC DRAM MVME177-002 50 MHz MC68060, 8MB Onboard ECC DRAM MVME177-003 50 MHz MC68060, 16MB Onboard ECC DRAM MVME177-004 50 MHz MC68060, 32MB Onboard ECCDRAM MVME177-005 50 MHz MC68060, 64MB Onboard ECC DRAM MVME177-006 50 MHz MC68060, 128MB Onboard ECC DRAM MVME177-011 60 MHz MC68060, 4MB Onboard ECC DRAM MVME177-012 60 MHz MC68060, 8MB Onboard ECC DRAM MVME177-013 60 MHz MC68060, 16MB Onboard ECC DRAM MVME177-014 60 MHz MC68060, 32MB Onboard ECCDRAM MVME177-015 60 MHz MC68060, 64MB Onboard ECC DRAM MVME177-016 60 MHz MC68060, 128MB Onboard ECC DRAM

1-1

General Information

Features

Features of the MVME177 are listed in the following table:

Table 1-2. MVME177 Features

Feature Description

Microprocessor MC68060 at 50 MHz (MVME177-00x) or 60 MHz (MVME177-01x) DRAM 4/8/16/32/64/128/256MB with ECC protection Flash Memory 4MB in four Intel 28F008SA chips with software control write

protection EPROM 1MB in two 44-pin PLCC sockets (organized as one bank of 32 bits) Jumper and software

control

SRAM 128KB (with optional battery backup) Status LEDs Eight LEDs: for FAIL, STAT, RUN, SCON, LAN, +12V (LAN

RAM 8K by 8 RAM and time of day clock with battery backup Switches RESET

Tick timers Four 32-bit tick timers for periodic interrupts Watchdog timer One watchdog timer Software interrupts Eight software interrupts I/O SCSI Bus interface with DMA

VMEbus interface VMEbus system controller functions

Remote connector For RESET and ABORT switches and LEDs

Mixed EPROM/Flash, or

All Flash conÞguration

power), SCSI, and VME.

ABORT

Four serial ports with EIA-232-D buffers with DMA

8-bit bidirectional parallel port

Ethernet transceiver interface with DMA

VMEbus interface to local bus (A24/A32, D8/ D16/D32

(D8/D16/D32/D64BLT) (BLT = Block Transfer)

Local bus to VMEbus interface (A16/A24/A32, D8/D16/D32)

VMEbus interrupter

Global CSR for interprocessor communications

DMA for fast local memory - VMEbus transfers (A16/A24/A32,

D16/D32 (D16/D32/D64BLT)

1-2

Speciﬁcations

General specifications for the MVME177 are listed in Table 1-3.

The following sections detail cooling requirements and FCC compliance.

Cooling Requirements

The Motorola MVME177 VMEmodule is specified, designed, and tested to operate reliably with an incoming air temperature range from 0û to 55û C (32û to 131û F) with forced air cooling at a velocity typically achievable by using a 100 CFM axial fan. Temperature qualification is performed in a standard Motorola VMEsystem chassis. Twenty-five watt load boards are inserted in two card slots, one on each side, adjacent to the board under test, to simulate a high power density system configuration. An assembly of three axial fans, rated at 100 CFM per fan, is placed directly under the VME card cage. The incoming air temperature is measured between the fan assembly and the card cage, where the incoming airstream first encounters the module under test. Test software is executed as the module is subjected to ambient temperature variations. Case temperatures of critical, high power density integrated circuits are monitored to ensure component vendors specifications are not exceeded.

Specifications

While the exact amount of airflow required for cooling depends on:

Ambient air temperature

❏

Type of board

❏

Number of boards

❏

Location of boards

❏

Other heat sources

❏

adequate cooling can usually be achieved with 10 CFM and 490 LFM flowing over the module. Less airflow is required to cool the module in environments having lower maximum ambients. Under

1-3

General Information

more favorable thermal conditions, it may be possible to operate the module reliably at higher than 55û C with increased airflow. It is important to note that there are several factors, in addition to the rated CFM of the air mover, which determine the actual volume and speed of air flowing over a module.

Forced air cooling is required for the Atlas motherboard. Additional cooling is required with the installation of the MPC604 RISC processor. A 3-pin header (J17) is provided on the motherboard for powering a dedicated fan. Refer to the

Requirements

section in the

General Information

chapter for temperature qualification information for the system board platform.

Table 1-3. MVME177 Speciﬁcations

Characteristics SpeciÞcations

Power requirements

(with both EPROM sockets populated and excluding external LAN transceiver)

Operating temperature (refer to

Cooling Requirements

Storage temperature -40û to +85û C Relative humidity 5% to 90% (non-condensing) Physical dimensions

PC board with mezzanine

module only

Height Depth

Thickness PC boards with connectors and front panel

Height

Depth

Thickness

section)

+5 Vdc (± 5%), 4.5 A (typical), 6.0 A (max.) (at 50 MHz, with 128MB ECC DRAM)

+12 Vdc (± 5%), 100 mA (max.)

(1.0 A (max.) with offboard LAN

transceiver)

-12 Vdc (± 5%), 100 mA (max.) 0û to 55û C at point of entry of forced air

(approximately 490 LFM)

Double-high VMEboard

9.187 inches (233.35 mm)

6.299 inches (160.00 mm)

0.662 inches (16.77 mm)

10.309 inches (261.85 mm)

7.4 inches (188 mm)

0.80 inches (20.32 mm)

Cooling

1-4

FCC Compliance

The MVME177 was tested in an FCC-compliant chassis, and meets the requirements for Class A equipment. FCC compliance was achieved under the following conditions:

1. Shielded cables on all external I/O ports.

2. Cable shields connected to earth ground via metal shell connectors bonded to a conductive module front panel.

3. Conductive chassis rails connected to earth ground. This provides the path for connecting shields to earth ground.

4. Front panel screws properly tightened.

For minimum RF emissions, it is essential that the conditions above be implemented; failure to do so could compromise the FCC compliance of the equipment containing the module.

General Description

The MVME177 is a double-high VMEmodule based on the MC68060 microprocessor. The MVME177 has:

4/8/16/32/64/128/256 MB of ECC-protected DRAM

❏

8KB of static RAM and time of day clock (with battery

❏

backup)

Ethernet transceiver interface

❏

Four serial ports with EIA-232-D interface

❏

Four tick timers

❏

Watchdog timer

❏

4 MB of Flash memory

❏

Two EPROM sockets

❏

SCSI bus interface with DMA

❏

1-5

General Information

One parallel port

❏

A 16/A24/A32/D8/D16/D32/D64 VMEbus master/slave

❏

interface

128KB of static RAM (with optional battery backup), and

❏

VMEbus system controller.

The I/O on the MVME177 is connected to the VMEbus P2 connector. The main board is connected through a P2 transition board and cables to the transition boards. The MVME177 supports the following transition boards:

MVME712-12

❏

MVME712-13

❏

MVME712M

❏

MVME712A

❏

MVME712AM

❏

1-6

MVME712B

❏

(referred to in this manual as MVME712

, unless separately

specified).

The MVME712

transition boards provide configuration headers

and industry standard connectors for the I/O devices.

The VMEbus interface is provided by an ASIC called the VMEchip2. The VMEchip2 includes:

Two tick timers

❏

A watchdog timer

❏

Programmable map decoders for the master and slave

❏

interfaces

VMEbus to/from local bus DMA controller

❏

VMEbus to/from local bus non-DMA programmed access

❏

interface

General Description

VMEbus interrupter

❏

VMEbus system controller

❏

VMEbus interrupt handler

❏

VMEbus requester

❏

Processor-to-VMEbus transfers can be:

❏

D16

❏

D32

❏

VMEchip2 DMA transfers to the VMEbus, however, can be:

D16

❏

D32

❏

D16/BLT

❏

D32/BLT

❏

D64/MBLT

❏

The PCCchip2 ASIC provides:

Two tick timers

❏

Interface to the LAN chip

❏

SCSI chip

❏

Serial port chip

❏

❏ Parallel (printer) port

❏ BBRAM

The MCECC memory controller ASIC provides the programmable interface for the ECC-protected DRAM mezzanine board.

1-7

General Information

Equipment Required

The following equipment is required to make a complete system using the MVME177:

❏ Terminal

❏ Disk drives and controllers

❏ One of the following Transition modules:

Ð MVME712-12 Ð MVME712-13 Ð MVME712M Ð MVME712A Ð MVME712AM Ð MVME712B

❏ Connecting cables

❏ P2 adapter

1-8

❏ Operating system

The MVME177Bug debug monitor firmware (177Bug) is provided in the two EPROMs in sockets on the MVME177 main module. It provides:

❏ Over 50 debug, up/downline load, and disk bootstrap load

commands

❏ Full set of onboard diagnostics

❏ One-line assembler/disassembler

177Bug includes a user interface which accepts commands from the system console terminal. 177Bug can also operate in a System Mode, which includes choices from a service menu. Refer to the

177Bug Diagnostics User's Manual and the Debugging Package for Motorola 68K CISC CPUs User's Manual for details.

Document Title

177Bug Diagnostics UserÕs Manual V177DIAA/UM

Debugging Package for Motorola 68K CISC CPUs User's Manual 68KBUG1/D and

Single Board Computers SCSI Software User's Manual SBCSCSI/D

Single Board Computers Programmer's Reference Guide VMESBCA/PG1

MVME712M Transition Module and P2 Adapter Board User's Manual

MVME712-12, MVME712-13, MVME712A, MVME712AM, and MVME712B Transition Module and LCP2 Adapter Board User's Manual

M68060 Microprocessor User's Manual M68060UM

The following publications are available from the sources indicated:

Number

68KBUG2/D

and VMESBCA/PG2

MVME712M/D

MVME712A/D

1-10

Versatile Backplane Bus: VMEbus, ANSI/IEEE Std 1014-1987, The Institute of Electrical and Electronics Engineers, Inc., 345 East 47th Street, New York, NY 10017 (VMEbus Specification). This is also available as Microprocessor system bus for 1 to 4 byte data, IEC 821 BUS, Bureau Central de la Commission Electrotechnique Internationale; 3, rue de VarembŽ, Geneva, Switzerland.

ANSI Small Computer System Interface-2 (SCSI-2), Draft Document X3.131-198X, Revision 10c; Global Engineering Documents, P.O.

Box 19539, Irvine, CA 92714.

CL-CD2400/2401 Four-Channel Multi-Protocol Communications Controller Data Sheet, order number 542400-003; Cirrus Logic, Inc.,

3100 West Warren Ave., Fremont, CA 94538.

82596CA Local Area Network Coprocessor Data Sheet, order number 290218; and 82596 User's Manual, order number 296853; Intel Corporation, Literature Sales, P.O. Box 58130, Santa Clara, CA 95052-8130.

NCR 53C710 SCSI I/O Processor Data Manual, order number NCR53C710DM; and NCR 53C710 SCSI I/O Processor ProgrammerÕs Guide, order number NCR53C710PG; NCR Corporation, Microelectronics Products Division, Colorado Springs, CO.

MK48T08 Timekeeper Static RAMs Databook, SGS-THOMPSON Microelectronics Group;

North & South American Marketing Headquarters, 1000 East Bell Road, Phoenix, AZ 85022-2699.

DS1643 Nonvolatile Timekeeping RAM, Dallas Semiconductor Data Manual, 4401 South Beltwood Parkway, Dallas, Texas 75244-3292.

Support Information

and 8Kx8 Zeropower TM RAM data sheet in

You can obtain connector interconnect signal information, parts lists, and schematics for the MVME177 free of charge by contacting your local Motorola sales office.

1-11

General Information

Manual T erminology

Throughout this manual, a convention is used which precedes data and address parameters by a character identifying the numeric format as follows:

$ dollar speciÞes a hexadecimal character % percent speciÞes a binary number & ampersand speciÞes a decimal number

Unless otherwise specified, all address references are in hexadecimal.

An asterisk (*) following the signal name for signals which are level significant denotes that the signal is true or valid when the signal is low.

An asterisk (*) following the signal name for signals which are edge significant denotes that the actions initiated by that signal occur on high to low transition.

1-12

In this manual, assertion and negation are used to specify forcing a signal to a particular state. In particular, assertion and assert refer to a signal that is active or true; negation and negate indicate a signal that is inactive or false. These terms are used independently of the voltage level (high or low) that they represent.

Data and address sizes are defined as follows:

❏ A byte is eight bits, numbered 0 through 7, with bit 0 being

the least significant

❏ A word is 16 bits, numbered 0 through 15, with bit 0 being the

least significant

❏ A longword is 32 bits, numbered 0 through 31, with bit 0

being the least significant

2Hardware Preparation and

Introduction

This chapter provides the following for the MVME177:

❏ Unpacking instructions

❏ Hardware preparation

❏ Installation instructions

The MVME712x transition module hardware preparation is provided in separate manuals. Refer to Related Documentation in Chapter 1.

Unpacking Instructions

Note If the shipping carton is damaged upon receipt, request

carrier's agent be present during unpacking and inspection of equipment

Installation

Caution

Unpack equipment from shipping carton. Refer to packing list and verify that all items are present. Save packing material for storing and reshipping of equipment.

Avoid touching areas of integrated circuitry; static discharge can damage circuits.

2-1

Hardware Preparation and Installation

Overview of Start-up Procedure

The following list identifies the things you will need to do before you can use this board, and where to find the information you need to perform each step. Be sure to read this entire chapter and read all Caution notes before beginning.

Table 2-1. Start-up Overview

What you will need to do ... Refer to ... On page ...

Set jumpers on your MVME177 module.

Ensure that EPROM devices are properly installed in the sockets.

Install your MVME177 module in the chassis.

Set jumpers on the transition board; connect and install the transition board, P2 adapter module, and optional SCSI device cables.

Connect a console terminal to the MVME712.

Connect any other optional devices or equipment you will be using.

Power up the system. Installation Instructions 2-12

Hardware Preparation 2-4

Installation Instructions 2-12

The userÕs manual you received with your MVME712 module, listed in Related Documentation

You may also wish to obtain the

Single Board Computer SCSI Software UserÕs Manual, listed in Related Documentation

Installation Instructions 2-12

The userÕs manual you received with your MVME712 module, listed in Related Documentation

EIA-232-D Interconnections A-1 Port Numbers B-34 Disk/Tape Controller Data C-1

Front Panel Indicators (DS1 - DS4) 3-3 Troubleshooting the MVME177;

Solving Start-up Problems

1-9

F-1

2-2

Overview of Start-up Procedure

Table 2-1. Start-up Overview (Continued)

What you will need to do ... Refer to ... On page ...

Note that the debugger prompt appears.

Initialize the clock. Installation Instructions 2-12

Examine and/or change environmental parameters.

Program the PPCchip2 and VMEchip2.

Installation Instructions 2-12 Debugger General Information. B-1 You may also wish to obtain the

Debugging Package for Motorola 68K CISC CPUs UserÕs Manual and the 177Bug Diagnostics UserÕs Manual, listed in Related Documentation

Debugger General Information B-1 Installation Instructions 2-12 Environment Command D-3 Memory Maps 3-4 You may also wish to obtain the

Single Board Computers ProgrammerÕs Reference Guide,

listed in Related Documentation

1-9

2-3

Hardware Preparation and Installation

Hardware Preparation

To select the desired configuration and ensure proper operation of the MVME177, certain option modifications may be necessary before installation. The MVME177 provides software control for most of these options. Some options cannot be done in software, so are done by jumpers on headers. Most other modifications are done by setting bits in control registers after the MVME177 has been installed in a system. (The MVME177 registers are described in

Chapter 4, and/or in the Single Board Computers Programmer's Reference Guide as listed in Related Documentation in Chapter 1).

The location of switches, jumper headers, connectors, and LED indicators on the MVME177 is illustrated in Figure 2-1.

The MVME177 has been factory tested and is shipped with the factory jumper settings described in the following sections. The MVME177 operates with its required and factory-installed Debug Monitor, MVME177Bug (177Bug), with these factory jumper settings.

Settings can be made for:

❏ General purpose readable jumpers on header (J1)

2-4

❏ SRAM backup power source select header (J2) (optional)

❏ System controller header (J6)

❏ Thermal sensing pins (J7)

❏ EPROM/Flash configuration jumper (J8)

❏ Serial port 4 clock configuration select headers (J9 and J10)

Refer to Table 2-2 to configure the jumper settings for each header.

Hardware Preparation

MVME

177

STATFAIL

RUN SCON

+12V

LAN

SCSI VME

ABORT

RESET

DS1

DS2

DS3

DS4

XU1

COMPONENTS ARE REMOVED FOR CLARITY

PRIMARY SIDE

S1 S2

POLYSWITCH

XU2

1615

2J71

A1B1C1

A32

B32

C32

MEZZANINE BOARD

A1B1C1

1817 9604

Figure 2-1. MVME177 Switches, Headers, Connectors, Polyswitches,

and LEDs

J10

A32

B32

C32

1 3

2-5

Hardware Preparation and Installation

1 2

2 3

Header

Number

Description ConÞguration Jumpers Notes

General purpose software readable jumpers

Table 2-2. Conﬁguring MVME177 Headers

Header

GPI0 - GPI2: User-deÞnable

GPI3: Reserved

GPI4 - GPI7: User-deÞnable

1 -- 2 (GPI0) 3 -- 4 (GPI1) 5 -- 6 (GPI2)

9-- 10 (GPI4) 11 -- 12 (GPI5) 13 -- 14 (GPI6) 15 -- 16 (GPI7)

GPI0 GPI1 GPI2

GPI3 GPI4 GPI5 GPI6

16GPI7

1, 2

(Factory

conÞguration)

VMEbus +5V STBY

2 -- 1

(Factory

conÞguration)

SRAM backup power source

Backup power disabled

4 -- 2

2 3

select header

Backup from

3 -- 2

battery

2-6

Hardware Preparation

Header

Number

Table 2-2. Conﬁguring MVME177 Headers (Continued)

Header

Description ConÞguration Jumpers Notes

3 2 1

THERM1

THERM2

System controller header

Thermal sensing pins

System controller

Auto system controller

Not system controller

Connected to MC68060 internal thermal resistor

1 -- 2

(Factory

conÞguration)

2 -- 3

None

(Factory

conÞguration)

EPROM/Flash conÞguration jumper

1MB EPROM and 2MB Flash enabled

4 MB Flash enabled

1 -- 2

(Factory

conÞguration)

None

2-7

Hardware Preparation and Installation

Table 2-2. Conﬁguring MVME177 Headers (Continued)

Header

Number

J10

Header

Description ConÞguration Jumpers Notes

Receive RTXC4 2 -- 3

(Factory

conÞguration)

Drive RTXC4 1 -- 2

Serial Port 4

clock conÞguration select headers

Receive TRXC4 2 -- 3

(Factory

conÞguration)

Drive TRXC4 1 -- 2

MVME177 Header Notes:

1. The general purpose readable jumpers on header J1 can be read as I/O control register 3 (at $FFF40088, bits 0-7) in the VMEchip2 LCSR (see Chapter 4, VMEchip2). The bit values are read as a 1 when the jumper is off, and as a 0 when the jumper is on.

2. On the MVME177, pins 7 and 8 (bit 3) are removed for board ID and the bit value is reserved.

2-8

Hardware Preparation

MVME177 Header Notes: (Continued)

3. Header J2 is used to select the power source used to back up the SRAM on the MVME177 when the backup battery is installed.

Do not remove all jumpers from J2. This may

disable the SRAM.

Caution

If you remove the battery, you must install jumpers on J2 between pins 2 and 4, as shown for Backup Power Disabled.

4. The MVME177 can be the VMEbus system controller. The system controller function is enabled, disabled, or conÞgured for automatic select by jumpers on header J6. If set for AUTO SCON, the MVME177 determines if it is the system controller by its position on the bus. If the MVME177 is in the Þrst slot from the left, it conÞgures itself as the system controller. When the MVME177 is system controller, the system controller when J6 is jumpered as shown.

SCON LED is turned on. The VMEchip2 may be conÞgured as a

Do not jumper J6 to Auto System Controller. At

Caution

this time, this feature is not functioning properly. Set up jumpers on J6 only as System Controller or Not System Controller.

Note

AUTO SCON only works with a non-active

backplane.

5. The thermal sensing pins, THERM1 and THERM2, are connected to an internal thermal resistor and provide information about the average temperature of the processor. Refer to the M68000 Microprocessors UserÕs Manual for additional information on the use of these pins.

6. The FLASH jumper, J8, is used to select the Flash memory and EPROM conÞguration on the MVME177. If the board is conÞgured for 1MB EPROM and 2MB Flash memory, the VMEchip2 GPIO bits can be programmed to select the Þrst or second 2MB of Flash. See Chapter 4 for more information on Flash memory. You can also use the 177Bug SFLASH command to map the Flash memory.

7. Serial port 4 can be conÞgured to use clock signals provided by the RTXC4 and TRXC4 signal lines. Headers J9 and J10 on the MVME177 conÞgure serial port 4 to drive or receive RTXC4 and TRXC4, respectively. Both jumpers should be set the same way. Factory conÞguration is with port 4 set to receive both signals. The remaining conÞguration of the clock lines is accomplished using the Serial Port 4 Clock ConÞguration Select header on the MVME712M transition board. Refer to the MVME712M Transition Module and P2 Adapter Board UserÕs Manual for conÞguration of that header.

2-9

Hardware Preparation and Installation

Setup Instructions

Even though the MVME177Bug EPROMs are installed on the MVME177 module in the factory, follow this setup procedure for 177Bug to operate properly with the MVME177.

Inserting or removing modules while power is applied

could damage module components.

Caution

1. Turn all equipment power OFF.

2. Refer to Table 2-2 in the Hardware Preparation section in this chapter and install/remove jumpers on headers as required for your particular application.

a. Jumpers on header J1 affect 177Bug operation as listed

below. The default condition is with seven jumpers installed between the following pairs of pins:

GPI0 GPI1 GPI2

GPI3 GPI4 GPI5 GPI6

16GPI7

2-10

The MVME177 may be configured with these readable jumpers. These jumpers can be read as a register (at $FFF40088) in the VMEchip2 LCSR. The bit values are read as a one when the jumper is off, and as a zero when the jumper is on. This jumper block (header J1) contains eight bits. Refer to the Single Board Computers Programmer's Reference Guide.

The MVME177Bug reserves/defines the four lower order bits (GPI3 to GPI0). The following table shows the bits reserved/defined by the debugger:

Hardware Preparation

Bit J1 Pins Description

Bit #0 (GPI0) 1-2 When this bit is a one (high), it instructs the debugger

to use local Static RAM for its work page (i.e., variables, stack, vector tables, etc.).

Bit #1 (GPI1) 3-4 When this bit is a one (high), it instructs the debugger

to use the default setup/operation parameters in ROM versus the user setup/operation parameters in NVRAM. This is the same as depressing the RESET and ABORT switches at the same time. This feature can be used in the event the user setup is corrupted or does not meet a sanity check. Refer to the ENV

command (Appendix B) for the ROM defaults. Bit #2 (GPI2) 5-6 Reserved for future use. Bit #3 (GPI3) 7-8 Reserved for bug board ID use. Bit #4 (GPI4) 9-10 Open to your application. Bit #5 (GPI5) 11-12 Open to your application. Bit #6 (GPI6) 13-14 Open to your application. Bit #7 (GPI7) 15-16 Open to your application.

b. Jumpers on headers J2, J6, J7, J8, J9, and J10 configure the

board as described in the instructions in Table 2-2.

3. Be sure that the two 256K x 16 177Bug EPROMs are installed in proper sockets on the MVME177 module. Install the odd label (such as B01) EPROM in socket XU1 (for Least Significant Words), and install the even label (such as B02) EPROM in XU2 (for Most Significant Words). Be sure that physical chip orientation is correct, with flatted corner of each EPROM aligned with corresponding portion of EPROM socket on the MVME177 module.

4. This completes the MVME177 Module hardware preparation procedures. Proceed to the next section to install the module in the chassis. Refer to the setup procedure for your particular chassis or system for details concerning the installation of the MVME177.

2-11

Hardware Preparation and Installation

MVME177 Module Installation Instructions

When you have configured the MVME177Õs headers and installed the selected EPROMs in the sockets as described previously, install the MVME177 module in the system as follows:

1. Turn all equipment power OFF and disconnect the power cable from the AC power source.

Caution

Warning

Inserting or removing modules while power is applied could result in damage to module components.

Dangerous voltages, capable of causing death, are present in this equipment. Use extreme caution when handling, testing, and adjusting.

2. Remove chassis cover as instructed in the equipment user's manual.

3. Remove the filler panel(s) from the appropriate card slot(s) at the front and rear of the chassis (if the chassis has a rear card cage). The MVME177 module requires power from both P1 and P2. It may be installed in any double-height unused card slot, if it is not configured as system controller. If the MVME177 is configured as system controller, it must be installed in the leftmost card slot (slot 1) to correctly initiate the bus-grant daisy-chain and to have proper operation of the IACK-daisy-chain driver. Install the MVME177 in the front of the chassis. You can install the MVME712x in the front or the rear of the chassis. Other modules in the system may have to be moved to allow space for the MVME712M which has a double-wide front panel.

2-12

4. Carefully slide the MVME177 module into the card slot. Be sure the module is seated properly into the P1 and P2 connectors on the backplane. Do not damage or bend connector pins. Fasten the module in the chassis with screws

MVME177 Module Installation Instructions

provided, making good contact with the transverse mounting rails to minimize RFI emissions.

5. Remove IACK and BG jumpers from the header on the chassis backplane for the card slot in which the MVME177 is installed.

6. Connect the P2 Adapter Board and specified cable(s) to the MVME177 at P2 on the backplane at the MVME177 slot, to mate with (optional) terminals or other peripherals at the EIA-232-D serial ports, parallel port, SCSI ports, and LAN Ethernet port. Refer to the manuals listed in Related Documentation in Chapter 1 for information on installing the P2 Adapter Board and the MVME712x transition module(s). (Some connection diagrams are in the Single Board Computers Programmer's Reference Guide). Some cable(s) are not provided with the MVME712x module(s), and therefore are made or provided by the user. (Motorola recommends using shielded cables for all connections to peripherals to minimize radiation). Connect the peripherals to the cable(s). Detailed information on the EIA-232-D signals supported is found in Appendix A.

7. Connect the terminal to be used as the 177Bug system console to the default debug EIA-232-D port at serial port 1 on backplane connector P2 through an MVME712x transition module. Refer to the Single Board Computers Programmer's Reference Guide for some possible connection diagrams. Set up the terminal as follows:

❏ Eight bits per character

❏ One stop bit per character

❏ Parity disabled (no parity)

❏ Baud rate 9600 baud (default baud rate of MVME177

ports at power-up)

After power-up, the baud rate of the debug port can be reconfigured by using the Port Format (PF) command of the 177Bug debugger.

2-13

Hardware Preparation and Installation

between 177Bug and the terminal to work, the terminal must do some form of handshaking. If the terminal being used does not do hardware handshaking via the CTS line, then it must do XON/XOFF handshaking. If you get garbled messages and missing characters, then you should check the terminal to make sure XON/XOFF handshaking is enabled.

8. If you want to connect devices (such as a host computer system and/or a serial printer) to the other EIA-232-D port connectors (marked SERIAL PORTS 2, 3, and 4 on the MVME712x transition module), connect the appropriate cables and configure the port(s) as detailed in step 6 above. After power-up, this(these) port(s) can be reconfigured by programming the MVME177 CD2401 Serial Controller Chip (SCC), or by using the 177Bug PF command.

Note that the MVME177 also contains a parallel port. To use a parallel device, such as a printer, with the MVME177, connect it to the "printer" port at P2 through an MVME712x transition module. Refer to the MVME177 Single Board Computers Programmer's Reference Guide for some possible connection diagrams. However, you could also use a module such as the MVME335 for a parallel port connection.

Note In order for high baud-rate serial communication

2-14

9. Install any other required VMEmodules in the system.

10. Replace the chassis cover.

11. Connect power cable to AC power source.

12. Turn equipment power ON. 177Bug executes some selfchecks and displays the debugger prompt "

177-Bug>" (if

177Bug is in Board Mode). However, if the ENV command has put 177Bug in System Mode, the system performs a selftest and attempts an autoboot. Refer to the ENV and MENU commands listed in the Debugger Command Table in Appendix B.

MVME177 Module Installation Instructions

Note that when the MVME177 comes up in a cold reset, 177Bug runs in System Mode. Using the Environment (ENV) or MENU commands can make 177Bug run in Board Mode. Refer to the Debugger Commands Table in Appendix B.

If the confidence test fails, the test aborts when the first fault is encountered. If possible, an appropriate message displays, and control then returns to the menu.

Refer to Appendix B for general information and operation of the Debugger.

13. At the the onboard Real-Time Clock (RTC) and to set the time and date.

14. Use the 177BugÕs ENV command to verify the NVRAM (BBRAM) parameters, and optionally use ENV to make changes to the environmental parameters. Refer to Appendix D for the environment parameters.

177-Bug> prompt, use the SET command to initialize

System Considerations

The MVME177 draws power from both P1 and P2 of the VMEbus backplane. P2 is also used for the upper 16 bits of data for 32-bit transfers, and for the upper 8 address lines for extended addressing mode. The MVME177 will not operate properly unless its main board is connected to P1 and P2 of the VMEbus backplane.

Whether the MVME177 operates as a VMEbus master or as a VMEbus slave, it is configured for 32 bits of address and for 32 bits of data (A32/D32). However, it handles A16 or A24 devices in the address ranges indicated in Chapter 3. D8 and/or D16 devices in the system must be handled by the MC68060 software. Refer to the memory maps in Chapter 3.

The MVME177 contains shared onboard DRAM whose base address is software-selectable. Both the onboard processor and offboard VMEbus devices see this local DRAM at base physical address $00000000, as programmed by the MVME177Bug

2-15

Hardware Preparation and Installation

address. Refer to the Single Board Computers Programmer's Reference Guide for details.

If the MVME177 attempts to access offboard resources in a nonexistent location, and is not system controller, and if the system does not have a global bus time-out, the MVME177 waits forever for the VMEbus cycle to complete. This causes the system to hang up. There is only one situation in which the system might lack this global bus time-out:

firmware. This may be changed, by software, to any other base

❏ The MVME177 is not the system controller, and

❏ There is no global bus time-out elsewhere in the system

Multiple MVME177 modules may be configured into a single VME card cage. In general, hardware multiprocessor features are supported.

Other MPUs on the VMEbus can:

❏ Interrupt

❏ Disable

❏ Communicate with, and

2-16

❏ Determine the operational status of

the processor(s). One register of the GCSR set includes four bits which function as location monitors to allow one MVME177 processor to broadcast a signal to other MVME177 processors, if any. All eight registers are accessible from any local processor as well as from the VMEbus.

The MVME177 provides +12 Vdc power to the Ethernet LAN transceiver interface through a 1 amp polyswitch F2 located on the MVME177 module. The +12V LED lights when +12 Vdc is available. The polyswitch is located near diode CR1. Polyswitches act like circuit breakers that reset automatically when the excessive load is removed. If the Ethernet transceiver fails to operate, check

MVME177 Module Installation Instructions

the polyswitch. When using the MVME712M module, the yellow LED (DS1) on the MVME712M front panel lights when LAN power is available, indicating that the polyswitch is good.

The MVME177 provides SCSI terminator power through a diode and a 1 amp polyswitch F1 located on the P2 Adapter Board. If the polyswitch is blown (i.e., open), the SCSI devices may not operate or may function erratically. When the P2 Adapter Board is used with an MVME712M and the SCSI bus is connected to the MVME712M, the green LED (DS2) on the MVME712M front panel lights when there is SCSI terminator power. If the LED flickers during SCSI bus operation, the polyswitch should be checked.

2-17

Hardware Preparation and Installation

2-18

3Operating Instructions

Introduction

This chapter provides necessary information to use the MVME177 module in a system configuration. This includes:

❏ Controls and indicators

❏ Memory maps

❏ Software initialization of the module

Controls and Indicators

On the front panel of the MVME177 module are the following:

❏ ABORT and RESET switches

❏ FAIL, STAT, RUN, SCON, LAN,+12V (LAN power), SCSI,

and VME indicators

ABORT Switch S1

When enabled by software, the recessed front panel ABORT switch generates an interrupt at a user-programmable level. It is normally used to abort program execution and return to the 177Bug debugger firmware located in the MVME177 EPROMs.

The ABORT switch interrupter in the VMEchip2 is an edge-sensitive interrupter connected to the ABORT switch. This interrupter is filtered to remove switch bounce.

3-1

Operating Instructions

RESET Switch S2

The recessed front panel RESET switch resets all onboard devices,

and drives SYSRESET* if the board is system controller. The RESET switch may be disabled by software.

The VMEchip2 includes both a global and a local reset driver. When the chip operates as the VMEbus system controller, the reset driver provides a global system reset by asserting the VMEbus signal SYSRESET*. A SYSRESET* may be generated by the following:

❏ RESET switch

❏ Power up reset

❏ Watchdog timeout

❏ Control bit in the LCSR

SYSRESET* remains asserted for at least 200 msec, as required by the VMEbus specification.

Similarly, the VMEchip2 provides an input signal and a control bit to initiate a local reset operation. By setting a control bit, software can maintain a board in a reset state, disabling a faulty board from participating in normal system operation. The local reset driver is enabled even when the VMEchip2 is not the system controller. A local reset may be generated by:

3-2

❏ RESET switch

❏ Power up reset

❏ Watchdog timeout

❏ VMEbus SYSRESET*

❏ Control bit in the GCSR

Front Panel Indicators (DS1 - DS4)

There are eight LEDs on the MVME177 front panel: FAIL, STAT, RUN, SCON, LAN, +12V (LAN power), SCSI, and VME. The purpose of each LED is as follows:

❏ The red FAIL LED (part of DS1) lights when the BRDFAIL

signal line is active

❏ The MC68060 status lines are decoded, on the MVME177, to

drive the yellow STAT (status) LED (part of DS1). In this case, a halt condition from the processor lights the LED

❏ The green RUN LED (part of DS2) lights when the local bus

TIP* signal line is low. This indicates one of the local bus masters is executing a local bus cycle

❏ The green SCON LED (part of DS2) lights when the

VMEchip2 in the MVME177 is the VMEbus system controller

❏ The green LAN LED (part of DS3) lights when the LAN chip

is local bus master

Controls and Indicators

❏ The MVME177 supplies +12V power to the Ethernet

transceiver interface through a fuse. The green +12V (LAN power) LED (part of DS3) lights when power is available to the transceiver interface

❏ The green SCSI LED (part of DS4) lights when the SCSI chip

is local bus master

❏ The green VME LED (part of DS4) lights when the board is

using the VMEbus (VMEbus AS* is asserted by the VMEchip2) or when the board is accessed by the VMEbus (VMEchip2 is the local bus master)

3-3

Operating Instructions

Memory Maps

There are two possible perspectives or points of view for memory

Local Bus Memory Map

maps:

❏ The mapping of all resources as viewed by local bus masters

(local bus memory map)

❏ The mapping of onboard resources as viewed by VMEbus

Masters (VMEbus memory map)

The local bus memory map is split into different address spaces by the transfer type (TT) signals. The local resources respond to the normal access and interrupt acknowledge codes.

There is some address translation capability in the VMEchip2. This allows multiple MVME177s on the same VMEbus with different virtual local bus maps as viewed by different VMEbus masters.

Normal Address Range

The memory map of devices that respond to the normal address range is shown in the following tables. The normal address range is defined by the Transfer Type (TT) signals on the local bus. On the MVME177, Transfer Types 0, 1, and 2 define the normal address range.

Table 3-1. Local Bus Memory Map, is the entire map from $00000000

to $FFFFFFFF. Many areas of the map are user-programmable, and suggested uses are shown in the table. The cache inhibit function is programmable in the MMUs. The onboard I/O space must be marked cache inhibit and serialized in its page table.

Table 3-2 on page 3-6 further defines the map for the local I/O

devices.

3-4

Table 3-1. Local Bus Memory Map

Address

Range Devices Accessed Port Size Size

$00000000 DRAMSIZE

DRAMSIZE $FF7FFFFF

$FF800000 $FFBFFFFF

$FFC00000 $FFDFFFFF

$FFE00000 $FFE1FFFF

$FFE20000 $FFEFFFFF

$FFF00000 $FFFEFFFF

$FFFF0000 $FFFFFFFF

User programmable (onboard ECC DRAM on mezzanine)

User programmable (VMEbus A32/A24)

EPROM/Flash D32 1MB

Reserved -- 2MB -- 5

Onboard SRAM (default) D32 128KB N 6

Onboard SRAM (repeated) D32 896KB N 6

Local I/O devices (refer to next table)

User programmable (VMEbus A16)

D32 DRAMSIZE N 1, 2

D32/D16 3GB - 3, 4

D32-D8 960KB

D32/D16 64KB - 2, 4

EPROM/ 4MB Flash

(1MB64KB)

Memory Maps

Software

Cache

Inhibit Notes

Notes:

1. Flash/EPROM devices appear at $FF800000 through $FFBFFFFF, and also appear at $00000000 through $003FFFFF if the ROM0 bit in the VMEchip2 EPROM control register is high (ROM0 = 1). The ROM0 bit is located at address $FFF40030 bit 20. ROM0 is set to 1 after each reset. The ROM0 bit must be cleared before other resources (DRAM or SRAM) can be mapped in this range ($00000000 through $003FFFFF). The VMEchip2 and DRAM map decoders are disabled by a local bus reset.

On the MVME177, the Flash/EPROM memory is mapped at $00000000 through $003FFFFF by hardware default through the VMEchip2.

3-5

Operating Instructions

2. This area is user-programmable. The suggested use is shown in the table. The DRAM decoder is programmed in the MCECC chip, and the local-to-VMEbus decoders are programmed in the

VMEchip2.

3. Size is approximate.

4. Cache inhibit depends on devices in area mapped.

5. This area is not decoded. If these locations are accessed and the local bus timer is enabled, the cycle times out and is terminated by a TEA signal.

6. The SRAM has optional battery backup on the MVME177.

The following table focuses on the Local I/O Devices portion of the local bus Main Memory Map.

Table 3-2. Local I/O Devices Memory Map

Address Range Devices Accessed Port Size Size Notes

$FFF00000 - $FFF3FFFF Reserved -- 256KB 5 $FFF40000 - $FFF400FF VMEchip2 (LCSR) D32 256B 1,4 $FFF40100 - $FFF401FF VMEchip2 (GCSR) D32-D8 256B 1,4 $FFF40200 - $FFF40FFF Reserved -- 3.5KB 5,7 $FFF41000 - $FFF41FFF Reserved -- 4KB 5 $FFF42000 - $FFF42FFF PCCchip2 D32-D8 4KB 1 $FFF43000 - $FFF430FF MCECC #1 D8 256B 1 $FFF43100 - $FFF431FF MCECC #2 D8 256B 1 $FFF43200 - $FFF43FFF MCECCs (repeated) -- 3.5KB 1,7 $FFF44000 - $FFF44FFF Reserved -- 4KB 5 $FFF45000 - $FFF451FF CD2401 (Serial Comm. Cont.) D16-D8 512B 1,9 $FFF45200 - $FFF45DFF Reserved -- 3KB 7,9 $FFF45E00 - $FFF45FFF Reserved -- 512B 1,9 $FFF46000 - $FFF46FFF 82596CA (LAN) D32 4KB 1,8 $FFF47000 - $FFF47FFF 53C710 (SCSI) D32/D8 4KB 1 $FFF48000 - $FFF4FFFF Reserved -- 32KB 5 $FFF50000 - $FFF6FFFF Reserved -- 128KB 5 $FFF70000 - $FFF76FFF Reserved -- 28KB 6

3-6

Memory Maps

Table 3-2. Local I/O Devices Memory Map (Continued)

Address Range Devices Accessed Port Size Size Notes

$FFF77000 - $FFF77FFF Reserved -- 4KB 2 $FFF78000 - $FFF7EFFF Reserved -- 28KB 6 $FFF7F000 - $FFF7FFFF Reserved -- 4KB 2 $FFF80000 - $FFF9FFFF Reserved -- 128KB 6 $FFFA0000 - $FFFBFFFF Reserved -- 128KB 5 $FFFC0000 - $FFFCFFFF DS1643/MK48T08 (BBRAM,

TOD Clock) $FFFD0000 - $FFFDFFFF Reserved -- 64KB 5 $FFFE0000 - $FFFEFFFF Reserved -- 64KB 2

D32-D8 64KB 1

Notes:

1. For a complete description of the register bits, refer to the data sheet for the specific chip. For a more detailed memory map, refer to the following detailed peripheral device memory maps.

2. On the MVME177 this area does not return an acknowledge signal. If the local bus timer is enabled, the access times out and terminates by a TEA signal.

3. Byte reads should be used to read the interrupt vector. These locations do not respond when an interrupt is not pending. If the local bus timer is enabled, the access times out and terminates by a TEA signal.

4. Writes to the LCSR in the VMEchip2 must be 32 bits. LCSR writes of 8 or 16 bits terminate with a TEA signal. Writes to the GCSR may be 8, 16 or 32 bits. Reads to the LCSR and GCSR may be 8, 16 or 32 bits.

5. This area does not return an acknowledge signal. If the local bus timer is enabled, the access times out and terminates by a TEA signal.

6. This area does return an acknowledge signal.

7. Size is approximate.

3-7

Operating Instructions

8. Port commands to the 82596CA must be written as two 16-bit writes: upper word first and lower word second.

9. The CD2401 appears repeatedly from $FFF45200 to $FFF45FFF

on the MVME177. If the local bus timer is enabled, the access times out and terminates by a TEA signal.

Software Initialization

Most functions that have been enabled with switches or jumpers on other modules are enabled by setting control registers on the MVME177. At power up or reset, the EPROMs that contain the 177Bug debugging package set up the default values of many of these registers.

Specific programming details may be determined by study of the M68060 Microprocessor User's Manual. You can also check the details of all the MVME177 onboard registers as given in the Single Board Computers Programmer's Reference Guide.

Multi-MPU Programming Considerations

Good programming practice dictates that only one MPU at a time has control of the MVME177 control registers.

Of particular note are:

❏ Registers that modify the address map

❏ Registers that require two cycles to access

❏ VMEbus interrupt request registers

Local Reset Operation

Local reset (LRST) is a subset of system reset (SRST). Local reset can

be generated five ways:

❏ Expiration of the watchdog timer

3-8

Software Initialization

❏ Pressing the front panel RESET switch (if the system

controller function is disabled)

❏ Asserting a bit in the board control register in the GCSR

❏ SYSRESET*

❏ Power-up reset

Note The GCSR allows a VMEbus master to reset the local

bus. This feature is very dangerous and should be used with caution. The local reset feature is a partial system reset, not a complete system reset such as power-up reset or SYSRESET*. When the local bus reset signal is asserted, a local bus cycle may be aborted. The VMEchip2 is connected to both the local bus and the VMEbus and if the aborted cycle is bound for the VMEbus, erratic operation may result. Communications between the local processor and a VMEbus master should use interrupts or mailbox locations; reset should not be used in normal communications. Reset should be used only when the local processor is halted or the local bus is hung and reset is the last resort.

Any VMEbus access to the MVME177 while it is in the reset state is ignored. If a global bus timer is enabled, a bus error is generated.

3-9

Operating Instructions

3-10

4Functional Description

Introduction

This chapter provides a block diagram level description for the MVME177 module. The functional description provides an overview of the module, followed by a detailed description of several blocks of the module. The block diagram of the MVME177 is shown in Figure 4-1 on page 4-3.

Descriptions of the other blocks of the MVME177, including programmable registers in the ASICs and peripheral chips, are given in the Single Board Computers Programmer's Reference Guide. Refer to it for the rest of the functional description of the MVME177 module.

MVME177 Functional Description

The MVME177 is a high functionality VMEbus single board computer designed around the MC68060 chip. The MVME177 has:

❏ 4/8/16/32/64/128/256MB of dynamic RAM

❏ SCSI mass storage interface

❏ Four serial ports

❏ One parallel port

❏ Ethernet transceiver interface

Data Bus Structure

The local data bus on the MVME177 is a 32-bit synchronous bus that is based on the MC68060 bus, and supports burst transfers and snooping. The various local bus master and slave devices use the

4-1

Functional Description

local bus to communicate. The local bus is arbitrated by priority type arbiter and the priority of the local bus masters from highest to lowest is:

❏ 82596CA LAN

❏ CD2401 serial (through the PCCchip2)

❏ 53C710 SCSI

❏ VMEbus

❏ MPU

In the general case, any master can access any slave; however, not all combinations pass the common sense test. Refer to the Single Board Computers Programmer's Reference Guide and to the user's guide for each device to determine:

❏ Port size

❏ Data bus connection

4-2

❏ Any restrictions that apply when accessing the device

MVME177 Functional Description

3 Async/1 Sync

4 Asynchronous or

SCSI

Peripherals

Ethernet

Transceiver

Port

Centronics

Parallel I/O

CD2401

Quad Serial

I/O Controller

SCSI

53C710

Coprocessor

Ethernet

Controller

i82596CA

ASIC

PCC2

MK48T08

DS1643 or

Battery Backed

8KB RAM/Clock

Control

Data

MUX

Address

4MB FLASH

1818 9604

4 to 256MB ECC DRAM

VMEbus

Master/Slave

A32/24:D64/32/16/08

Figure 4-1. MVME177 Block Diagram

EPROM

2 44-pin PLCC

VMEbus

interface

VMEchip 2

MPU

MC68060

50 or 60 MHZ

128KB

SRAM w/

battery option

4-3

Functional Description

MC68060 MPU

The MC68060 microprocessor is the main processor for the MVME177. The superscalar MC68060 processor has:

❏ Two MC68040-compatible CPU integer cores

❏ MC68040-compatible floating point core

❏ Independent 8KB instruction and operand data caches

❏ MC68040-compatible paged memory management unit

❏ A bus controller

The processor is in a PGA socket. Its clock speed is 50 MHz (for the

-00x models), and 60 MHz (for the -01x models). Note that the local processor bus runs at only half the processor speed. Refer to the MC68060 user's manual for more information.

Flash Memory and EPROM

Flash Memory

The MVME177 includes four 28F008SA Flash memory devices. The Flash devices provide 4MB of ROM at address $FF800000$FFBFFFFF. The Flash is organized as one 32-bit bank for 32-bit code execution from the processor. The Flash could, for instance, be used for the onboard debugger firmware (177Bug) which would be downloaded from I/O resources such as:

4-4

❏ Ethernet

❏ SCSI

❏ A serial port, or

❏ The VMEbus

When Flash is used with EPROM, either the top or bottom 2MB of Flash is available in the second 2MB of memory space after the EPROM. Refer to Table 4-1 below.

MVME177 Functional Description

Table 4-1. EPROM and Flash Control and Conﬁguration

Jumper or Control Bit Control Condition Memory ConÞguration

FLASHJP jumper J8 Jumper in (= low) 2MB EPROM (lower) and 2MB Flash

(upper)

Jumper out (= high) All 4MB Flash

VMEchip2 bit GPIO2 GPIO2 bit low (and

with J8 jumper in) GPIO2 bit high (and

with J8 jumper in)

Note: These 2MB of Flash will be following the EPROMs in memory if the FLASHJP (J8) jumper is in, and could be read or write depending on the Flash write protect control.

First 2MB Flash accessible (Note)

Second 2MB Flash accessible (Note)

Because only 1M x 8-bit Flash chips are used, there is no userconfigured jumper selection block required to pick the Flash chip size.

The memory map for the Flash devices is controlled by the VMEchip2 ASIC. The 32-bit wide Flash can support:

❏ 8 bit

❏ 16 bit, and

❏ 32 bit access

Flash write protection is programmable through the VMEchip2 GPIO register. The address map location of Flash is at $000000 through $3FFFFF at local reset if the FLASHJP jumper (J8) is in, providing for the all-Flash mode. In the mixed EPROM/Flash mode, half of the Flash is accessable at addresses $200000 through $3FFFFF, depending on the condition of the VMEchip2 GPIO2 bit.

Because the MVME177 uses 1M x 8-bit Flash memory devices and EPROMs with no download ROM, the software programs the VMEchip2 ROM0 and REV EROM bits properly so that the Flash/EPROM appears at address $0 after powerup. The hardware is implemented so that the EPROM/Flash appears at address $00000000 following a local bus reset.

4-5

Functional Description

The MVME177 implements Flash write protection through clearing a control bit (GPIO1) in the GPIO register in the VMEchip2, to enable write by the software after download process/ programming is completed.

EPROM

There are two 44-pin PLCC/CLCC EPROM sockets for SGSThompson M27C4002 (256K x 16) or AMD 27C4096 type EPROMs. They are organized as one 32-bit wide bank that supports:

❏ 8 bit

❏ 16 bit, and

❏ 32-bit read accesses

The EPROMs as shipped are normally used for the onboard debugger firmware (177Bug), but could be used to download user code to Flash. The EPROMs make up only 1MB of memory, but can share the first 2MB of space with the first 2MB of Flash. The EPROMs occupy only 1MB space in the ROM space in mixed mode and will be repeated in the second 1MB space (which is reserved for future expansion). The EPROMs could coexist with this 2MB of Flash, or could be used to program all 4MB of Flash, then the J8 jumper could be removed to make only Flash available.

4-6

After a system reset, the EPROMs are mapped to the default addresses $00000 through $FFFFF, and could be mapped to $FF800000 through $FF8FFFFF if needed. The control between mapping EPROM/Flash mixed mode and all Flash mode is done by the combination of external board jumper J8 and the VMEchip2 bit GPIO2. Table 4-1 shows how the ÒFlashÓ jumper and GPIO bit 2 change the EPROM/Flash configuration.

MVME177 Functional Description

The EPROMs/Flashes are mapped to local bus address 0 following a local bus reset. This allows the MC68060 to access the reset vector and execution address following a reset. The EPROMs are controlled by the VMEchip2. The following items are all programmable:

SRAM

❏ Map decoder

❏ Access time

❏ Time they appear at address 0

For more detail, refer to the VMEchip2 in the Single Board Computers Programmer's Reference Guide.

The boards include 128KB of 32-bit wide static RAM arrays that are not parity protected and support:

❏ 8 bit

❏ 16 bit, and

❏ 32 bit wide accesses

The SRAM allows the debugger to operate and limited diagnostics to be executed without the DRAM mezzanine. The SRAM will not support burst cycles. The SRAM is controlled by the VMEchip2, and the access time is programmable. Refer to the VMEchip2 in the Single Board Computers Programmer's Reference Guide for more detail. The boards are populated with 100 ns SRAMs.

SRAM battery backup is optionally available on the MVME177. The battery backup function is provided by a Dallas DS1210S. Only one backup power source is supported on the MVME177. The battery supplies VCC to the SRAMs when main power is removed.

Each time the MVME177 is powered up, the DS1210S checks the power source. If the voltage of the backup source is less than two volts, the second memory cycle is blocked. This allows software to

4-7

Functional Description

provide an early warning to avoid data loss. Because the DS1210S may block the second access, the software should do at least two accesses before relying on the data.

Optionally, the MVME177 provides jumpers that allow the power source of the DS1210S to connect to the VMEbus +5 V STDBY pin

or the onboard battery.

The optional power source for the SRAM is a socketed Sanyo CR2430 battery. A small capacitor is provided to allow the battery to be quickly replaced without data loss.

The lifetime of the battery is very dependent on the ambient temperature of the board and the power-on duty cycle. The FB1225 and CR2430 lithium batteries should provide at least two years of backup time with the board powered off and the board at 40û C. If the power-on duty cycle is 50% (the board is powered on half of the time), the battery lifetime is four years. At lower ambient temperatures the backup time is greatly extended and may approach the shelf life of the battery.

When a board is stored, if the battery is present, it should be disconnected to prolong battery life. This is especially important at high ambient temperatures. MVME177 boards with battery backup are shipped with the batteries disconnected.

4-8

The power leads from the battery are exposed on the solder side of the board, therefore the board should not be placed on a conductive surface or stored in a conductive bag unless the battery is removed.

Note Lithium batteries incorporate inflammable materials

such as lithium and organic solvents. If lithium batteries are mistreated or handled incorrectly, they may burst open and ignite, possibly resulting in injury and/or fire. When dealing with lithium batteries, carefully follow the precautions listed below in order to prevent accidents:

❏ Do not short circuit

❏ Do not disassemble, deform, or apply excessive pressure

❏ Do not heat or incinerate

❏ Do not apply solder directly

❏ Do not use different models, or new and old batteries

❏ Do not charge

❏ Always check proper polarity

To remove the battery from the module, carefully pull the battery from the socket.

Onboard DRAM

The MVME177 onboard DRAM is located on a mezzanine board. The mezzanine boards use error checking and correction (ECC) protection to correct single-bit errors and detect double-bit errors. Interrupts or bus exception can be enabled when a bit error is detected. The interrupt output from the memory mezzanine is connected to the VMEchip2 PEIRQ* interrupt input.

together

MVME177 Functional Description

Mezzanine board sizes are:

❏ 4MB

❏ 8MB

❏ 16MB

❏ 32MB

❏ 64MB

❏ 128MB (ECC)

4-9

Functional Description

Two mezzanine boards may be stacked to provide 256MB of onboard RAM. The main board and a single mezzanine board together take one slot. The stacked configuration requires two VMEboard slots. The DRAM is four-way interleaved to efficiently support cache burst cycles.

The DRAM map decoder can be programmed to accommodate different base address(es) and sizes of mezzanine boards. The onboard DRAM is disabled by a local bus reset and must be programmed before the DRAM can be accessed. Refer to the MCECC in the Single Board Computers Programmer's Reference Guide for detailed programming information. Most DRAM devices require some number of access cycles before the DRAMs are fully operational. Normally this requirement is met by the onboard refresh circuitry and normal DRAM initialization. However, software should insure a minimum of 10 initialization cycles are performed to each bank of RAM.

Battery Backed Up RAM and Clock

The DS1643/MK48T08 RAM and clock chip is used on the MVME177. This chip provides the following items, all in one 28-pin package:

❏ Time of day clock

❏ Oscillator

❏ Crystal

4-10

❏ Power fail detection

❏ Memory write protection

❏ 8KB of RAM

❏ A battery

The clock provides:

❏ Seconds

❏ Minutes

❏ Hours

❏ Day

❏ Date

MVME177 Functional Description

❏ Month

❏ Year

in BCD 24-hour format. Corrections for 28-, 29- (leap year), and 30-day months are automatically made. No interrupts are generated by the clock. The DS1643/MK48T08 is an 8 bit device; however, the interface provided by the PCCchip2 supports:

❏ 8 bit

❏ 16 bit, and

❏ 32 bit accesses to the DS1643/MK48T08

Refer to the PCCchip2 in the Single Board Computers Programmer's Reference Guide and to the DS1643/MK48T08 data sheet for detailed

programming information.

VMEbus Interface

The local bus to VMEbus interface, the VMEbus to local bus interface, and the local-VMEbus DMA controller functions on the MVME177 are provided by the VMEchip2. The VMEchip2 can also provide the VMEbus system controller functions. Refer to the VMEchip2 in the Single Board Computers Programmer's Reference Guide for detailed programming information.

I/O Interfaces

The MVME177 provides onboard I/O for many system applications. The I/O functions include:

❏ Serial ports

4-11

Functional Description

❏ Parallel (printer) port

❏ Ethernet transceiver interface

❏ SCSI mass storage interface

Serial Port Interface

The CD2401 serial controller chip (SCC) is used to implement the four serial ports. The serial ports support the standard baud rates (110 to 38.4K baud). The four serial ports are different functionally because of the limited number of pins on the P2 I/O connector. Serial port 1 is a minimum function asynchronous port. It uses:

❏ RXD

❏ CTS

❏ TXD

❏ RTS

Serial ports 2 and 3 are full function asynchronous ports. They use:

4-12

❏ RXD

❏ CTS

❏ DCD

❏ TXD

❏ RTS

❏ DTR

Serial port 4 is a full function asynchronous or synchronous port. It can operate at synchronous bit rates up to 64 k bits per second. It uses:

❏ RXD

❏ CTS

❏ DCD

MVME177 Functional Description

❏ TXD

❏ RTS

❏ DTR

It also interfaces to the synchronous clock signal lines. Refer to the Single Board Computers Programmer's Reference Guide for drawings of the serial port interface connections.

All four serial ports use EIA-232-D drivers and receivers located on the main board, and all the signal lines are routed to the I/O connector. The configuration headers are located on the main board and the MVME712x transition board. An external I/O transition board such as the MVME712x should be used to convert the I/O connector pinout to industry-standard connectors.

Note The MVME177 board hardware ties the DTR signal

from the CD2401 to the pin labeled RTS at connector P2. Likewise, RTS from the CD2401 is tied to DTR on P2. Therefore, when programming the CD2401, assert DTR when you want RTS, and RTS when you want DTR.

The interface provided by the PCCchip2 allows the 16-bit CD2401 to appear at contiguous addresses; however, accesses to the CD2401 must be 8 or 16 bits. 32-bit accesses are not permitted. Refer to the CD2401 data sheet and to the PCCchip2 in the Single Board Computers Programmer's Reference Guide for detailed programming information.

The CD2401 supports DMA operations to local memory. Because the CD2401 does not support a retry operation necessary to break VMEbus lockup conditions, the CD2401 DMA controllers should not be programmed to access the VMEbus. The hardware does not restrict the CD2401 to onboard DRAM.

4-13

Functional Description

Parallel Port Interface

The PCCchip2 provides an 8-bit bidirectional parallel port. All eight bits of the port must be either inputs or outputs (no individual selection). In addition to the 8 bits of data, there are two control pins and five status pins. Each of the status pins can generate an

interrupt to the MPU in any of the following programmable conditions:

❏ High level

❏ Low level

❏ High-to-low transition

❏ Low-to-high transition

This port may be used as a Centronics- compatible parallel printer port or as a general parallel I/O port.

When used as a parallel printer port, the five status pins function as Printer:

4-14

❏ Acknowledge (ACK)

❏ Fault (FAULT*)

❏ Busy (BSY)

❏ Select (SELECT)

❏ Paper Error (PE)

The control pins act as:

❏ Printer Strobe (STROBE*)

❏ Input Prime (INP*)

The PCCchip2 provides an auto-strobe feature similar to that of the MVME147 PCC. In auto-strobe mode, after a write to the Printer Data Register, the PCCchip2 automatically asserts the STROBE* pin for a selected time specified by the Printer Fast Strobe control bit. In manual mode, the Printer Strobe control bit directly controls the state of the STROBE* pin.

Refer to the Single Board Computers Programmer's Reference Guide for drawings of the printer port interface connections.

Ethernet Interface

The 82596CA is used to implement the Ethernet transceiver interface. The 82596CA accesses local RAM using DMA operations to perform its normal functions. Because the 82596CA has small internal buffers and the VMEbus has an undefined latency period, buffer overrun may occur if the DMA is programmed to access the VMEbus. Therefore, the 82596CA should not be programmed to access the VMEbus.

Every MVME177 is assigned an Ethernet Station Address. The address is $08003E2xxxxx, where xxxxx is the unique 5-nibble number assigned to the board (i.e., every MVME177 has a different value for xxxxx).

Each module has an Ethernet Station Address displayed on a label attached to the VMEbus P2 connector. In addition, the six bytes including the Ethernet address are stored in the configuration area of the BBRAM. That is, 08003E2xxxxx is stored in the BBRAM. At an address of $FFFC1F2C, the upper four bytes (08003E2x) can be read. At an address of $FFFC1F30, the lower two bytes (xxxx) can be read. Refer to the BBRAM, TOD Clock memory map description in Chapter 3. The MVME177 debugger has the capability to retrieve or set the Ethernet address.

MVME177 Functional Description

If the data in the BBRAM is lost, the user should use the number on the VMEbus P2 connector label to restore it.

The Ethernet transceiver interface is located on the MVME177 main module, and the industry standard connector is located on the MVME712x transition module.

Support functions for the 82596CA are provided by the PCCchip2. Refer to the 82596CA user's guide and to the Single Board Computers Programmer's Reference Guide for detailed programming information.

4-15

Functional Description

SCSI Interface

The MVME177 provides for mass storage subsystems through the industry-standard SCSI bus. These subsystems may include:

❏ Hard and floppy disk drives

❏ Streaming tape drives

❏ Other mass storage devices

The SCSI interface is implemented using the NCR 53C710 SCSI I/O controller.

The SCSI clock input to the 53C710 is fixed at 50 MHz, in order to have higher SCSI bus performance, and to make it easier for software to program the 53C710 controller when the MC68060 processor speed changes.

Support functions for the 53C710 are provided by the PCCchip2. Refer to the 53C710 user's guide and to the Single Board Computers Programmer's Reference Guide for detailed programming information.

SCSI Termination

The system configurer must ensure that the SCSI bus is properly terminated at both ends. On the MVME177, sockets are provided for the terminators on the P2 transition board. If the SCSI bus ends at the P2 transition board, then termination resistors must be installed on the P2 transition board. +5V power to the SCSI bus TERM power line and termination resistors is provided through a fuse on the MVME712 transition board, and a diode located on the P2 transition board.

Local Resources

The MVME177 includes many resources for the local processor. These include:

❏ Tick timers

❏ Software programmable hardware interrupts

❏ Watchdog timer

4-16

MVME177 Functional Description

❏ Local bus time-out

Note The time basis for all local resources is set by Prescaler

Programmable Tick Timer s

Four 32-bit programmable tick timers with 1 µs resolution are

provided:

❏ Two in the VMEchip2 and

❏ Two in the PCCchip2

The tick timers can be programmed to generate periodic interrupts to the processor. Refer to the VMEchip2 and PCCchip2 in the Single Board Computers Programmer's Reference Guide for detailed programming information.

Watchdog Timer

A watchdog timer function is provided in the VMEchip2. When the watchdog timer is enabled, it must be reset by software within the programmed time or it times out. The watchdog timer can be programmed to generate:

❏ A SYSRESET signal

❏ Local reset signal, or

❏ Board fail signal if it times out

Refer to the VMEchip2 in the Single Board Computers Programmer's Reference Guide for detailed programming information.

Software-Programmable Hardware Interrupts

Eight software-programmable hardware interrupts are provided by the VMEchip2. These interrupts allow software to create a hardware interrupt. Refer to the VMEchip2 in the Single Board Computers Programmer's Reference Guide for detailed programming information.

4-17

Functional Description

Local Bus Time-out

The MVME177 provides a time-out function for the local bus. When the timer is enabled and a local bus access times out, a Transfer Error Acknowledge (TEA) signal is sent to the local bus master. The time-out value is selectable by software for:

❏ 8 µsec ❏ 64 µsec ❏ 256 µsec

❏ Infinite

The local bus timer does not operate during VMEbus bound cycles. VMEbus bound cycles are timed by the VMEbus access timer and the VMEbus global timer. Refer to the VMEchip2 in the Single Board Computers Programmer's Reference Guide for detailed programming information.

Module Identiﬁcation

Software distinguishes between an MVME177 module and an MVME176 module by use of the I/O control register (GPI) bit 3. On an MVME177, the I/O control register (GPI) bit 3 is out (open) for a ÒhighÓ (one). On an MVME176, the I/O control register (GPI) bit 3 is hardwired in (shorted) for a ÒlowÓ (zero).

Timing Performance

This section provides the performance information for the MVME177. Various MVME177s are designed to operate at 50 MHz or 60 MHz (when supported by 060).

Local Bus to DRAM Cycle Times

The PCCchip2 and VMEchip2 have the same local bus interface timing as the MC68060, therefore the following cycle times also apply to the PCCchip2 and the VMEchip2. Read accesses to

4-18

onboard DRAM require 5 bus clock cycles with the bus error reported in the current cycle. Write accesses to onboard DRAM require 2 bus clock cycles.

Burst read accesses require 8 (5-1-1-1) bus clock cycles with the bus error reported in the current cycle. Burst write cycles require 5 (2-1-1-1) bus clock cycles.

ROM Cycle Times

The ROM cycle time is programmable from 4 to 11 bus clock cycles. The data transfers are 32 bits wide. Refer to the Single Board Computers Programmer's Reference Guide.

SCSI T ransfers

The MVME177 includes a SCSI mass storage bus interface with DMA controller. The SCSI DMA controller uses a FIFO buffer to interface the 8-bit SCSI bus to the 32-bit local bus. The FIFO buffer allows the SCSI DMA controller to efficiently transfer data to the local bus in four longword bursts. This reduces local bus usage by the SCSI device.

MVME177 Functional Description

The first longword transfer of a burst, with snooping disabled, requires:

❏ Four bus clocks with parity off, and

❏ Five bus clocks with parity on

Each of the remaining three transfers requires one bus clock.

The transfer rate of the DMA controller is 44MB/sec at 25 MHz with parity off. Assuming a continuous transfer rate of 5MB/sec on the SCSI bus, 12% of the local bus bandwidth is used by transfers from the SCSI bus.

Note The actual SCSI bus transfer rate is fixed, no matter

what the speed of the microprocessor.

4-19

Functional Description

LAN DMA Transfers

The MVME177 includes a LAN interface with DMA controller. The LAN DMA controller uses a FIFO buffer to interface the serial LAN bus to the 32-bit local bus. The FIFO buffer allows the LAN DMA controller to efficiently transfer data to the local bus.

The 82596CA does not execute MC68060 compatible burst cycles, therefore the LAN DMA controller does not use burst transfers. DRAM write cycles require 3 clock cycles, and read cycles require:

❏ 5 clock cycles with parity off and

❏ 6 clock cycles with parity on

The transfer rate of the LAN DMA controller is 20MB/sec at 25 MHz (or 24MB/sec at 30 MHz) with parity off. Assuming a continuous transfer rate of 1MB/sec on the LAN bus, 5% (or 4%) of the local bus bandwidth is used by transfers from the LAN bus.

Remote Status and Control

The remote status and control connector, J3, is a 20-pin connector located behind the front panel of the MVME177. It provides system designers the flexibility to access critical indicator and reset functions. This allows a system designer to construct a RESET/ABORT/LED panel that can be located remotely from the MVME177.

In addition to the LED and the RESET and ABORT switches access, this connector also includes:

4-20

❏ Two general purpose TTL-level I/O pins

❏ One general purpose interrupt pin which can also function as

a trigger input. This interrupt pin is level programmable

AEIA-232-D Interconnections

Introduction

The EIA-232-D standard is the most widely used terminal/computer and terminal/modem interface, and yet it is not fully understood. This may be because not all the lines are clearly defined, and many users do not see the need to follow the standard in their applications. Often designers think only of their own equipment, but the state of the art is computer-to-computer or computer-to-modem operation. A system should easily connect to any other system.

The EIA-232-D standard was originally developed by the Bell System to connect terminals via modems. Several handshaking lines were included for that purpose. Although handshaking is unnecessary in many applications, the lines themselves remain part of many designs because they facilitate troubleshooting.

Table A-1 lists the standard EIA-232-D interconnections. To interpret this information correctly, remember that EIA-232-D was intended to connect a terminal to a modem. When computers are connected to each other without modems, one of them must be configured as a terminal (data terminal equipment: DTE) and the other as a modem (data circuit-terminating equipment: DCE). Since computers are normally configured to work with terminals, they are said to be configured as a modem in most cases.

Signal levels must lie between +3 and +15 volts for a high level, and between -3 and -15 volts for a low level. Connecting units in parallel may produce out-of-range voltages and is contrary to EIA-232-D specifications.

A-1

EIA-232-D Interconnections

Table A-1. EIA-232-D Interconnections

Number

01 Not used. 02 TxD TRANSMIT DATA. Data to be transmitted; input to the modem

03 RxD RECEIVE DATA. Data which is demodulated from the receive

04 RTS REQUEST TO SEND. Input to the modem from the terminal

05 CTS CLEAR TO SEND. Output from the modem to the terminal to

06 DSR DATA SET READY. Output from the modem to the terminal to

07 SIG-GND SIGNAL GROUND. Common return line for all signals at the

08 DCD DATA CARRIER DETECT. Output from the modem to the

09-14 Not used.

15 TxC TRANSMIT CLOCK (DCE). Output from the modem to the

16 Not used. 17 RxC RECEIVE CLOCK. Output from the modem to the terminal;

18, 19 Not used.

20 DTR DATA TERMINAL READY. Input to the modem from the

21 Not used.

Signal

Mnemonic Signal Name and Description

from the terminal.

line; output from the modem to the terminal.

when required to transmit a message. With RTS off, the modem carrier remains off. When RTS is turned on, the modem immediately turns on the carrier.

indicate that message transmission can begin. When a modem is used, CTS follows the off-to-on transition of RTS after a time delay.

indicate that the modem is ready to transmit data.

modem interface.

terminal to indicate that a valid carrier is being received.

terminal; clocks data from the terminal to the modem.

clocks data from the modem to the terminal.

terminal; indicates that the terminal is ready to send or receive data.

A-2

Levels of Implementation

Table A-1. EIA-232-D Interconnections (Continued)

Number

22 RI RING INDICATOR. Output from the modem to the terminal;

23 Not used. 24 TxC TRANSMIT CLOCK (DTE). Input to modem from terminal;

25 BSY BUSY. Input to modem from terminal. A positive EIA signal

Signal

Mnemonic Signal Name and Description

indicates to the terminal that an incoming call is present. The terminal causes the modem to answer the phone by carrying DTR true while RI is active.

same function as TxC on pin 15.

applied to this pin causes the modem to go off-hook and make the associated phone busy.

Notes:

1. A high EIA-232-D signal level is +3 to +15 volts. A low level is -3 to -15 volts. Connecting units in parallel may produce out-of-range voltages and is contrary to specifications.

2. The EIA-232-D interface is intended to connect a terminal to a modem. When computers are connected without modems, one must be configured as a modem and the other as a terminal.

Levels of Implementation

There are several levels of conformance that may be appropriate for typical EIA-232-D interconnections. The bare minimum requirement is the two data lines and a ground. The full implementation of EIA-232-D requires 12 lines; it accommodates:

❏ Automatic dialing

❏ Automatic answering

❏ Synchronous transmission

A middle-of-the-road approach is illustrated in Figure A-1.

A-3

EIA-232-D Interconnections

Signal Adaptations

One set of handshaking signals frequently implemented are RTS and CTS. CTS is used in many systems to inhibit transmission until the signal is high. In the modem application, RTS is turned around and returned as CTS after 150 microseconds. RTS is programmable in some systems to work with the older type 202 modem (half duplex). CTS is used in some systems to provide flow control to avoid buffer overflow. This is not possible if modems are used. It is usually necessary to make CTS high by connecting it to RTS or to some source of +12 volts such as the resistors shown in Figure A-1. CTS is also frequently jumpered to an MC1488 gate which has its inputs grounded (the gate is provided for this purpose).

Another signal used in many systems is DCD. The original purpose of this signal was to inform the system that the carrier tone from the distant modem was being received. This signal is frequently used by the software to display a message like the user to diagnose failure to communicate. Obviously, if the system is designed properly to use this signal and is not connected to a modem, the signal must be provided by a pullup resistor or gate as described above (see Figure A-1).

CARRIER NOT PRESENT to help

Many modems expect a DTR high signal and issue a DSR response. These signals are used by software to help prompt the operator about possible causes of trouble. The DTR signal is sometimes used to disconnect the phone circuit in preparation for another automatic call. These signals are necessary in order to communicate with all possible modems (see Figure A-1).

Sample Conﬁgurations

Figure A-1 is a good minimum configuration that almost always works. If the CTS and DCD signals are not received from the modem, the jumpers can be moved to artificially provide the needed signal.

A-4

6850

TXD

RXD

RTS

CTS

DCD

TXC RXC

TXD

RXD

RTS

CTS

DCD TXC

RXC

-12V

+12V

-12V

LS08

OPTIONAL

HARDWARE

TRANSPARENT

MODE

LS08

39kΩ

470Ω

39kΩ

-12V

+12V

39kΩ

-12V

+12V

470Ω 470Ω 470Ω

LOGIC

GND

+12V

470Ω

Levels of Implementation

RXD

TXD

CTS DSR

DCD

SIG GND

DTR

TXD

RXD

RTS

CTS

DCD

CONNECTOR TO TERMINAL

5 6

CHASSIS GND

7 1

CONNECTOR TO MODEM OR

HOST SYSTEM

MODULE

Figure A-1. Middle-of-the-Road EIA-232-D Conﬁguration

cb181 9210

A-5

EIA-232-D Interconnections

Figure A-2 shows a way of wiring an EIA-232-D connector to enable a computer to connect to a basic terminal with only three lines. This is feasible because most terminals have a DTR signal that is ON, and which can be used to pull up the CTS, DCD, and DSR signals.

Two of these connectors wired back-to-back can be used. In this implementation, however, diagnostic messages that might otherwise be generated do not occur because all the handshaking is bypassed. In addition, the TX and RX lines may have to be crossed since TX from a terminal is outgoing but the TX line on a modem is an incoming signal.

EIA-232-D CONNECTOR

GND 1

TxD 2

A-6

RxD 3 RTS 4 CTS 5 DSR 6

GND 7 DCD 8

DTR 20

. . . .

Figure A-2. Minimum EIA-232-D Connection

Proper Grounding

Another subject to consider is the use of ground pins. There are two pins labeled GND. Pin 7 is the SIGNAL GROUND and must be connected to the distant device to complete the circuit. Pin 1 is the CHASSIS GROUND, but it must be used with care. The chassis is connected to the power ground through the green wire in the power cord and must be connected to the chassis to be in compliance with the electrical code.

The problem is that when units are connected to different electrical outlets, there may be several volts of difference in ground potential. If pin 1 of each device is interconnected with the others via cable, several amperes of current could result. This condition may not only be dangerous for the small wires in a typical cable, but may also produce electrical noise that causes errors in data transmission. That is why Figure A-1 shows no connection for pin 1. Normally, pin 7 should only be connected to the CHASSIS GROUND at one point; if several terminals are used with one computer, the logical place for that point is at the computer. The terminals should not have a connection between the logic ground return and the chassis.

Levels of Implementation

A-7

EIA-232-D Interconnections

A-8

BDebugger General Information

Overview of M68000 Firmware

The firmware for the M68000-based (68K) series of board and system level products has a common genealogy, deriving from the debugger firmware currently used on all Motorola M68000-based CPU modules. The M68000 firmware family provides:

❏ A high degree of functionality

❏ User friendliness

❏ Portability

❏ Ease of maintenance

This member of the M68000 firmware family is implemented on the MVME177 Single Board Computer, and is known as the MVME177Bug, or simply 177Bug.

Description of 177Bug

The 177Bug package is a powerful evaluation and debugging tool for systems built around the MVME177 CISC-based microcomputers. Facilities are available for loading and executing user programs under complete operator control for system evaluation. 177Bug includes:

❏ Commands for display and modification of memory

❏ Breakpoint and tracing capabilities

❏ A powerful assembler/disassembler useful for patching

programs

❏ A self-test at power-up feature which verifies the integrity of

the system

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Debugger General Information

❏ Various 177Bug routines that handle I/O, data conversion,

and string functions available to user programs through the TRAP #15 system calls

177Bug consists of three parts:

❏ A command-driven user-interactive software debugger,

described in this appendix, and hereafter referred to as Òthe debuggerÓ or Ò177BugÓ

❏ A command-driven diagnostic package for the MVME177

hardware, hereafter referred to as Òthe diagnosticsÓ

❏ A user interface which accepts commands from the system

console terminal

When using 177Bug, you operate out of either the debugger directory or the diagnostic directory. If you are in the debugger directory, the debugger prompt Ò177-Bug>Ó displays and you have all of the debugger commands at your disposal. If you are in the diagnostic directory, the diagnostic prompt Ò177-Diag>Ó displays and you have all of the diagnostic commands at your disposal as well as all of the debugger commands. You may switch between directories by using the Switch Directories (SD) command, or may examine the commands in the particular directory that you are currently in by using the Help (HE) command.

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Because 177Bug is command-driven, it performs its various operations in response to user commands entered at the keyboard. When you enter a command, 177Bug executes the command and the prompt reappears. However, if you enter a command that causes execution of user target code (e.g., ÒGOÓ), then control may or may not return to 177Bug, depending on the outcome of the user program.

If you have used one or more of Motorola's other debugging packages, you will find the CISC 177Bug very similar. Considerable effort has also been made to make the interactive commands more consistent. For example, delimiters between commands and arguments may now be commas or spaces interchangeably.

Autoboot

177Bug Implementation

MVME177Bug is written largely in the ÒCÓ programming language, providing benefits of portability and maintainability. Where necessary, assembler has been used in the form of separately compiled modules containing only assembler code - no mixed language modules are used.

Physically, 177Bug is contained in two 44-pin PLCC/CLCC EPROMs, providing 512KB (128K longwords) of storage. Both EPROMs are necessary regardless of how much space is actually occupied by the firmware, because of the 32-bit longword-oriented MC68060 memory bus architecture. The executable code is checksummed at every power-on or reset firmware entry, and the result (which includes a pre-calculated checksum contained in the EPROMs) is tested for an expected zero. Thus, users are cautioned against modification of the EPROMs unless re-checksum precautions are taken. The power-on defaults for the MVME177 debug port are:

❏ Eight bits per character

❏ One stop bit per character

❏ Parity disabled (no parity)

Autoboot

❏ Baud rate 9600 baud (default baud rate of MVME177 ports at

power-up)

After power-up, the baud rate of the debug port can be reconfigured by using the Port Format (PF) command of the 177Bug debugger.

Autoboot is a software routine that is contained in the several 177Bug EPROMs to provide an independent mechanism for booting an operating system. This autoboot routine automatically scans for controllers and devices in a specified sequence until a valid bootable device containing a boot media is found, or the list is

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Debugger General Information

exhausted. If a valid bootable device is found, a boot from that device begins. The controller scanning sequence goes from the lowest controller Logical Unit Number (LUN) detected to the highest LUN detected.

At power-up, Autoboot is enabled, and providing the drive and controller numbers encountered are valid, the following message displays on the system console:

"Autoboot in progress... To abort hit <BREAK>"

Following this message there is a delay to allow you an opportunity to abort the Autoboot process if you wish. Then the actual I/O begins: the program pointed to within the volume ID of the media specified loads into RAM and control passes to it. If, however, during this time you want to gain control without Autoboot, you can press the:

❏ BREAK key

❏ Software ABORT switch

❏ RESET switch

Autoboot is controlled by parameters contained in the ENV command. These parameters allow:

Caution

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❏ Selection of specific boot devices

❏ Selection of files

❏ Programming of the Boot delay

Refer to the ENV command in the Commands Table for more details.

Although streaming tape can be used to autoboot, the same power supply must be connected to the:

❏ Streaming tape drive

❏ Controller

❏ MVME177

At power-up, the tape controller positions the streaming tape to load point where the volume ID can correctly be read and used.

If, however, the MVME177 loses power but the controller does not, and the tape happens to be at load point, the sequences of commands required (attach and rewind) cannot be given to the controller and autoboot will not be successful.

ROMboot

The ROMboot function is configured/enabled by the Environment (ENV) command (refer to Commands Table at the end of this Appendix) and executes:

ROMboot

❏ At power-up

❏ At reset (optionally)

❏ By the RB command, assuming there is valid code in the

EPROMs (or optionally elsewhere on the module or VMEbus) to support it.

If ROMboot code is installed, a user-written routine is given control (if the routine meets the format requirements). One use of ROMboot might be resetting SYSFAIL* on an unintelligent controller module. The NORB command disables the function.

For a user's ROMboot module to gain control through the ROMboot linkage, four requirements must be met:

❏ Power must have just been applied (but the ENV command

can change this to also respond to any reset)

❏ Your routine must be located within the MVME177 ROM

memory map (but the ENV command can change this to any other portion of the onboard memory, or even offboard VMEbus memory)

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Debugger General Information

❏ The ASCII string ÒBOOTÓ must be located within the

specified memory range

❏ Your routine must pass a checksum test, which ensures that

this routine was really intended to receive control at powerup

For complete details on how to use ROMboot, refer to the Debugging Package for Motorola 68K CISC CPUs User's Manual.

Network Boot

Network Auto Boot is a software routine contained in the 177Bug EPROMs that provides a mechanism for booting an operating system using a network (local Ethernet interface) as the boot device. The Network Auto Boot routine automatically scans for controllers and devices in a specified sequence until a valid bootable device containing a boot media is found or the list is exhausted. If a valid bootable device is found, a boot from that device begins. The controller scanning sequence goes from the lowest controller Logical Unit Number (LUN) detected to the highest LUN detected.

At power-up, Network Boot is enabled, and providing the drive and controller numbers encountered are valid, the following message displays on the system console:

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"Network Boot in progress... To abort hit <BREAK>"

Following this message there is a delay to allow you to abort the Auto Boot process if you wish. Then the actual I/O begins: the program pointed to within the volume ID of the media specified loads into RAM and control passes to it. If, however, during this time you want to gain control without Network Boot, you can pres the:

❏ BREAK key ❏ Software ABORT switch ❏ RESET switch

Restarting the System

Network Auto Boot is controlled by parameters contained in the NIOT and ENV commands. These parameters allow:

❏ Selection of specific boot devices

❏ Selection of systems

❏ Selection of files

❏ Programming of the Boot delay

Refer to the ENV and NIOT commands in the Commands Table in this Appendix for more details. Also refer to the ENV parameters in Appendix D.

Restarting the System

You can initialize the system to a known state in three different ways:

❏ Reset

❏ Abort

❏ Break

Each has characteristics which make it more appropriate than the others in certain situations.

The debugger has a special feature upon a reset condition. This feature is activated by depressing the RESET and ABORT switches at the same time. This feature instructs the debugger to use the default setup/operation parameters in ROM versus your setup/operation parameters in NVRAM. This feature can be used in the event your setup/operation parameters are corrupted or fail to pass a sanity check.

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Debugger General Information

Reset

Pressing and releasing the MVME177 front panel RESET switch initiates a system reset. COLD and WARM reset modes are available. By default, 177Bug is in COLD mode. During COLD reset, a total system initialization occurs, as if the MVME177 had just been powered up. In other words, during a COLD reset:

❏ All static variables (including disk device and controller

parameters) restore to their default states

❏ The breakpoint table and offset registers are cleared

❏ The target registers are invalidated

❏ Input and output character queues are cleared

❏ Onboard devices (timer, serial ports, etc.) are reset

❏ The first two serial ports are reconfigured to their default state

During WARM reset, the 177Bug preserves the following:

❏ Variables

❏ Tables

Abort

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❏ Target state registers

❏ Breakpoints

Reset must be used if the processor ever halts, or if the 177Bug environment is ever lost (vector table is destroyed, stack corrupted, etc.).

You can initiate an abort by pressing and releasing the ABORT switch on the MVME177 front panel. If an abort is initiated while executing a user program (running target code), a ÒsnapshotÓ of the processor state is captured and stored in the target registers. For this reason, abort is most appropriate when terminating a user

Restarting the System

Break

program that is being debugged. Abort should be used to regain control if the program gets caught in a loop, etc. The target PC and register contents assist you in locating the malfunction.

Pressing and releasing the ABORT switch generates a local board condition that causes:

❏ A processor interrupt (if enabled)

❏ The target registers (reflecting the machine state at the time

the ABORT switch was pressed) display on the screen

❏ All breakpoints installed in your code are removed

❏ Breakpoint table remains intact

❏ Control returns to the debugger

You can generate a ÒBreakÓ by pressing and releasing the BREAK key on the terminal keyboard. Break does not generate an interrupt. The only time break is recognized is when characters are sent or received by the console port. A Break causes:

❏ All breakpoints in your code to be removed

❏ Breakpoint table to be maintained intact

❏ A snapshot to be taken of the machine state if the function

was entered using SYSCALL

❏ The snapshot is accessible to you for diagnostic purposes

Often it is desirable to terminate a debugger command prior to its completion; for example, during the display of a large block of memory. Break allows you to terminate the command immediately.

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Debugger General Information

SYSFAIL* Assertion/Negation

Upon a reset/power-up condition the debugger asserts the VMEbus SYSFAIL* line (refer to the VMEbus specification). SYSFAIL* stays asserted if any of the following has occurred:

❏ Confidence test failure

❏ NVRAM checksum error

❏ NVRAM low battery condition

❏ Local memory configuration status

❏ Self test (if system mode) has completed with error

❏ MPU clock speed calculation failure

After debugger initialization is done and none of the above situations have occurred, the SYSFAIL* line is negated. This indicates to the user or VMEbus masters the state of the debugger. In a multi-computer configuration, other VMEbus masters could view the pertinent control and status registers to determine which CPU is asserting SYSFAIL*. SYSFAIL* assertion/negation is also affected by the ENV command.

MPU Clock Speed Calculation

The clock speed of the microprocessor is calculated and checked against a user definable parameter housed in NVRAM (refer to the CNFG command in the Commands Table). If the check fails, a warning message displays. The calculated clock speed is also checked against known clock speeds and tolerances.

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Memory Requirements

The program portion of 177Bug is approximately 512KB of code, consisting of:

❏ Download

❏ Debugger

❏ Diagnostic packages

and is contained entirely in EPROM. The EPROM sockets on the MVME177 are mapped starting at location $FF800000.

177Bug requires a minimum of 64KB of contiguous read/write memory to operate.

The ENV command controls where this block of memory is located. Regardless of where the onboard RAM is located, the first 64KB is used for 177Bug stack and static variable space and the rest is reserved as user space. Whenever the MVME177 is reset:

❏ Target PC is initialized to the address corresponding to the

beginning of the user space

❏ Target stack pointers are initialized to addresses within the

user space

❏ Target Interrupt Stack Pointer (ISP) set to the top of the user

space

At power-up or reset, all 8KB of memory at addresses $FFE0C000 through $FFE0DFFF is completely changed by the 177Bug initial stack.

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Debugger General Information

Terminal Input/Output Control

When entering a command at the prompt, the following control codes may be entered for limited command line editing.

Note The presence of the caret ( ^ ) before a character

indicates that the Control (CTRL) key must be held down while striking the character key

^X (cancel line) The cursor is backspaced to the beginning of the line. If

the terminal port is conÞgured with the hardcopy or TTY option (refer to PF command), then a carriage return and line feed is issued along with another prompt.

^H (backspace) The cursor is moved back one position. The character at

the new cursor position is erased. If the hardcopy option is selected, a Ò/Ó character is typed along with the deleted character.

^D (redisplay) The entire command line as entered so far is

redisplayed on the following line.

^A (repeat) Repeats the previous line. This happens only at the

command line. The last line entered is redisplayed but not executed. The cursor is positioned at the end of the line. You may enter the line as is or you can add more characters to it. You can edit the line by backspacing and typing over old characters.

<DEL> (delete or rubout) Performs the same function as ^H.

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When observing output from any 177Bug command, the XON and XOFF characters which are in effect for the terminal port may be entered to control the output, if the XON/XOFF protocol is enabled

Disk I/O Support

(default). These characters are initialized to ^S and ^Q respectively by 177Bug, but you may change them with the PF command. In the initialized (default) mode, operation is as follows:

^S (wait) Console output is halted. ^Q (resume) Console output is resumed.

Disk I/O Support

177Bug can initiate disk input/output by communicating with intelligent disk controller modules over the VMEbus. Disk support facilities built into 177Bug consist of:

❏ Command-level disk operations

❏ Disk I/O system calls (only via one of the TRAP #15

instructions) for use by user programs

❏ Defined data structures for disk parameters

Parameters such as:

❏ Address where the module is mapped

❏ Device type

❏ Number of devices attached to the controller module

are kept in tables by 177Bug. Default values for these parameters are assigned at power-up and cold-start reset, but may be altered as described in the section on default parameters, later in this chapter.

Blocks V ersus Sectors

The logical block defines the unit of information for disk devices. A disk is viewed by 177Bug as a storage area divided into logical blocks. By default, the logical block size is set to 256 bytes for every block device in the system. You can change the block size on a per device basis with the IOT command.

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Debugger General Information

The sector defines the unit of information for the media itself, as viewed by the controller. The sector size varies for different controllers, and the value for a specific device can be displayed and changed with the IOT command.

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Disk I/O Support

When a disk transfer is requested:

❏ Start and size of the transfer is specified in blocks

❏ 177Bug translates this into an equivalent sector specification

❏ Passes the sector specification on to the controller to initiate

the transfer

If the conversion from blocks to sectors yields a fractional sector count, an error is returned and no data is transferred.

Device Probe Function

A device probe with entry into the device descriptor table is performed whenever a specified device is accessed; i.e., when system calls:

❏ .DSKRD

❏ .DSKWR

❏ .DSKCFIG

❏ .DSKFMT

❏ .DSKCTRL

or debugger commands:

❏ BH

❏ BO

❏ IOC

❏ IOP

❏ IOT

❏ MAR

❏ MAW

are used.

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Debugger General Information

The device probe mechanism utilizes the SCSI commands ÒInquiryÓ and ÒMode SenseÓ. If the specified controller is non-SCSI, the probe simply returns a status of Òdevice present and unknownÓ. The device probe makes an entry into the device descriptor table with the pertinent data. After an entry has been made, the next time a probe is done it simply returns with Òdevice presentÓ status (pointer to the device descriptor).

Disk I/O via 177Bug Commands

The 177Bug commands listed in the following paragraphs are provided for disk I/O. Detailed instructions for their use are found in the Debugging Package for Motorola 68K CISC CPUs User's Manual. When a command is issued to a particular controller LUN and device LUN, these LUNs are remembered by 177Bug so that the next disk command defaults to use the same controller and device.

IOI (Input/Output Inquiry)

This command probes the system for all possible CLUN/DLUN combinations and displays inquiry data for devices which support it. The device descriptor table has space for a maximum of 16 device descriptors. Use the IOI command to view the table or clear it if necessary.

IOP (Physical I/O to Disk)

IOP allows you to:

❏ Read blocks of data

❏ Write blocks of data

❏ Format a specified device in a certain way

IOP creates a command packet from the arguments you have specified, then invokes the proper system call function to carry out the operation.

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Disk I/O Support

IOT (I/O Teach)

IOT allows you to change any configurable parameters and attributes of the device. In addition, it allows you to view the controllers available in the system.

IOC (I/O Control)

IOC allows you to send command packets as defined by the particular controller directly. IOC can also be used to examine the resultant device packet after using the IOP command.

BO (Bootstrap Operating System)

BO reads an operating system or control program from the specified device into memory, then transfers control to it.

BH (Bootstrap and Halt)

BH reads an operating system or control program from a specified device into memory, then returns control to 177Bug. It is used as a debugging tool.

Disk I/O via 177Bug System Calls

All operations that actually access the disk are done directly or indirectly by 177Bug TRAP #15 system calls. (The command-level disk operations provide a convenient way of using these system calls without writing and executing a program).

The following system calls allow user programs to perform disk I/O:

.DSKRD Disk read. Use this system call to read blocks from a disk into memory. .DSKWR Disk write. Use this system call to write blocks from memory onto a

disk.

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Debugger General Information

.DSKCFIG Disk conÞgure. Use this system call to change the conÞguration of the

speciÞed device.

.DSKFMT Disk format. Use this system call to send a format command to the

speciÞed device.

.DSKCTRL Disk control. Use this system call to implement any special device

control functions that cannot be accommodated easily with any of the other disk functions.

Refer to the Debugging Package for Motorola 68K CISC CPUs User's Manual for information on using these and other system calls.

To perform a disk operation, 177Bug must eventually present a particular disk controller module with a controller command packet which has been especially prepared for that type of controller module. (This is accomplished in the respective controller driver module.) A command packet for one type of controller module usually does not have the same format as a command packet for a different type of module. The system call facilities which perform disk I/O:

❏ Accept a generalized (controller-independent) packet format

as an argument

❏ Translate it into a controller-specific packet

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❏ Send it to the specified device

Refer to the system call descriptions in the Debugging Package for Motorola 68K CISC CPUs User's Manual for details on the format and

construction of these standardized ÒuserÓ packets.

The packets which a controller module expects to receive vary from controller to controller. The disk driver module for the particular hardware module (board) must take the standardized packet given to a trap function and create a new packet which is specifically tailored for the disk drive controller receiving it. Refer to documentation on the particular controller module for the format of its packets, and for using the IOC command.

Disk I/O Support

Default 177Bug Controller and Device Parameters

177Bug initializes the parameter tables for a default configuration of controllers and devices (refer to Appendix C). If the system needs to be configured differently than this default configuration (for example, to use a 70MB Winchester drive where the default is a 40MB Winchester drive), then these tables must be changed.

There are three ways to change parameter table contents:

❏ Using BO or BH. When you invoke one of these commands,

the configuration area of the disk is read and the parameters corresponding to that device are rewritten according to the parameter information contained in the configuration area. This is a temporary change. If a cold-start reset occurs, then the default parameter information is written back into the tables.

❏ Using the IOT. You can use this command to reconfigure the

parameter table manually for any controller and/or device that is different from the default. This is also a temporary change and is overwritten if a cold-start reset occurs.

❏ Obtain the source. You can then change the configuration

files and rebuild 177Bug using different defaults. Changes made to the defaults are permanent until changed again.

Disk I/O Error Codes

177Bug returns an error code if an attempted disk operation is unsuccessful.

Network I/O Support

The Network Boot Firmware provides the capability to boot the CPU through the ROM debugger using a network (local Ethernet interface) as the boot device.

The booting process executes in two distinct phases:

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Debugger General Information

❏ The first phase: the diskless remote node discovers its

network identify and the name of the file to be booted

❏ The second phase: the diskless remote node reads the boot

file across the network into its memory

The various modules (capabilities) and the dependencies of these modules that support the overall network boot function are described in the following paragraphs

Intel 82596 LAN Coprocessor Ethernet Driver

This driver manages/surrounds the Intel 82596 LAN Coprocessor. Management is in the scope of:

❏ Reception of packets

❏ Transmission of packets

❏ Receive buffer flushing

❏ Interface initialization

This module ensures that the packaging and unpackaging of Ethernet packets is performed correctly in the Boot PROM.

UDP/IP Protocol Modules

The Internet Protocol (IP) is designed for use in interconnected systems of packet-switched computer communication networks. The Internet protocol provides for transmitting of blocks of data called datagrams (hence User Datagram Protocol, or UDP) from sources to destinations, where sources and destinations are hosts identified by fixed length addresses.

The UDP/IP protocols are necessary for the TFTP and BOOTP protocols; TFTP and BOOTP require a UDP/IP connection.

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Motorola MVME177 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

MVME177

Single Board Computer

Installation and Use Manual

Notice

Restricted Rights Legend

Preface

All Rights Reserved

Printed in the United States of America

June 1996

Ground the Instrument.

Do Not Operate in an Explosive Atmosphere.

Keep Away From Live Circuits.

Do Not Service or Adjust Alone.

Use Caution When Exposing or Handling the CRT.

Do Not Substitute Parts or Modify Equipment.

Dangerous Procedure Warnings.

Introduction

General information

Model Designations

Table 1-1. MVME177 Model Designations

Model Number Speed Major Differences

Features

Feature Description

Cooling Requirements

Specifications

Characteristics SpeciÞcations

FCC Compliance

1. Shielded cables on all external I/O ports.

4. Front panel screws properly tightened.

General Description

Equipment Required

Related Documentation

Document Title

Support Information

Manual T erminology

Introduction

Unpacking Instructions

Overview of Start-up Procedure

What you will need to do ... Refer to ... On page ...

Hardware Preparation

Header

Description ConÞguration Jumpers Notes

Setup Instructions

1. Turn all equipment power OFF.

Bit J1 Pins Description

MVME177 Module Installation Instructions

10. Replace the chassis cover.

11. Connect power cable to AC power source.

System Considerations

3Operating Instructions

Introduction

Controls and Indicators

ABORT Switch S1

RESET Switch S2

Memory Maps

Local Bus Memory Map

Normal Address Range

Table 3-1. Local Bus Memory Map

Range Devices Accessed Port Size Size

D32 DRAMSIZE N 1, 2

D32/D16 3GB - 3, 4

D32/D16 64KB - 2, 4

Inhibit Notes

Address Range Devices Accessed Port Size Size Notes

Software Initialization

Local Reset Operation

4Functional Description

Introduction

MVME177 Functional Description

Data Bus Structure

Figure 4-1. MVME177 Block Diagram

MC68060 MPU

Flash Memory and EPROM

Flash Memory

Jumper or Control Bit Control Condition Memory ConÞguration

EPROM