Motorola MVME162P-244LE, MVME162P-244LSE, MVME162P-244 Series, MVME162P4 Series, MVME162P-344 Installation And Use Manual

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MVME162P4

VME Embedded Controller

Installation and Use

V162P4A/IH2

Edition of November 2000

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Printed in the United States of America.

Motorola

and the Motorola logo are registered trademarks of Motorola, Inc.

MC68040™ and MC68060™ are trademarks of Motorola, Inc. IndustryPack™ and IP™ are trademarks of GreenSpring Computers, Inc. All other products ment io ned i n this document are tradema rks or registered tradema rk s of

their respective holders.

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Safety Summary

The following general safety precautions must be observed during all phases of operation, service, and repair of this equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual could result in personal injury or damage to the equipment.

The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. Y ou, as the user of the product, shoul d foll ow these warni ngs and al l other sa fety pr ecauti ons nece ssary fo r the safe ope ration of the equipment in your operating environment.

Ground the Instrument.

To minimize shock hazard, the equipment chassis and enclosure must be connected to an electrical ground. If the equipment is su pplied wi th a three-c onductor A C power ca ble, the po wer cable m ust be plug ged into an a pproved three-contact electrical outlet, with the grounding wire (green/yellow) reliably connected to an electrical ground (safety ground) at the power outlet. The power jack and mating plug of the power cable meet International Electrotechnical Commission (IEC) safety standards and local electrical regulatory codes.

Do Not Operate in an Explosive Atmosphere.

Do not operate the equipment in any explosive atmosphere such as in the presence of flammable gases or fumes. Operation of any electrical equipment in such an environment could result in an explosion and cause injury or damage.

Keep Away From Live Circuits Inside the Equipment.

Operating personnel must not remove equipment covers. Only Factory Authorized Service Personnel or other qualified service personnel may remove equipment covers for internal subassembly or component replacement or any internal adjust ment. Service pe rsonnel should n ot replace compon ents with power c able connected. Under certain conditions, dangero us voltages may exist even with the power cable remo ved. T o avoid inju ries, such pers onnel should always disconnect power and discharge circuits before touching components.

Use Caution When Exposing or Handling a CRT.

Breakage of a Cathode-Ray Tube (CRT) causes a high-velocity scattering of glass fragments (implosion). To prevent CRT implosion, do not handl e the CRT and avoid rough handling o r jarring of t he equipment . Handling o f a CRT should be done only by qualified service personnel using approved safety mask and gloves.

Do Not Substitute Parts or Modify Equipment.

Do not install substitute parts or perform any unauthorized modification of the equipment. Contact your local Motorola representative for service and repair to ensure that all safety features are maintained.

Observe Warnings in Manual.

W arn ings , such as th e exa mple be low, prece de pote nt ially danger ous p rocedu res th rough out th is manu al. In str uction s contained in the warnings m ust be follow ed. You should also employ all ot her safety precautions w hich you dee m necessary for the operation of the equ ipment in your oper at ing environment.

To prevent serious injury or death from dangerous voltages, use extreme caution when handling, testing, and adjusting this equipment and its

Warning

components.

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Flammability

All Motorola PWBs (printed wiring boards) are manufactured with a flammability rating of 94V-0 by UL-recognized manufacturers.

EMI Caution

This equipment ge ner ates, uses a nd can radi ate el ectro magne tic energy . It

Caution

This product contains a lithium battery to power the clock and calendar circuitry.

Caution

may cause or be susceptible to electromagnetic interference (EMI) if not installed and used with adequate EMI protection.

Lithium Battery Caution

Danger of explosion if battery is re placed incorrect ly. Replace battery only with the same or equivalent type recommended by the equipment

manufacturer. Dispose of used batteries according to the manufacturer’s instructions.

Attention

Vorsicht

Il y a danger d’explosion s’il y a remplacement incorrect de la batterie. Remplacer uniquement avec une batterie du même type ou d’un type équivalent recommandé par le constructeur. Mettre au rebut les batteries usagées conformément aux instructions du fa bricant.

Explosionsgefahr bei unsachgemäßem Austausch der Batterie. Ersatz nur durch denselben ode r einen vom Herstel ler empfohle nen Typ. Entsorgu ng gebrauchter Batterien nach Angaben des Herstellers.

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CE Notice (European Community)

Motorola Compute r Group pro ducts wi th the CE mar king co mply with the EMC Dir ective (89/336/EEC). Compliance with this directive implies conformity to the following European Norms:

EN55022 “Limits and Methods of Meas urement of Radio Int erferen ce Chara cteri stic s of Information Technology Equipment”; this product tested to Equipment Class B

EN50082-1:1997 “Electromag netic Compatibi lit y—Gener ic Im munity St andard , Part

1. Residential, Commercial and Light Industry”

System products al so fulf ill EN60950 ( product saf ety) which i s essenti ally the r equirement for the Low Voltage Directive (73/23/EEC).

Board products are tested in a representative system to show compli ance with the above mentioned requirements. A proper installation in a CE-marked system will maintain the required EMC /safety performance.

In accordance with European Community directives, a “Declaration of Conformity” has been made and is on file within the European Union. The “Declaration of Conformity” is available on request. Please contact your sales representative.

Notice

While reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. a ssumes n o lia bility r esulti ng from any omissio ns in this docu ment, or from the use of the information obtained the rein. Motorola reserves the right to revise this document and to ma ke c hanges from time to time in the conten t hereof without obligation of Motorola to notify any person of such revision or changes.

Electronic versions of this material may be read online, downloaded for personal use, or referenced in another document as a URL to the Motorola Comput er Group website. The text itself may not b e published commerci ally in print o r electronic for m, edited, transla ted, or otherwise altered without the permiss ion of Motoro la, Inc.

It is possible th at t hi s publication may contain reference to or in for mation about Motorola products (machines and pr ograms), progra mming, or services that are not av ailable in your country. Such references or information must not be construed to mean that Motorola intends to announce such Motorola products, programming, or services in your country.

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Limited and Restricted Rights Legend

If the documentation contained herein is supplied, directly or indirectly, to the U.S. Government, the following notice shall apply unless otherwise agreed to in writing by Motorola, Inc.

Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (b)(3) of t he Rig hts i n Technical Data clause at DFARS 252.227-7013 (Nov.

1995) and of the Rights in Noncommerc ial Computer Software and Docume ntation c lause at DFARS 252.227-7014 (Jun. 1995).

Motorola, Inc. Computer Group 2900 South Diablo Way Tempe, Arizona 85282

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About This Manual

Summary of Changes.................................................................................................xvi

Overview of Contents................................................................................................xvi

Comments and Suggestions......................................................................................xvii

Conventions Used in This Manual...........................................................................xviii

CHAPTER 1 Hardware Preparation and Installation

Introduction ................................................................................................................1-1

Getting Started ...........................................................................................................1-1

Overview of Installation Procedure....................................................................1-1

Equipment Required...........................................................................................1-2

Guidelines for Unpacking...................................................................................1-2

ESD Precautions.................................................................................................1-3

Preparing the Board ............................................................ .......................................1-4

MVME162P4 Configuration..............................................................................1-5

VME System Controller (J1)..............................................................................1-7

IP Bus Clock (J14)..............................................................................................1-8

SIM Selection for Serial Port B (J15).................................................................1-9

Removal of Existing SIM..........................................................................1-10

Installation of New SIM............................................................................1-11

Serial Port 1/Console Clock (J16) ....................................................................1-12

Serial Port 2 Clock (J17)...................................................................................1-12

IP Bus Strobe (J19)...........................................................................................1-13

SRAM Backup Power Source (J22).................................................................1-13

EPROM Size (J23)............................................................................................1-14

Flash Write Protection (J24).............................................................................1-15

MC2 DRAM Size (S3) .....................................................................................1-15

General-Purpose Readable Switch (S4 Pin 5)..................................................1-17

IP DMA Snoop Control (S5 Pins 1/2)..............................................................1-18

IP Reset Mode (S5 Pin 3) .................................................................................1-19

Flash Write Enable Mode (S5 Pin 4)................................................................1-20

MCECC DRAM Size (S6)................................................................................1-21

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Installation Instructions ................................... ...... ..... ...... ...... .................................1-22

IP Installation on the MVME162P4.................................................................1-23

MVME162P4 Installation ................................................................................1-23

System Considerations.....................................................................................1-26

Serial Connections............................................................................................ 1-28

CHAPTER 2 Startup and Operation

Introduction ...............................................................................................................2-1

Front Panel Switches and Indicators..................................................................2-1

Initial Conditions.......................................................................................................2-2

Applying Power.........................................................................................................2 -3

Pre-Startup Checklist.................................................................................................2-4

Bringing up the Board ...............................................................................................2-5

Autoboot............................................................................................................. 2-9

ROMboot..........................................................................................................2-10

Network Boot...................................................................................................2-11

Restarting the System..............................................................................................2-12

Reset.................................................................................................................2-12

Abort.................................................................................................................2-13

Break ................................................................................................................ 2-14

Diagnostic Facilities ................................................................................................2-14

CHAPTER 3 162Bug Firmware

Introduction ...............................................................................................................3-1

162Bug Overview......................................................................................................3-1

162Bug Implementation............................ ...... ..........................................................3-3

Memory Requirements.............................................. ...... ...................................3-4

Using 162Bug............................................................................................................3-5

Debugger Commands................................................................................................3-6

Modifying the Environment......................................................................................3-9

CNFG - Configure Board Information Block ....................................................3-9

ENV - Set Environment ................................................................................... 3-11

Configuring the 162Bug Parameters......................................................... 3-11

Configuring the IndustryPacks..................................................................3-19

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CHAPTER 4 Functional Description

Introduction................................................................................................................4-1

Summary of Features.................................................................................................4-1

Processor and Memory ................................................ ..... ...... ............................4-2

I/O Implementation.............................................................................................4-3

ASICs..................................................................................................................4-4

Block Diagram...........................................................................................................4-4

Functional Description ...............................................................................................4-4

Data Bus Structure..............................................................................................4-6

Microprocessor ...................................................................................................4-6

MC68xx040 Cache......................................................................................4-6

No-VMEbus-Interface Option............................................................................4-7

Memory Options.............................................. ...... .............................................4-7

DRAM ..................................... ...... ...... ........................................................4-7

SRAM............................................ ...... ........................................................4-8

About the Battery.........................................................................................4-9

EPROM and Flash Memory......................................................................4-11

Battery-Backed-Up RAM and Clock................................................................4-11

VMEbus Interface and VMEchip2...................................................................4-12

I/O Interfaces ....................................................................................................4-12

Serial Communications Interface..............................................................4-12

IndustryPack (IP) Interfaces......................................................................4-15

Ethernet Interface ......................................................................................4-16

SCSI Interface............................................................................................4-17

SCSI Termination......................................................................................4-17

Local Resources................................................................................................4-17

Programmable Tick Timers.......................................................................4-17

Watchdog Timer........................................................................................4-18

Software-Programmable Hardware Interrupts...........................................4-18

Local Bus Timeout ....................................................................................4-18

Local Bus Arbiter..............................................................................................4-19

Connectors........................................................................................................4-19

Remote Status and Control........................................................................4-20

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CHAPTER 5 Pin Assignments

Connector Pin Assignments....................................................................................... 5-1

IndustryPack A, B, C, D Connectors.........................................................................5-1

Remote Reset Connector - J6.................................................................................... 5-3

Serial Port Module Connector - J15..........................................................................5-4

Serial Port 2 Connector - J18.....................................................................................5-5

Serial Port 1/Console Connector - J25 ......................................................................5-6

VMEbus Connectors - P1, P2.................................................................................... 5-6

APPENDIX A Specifications

Board Specifications.................................................................................................A-1

Cooling Requirements..............................................................................................A-2

Special Considerations for Elevated-T emperature Operation ...........................A-3

EMC Regulatory Compliance ..................................................................................A-4

APPENDIX B Troubleshooting

Solving Startup Problems......................................................................................... B-1

APPENDIX C Network Controller Data

Network Controller Modules Supported.................................................................. C-1

APPENDIX D Disk/Tape Controller Data

Controller Modules Supported................................................................................. D-1

Default Configurations......................... ....................................................................D-2

IOT Command Parameters....................................................................................... D-5

APPENDIX E Related Documentation

MCG Documents.......................................................................................................E-1

Manufacturers’ Documents.......................................................................................E-2

Related Specifications ...............................................................................................E-3

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List of Figures

Figure 1-1. MVME162P4 Board Layout...................................................................1-6

Figure 1-2. Serial Interface Module, Connector Side................................................1-9

Figure 1-3. EIA-232-D Connections to MVME712M (Sheet 1 of 6)......................1-29

Figure 1-4. EIA-530 Connections (Sheet 1 of 2).....................................................1-35

Figure 1-5. EIA-485/EIA-422 Connections.............................................................1-37

Figure 2-1. MVME162P4/Firmware System Startup................................................2-3

Figure 4-1. MVME162P4 Block Diagram.................................................................4-5

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List of T ables

T ab le 1-1. Startup Overview.............................. ..... ...... .............................................1-1

Table 1-2. MVME162P4 Configuration Settings ......................................................1-5

Table 1-2. Serial Interface Module Part Numbers ...................................................1-10

Table 1-3. MC2 DRAM Size Settings .....................................................................1-16

Table 1-4. Switch S5 Snoop Control Encoding .......................................................1-18

Table 1-5. MCECC DRAM Size Settings ................................................................1-22

Table 2-1. MVME162P4 Front Panel Controls .........................................................2-1

T ab le 2-2. Software-Readable Switches............................. ..... ...... ............................2-6

Table 3-1. Memory Offsets with 162Bug ..................................................................3-4

T ab le 3-2. Debugger Command s........................................ .......................................3-6

Table 3-3. ENV Command Parameters....................................................................3-11

T ab le 4-1. MVME162P4 Features............................................................ ...... ...... .....4-1

Table 4-2. Local Bus Arbitration Priority ................................................................4-19

T ab le 5-1. IndustryPack Interconnect Signals......... ...... ...... .......................................5-2

Table 5-2. Remote Reset Connector J6 Pin Assignments..........................................5-3

Table 5-3. Serial Port Module Connector Pin Assignments ......................................5-4

Table 5-4. Serial Connector J18 Pin Assignments.....................................................5-5

Table 5-5. Serial Connector J25 Pin Assignments.....................................................5-6

Table 5-6. VMEbus Connector P1 Pin Assignments.................................................5-7

Table 5-7. VMEbus Connector P2 Pin Assignment...................................................5-8

Table A-1. MVME162P4 Specifications .................................................................A-1

Table B-1. Troubleshooting MVME162P4 Boards .................................................B-1

Table E-1. Motorola Computer Group Documents .................................................E-1

Table E-2. Manufacturers’ Documents .................................................... ................ E-2

Table E-3. Related Specifications ............................................................................ E-3

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About This Manual

MVME162P4 VME Embedded Controller Installation and Use provides instructions for hardware preparation and installation; a board-level hardware overview ; and firmwa re-rel ated genera l inform ation and st artup instructions for the MVME162P-244 and -344 series of embedded

controllers, known collectively as the ‘‘MVME162P4’’ because they are equipped with the “Petra” chip and accommodate up to four IP modules.

The “Petra” chip that dist inguishes MVME162P4 embe dded control lers is an application-specific integrated circuit (ASIC) which combines the functions previously covered by the MC2 chip, the IP2 chip, and the MCECC chip in a single ASIC. As of the publica tion date, the informati on presented in this manual applies to the following MVME162P4 models:

Model Number Characteristics

MVME162P-244L 25MHz 68LC040, 16MB SDRAM, 2 SIO, 4 DMA IP MVME162P-244LE 25MHz 68LC040, 16MB SDRAM, 2 SIO, 4 DMA IP, Ethernet MVME162P-244LSE 25MHz 68LC040, 16MB SDRAM, 2 SIO, 4 DMA IP, SCSI/Ethernet MVME162P-344 32MHz 68040, 16MB SDRAM, 2 SIO, 4 DMA IP MVME162P-344S 32MHz 68040, 16MB SDRAM, 2 SIO, 4 DMA IP, SCSI MVME162P-344E 32MHz 68040, 16MB SDRAM, 2 SIO, 4 DMA IP, Ethernet MVME162P-344SE 32MHz 68040, 16MB SDRAM, 2 SIO, 4 DMA IP, SCSI/Ethernet

If the part number of your board includes a "PA" (for example: MVME162PA-244L), your board is equipped with a second-generation Petra ASIC. All other particulars of the board remain the same.

This manual is intended for anyone who designs OEM systems, adds capability to an existing compatible system, or works in a lab environment for experimental purposes. A basic knowledge of computers and digital logic is assumed. To use this manual, you may also wish to become familiar with the publications listed in the Related Documentation section in Appendix E.

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Summary of Changes

This is the second edition of MVME162P4 Installati on and Use. It supersedes the June 2000 edition and incorporates the following updates.

Date Description of Change

October 2000 In the description of the snoop control switch on page 1-18, entries in the table

concerning boards equipped with the MC68060 processor have been corrected.

October 2000 Several jumper drawings and configuration descriptions in Chapters 1 and 2

have been updated to reflect the current board layout and shipping configuration.

October 2000 Drawings pertaining to MVME712A/AM/-12/-13 seri es transition boards have

been deleted from the illustrations of serial connections at the end of Chapter 1, as those boards are out of production. References to them in the Serial Communications Interface section of Chapter 4 have been dropped as well.

October 2000 In the descriptions of the MC2 and MCECC DRAM size switches on pages

1-15 and 1-21, the importance of executing env;d after modifying switch

settings has been emphasized.

Overview of Contents

Chapter 1, Hardware Preparation and Installation, provides unpacking

instructions, hardware preparation guidelines, and installation instructions for the MVME162P4 VME Embedded Controller.

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Chapter 2, Startup and Operation, provides information on powering up

the MVME162P4 VME Embedded Controller after its installation in a system and describes the functionality of the switches, status indicators, and I/O ports.

Chapter 3, 162Bug Firmware, describes the basics of 162Bug and its

architecture, describes the monitor (interactive command portion of the firmware) in detail, and gives information on using the debugger and special commands.

Chapter 4, Functional Description, describes the MVME162P4 VME

Embedded Controller on a bl ock diagram level.

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Chapter 5, Pin Assignments , summarizes the pin assignments for the

various groups of interconnect signals on the MVME162P4.

Appendix A, Specifications, lists the general specifications for the

MVME162P4 Embedded Controller. Subsequent sections of the appendix detail cooling requirements and EMC regulatory compliance.

Appendix B, Troubleshooting, includes simple troubleshooting steps to

follow in the event t hat you hav e diffic ulty with your MVME162P4 VME Embedded Controller.

Appendix C, Network Controller Data, describes the VMEbus network

controller modules that are supported by the 162Bug firmware.

Appendix D, Disk/Tape Controll er Data, de scribes th e VMEbus disk/t ape

controller modules that are supported by the 162Bug firmware.

Appendix E, Related Documentation, provides all documentation related

to the MVME162P4.

Comments and Suggestions

Motorola welcomes and appreciates your comments on its doc umentation. We want to know what y ou think about our manuals and how we can make them better. Mail comments to:

Motorola Computer Group Reader Comments DW164 2900 S. Diablo Way Tempe, Arizona 85282

You can also submit comments to the following e-mail address:

reader-comments@mcg.mot.com

In all your corres pondence , plea se li st your name, po siti on, and c ompan y. Be sure to include the title and par t number of the manual and tell how you used it. Then tell us your feelings about its strengths and weaknesses and any recommendations for improvements.

xvii

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Conventions Used in This Manual

The following typographical conventions are used in this document:

bold

is used for user inpu t that you t ype just as i t appears ; it is al so used for commands, options and arguments to commands, and names of programs, directories and files.

italic

is used for names of variables to which you assign values. Italic is also used for comments in screen dis plays and examples, and to introduce new terms.

courier

is used for system output (for example, screen displays, reports), examples, and system prompts.

<CR> represents the carriage return or Enter key.

CTRL

xviii

represents the Control key. Execute control character s by pressin g the Ctrl key and the letter simultaneously, for example, Ctrl-d.

A character precedes a data or address parameter to specify the numeric format, as follows:

$ Specifies a hexadecimal character 0x Specifies a hexadecimal number % Specifies a binary number & Specifies a decimal number

An asterisk (∗) following a signal name for si gnals that are level sig nificant denotes that the signal is true or valid when the signal is low. An asterisk (∗) following a signal name for signals that are edge significant denotes that the actions initiated by that signal occur on high to low transition.

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1Hardware Preparation and

Introduction

This chapter provides unpacking instructions, hardware preparation guidelines, and installation instructions for the MVME162P4 VME Embedded Controller. Hardware preparation of the MVME712 series transition modules compatible with this board is described in separate manuals.

Getting Started

This section supplies an overview of startup procedures applicable to the MVME162P4. Equipment requirements, directions for unpacking, and ESD precautions that you should take complete the section.

Overview of Installation Procedure

The following table li sts the things you will need to do to use this board and tells where to find the info rmat io n you need to perform each step. Be sure to read this entire chapter, including all Cautions and Warnings, before you begin.

Installation

Table 1-1. Startup Overview

What you need to do... Refer to...

Unpack the hardware. Guidelines for Unpacking on page 1-2. Reconfigure jumpers or swit ches

on the MVME162P 4 board as necessary.

Ensure that IP modules are properly installed on the MVME162P4 boar d.

Install the MVM E162P4 board in a chassis.

Connect a display terminal. Serial Connections on page 1-28.

Preparing the Board on page 1-4.

IP Installation on page 1-23.

MVME162P4 Installation on page 1-23.

1-1

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Hardware Preparation and Installation

Table 1-1. Startup Overview (Continued)

What you need to do... Refer to...

Connect any other equipment you will be using.

Power up the system. Applying Power on page 2-3.

Note that the firmware initializes and tests the board.

Initialize the system clock. Using 162Bug, Debugger Commands on page 3-6. Examine and/or change

environmental parameters. Program the boar d as needed for

your applications.

Connector Pin Assignments in Chapter 5. For more information on optional de vi ces and equipment , ref er

to the documentation provided with the equipm ent.

Troubleshooting; Solving Startup Problems on page B-1. Bringing Up the Board on page 2-5.

You may also wish to obtain the 162Bug Firmware User’s Manual, listed in the Relate d Documentation appendix.

Using 162Bug, Modi fying the Environment on page 3-9.

Programmer’s Reference Guide, listed in the Related Documentation appendix.

Equipment Required

The following equipm ent is necessary to complete an MVME162P4 system:

❏ VME system enclosure ❏ System console terminal ❏ Operating system (and / or application software) ❏ Disk drives (and / or other I/O) and controllers

Guidelines for Unpacking

Note If the shipping carton is damaged upon receipt, request that the

carrier’s agent be present during the unpa cking and inspe ction of the equipment.

Unpack the equipment from the shipping carton. Refer to the packing list and verify that al l items are present. Save the packi ng mat erial for storing and reshipping of equipment.

1-2 Computer Group Literature Center Web Site

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Getting Started

Caution

Avoid touching areas of integrated circuitry; static discharge can damage circuits.

ESD Precautions

This section applies to all hardware installations you may perform that involve the MVME162P4 board.

Motorola strongly recommends the use of an antistatic wrist strap and a conductive foam pad when you install or upgrade the board. Electronic components can be extremely sensi tive to ESD. After removi ng the board from the chassis or from its protective wrapper, place the board flat on a grounded, static-free surface, component side up. Do not slide the board over any surface.

If no ESD station is available, you can av oid dama ge re sul ti ng fr om ESD by wearing an antistatic wrist strap (available at electronics st ores). Place the strap around your wrist and attach the grounding end (usually a piece of copper foil or an alligator clip) to an electrical ground. An electrical ground can be a piece of metal that literally runs into the ground (such as an unpainted met al pipe) or a metal part of a grounded electric al appliance. An appliance is grou nded if it has a thr ee-pro ng plug and i s plugged i nto a three-prong grounde d outlet . You can not use th e chassi s in which you are installing the MVME162P4 itself as a ground, because the enclosure is unplugged while you work on it.

http://www.motorola.com/computer/literature 1-3

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Hardware Preparation and Installation

Turn the system’s powe r off be fore you perform t hese proc edures. Fail ure

Warning

to turn the power off before opening the enclosure can result in personal injury or damage to the equipment. Hazardous voltage, current, and ene rgy levels are present in the chassis. Hazardous voltages may be present on power switch terminals even when the powe r switc h is off. Neve r opera te the system with the cover removed. Always replace the cover before powering up the system.

Preparing the Board

To produce the desired configuration and ensure proper operation of the MVME162P4, you may need to reconfigure hardware to some extent before installing the module.

Most options on the MVME162P4 are under software control: By setting bits in control registers after installing the module in a system, you can modify its configurat ion. (The MVME162P4 registers are described in Chapter 3 under ENV – Set Environment, and/ or in the MVME1X2P4 VME Embedded Controller Progr ammer's Reference Guide as listed in “Relate d Documentation” in Appendix E.)

Some options, though, are not software-programmable. Such options are either set by configuration switches or are controlled through physical installation or removal of head er jumpers o r interface modules on th e base board.

1-4 Computer Group Literature Center Web Site

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MVME162P4 Configuration

Figure 1-1 illustrates the placement of the jumper headers, connectors,

configuration switches, and various other components on the MVME162P4. Manually configurable jumper headers and configuration switches on the MVME162P4 are listed in the following table.

Table 1-2. MVME162P4 Configuration Settings

Function Factory Default

VME System Controller (J1) on page 1-7

Preparing the Board

2-3

IP Bus Clock (J14) on page 1-8 SIM Selection for Serial Port B (J15) on page 1-9 Serial Port 1/Console Clock (J16) on page 1-12 Serial Port 2 Clock (J17) on page 1-12 IP Bus Strobe (J19) on page 1-13 SRAM Backup Power Source (J22) on page 1-13

SIMM06 No Jumpers No Jumpers

No Jumper

1-3, 2-4

EPROM Size (J23) on page 1-14 Flash Write Protection (J24) on page 1-15 MC2 DRAM Size (S3) on page 1-15

Jumper On

Off-Off-Off

General-Purpose Readable Switch (S4 Pin 5) on page 1-17 IP DMA Snoop Control (S5 Pins 1/2) on page 1-18

On-On

IP Reset Mode (S5 Pin 3) on page 1-19 Flash Write Enable Mode (S5 Pin 4) on page 1-20 MCECC DRAM Size (S6) on page 1-21

On-Off-On

J3 is a PLD programming header for lab or factory use. It has no user function.

1-2

2-3

On On

http://www.motorola.com/computer/literature 1-5

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Hardware Preparation and Installation

FAIL

SCONRUN

STAT

FUSELAN

VMESCSI

DS2

DS1 DS3 DS5 DS7

DS4 DS6 DS8

J10

J20

J29

1313

3 4

121

ABORT

RESET

SERIAL PORT 2 SERIAL PORT 1 / CONSOLE

J18 J25

2646 0005

910

J14J1

1 2

J16J17

J15

J27

J26

J24

J11

A32

B32

C32

J19

J21

J23

BT1

J22

J30

XU1

A32

B32

C32

Figure 1-1. MVME162P4 Board Layout

1-6 Computer Group Literature Center Web Site

Page 25

VME System Controller (J1)

The MVME162P4 board is factory-configured in "automatic" system controller mode with a jumper across J1 pins 2 -3. In this confi guration, the MVME162P4 determines whe ther it is the system cont roller by its positi on on the bus. If the bo ard is located i n the first sl ot from the lef t, it configure s itself as the system controller. When the board is operating as system controller, the

If you want the MVME162P4 to fu nction as syste m controlle r in all cases, move the jumper to pins 1-2. If the MVME162P4 is not to be system controller under any circumstances, remove the jumper from J1.

Note On MVME16 2P4 boards without the opt ional VMEbus interface

SCON LED is turned on.

(i.e., with no VMEchip2 ASIC), the jumper may be installed or removed with no effect on n ormal operation.

Preparing the Board

123

System Controller

123

Auto System Controller

(factory configuration)

123

Not System Controller

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Hardware Preparation and Installation

IP Bus Clock (J14)

Header J14 selects the speed of the IP bus clock. The IP bus clock speed may be 8MHz or it may be set synchronous to the processor bus clock (25MHz or 32MHz for the MC68040 and MC68LC040). The default factory configuration has a jumper installed on pins 1-2, denoting an 8MHz clock.

If the jumper is installed on J14 pins 2-3, the IP bus clock speed matches that of the processor bus clock (25/32MHz), allowing the IP module to pace the MPU. Whether the setting is 8MHz or the processor bus clock speed, all IP ports operate at the same speed.

The setting of the IP32 bit in t he Control/St atus regist ers (Petra IP2 sector ,

Caution

register at offs et $1 D, bit 0) must co rresp ond to tha t of th e jumper. Th e bit is cleared (0) for 8MHz, or set (1) t o match the proce ssor bus clock spe ed. If the jumper and the CSR bi t a re not configured the same, the board may not run properly.

J14

123

Bus Clock = 8MHz

(Factory configuration)

1-8 Computer Group Literature Center Web Site

Bus Clock = Proc. Bus Clock

J14

123

(from MPU Bus Clock)

Page 27

SIM Selection for Serial Port B (J15)

Port B of the MVME162P4 Z85230 serial communications controller is configurable via a serial interface module (SIM) that is installed at connector J15 on the board. Five serial interface modules are available:

❏ EIA-232-D (DCE and DTE) ❏ EIA-530 (DCE and DTE) ❏ EIA-485/EIA-422 (DCE or DTE)

You can change Port B from an EIA-232-D to an EIA-530 interface or to an EIA-485/EIA-42 2 interface (or vice -versa) by mounting the appropriate serial interface module. Port B i s rout ed (vi a the SIM at J 15) to the 25- pin DB25 front panel connector marked

For the location of SI M connector J15 on the MVME162 P4, refer to Figur e

1-1. Figure 1-2 illustrates the sec ondary s ide (b ott om) of a seria l in ter face

module, showing the J1 connecto r which plugs int o SIM connector J15 on the MVME162P4. Figure 1-3 (sheets 3-6), Figure 1-4, and Figure 1-5 illustrate the seven configurations available for Port B.

Preparing the Board

SERIAL PORT 2.

39 1 40 2

SECONDARY SIDE

1568 9502

Figure 1-2. Serial Interface Module, Connector Side

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Hardware Preparation and Installation

For the part numbers of the serial interf ace modules, refer to Table 1-2. The part numbers are ord ina ri ly printed on the primary side (top) of the SIMs, but may be found on the secondary side in some versions.

If you need to replace an existing serial interface module with a SIM of another type, go to Removal of Existing SIM below. If there is no SIM on the main board, skip to Installation of New SIM.

Table 1-2. Serial Interface Module Part Numbers

EIA Standard Configuration Part Number

EIA-232-D DTE 01-W3846B SIMM05

EIA-530 DTE 01-W3868B SIMM07

EIA-485 -or EIA-422 DTE or DCE

Removal of Existing SIM

1. Each serial interface module is retained by two 4-40 x Phillips-head screws in opposite corners. (Exception: SIMM09 is retained by one Phillips-head screw in the center of the module.) Remove the screw(s) and store them in a safe place for later use.

2. Grasp opposite sides of the SIM and gently lift straight up.

Avoid lifting the SIM by one side only, as the connector can be damaged

Caution

on the SIM or the main board.

3. Place the SIM in a static-safe cont ainer for possible reuse.

Model

Number

DCE 01-W3865B SIMM06

DCE 01-W3867B SIMM08

01-W3002F SIMM09

/16-in.

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Page 29

Installation of New SIM

1. Observe the orientati on of the connect or keys on SIM connec tor J1 and MVME162P4 connector J15. Turn th e SIM so that the keys line up and place it gently on connector J15, aligning the mounting hole(s) at the SIM c orners (or center) wi th the mat ching stand off(s) on the MVME162P4.

2. Gently press the top of the SIM to seat it on the connector. If the SIM does not seat with gentle pressure, recheck the orientation. If the SIM connector is oriente d incorrectly, the mounti ng hole(s) will not line up with the st andoff(s).

Do not attemp t to force the SIM into place if it is oriented incorrectly .

Caution

3. Place the one or two 4-40 x

previously removed (or that were supplied with the new SIM) into the one center or two opposite-corner mounting hole(s). Turn the screw(s) into the standoff(s) but do not overtighten.

The signal relationships and signal connections in the various serial configurations available for ports A and B are illustrated in Figures 1-3 through 1-6.

Preparing the Board

/16” Phillips-head screw(s) that you

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Hardware Preparation and Installation

Serial Port 1/Console Clock (J16)

The MVME162P4 is shipped from the factory with the SERIAL PORT

1/CONSOLE header configured for asynchronous communications (i.e.,

jumpers removed). To selec t synchronous c ommunications f or

PORT 1/CONSOLE connection, install jumpers acr oss pins 1- 2 and pins 3-4.

J16 J16

3434

1212

External ClockInternal Clock

(Factory configuration)

the SERIAL

Serial Port 2 Clock (J17)

The MVME162P4 is shipped from the factory with the SERIAL PORT 2 header configured for asynchronous communications (i.e., jumpers removed). To select sync hronous communica tions for t he connection, install jumpers across pins 1-2 and pins 3-4.

SERIAL PORT 2

J17 J17

3434

1212

(Factory configuration)

External ClockInternal Clock

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Page 31

IP Bus Strobe (J19)

Some IP bus implementations make use of the Strobe∗ signal (pin AA19 on the Petra ASIC) a s an input to the IP mod ules from t he Petra IP 2 sector. Other IP interfaces require that the strobe be disconnected.

With a jumper installed between J19 pin s 1-2, a programmable fr equency source is connecte d to the Strobe ∗ signal on the IP bus (for details, refer to the Petra/IP2 chip programming model in the Programmer’s Reference Guide).

If the jumper is removed from J19, the strobe line is available for a sideband type of mes saging between I P modules. The Strobe∗ signal is not connected to any active d evices on th e board, but i t may be connect ed to a pull-up resistor.

Preparing the Board

J19

IP Strobe disconnected

(Factory configuration)

SRAM Backup Power Source (J22)

Header J22 determines the source for onboard static RAM backup power on the MVME162P4. In the factory c onfigur atio n, VMEbus +5 V standby voltage serves as primary and secondary power source (the onboard battery is disconnected).

The backup power configurations available for onboard SRAM through header J22 are illustrate d in the following diagram.

Note For MVME1 62P4s without the optional VMEbus interface ( i.e .,

without the VMEchip2 ASIC), you must select the onboard battery as the backup power source.

J19

IP Strobe connected

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Hardware Preparation and Installation

Removing all jumpers may temporarily disable the SRAM. Do not remove

all jumpers from J22, except for storage.

Caution

J22

Primary Source Onboard Battery

Secondary Source Onboard Battery

Primary Source VMEbus +5V STBY Secondary Source Onboard Bat ter y

J22

Backup Power Disabled

(For storage only)

Primary Source Onboard Battery

Secondary Source VMEbus +5V STBY

Primary Source VMEbus +5V STBY

Secondary Source VMEbus +5V STBY

J22

(Factory configuration)

EPROM Size (J23)

Header J23 selects the EPROM size. The MVME162P4 is factoryconfigured for a 4Mbit EPROM.

J23

3 2

8Mbit EPROM

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J23

3 2

4Mbit EPROM

(Factory configuration)

Page 33

Flash Write Protection (J24)

When the Flash write-enable jumper is installed (factory configuration), Flash memory can be writte n to via the normal software routines. When the jumper is removed, Flash memory is not writable.

Preparing the Board

J24

Flash Write-Protected

MC2 DRAM Size (S3)

MVME1X2P4 boards use SDRAM (Synchronous DRAM) in place of

DRAM. The MVME162P4’s 16/32MB shared SDRAM is configurabl e to emulate either of the following memory models:

❏ 1MB, 4MB, 8MB, or 16MB shared parity-protected DRAM ❏ 4MB, 8MB, 16MB, or 32MB ECC-protected DRAM

The two memory controllers modeled in the Petra ASIC duplicate the functionality of the “parity memory controller” found in MC2 ASICs as well as that of the “single-bit error correcting/double-bit error detecting” memory controller found in MCECC ASICs. Board firmware will initialize the memory controller as appr opriate.

J24

Flash Write-Enabled

(Factory configuration)

If the Petra ASIC is supporting MVME1X2P4 functionality, firmware will enable the parity (MC2) memory controller model. If the P etra ASIC is supporting MVME1X2P2 functionality, firmware will enable either the parity or the MCECC memory controller model, depending on the board configuration. Board configuration is a function of switch settings and resistor population options.

S3 comes into play in the MC2 memory controller model. S3 is a foursegment slide switc h whose lower th ree seg ment s estab lish t he si ze of t he parity DRAM (segment 4 is not used.) Refer to the illustration and ta ble below for specifics.

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Hardware Preparation and Installation

ON OFF

MC2 DRAM SIZE

16MB

(factory configuration)

2734 0004

Table 1-3. MC2 DRAM Size Settings

Segment 1

ON ON ON 1MB OFF ON ON 4MB OFF ON OFF 8MB OFF OFF ON Disabled OFF OFF OFF 16MB

Segment 2

Segment 3

MC2 DRAM

Size

Notes As shown in the preceding table, the Petra/MC2 interface

supports parity DRAM emulations up to 16MB. For sizes beyond 16MB, it is necesary to use the MCECC memory model.

For access to the MCECC registers, you must first disable the MC2 interface by setting S3 to 001 (Off/Off/On). Further details on selecting the MCECC emul ation c an be foun d under MCECC

DRAM Size (S6).

If you modify the swit ch setting s, you will ne ed to execute env;d <CR> so that the f irmware recogniz es the new memory default s.

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Page 35

General-Purpose Readable Switch (S4 Pin 5)

Switch S4 is similar in func tion to the general-purpose readable jumper headers found on earlier MVME162/172 ser ie s boards. S4 provides eight software-readable switch segments. These switches can be read as bits in a register (at address $FFF4202C) in the MC2 General-Purpose Inputs register in the Petra ASIC (refer to the Programmer’s Reference Guide for details). Bit GPI7 is associated with switch segment 1; bit GPI0 is associated with switch segme nt 8. Th e bit values are read as a 0 when the switch is on, and as a 1 when the switch is off. The MVME162P4 is shipped from the factory with S4 set to all 0s (all switches set to diagrammed below.

If the MVME162Bug firmware is installed, four bits are user-definable (i.e., switch segments 1-4). If the MVME162Bug fir mware is not instal led, seven bits are user-definable (i.e., segments 1-4 and segments 6-8).

Note Swi tch segment 5 (GPI3) is reserved to sele ct either the Fl ash

ON) or the EPROM memory map

USER-DEFINABLE

OFF ON

GPI7

memory map (switch set to (switch set to

OFF). GPI3 is not user-definable.

162 BUG Installed (default) User Code Installed

USER-DEFINABLE

Preparing the Board

ON), as

GPI6

GPI5

GPI4

GPI3

GPI2

GPI1

GPI0

Flash Selected

(factory configuration)

USER-DEFINABLE

ON=FLASH; OFF=EPROM

REFER TO DEBUG MANUAL

USER-DEFINABLE

ON=FLASH; OFF=EPROM

REFER TO DEBUG MANUAL

2735 0004

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Hardware Preparation and Installation

IP DMA Snoop Control (S5 Pins 1/2)

Segments 1 and 2 of switch S5 define the state of the snoop control bus when an IP DMA controller is local bus master . As shown in Table 1-4, S5 segment 1 controls Snoop Contr ol signal 1 on the MC68 0x0 processor. S5 segment 2 controls Snoop Control signal 0. Setting a segment to produces a logical 0; setting it to

ON OFF

OFF produces a logical 1.

Snoop inhibited (factory configuration)

2736 0004 (1-3)

S5 varies in function according to the type of processor installed. For MVME162P4 boards with an MC68040 pro cessor, settin g segments 1 and 2 of switch S5 to

OFF or leaving both segments set to ON (the factory

configuration) inhibits snooping. Enabling snooping requires one of two possible

ON/OFF combinations, according to the operation desired.

MVME172P4 boards with an MC68060 processor have different snoop functionality.

The following table lists the snoop operations represented by the settings of S5 with both types of processor. For further details, refer to the

MC68040 or MC68060 microprocessor user’s manuals listed in the Related Documentation appendix.

Table 1-4. Switch S5 Snoop Control Encoding

S5-1

(SC1)

On On Snoop disabled Snoop enabled

On Off Source dirty, sink byte/word/longword Snoop disabled Off On Source dirty , invalidate line Snoop enabled Off Off Snoop disabled (Reserved) Snoop disabled

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S5-2

(SC0)

Requested Snoop Operation MC68040 MC68060

Page 37

IP Reset Mode (S5 Pin 3)

Segment 3 of switch S5 defi nes the IP controller model (IP1 or IP2) to be emulated when the board comes up. With S5 segment 3 set to factory configuration), the board initializes in IP2 mode. With S5 segment 3 set to

In IP2 mode, IP resets occur only in response to a direct software write or to a power-up reset; the IP reset cont rol bit is not self-clearing.

In IP1 mode, the IP reset control bit clears itself after after a 1msec interval. IP resets may occur in response to a software write, a power-up reset, or a local b us reset. For details, r efer to the Programmer’s Reference

Guide listed in “Related Documentation” in Appendix E.

OFF, the board initializes in IP1 mode.

Preparing the Board

ON (the

ON OFF

IP2 reset mode (factory configuration )

2736 0004 (2-3)

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Hardware Preparation and Installation

Flash Write Enable Mode (S5 Pin 4)

Segment 4 of switch S5 define s the Flash memor y controlle r model (MC1 or MC2) to be emulated when enabling or disabling Flash memory accesses on the MVME162P4 board. With S5 segment 4 set to factory configuration), the board initializes in MC2 mode. With S5 segment 4 set to

OFF, the board initializes in MC1 mode.

ON OFF

MC2 Flash write enable mode (factory configuration )

In MC2 mode, writes to Flash memory are enabled or inhibited by a control bit at memory location $FFF42042. With the control bit set to Flash memory is write-enabled.

ON (the

2736 0004 (3-3)

In MC1 mode, writes to Flash memo ry are enabled by a me mory access to any location in the range $FFFCC000-$FFFCFFF. Writes to Flash memory are disabled by a memory access to any location in the range $FFFC8000-$FFFCBFFF. For details, refer to the Programmer’s

Reference Guide listed in “Related Documentation” in Appendix E.

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Page 39

MCECC DRAM Size (S6)

MVME1X2P4 boards use SDRAM (Synchronous DRAM) in place of

DRAM. The MVME162P4’s 16/32MB shared SDRAM is configurabl e to emulate either of the following memory models:

❏ 1MB, 4MB, 8MB, or 16MB shared parity-protected DRAM ❏ 4MB, 8MB, 16MB, or 32MB ECC-protected DRAM

Preparing the Board

S6 comes into pla y in th e MCECC me mory contr oller model . S6 is a f oursegment slide switc h whose lower th ree seg ment s estab lish t he si ze of t he ECC DRAM (segment 4 is not used.) Refer to the illustration and table below for specifics.

ON OFF

16MB MCECC DRAM (factory configuration )

2737 0004

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Hardware Preparation and Installation

Table 1-5. MCECC DRAM Size Settings

Segment 1

ON ON ON 4MB ON ON OFF 8MB ON OFF ON 16MB ON OFF OFF 32MB OFF ON ON 64MB

Segment 2

Note For the MCECC memory model to be enabled, the MC2

emulation must be disabled. You disable the MC2 memory model by setting the MC2 DRAM size select switch (S3) to 110 (Off/Off/On). Refe r to MC2 DRAM Size (S3 ) for further details.

The factory default setting for S6 is 16MB (On/Off/On). If you modify the switch settings, you will need to execute env;d <CR> so that the firmware recognizes the new memory defaults.

Installation Instructions

Segment 3

MCECC

DRAM Size

This section covers:

❏ Installation of IndustryPacks (IPs) on the MVME162P4 ❏ Installation of the MVME162P4 in a VME chassis ❏ System considerations relevant to the installation. Ensure that an

EPROM device is installed as needed. Before installing IndustryPacks, ensure that the serial ports and all header jumpers and configuration switches are set as appropriate.

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IP Installation on the MVME162P4

The MVME162P4 accommodates up to four IndustryPack (IP) modules. Install the IP modules on the MVME162P4 as follows:

1. Each IP module has two 50-pin connectors that plug into two corresponding 50-pin connectors on the MVME162P4: J4/J5, J10/J11, J20/J21, J29/J30. See Figure 2-1 for the MVME162P4 connector locations.

– Orient the IP module(s) so that the tapered connector shells mate

properly. Plug IP_a into co nnectors J4 and J5; plug IP _b into J10 and J11. Plug IP_c into J20 and J21; pl ug IP_d into J29 and J30. If a double-sized IP is us ed, plug I P_ab in to J4, J5, J10, a nd J11; plug IP_cd into J20, J21, J29, and J30.

2. Four additional 50-pin connectors (J7, J8, J26, and J27) are provided behind the MVME162P4 front panel for external cabling connections to the IP modules. There is a one-to-one correspondence between the signals on the cabling connectors and the signals on the associated IP connectors (i.e., J8 has the same IP_a signals as J4; J7 ha s the same IP_b signals as J10; J27 has the same IP_c signals as J20; and J2 6 has the same I P_d signal s as J29).

Installation Instructions

– Connect user-supplied 50-pin cables to J7, J8, J26, and J27 as

needed. (Because of th e vary ing re qui rements fo r eac h diff erent kind of IP, Motorola does not supply these cables.)

– Bring the IP cables out the narrow slots in the MVME162P4

front panel and attach them to the appropriate extern al equipment, depending on the nature of the particular IP(s).

MVME162P4 Installation

With EPROM, SIM, and IP modules installed and headers or switches properly configured, proceed as follows to install the MVME162P4 in a VME chassi s:

1. Turn all equipment power OFF and disconnect the power cable from the AC power source.

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Hardware Preparation and Installation

Caution

Warning

Inserting or removing modules while power is applied could result in

damage to module components.

Dangerous voltages, capable of causing death, are present in this equipment. Use extreme caution when handling, testing, and adjusting.

2. Remove the chassis cover as instructed in the user’s manual for the equipment.

3. Remove the filler panel from the card slot where you are going to install the MVME162P4.

– If you intend to use the MVME162P4 as system controller, it

must occupy the leftmost card slot (slot 1). The system controller must be in slot 1 to correctly initiate the bus-grant daisy-chain and to ensure proper operation of the IACK daisy-chain driver.

– If you do not intend to use the MVME162P4 as system

controller, it can occupy any unused double-height card slot.

4. Slide the MVME162P4 into the selected card slot. Be sure the module is seated properly in the P1 and P2 connectors on the backplane. Do not damage or bend connector pins.

5. Secure the MVME162P4 in the chassis with the screws provided, making good contact wi th the transverse mou nting rails to minimize RF emissions.

6. Install the MVME712 series transition module in the front or the rear of the VME chassis. (To install an MVME712M, which has a double-wide front pan el, you may need to shif t other modules in the chassis.)

7. On the chassis backplane, remove the (IACK) and slot occupied by the MVME162P4.

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BUS GRANT (BG) jumpers from the header for t he card

INTERRUPT ACKNOWLEDGE

Page 43

Installation Instructions

Note Some VME backplanes (e.g., those used in Motorola "Modular

Chassis" systems) have an autojumpering feature for automatic propagation of the IACK and BG signals. Step 7 does not apply to such backplane designs.

8. Connect the P2 Adapter Boar d or LCP2 Adapter Board and cable(s) to MVME162P4 backplane connector P2. This provides a connection point for terminals or other peripherals at the EIA-232D serial ports, SCSI por ts, and LAN Ethern et por t. For i nform ation on installing the P2 or LCP2 Adapter Board and the MVME712

series transition module(s), refer to the corresponding user’s manuals (the Programmer’s Reference Guide provides some connection diagrams).

Note I f you intend to us e the MVME162P4 with Por t B in an EIA-

530 configuration or an EIA-4 85/EIA- 422 conf igura tion, d o not install the P2 or LCP2 Adapt er Board and the MVME712 series transition module. They are incompatible with the EIA-530 interface and the EIA-485/EIA-422 interface.

9. Connect the appropriate cable(s) to the panel connectors for the serial ports, SCSI port, and LAN Ethernet port.

– Note that some cables are not provided with the MVME712

series transition module and must be made or purchased by the user. (Motorola recommends shielded cable for all peripheral connections to minimize radiation.)

10. Connect the peripheral(s) to the cable(s).

11. Install any other required VMEmodules in the system.

12. Replace the chassis cover.

13. Connect the power cable to the AC power source and turn the equipment power ON.

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Hardware Preparation and Installation

System Considerations

The MVME162P4 draws power from VMEbus backplane connectors P1 and P2. P2 is also used for the upper 16 bits of data in 3 2-bit tr ansfers, an d for the upper 8 address lines in extended addressing mode. The MVME162P4 may not operate pr operly wi thout it s main boar d connecte d to VMEbus backplane connectors P1 and P2.

Whether the MVME162P4 operates as a VMEbus master or VMEbus slave, it is c onfigured for 3 2 bits of address and 32 bits o f data (A32/D32). However, it handles A1 6 or A24 devi ces in the address ran ges indicated in the VMEchip2 chapter of the Pro grammer’s Reference Guide. D8 and/or D16 devices in the syste m must be handled by the MC680x0/MC68L C0x0 software. For specifics, refer to the memory maps in the Programmer’s Reference Guide.

The MVME162P4 contains shar ed onboard DRAM whose base address is software-selectable. Both the onboard processor and offboard VMEbus devices see this local DRAM at base physical address $00000000, as programmed by the MVME162Bug firmware. This may be changed via software to any other base address. Refer to the Programmer’s Reference Guide for more information.

If the MVME162P4 tries to access offboard resources in a nonexistent location and is not system controller, and if the system does not have a global bus timeout, the MVME16 2P4 waits forever f or the VMEbus cycle to complete. This will cause the system to lock up. There is only one situation in which th e syste m might lack th is gl obal bus timeou t: when t he MVME162P4 is not the system controller and there is no global bus timeout el sewhere in the system.

Multiple MVME162P4s may be installed in a single VME chassis. In general, hardware multiprocessor features are supported.

Note If you are installing multiple MVME162P4s in an MVME945

chassis, do not install an MVME162P4 in slot 12. The height of the IP modules may cause clearance difficulties in that slot position.

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Installation Instructions

Other MPUs on the VMEbus can interrupt, disable, communicate with, and determine the opera tional status of the proc essor(s). One registe r of the GCSR (global control/s tatus regi ster) s et in the VMEchip2 ASIC i ncludes four bits that function as location monitors to allow one MVME162P4 processor to broadcas t a si gnal to any othe r MVME162P4 p rocess ors. Al l eight registers of the GCSR set are acc essib le from any loc al process or as well as from the VMEbus.

The following circuits are protected by solid-state fuses that open during overload conditions and reset themselves once the overload is removed:

❏ IndustryPack +5V (F1, F6) ❏ Remote reset connector +5V (F2) ❏ LAN AUI +12V (F3) ❏ IndustryPack ±12V (F4, F5)

FUSE LED illuminates to indi cate that +1 2 Vdc is avai lable. W hen an

The MVME712M module is used, the yellow DS1 LED on the MVME712M illuminates when LAN power is available, si gnifying that the fuse is good . If the Ethernet transceiver fails to operate, check fuse F3.

The MVME162P4 provides SCSI terminato r power through a 1A fuse (F1) located on the P2 Adapter Board or LCP2 Adapter Board. If the fuse is blown, the SCSI device( s) may f uncti on err atic ally or not at a ll. When the P2 Adapter Board is used with an MVME712M and the SCSI bus is connected to the MVME712M, the green DS2 LED on the MVME712M front panel illumina tes when SCSI terminator power is available. If the green DS2 LED flickers during SCSI bus operation, check P2 Adapter Board fuse F1.

If a solid-state fuse opens, you will need to remove power for several minutes to let the fuse reset to a closed or shorted condition.

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Hardware Preparation and Installation

Serial Connections

The MVME162P4 uses a Zilog Z85230 serial port cont roller to implement the two serial communications interfaces. Each interface supports:

❏ CTS, DCD, RTS, and DTR control signals ❏ TXD and RXD transmit/receive data signals ❏ TXC and RXC synchronous clock signals

The Z85230 supports synchronous (SDLC/HDLC) and asynchronous protocols. The MVME162P4 hardwa re supports async hronous serial ba ud rates of 110b/s to 38.4Kb/s.

For additional information on the MVME162P4 serial communications interface, refer to the Z85230 Serial Communications Controller Product

Brief listed under Manufacturer’s Documents in the Related Documentation appendix. For additional information on the EIA-232-D

interface, refer to the EIA-232-D Standard. The following figures illustrate the signal relationships and signal

connections in the various serial configurations available for ports A and B.

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Page 47

TXD

RXD

Installation Instructions

712M TRANSITION

MODULE

PORT 2

TO MODEM

P2-C27

TXD2

P2-C28

RXD2

P2-C29

RTS

CTS

DTR

DCD

P2-C30 P2-C31 P2-C32

RTS2 CTS2 DTR2 DCD2

J27

P2 CABLE

TO TERMINAL

J16

+12V

1.5K

MVME 712M EIA- 232-D DTE CONFIGURATION (TO MODEM)

TXD RXD RTS CTS DTR DCD DSR TXC RXC TXCO

DB25

PIN 2 PIN 3 PIN 4 PIN 5 PIN 20 PIN 8 PIN 6 PIN 15 PIN 17 PIN 24

PIN 7

TXD RXD RTS CTS DTR DCD DSR TXC RXC

TXCO

FRONT PANEL

DB25

PIN 2 PIN 3 PIN 4 PIN 5 PIN 20 PIN 8 PIN 6 PIN 15 PIN 17 PIN 24

PIN 7

PORT 1

MVME162P4 EIA-232-D DCE CONFIGURATION

(TO TERMINAL)

Z85230 A PORT

RXD

DCD

RXC

TXD

RTS CTS DTR

TXC

132

J26

R D D D

10970.01 (1-6) 9704

Figure 1-3. EIA-232-D Connections to MVME712M (Sheet 1 of 6)

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Hardware Preparation and Installation

712M TRANSITION

MODULE

PORT 2

TXD

RXD

TO MODEM

P2-C27

TXD2

P2-C28

RXD2

P2-C29

RTS

CTS

DTR

DCD

P2-C30 P2-C31 P2-C32

RTS2 CTS2 DTR2 DCD2

J27

P2 CABLE

TO TERMINAL

J16

+12V

1.5K

MVME 712M EIA- 232-D DTE CONFIGURATION (TO MODEM)

TXD RXD RTS CTS DTR DCD DSR TXC RXC TXCO

DB25

PIN 2 PIN 3 PIN 4 PIN 5 PIN 20 PIN 8 PIN 6 PIN 15 PIN 17 PIN 24

PIN 7

TXD RXD RTS CTS DTR

DCD

DSR TXC

RXC

TXCO

FRONT PANEL

DB25

PIN 2 PIN 3 PIN 4 PIN 5 PIN 20 PIN 8 PIN 6 PIN 15 PIN 17 PIN 24

PIN 7

PORT 1

MVME162P4 EIA-232-D DCE CONFIGURATION

(TO TERMINAL)

Z85230 A PORT

DCD

TXD RXD RTS CTS DTR

TXC RXC

132

J26

R D D D

10970.01 (1-6) 9704

Figure 1-3. EIA-232-D Connections to MVME712M (Sheet 2 of 6)

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TXD

RXD

Installation Instructions

712M TRANSITION

MODULE

PORT 4

TO MODEM

P2-A25

TXD4

P2-A26

RXD4

P2-A27

RTS

CTS

DTR

DCD

RTXC

TRXC

P2-A29 P2-A30 P2-A31

P2-A32 P2-A28

RTS4 CTS4 DTR4

DCD4

RTXC4 TRXC4

P2 CABLE

+12V

1.5K

J19

TO TERMINAL

J18

J15

MVME712M EIA-232-D DTE CONFIGURATION (TO MODEM)

NOTE: WITH DTE MODULE, THE RECEIVE CLOCK OF 85230 ON B INTERFACE MUST BE PROGRAMMED AS INPUT TO PREVENT BUFFER CONTENTION

TXD RXD RTS CTS DTR DCD DSR TXC RXC TXCO

DB25

PIN 2 PIN 3 PIN 4 PIN 5 PIN 20 PIN 8 PIN 6 PIN 15 PIN 17 PIN 24

PIN 7

Z85230 B PORT

TXD RXD RTS CTS DTR DCD TXC RXC

3 142

J17

SIM05

EIA-232-D DTE

+5V

TXD

RXD

RTS CTS

DTR DCD DSR

TXC RXC

TXCO

FRONT PANEL

DB25

PIN 2 PIN 3 PIN 4 PIN 5 PIN 20 PIN 8 PIN 6 PIN 15 PIN 17 PIN 24

PIN 7

PORT 2

MVME 162P4 EIA-232-D DTE CONFIGURATION

(TO MODEM)

10970.01 (3-6) 9704

Figure 1-3. EIA-232-D Connections to MVME712M (Sheet 3 of 6)

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Hardware Preparation and Installation

712M TRANSITION

MODULE

PORT 4

TXD

RXD

TO MODEM

P2-A25

TXD4

P2-A26

RXD4

P2-A27

RTS

CTS

DTR

DCD

RTXC

TRXC

P2-A29 P2-A30 P2-A31

P2-A32 P2-A28

RTS4

CTS4 DTR4 DCD4

RTXC4 TRXC4

P2 CABLE

+12V

1.5K

J19

TO TERMINAL

J18

J15

MVME712M EIA-232-D DCE CONFIGURATION (TO TERMINAL)

TXD RXD RTS CTS DTR DCD DSR TXC RXC TXCO

DB25

PIN 2 PIN 3 PIN 4 PIN 5 PIN 20 PIN 8 PIN 6 PIN 15 PIN 17 PIN 24

PIN 7

Z85230 B PORT

DCD

TXD RXD RTS CTS DTR

TXC RXC

3 142

J17

SIM06

EIA-232-D DCE

+5V

D D

TXD RXD RTS CTS DTR

DCD

DSR TXC

RXC

TXCO

FRONT PANEL

DB25

PIN 2 PIN 3 PIN 4 PIN 5 PIN 20 PIN 8 PIN 6 PIN 15 PIN 17 PIN 24

PIN 7

PORT 2

MVME 162P4 EIA-232-D DCE CONFIGURATION

(TO TERMINAL)

10970.01 (4-6) 9704

Figure 1-3. EIA-232-D Connections to MVME712M (Sheet 4 of 6)

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Z85230 B PORT

RXD

DCD

RXC

TXD

RTS CTS DTR

TXC

3 142

J17

SIM05

EIA-232-D DTE

+5V

Installation Instructions

712M TRANSITION

MODULE

PORT 4

TO MODEM

TXD

RXD

P2-A25

TXD4

P2-A26

RXD4

P2-A27

RTS

CTS

DTR

DCD

RTXC

TRXC

P2-A29 P2-A30 P2-A31

P2-A32 P2-A28

RTS4 CTS4 DTR4

DCD4

RTXC4 TRXC4

P2 CABLE

+12V

1.5K

J19

TO TERMINAL

J18

J15

MVME712M EIA-232-D CONFIGURATION (TO TERMINAL)

NOTES:

1. WITH DTE MODULE AND MVME 712 JUMPERED AS TO TERMINAL, THE CLOCKS (TXC AND RXC) ARE THE W RONG DIRECTION.

THE CLOCKS ARE BOTH INPUTS. THEY SHOULD BOTH BE OUTPUTS.

2. WITH DTE MODULE, THE RECEIVE CLOCK OF 85230 ON B INTERFACE

MUST BE PROGRAMMED AS INPUT TO PREVENT BUFFER CONTENTION.

FRONT PANEL

DB25

PIN 2 PIN 3 PIN 4 PIN 5 PIN 20 PIN 8 PIN 6 PIN 15 PIN 17 PIN 24

PIN 7

PORT 2

MVME 162P4 EIA-232-D DTE CONFIGURATION

(TO MODEM)

TXD RXD RTS CTS DTR DCD DSR TXC

RXC

TXCO

10970.01 (5-6) 9704

TXD RXD RTS CTS DTR DCD DSR TXC RXC TXCO

DB25

PIN 2 PIN 3 PIN 4 PIN 5 PIN 20 PIN 8 PIN 6 PIN 15 PIN 17 PIN 24

PIN 7

Figure 1-3. EIA-232-D Connections to MVME712M (Sheet 5 of 6)

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Hardware Preparation and Installation

712M TRANSITION

MODULE

PORT 4

TO MODEM

P2-A25

TXD

RXD

RTS

CTS

DTR

DCD

RTXC

TRXC

P2-A26 P2-A27 P2-A29 P2-A30 P2-A31

P2-A32 P2-A28

TXD4

RXD4

RTS4

CTS4 DTR4 DCD4

RTXC4 TRXC4

P2 CABLE

+12V

1.5K

J19

TO TERMINAL

J18

J15

MVME712M EIA-232-D DTE CONFIGURATION (TO MODEM)

NOTE:

WITH DCE MODULE AND MVME 712 JUMPERED AS TO TERMINAL,

THE CLOCKS (TXC AND RXC) ARE THE WRONG DIRECTION.

THE CLOCKS ARE BOTH OUTPUTS. THEY SHOULD BOTH BE INPUTS.

TXD RXD RTS CTS DTR DCD DSR TXC RXC TXCO

DB25

PIN 2 PIN 3 PIN 4 PIN 5 PIN 20 PIN 8 PIN 6 PIN 15 PIN 17 PIN 24

PIN 7

Z85230 B PORT

DCD TXC RXC

TXD RXD RTS CTS DTR

3 142

J17

SIM06

EIA-232-D DCE

+5V

D D

TXCO

TXD RXD RTS CTS DTR DCD DSR TXC RXC

FRONT P ANEL

DB25

PIN 2 PIN 3 PIN 4 PIN 5 PIN 20 PIN 8 PIN 6 PIN 15 PIN 17 PIN 24

PIN 7

PORT 2

MVME 162P4 EIA-232-D DCE CONFIGURATION

(TO TERMINAL)

10970.01 (6-6) 9704

Figure 1-3. EIA-232-D Connections to MVME712M (Sheet 6 of 6)

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MVME 162P4 EIA-530 DTE CONFIGURATION

(TO MODEM)

Installation Instructions

P2 CONNECTOR

TXD_B

P2-C18

TXD_A

P2-A25

RXD_B

P2-A19

RXD_A

P2-A26

RTS_B

P2-C19

RTS_A

P2-A27

CTS_B

P2-C26

CTS_A

P2-A29

DTR_B

P2-A23

DTR_A

P2-A30

DCD_B

P2-C22

DCD_A

P2-A31

DSR_B

P2-A22

DSR_A

P2-A20

TXC_B

P2-C24

TXC_A

P2-A32

RXC_B

P2-C21

RXC_A

P2-A28

TXCO_B

P2-C23

TXCO_A

P2-A24

TM_A

P2-C25

LL_A

P2-C20

RL_A

P2-A21

Z85230

B PORT

TXD

RXD

RTS*

RTS

CTS*

DTR*

DCD*

TXC

RXC

SIM07

EIA-530 DTE

+5V

J27

+5V

TXD_B TXD_A

RXD_B RXD_A

RTS_B RTS_A

CTS_B CTS_A

DTR_B DTR_A

DCD_B DCD_A

DSR_B DSR_A

TXC_B TXC_A

RXC_B RXC_A

TXCO_B TXCO_A

TM_A

LL_A

RL_A

FRONT PANEL

DB 25

PIN 1

PIN 14 PIN 2

PIN 16 PIN 3

PIN 19 PIN 4

PIN 13 PIN 5

PIN 23 PIN 20

PIN 10 PIN 8

PIN 22 PIN 6

PIN 12 PIN 15

PIN 9 PIN 17

PIN 11 PIN 24

PIN 25

PIN 18

PIN 21

PIN 7

PORT

10971.01 (1-2) 9704

Figure 1-4. EIA-530 Connections (Sheet 1 of 2)

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Hardware Preparation and Installation

P2 CONNECTOR

TXD_B

P2-C18

TXD_A

P2-A25

RXD_B

P2-A19

RXD_A

P2-A26

RTS_B

P2-C19

RTS_A

P2-A27

CTS_B

P2-C26

CTS_A

P2-A29

DTR_B

P2-A23

DTR_A

P2-A30

DCD_B

P2-C22

DCD_A

P2-A31

DSR_B

MVME 162P4 EIA-530 DCE CONFIGURATION

(TO TERMINAL)

DSR_A

TXC_B

TXC_A RXC_B RXC_A

TXCO_B TXCO_A

TM_A

LL_A

RL_A

P2-A22 P2-A20 P2-C24 P2-A32 P2-C21 P2-A28 P2-C23 P2-A24 P2-C25 P2-C20 P2-A21

Z85230

B PORT

TXD

RXD

RTS*

CTS*

DTR*

DCD*

TXC

RXC

SIM08

EIA-530 DCE

J27

+5V

TXD_B TXD_A

RXD_B RXD_A

RTS_B RTS_A

CTS_B CTS_A

DTR_B DTR_A

DCD_B DCD_A

DSR_B DSR_A

TXC_B TXC_A

RXC_B RXC_A

TXCO_B TXCO_A

TM_A

LL_A

RL_A

FRONT PANEL

DB 25

PIN 1

PIN 14 PIN 2

PIN 16 PIN 3

PIN 19 PIN 4

PIN 13 PIN 5

PIN 23 PIN 20

PIN 10 PIN 8

PIN 22 PIN 6

PIN 12 PIN 15

PIN 9 PIN 17

PIN 11 PIN 24

PIN 25

PIN 18

PIN 21

PIN 7

PORT

10971.01 (2-2) 9704

Figure 1-4. EIA-530 Connections (Sheet 2 of 2)

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Z85230

B PORT

TXD

SIMM09

EIA-485/EIA-422

Installation Instructions

P2 CONNECTOR

TXD_B

P2-C18

TXD_A

P2-A25

RXD_B

P2-A19

RXD_A

P2-A26

TXC_B

P2-C24

TXC_A

P2-A32

RXC_B

P2-C21

RXC_A

P2-A28

FRONT PANEL

DB-25

TXD_B TXD_A

PIN 14 PIN 2

PORT

RXD

RXC

TXC

DTR

RTS

FO2

DRIVER/RECEIVER CONTROLLER

REFER TO INSTALLATION MANUAL

Figure 1-5. EIA-485/EIA-422 Connections

RXD_B RXD_A

TXC_B TXC_A

RXC_B RXC_A

PIN 16 PIN 3

PIN 12 PIN 15

PIN 9 PIN 17

1566 9501

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Hardware Preparation and Installation

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2Startup and Operation

Introduction

This chapter provide s information on poweri ng up the MVME162P4 VME Embedded Controller after its installation in a system, and describes the functionality of the switches, status indicators, and I/O ports.

For programming infor mation, cons ult the MVME1X2P 4 VME Embedded

Controller Programmer’s Reference Guide.

Front Panel Switches and Indicators

There are two switches (ABORT and RESET) and eight LEDs (FAIL, STA T,

RUN, SCON, LAN, FUSE, SCSI, and VME) located on the MVME162P4 front

panel.

Table 2-1. MVME162P4 Front Panel Controls

Control/Indicator Function

Abort Switch (

Reset Switch (

FAIL LED (DS1, red) Board failure. Lights if a fault occurs on the MVME162P4 board. STAT LED (DS2, amber) CPU status. Lights if the processor enters a halt condition. RUN LED (DS3, green) CPU activity. Indicates that one of the local bus masters is executing

ABORT) Sends an interrupt signal to the processor. The interrupt is normally

used to abort program execution and return control to the debugger firmware located in the MVME162P4 Flash memory.

The interrupter connected to the Abort switch is an edge-sensitive circuit, filtered to remove switch bounce.

RESET) Resets all onboard devices. Also drives a SYSRESET∗ signal if the

MVME162P4 is system controller. SYSRESET∗ signals may be generated by the Reset switch, a power-up reset, a watchdog timeout, or by a control bit in the Local Control/Status Register (LCSR) in the VMEchip2 ASIC. For further details, refer to Chapter 4, Functional Description.

a local bus cycle.

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Startup and Operation

Table 2-1. MVME162P4 Front Panel Controls

Control/Indicator Function

SCON LED (DS4, green) System controller. Lights when the VMEchip2 ASIC is functioning

as VMEbus system controller.

LAN LED (DS5, green) LAN activity. Lights when the LAN controller is functioning as local

bus master.

FUSE LED (DS6, green) Fuse OK. Indicates that +5Vdc, +12Vdc, and –12Vdc power is

available to the LAN and SCSI interfaces and IP connectors.

SCSI LED (DS7, green) SCSI activity . Lights when the SCSI controller is functioning as local

bus master.

VME LED (DS8, green) VME activity. Lights when the board is using the VMEbus or being

accessed from the VMEbus.

Initial Conditions

After you have verified that all necessary hardware preparation has been done, that all connections have been made correctly, and that the installation is compl ete, yo u can power up the sys tem. Apply ing power to the system (a s well as resetting it) trigg ers an initiali zation of the

MVME162P4’s MPU, hardware, and firmware along with the rest of the system.

The Flash-resident fi rmware initializes the devices on the MVME162P4 board in preparation for booting the operating system. The firmware is shipped from the factory with a set of defaul ts appropr iate to the boa rd. In most cases there is no need to modify the firmware configuration before you boot the operating sys tem. For specifics in this regard, refer to Chapter 3 and to the user documentation for the MVME162Bug firmware.

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Applying Power

When you power up ( or when you re set) the sys tem, the firmwar e executes some self- checks and proceeds to the hardware initializa tion. The system startup flows in a predetermined sequence, following the hierarchy inherent in the processor and the MVME162P4 hardware. The figure below charts the flow of the basic initialization sequence that takes p lace during system startup.

STARTUP

INITIALIZATION

POST

Power-up/reset initialization

Initialization of devices on the MVME162P4 module/system

Power-On Self-Test diagnostics

BOOTING

MONITOR

Firmware-configured boot mechanism, if so configured. Default is no boot.

Interactive, command-driven on-line debugger, when terminal connected.

Figure 2-1. MVME162P4/Firmware System Startup

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Startup and Operation

Pre-Startup Checklist

Before you power up the MVME162P4 sy stem, be sure that the fol lowing conditions exist:

1. Jumpers and/or configuration switches on the MVME162P4 VME Embedded Controller and associated equipment are set as required for your particular application.

2. The MVME162P4 board is installed and cabled up as appropriate for your particular chassis or system, as outlined in Chapter 1.

3. The terminal that you plan to use as the system cons ole is connecte d to the console port (serial port 1) on the MVME162P4 module.

4. The terminal is set up as follows:

– Eight bits per charac ter – One stop bit per character – Parity disabled (no parity protect ion) – Baud rate 9600 baud (the default baud rate of many serial ports

at power-up)

5. Any other device that you wish to use, such as a host computer system and/or peripheral equipment, is cabled to the appropriate connectors.

After you comple te the ch ecks lis ted above, you are ready to power up th e system.

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Bringing up the Board

The MVME162P4 comes with MVME162Bug fi rmware installed. For the firmware to operate properly with the board, you must follow the steps below.

Caution

Inserting or removing boards with power applied may damage board components.

Turn all equipment pow er OFF. Refe r to MVME162P4 Configuration on

page 1-5 and verify that jumpers and switches are configured as necessary

for your particular application.

1. Configuration switch S4 on the MVME162P4 contains eight segments, which all affect the operation of the firmware. They are read as a regist er ( at l ocati on $FFF4 202C) i n the Petr a MC2 sect or. (The MVME1X2P4 VME Embedded Controller Programmer’s Reference Guide has additional information on the Petra MC2 emulation.) The bit values are read as a 0 when the corresponding switch segment is set to

OFF.

The defaul t configuration for S4 has S4 set to a ll 0s (all switch segments set to lower order bits (GPI0 to GPI3, switch segments 5-8). Table 2-2 describes the bit assignments on S4.

ON). The 162Bug firmware reser ves/defines the four

ON, or as a 1 when that segm ent is set to

2. Configure header J1 as appropria te for the des ired system controller functionality (alwa ys system contro ller, neve r system cont roller , or self-regulating) on the MVME162P4.

3. Header J14 configures the IP bus clock for either 8MHz or the processor bus clock spe ed (25MHz or 32MHz for the MC68040 a nd MC68LC040). The factory configuration has a jumper installed on J14 pins 1-2, denoting an 8MHz clock. Verify that this setting is appropriate for your application.

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Startup and Operation

Bit No. S4 Segmen t Function

GPI0 8 When set to 1 (high) , i ns t ructs th e debugger to use local static RAM for

GPI1 7 When set to 1 (high), instructs the de bugger to use the default

GPI2 6 Reserved for future use. GPI3 5 When set to 0 (low), informs the debugger that it is executing out of

GPI4 4 Open to your application. GPI5 3 Open to your application. GPI6 2 Open to your application. GPI7 1 Open to your application.

Table 2-2. Software-Readable Switches

its work page (variables, stack, vector tables, etc.).

setup/operation parameters in ROM instead of the user se tup/operation parameters in NVRAM. The effect is the same as pressing the

ABORT switches simultaneously.

and This feature can be helpful in the event the user setup is corrupted or

does not meet a sanity check. Refer to the ENV command description for the Flash/ROM defaults.

Flash memory. When set to 1 (high), it informs the debugger that it is executing out of the PROM.

RESET

4. You may configure Port B of the Z85230 serial communications controller with a ser ial interfac e module (SIM), which you install a t connector J15 on the MVME162P4 board. Five serial interface modules are available:

– EIA-232- D DTE (SIMM05) – EIA-232-D DCE (SIMM06) – EIA-530 D TE (SIMM07) – EIA-530 DCE (SIMM08) – EIA-485, or EIA-422 DTE or DCE (all with SIMM09) For information on removing and/or installing a SIM, refer to

Chapter 1.

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Bringing up the Board

5. Headers J16 and J17 configure serial ports 1 and 2 to drive or receive clock signals provided by the TXC and RXC signal lines. The MVME162P4 is factory-configured for asynchronous communication: it comes with no jumpers on J16 or J17. Refer to the instruct ions in Chapter 1 if your a pplication req uires config uring ports 1 and 2 for synchronous communication.

6. Header J19 enables or disables the IP bus strobe function on the MVME162P4. The factory configuration puts no jumper on J19, disabling the Strobe∗ signal to the Petra/IP2 chip disconnected. Verify that this setting is appropriate for your application.

7. The jumpers on header J22 establish the SRAM backup power source on the MVME162P4. The factory configuration uses VMEbus +5V standby voltage as the primary and s econdary powe r source (the onboard battery is disconnected). Verify that this configuration is appropriate for your application.

8. The EPROM size select header, J23, should be jumpered between pins 2-3. This sets i t up for a 4Mbit x 8 EPROM density, t he factory default.

9. Header J24 defines the s tate of Fl ash memory write protecti on. The factory configuration has the jumper installed, allowing writes to Flash. Verify that this setting is appropriate for your application.

10. Verify that the se tt ing s of configuration switches S3 (MC2 DRAM size), S5 (IP DMA snoop control, IP Reset mode, and Flash Write Enable mode), and S6 (MCECC DRAM size) are appropriate for your memory controller emulation.

11. Refer to the setup p rocedure for your parti cular chassis or syst em for details concerning the installation of the MVME162P4.

12. Connect the termin al to be used a s the 162Bug system co nsole to the default EIA-232-D port at Serial Port 1 on the front panel of the MVME162P4, or Serial Por t 2 on the MVME712 x series transition module. (For other connection options, refer to Serial Connections in Chapter 1.) Set the terminal up as follows:

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Startup and Operation

– Eight bits per charac ter – One stop bit per character – Parity disabled (no parity) – Baud rate 9600 baud (the power-up default) After power-up, you can reconf igure the baud rate of the de bug port

by using the 162Bug Port Format (PF) command.

Note Whatever the b aud rate, some form of hardware hands haking —

either XON/XOFF or via the RTS/CST line — is desirable if the system supports it. If you get garbled messages and missing characters, you should check the terminal to make sure that handshaking is enabled.

13. If you have equipment (such as a host computer system and/or a serial printer) to connect to the other EIA-232-D port connectors (marked connect the appropri ate ca ble s and conf igure t he port (s) as deta iled in Step 12 above. After power-up, you can reconfigure the port(s) by programming the MVME162P4 Z85230 Serial Communicati ons Controller (SCC) or by using the 162Bug PF command.

SERIAL PORT on the MVME712x transition module),

14. Power up the system. 162Bug executes some self-checks and displays the debugger prompt

162-Bug> if the firmware is in Board

mode. However, if the ENV command has placed 162Bug in System

mode, the system performs a self-test and tries to aut oboot. Refe r to the ENV and MENU commands (Table 3-2).

If the confidence test fails, the test is aborted when the first fault is encountered. If possible, an appropriate message is displayed, and control then returns to the menu.

15. Before using the MVME162P4 after the initial installation, set the date and time using the following command line structure:

162-Bug> SET [mmddyyhhmm]|[<+/-CAL>;C]

For example, the followi ng command line starts the real -time clock and sets the date and time to 10:37 a.m., September 7, 2000:

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Bringing up the Board

Autoboot

162-Bug> SET 0907001037

The board’s self-tests and operating systems require that the realtime clock be running.

Note If you wish to execute the debugger out of Flash and Flash

does not contain 162 Bug, you may copy the EPROM version of 162Bug to Flash memory. To c opy the EPROM version of 162Bug to Flash memory, first ve rify that a jumper is in place on J24 to enable Fl ash writes, set switch S4 seg ment 5 to make sure that 162Bug is in Bug mode. Then copy the EPROM contents to Flash memory with the PFLASH command as follows:

162-Bug> PFLASH FF800000:80000 FFA00000

Then remove the jumper from J24 (if you wish to disable subsequent Flash writes ) and slide switch S4 segment 5 back to

OFF. (162Bug always executes f rom memory location FF800000;

the setting of S4 determin es whether that location is in EPROM or Flash.)

ON,

Autoboot is a software routine included in the 162Bug Flash/EPROM to provide an independent mechanism for booting operating systems. The autoboot routine automatically scans for controllers and devices in a specified sequen ce until a val id bootable devi ce containing a boot media is found or the list is exhausted. If a valid bootable device is found, a boot from that device is started. The control ler scanning sequence goes from the lowest controller Logical Unit Number (LUN) d etected to the highest LUN detected. Controllers, devices, and their LUNs are listed in Appendix D.

At power-up, Autoboot is enabled and (provided that the drive and controller numbers encountered are valid) the following message is displayed upon the system console:

Autoboot in progress... To abort hit <BREAK>

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Startup and Operation

Caution

A delay follows this message so that you can abort the Autoboot proces s if you wish. Then the actual I/O begins: the program designated within the volume ID of the media specified is loaded into RAM and control passes to it. If you want to gain control without Autoboot during this time, however, you can press the <BREAK> key or use the switches on the front panel.

The Autoboot process is controlled by parameters contained in the ENV command. These parameters allow the selection of specific boot devices and files, and allow programming of the Boot delay. Refer to the ENV command description in Chapter 3 for more details.

Although you can use streaming tape to autoboot, the same power supply must be connected to the ta pe drive, t he control ler, and the MVME16 2P4. At power-up, the tape controller will position the streaming tape to the load point where the volume ID can correctly be read and used.

However, if the MVME162P4 loses powe r but the controller does not, and the tape happens to be at load point, the necessary command sequences (Attach and Rewind) cannot be given to the controller and the autoboot will not succeed.

ABORT or RESET

ROMboot

As shipped from the factory, 162Bug occupies the first quarter of Flash memory. This leaves the remainder of the Fla sh memory a nd the EPROM socket (XU1) available for your use.

Note You may wish to contact your Motorola sales office for

assistance in using these resources.

The ROMboot function is configured/enabled via the ENV command (refer to Chapter 3) and is executed at power-up (optionally also at reset).

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Bringing up the Board

You can also execute the ROMboot function via the RB command, assuming there is valid code in the memory devi ces (or optionally elsewhere on the board or VMEbus) to support it. If ROMboot code is installed, a user-written routine is given control (if the routine meets the format requi rements).

One use of ROMboot might be resetting the SYSFAIL∗ line on an unintelligent controller module. The NOR B command disab l es the function.

For a user’s ROMboot module to gain control through the ROMboot linkage, four conditions must exist:

❏ Power has just been applied (but the ENV command can change this

to also respond to any reset).

❏ Your routine is located within the MVME162P4 Flash/PROM

memory map (but the ENV command can change this to any other portion of the onboard memory, or even offboard VMEbus memory).

❏ The ASCII string "BOOT" is f ound i n the speci fied me mory ra nge. ❏ Your routine pass es a checksum tes t, which ensu res that this routine

was really intended to receive control at powerup.

For complete details on using the ROMboot function, refer to the Debugging Package for Motorola 68K CISC CPUs User’s Manual.

Network Boot

Network Auto Boot is a software routine in the 162Bug Flash/EPROM which provides a mechanism for booting an operating system using a network (local Ethernet interface) as the boot device. The Network Auto Boot routine automa tically scans for contr ollers and device s in a spec ified sequence until a vali d bootable device containing boot media is found or until the list is exhausted. If a valid bootable device is found, a boot from that device is started. The controller scanning sequence goes from the lowest controller Logical Unit Number (LUN) d etected to the highest LUN detected. (Refer to Appendix C for defaul t LUNs.)

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Startup and Operation

At power-up, Network Boot is enabled and (provided that the drive and controller numbers encountered are valid) the following message is displayed upon the system console:

Network Boot in progress... To abort hit <BREAK>

After this mess age, there is a delay to let yo u abort the Auto Boot process if you wish. Then the actual I/O is begun: the program designated within the volume I D of the media specified is lo aded into RAM and control passes to it. If you wa nt t o ga in control without Network Boot during this time, however, you can pr ess the <BREAK> key or use the software

ABORT or RESET switches.

Network Auto Boot is controlled by parameters contained in the NIOT and ENV commands. These parameters allow the selection of specific boot devices, systems, and files, and allow programmin g of the Boot delay. Refer to the ENV command description in Chapter 3 for more details.

Restarting the System

You can initialize the system to a known state in three different ways: Reset, Abort, and Break. Each method has characteristics which make it more suitable than the others in certain situations.

A special debugger function is accessible during resets. This feature instructs the debugger to use the default setup/operation parameters in ROM instead of your own setup/operation parameters in NVRAM. To activate this function, you press the same time. This feature can be helpful in the event that your setup/operation parameters are corrupted or do not meet a sanity check. Refer to the ENV command description in Chapter 3 for the ROM defaults.

RESET and ABORT switches at the

Reset

Powering up the MVME162P4 initiates a system reset. You can also initiate a reset by pressing and quick ly releasing the MVME162P4 front panel, or re set the board in software.

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RESET switch on the

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Restarting the System

Abort

For details on resett ing the MVME162 P4 board thr ough software, r efer to the MVME1X2P4 Embedded Controller Programmer’s Reference Guide.

Both “cold” and “warm” r eset modes are a vaila ble. By defaul t, 162Bug is in “cold” mode. During cold resets, a tot al system initiali zation takes place, as if the MVME162P4 had just been powered up. All static variables (including disk device and controller parameters) are restored to their default states. The breakpoint table and offset registers are cleared. The target registers are invalidated. Input and output character queues are cleared. Onboard devices (timer, serial ports, etc.) are reset, and the two serial ports are reconfigured to their default state.

During warm resets, the 162Bug variable s and tables are preserved, as we ll as the target state registers and breakpoints.

Note that when the MVME162P4 comes up in a cold reset, 162Bug runs in Board mode. Using the Environment ( ENV) or MENU commands can make 162Bug run in System mode. Refer to Chapter 3 for specifics.

You will need to reset your system if the processor ever halts, or if the 162Bug environment is ever lost (vector table is destroyed, stack corrupted, etc.).

Aborts are invoked by pressing and releasing the ABORT switch on the MVME162P4 front panel. When you invoke an abort while executing a user program (running target code), a snapshot of the processor state is stored in the target registers. This characteristic makes aborts most appropriate for terminating user programs that are being debugged.

If a program gets caught in a loop, for instance, aborts should be used to regain control. The target PC, register contents, etc., help to pinpoint the malfunction.

Pressing and releasi ng the which may interrupt the processor if enabled. The target registers, reflecting the mac hine state at the time the

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ABORT switch generates a local board condition

ABORT switch was pressed, are

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displayed on the screen. Any breakpoints installed in your code are removed and the breakpoint table remains intact. Control returns to the debugger.

Break

Pressing and releasing the <BREAK> key on the terminal keyboard generates a ‘‘power break’’. Breaks do not produce interrupts. The only

time that breaks are recognized is while characters are being sent or received by the console port. A break removes any breakpoints in your code and keeps the breakpoint table intact. If the function was entered using SYSCALL, Break also takes a snapshot of the machine state. This machine state is then accessible to you for diagnostic purposes.

In many cases, you may wish to ter minate a de bugger command before i ts completion (for example , during the display of a large block of memory). Break allows you to terminate the command.

Diagnostic Facilities

The 162Bug package includes a set of hardware diagnostics for testing and troubleshooting the MVME162P4. To use the diagnostics, switch directories to the diagnostic directory.

If you are in the debugger directory, you can switch to the diagnostic directory with the debugger command Switch Directories (SD). The diagnostic prompt for Motorola 68K CISC CPUs User’s Manual for complete descriptions of the diagnostic routines available and instructions on how to invoke them. Note that some diagnostics depend on restart defaults that are set up only in a particular restart mode. The documentation for such diagnostics includes restart information.

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162-Diag> appears. Refer to the Debugging Package

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Introduction

The 162Bug firmware i s the layer of software just above the hardware . The firmware supplies the appropriate initialization for devices on the MVME162P4 board upon power-up or reset.

This chapter descri bes the basic s of 162Bug and its a rchitectur e, describes the monitor (interactive c ommand portion of the firmware) in detail, and gives information on using the debugger and special commands. A list of 162Bug commands appears at the end of the chapter.

For complete user information about 162Bug, refer to the Debugging

Package for Motorola 68K CISC CPUs User’s Manual and to the MVME162Bug Diagnostics User’s Manual, listed under Related Documentation.

3162Bug Firmware

162Bug Overview

The firmware for the M68000-based (68K) series of board and system level products has a c ommon ge nealogy, deriving from the Bug firmware currently used on all Motorola M68000-based CPUs. The M68000 firmware version implemented on the MVME162P4 MC68040- or MC68LC040-based embedded contro ll er is known as MVME162Bug, or 162Bug. It includes diagnostics for testing and configuring IndustryPack modules.

162Bug is a powerful evaluation and debugging tool for systems built around MVME162P4 CISC-based micr ocomputers. Facilities are available for loading and executing user programs under com plete operator control for system evaluation. The 162Bug firmware provides a high degree of functionality, user friendliness, portability, and ease of maintenance.

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162Bug includes:

❏ Commands for display and modification of memory

❏ Breakpoint and tracing capabilities ❏ A powerful assembler/dis assembler useful for patching programs ❏ A “self-test at po wer- up” feature which verifies the integrity of t he

system

In addition, the TRAP #15 syst em calls make various 162Bug rou tines that handle I/O, data conversion, and string functions available to user programs.

162Bug consists of three parts:

❏ A command-driven user-interactive software debugger, described

in this chapter . It is re fe rred to her e as “ th e debugg er” or “162Bug ”.

❏ A command-driven diagnostic package for the MVME162P4

hardware, referred to here as “the diagnostics”.

❏ A user interface or debug/diagnostics monitor that accepts

commands from the system console terminal.

When using 162Bug, you operate out of either the debugger directory or the diagnostic directory.

❏ If you are in the deb ugger director y, the debugger prompt 162-Bug>

is displayed and you have all of the debugger commands at your disposal.

❏ If you are in the diagnostic directory, the diagnostic prompt 162-

Diag> is displayed and you have all of the diagnostic commands at

your disposal as well as all of the debugger commands.

Because 162Bug is command-driven, it performs its vari ous operati ons in response to user commands entered at the keyboard. When you enter a command, 162Bug executes the command and the prompt reappears. However, if you enter a command that causes executi on of user target code (for example, GO), then cont rol may or may not return to 162Bug, depending on the outcome of the user program.

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If you have used one or more of Motorol a’s other debugging packages, you will find the CISC 162Bug very similar. Some effort has also been made to improve th e consistency of interactive commands. F or example, delimiters between commands and arguments may be commas or spaces interchangeably.

162Bug Implementation

Physically, 162Bug is contained in a 28F016SA Flash memory chip, providing 512KB (128K longwords) of storage. Optionally, the 162Bug firmware can be loaded and executed in a single 27C040 DIP EPROM installed in socket XU1. The executable code is checksummed at every power-on or reset firmware entry, and the result (which includes a precalculated chec ksum cont ained in the memory de vices) is t ested for a n expected zero. Users are cautioned against modification of the memory devices unless precautions for re-checksumming are taken.

162Bug Implementation

Note MVME162P4 boards ordered without the VMEbus interface

are shipped with Flash m emory blank (the factory uses the VMEbus to program the Flash memory wit h debugger code). To use the 162Bug package, be sure that switch S4 segment 5 is configured to select the EPROM memory map.

If you subsequently wish to run the debugger from Flash memory, you must first initialize Flash memory with the PFLASH command, then reconfigure S4. Refer to Step 15 (Note) under Bringing up the Board on page 2-5 for further details.

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Memory Requirements

The program portion of 162Bug is approximately 512KB of code,

consisting of download, debugger, and diagnostic packages contained entirely in Flash memory or in EPROM.

The 162Bug firmware ex ecutes from address $FF800000 whether i n Flash or EPROM. If you set switch S4 segment 5 to

ON, the address spaces of the

Flash and EPROM are swapped. For MVME162P-244 and -344 series boards (MVME162P4), the factory ship configuration except in the noVMEbus case has switch S4 segment 5 set to

OFF (162Bug operating out

of Flash). The 162Bug initial stack completely changes 8KB of SRAM memory at

addresses $FFE0C000 through $FFE0DFFF, at power-up or reset.

Table 3-1. Memory Offsets with 162Bug

Type of Memory Present Default DRAM

4/8/16/32MB synchron ous DRAM (S DRAM). Appears as parity memory at 1/8/16MB, ECC at 32MB.

The synchronous DRAM can be modeled as ECC or parity type, as indicated above.

The 162Bug firmware requires 2KB of NVRAM for storage of board configuration, commun ic ati on, and booting parameters. This storage area begins at $FFFC16F8 and ends at $FFFC1EF7.

162Bug requires a minimum of 6 4KB of contiguous rea d/write memory to operate. The ENV command controls where this block of memory is located. Regardless of where the onboard RAM is located, the first 64KB is used for 162Bug stack and static variable space and the rest is reserved as user space. Whenever the MVME162P4 is reset, the target PC is initialized to the address correspon ding to t he beginni ng of th e user sp ace, and the target stack pointers are initialized to addresses within the user space, with the targ et Interrupt Stack Pointer (ISP) set to the to p of the user space.

Default SRAM

Base Address

$00000000 $FFE00000

Base Address

(onboard SRAM)

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Using 162Bug

162Bug is command-driven; it perfor ms its various o perations i n response to commands that you enter a t the k eyboard. Whe n the appears on the terminal screen, the debugger is ready to accept debugger commands. When the debugger is ready to accept diagnostics commands.

To switch from one mode to the other, enter SD (Switch Directories). To examine the commands in the directory that you are currently in, use the Help command (HE).

What you key in is stored in an internal buff er. Execution begi ns only after the carriage return is entered. This allows you to correct entry errors, if necessary, with the control characters de scribed in the Debugging Package for Motorola 68K CISC CPUs User’s Manual, Chapter 1.

After the debugger executes the command you have entered, the prompt reappears. However, if the command ca uses exe cution of user targ et code (for example GO), then control may or may not return to the debugger, depending on what the user program does.

Using 162Bug

162-Bug> prompt

162-Diag> prompt appears on the screen, the

For example, if a bre akpoint has bee n specified, t hen contro l returns to t he debugger when the br eakpoint is enc ountered during e xecution of the user program. Alternativel y, the user program could return to the debugger by means of the System Call Handler routine RETURN (described in the Debugging Package for Motorola 68K CISC CPUs User’s Manual, Chapter 5).

A debugger command is made up of the following parts:

❏ The command name, either uppercase or lowercase (e.g., MD or

md).

❏ A port number (if the c ommand is set up to work with more than one

port).

❏ Any required arguments, as specified by the command. ❏ At least one space before the first argument. Precede all other

arguments with either a space or comma.

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162Bug Firmware

❏ One or more options. Precede an option or a string of options with

a semicolon (;). If no option is entered, the command’s default option conditions are used.

Debugger Commands

The 162Bug debugger commands are summarized in the following table. The commands are described in detail in the Debugging Package for Motorola 68K CISC CPUs User’s Manual.

Table 3-2. Debugger Commands

Command Description

AB Automatic Bootstrap Operating System NOAB No Autobo ot AS One Line Assembler BC Block of Memory Compare BF Block of Memor y Fill BH Bootstrap Operating System and Halt BI Block of Memory Initialize BM Block of Memory Move BO Bootstrap Operating System BR Bre akpoint Insert NOBR Breakpoint Delete BS Block of Memory Search BV Block of Memory Verify CM C oncu rren t Mode NOCM No Concurrent Mode CNFG Configure Board Information Block CS Checksum DC Data Conversion DMA DMA Block of Memory Move DS One Line Disassembler DU Dump S-records ECHO Echo String ENV Set Environment to Bug/Operating System

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Table 3-2. Debugger Commands (Continued)

Command Description

GD Go Direct (Ignore Breakpoints) GN Go to Next Instruction GO Go Execute User Program GT Go to Temporary Breakpoint HE Help IOC I/O Control for Disk IOI I/O Inquiry IOP I/O Physical (Direct Disk Access) IOT I/O "Teach" for Configuring Disk Controller IRQM Interrupt Request Mask LO Load S-records from Host MA Macro Define/Display NOMA Macro Delete MAE Macro Edit MAL Enable Macro Expansion Listing NOMAL Disable Macro Expansion Listing MAW Save Macros MAR L oad Macros MD Memory Display MENU Menu MM Memory Modify MMD Memory Map Diagnostic MS Memory Set MW Memory Write NAB Automatic Network Boot Operating System NBH Network Boot Operating System and Halt NBO Network Boot Operating System NIOC Network I/O Control NIOP Network I/O Physical NIOT Network I/O Teach NPING Network Ping OF Offset Registers Display/Modify PA Printer Attach

Debugger Commands

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Table 3-2. Debugger Commands (Continued)

Command Description

NOPA Printer Detach PF Port Format NOPF Port Detach PFLASH Program FLASH Memory PS Put RTC Into Power Save Mode for Storage RB ROMboot Enable NORB ROMboot Disable RD Register Display REMOTE Connect the Remote Modem to CSO RESET Cold/Warm Reset RL Read Loop RM Register Modify RS Register Set SD Switch Directories SET Set Time and Date SYM Symbol Table Attach NOSYM Symbol Table Detach SYMS Symbol Table Display/Search T Trace TA Terminal Attach TC Trace on Change of Control Flow TIME Display Time and Date TM Transparent Mode TT Trace to Temporary Breakpoint VE Verify S-Records Against Memory VER Display Revision/Version WL Write Loop

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Modifying the Environment

You can use the factory-installed debug monitor, 162Bug, to modify certain parameters contained in the MVME162P4’s Non-Volatile RAM (NVRAM), also known as Battery Backed-Up RAM (BBRAM).

❏ The Board Information Block in NVRAM contains various entries

that define operating parameters of the board hardware. Use the 162Bug command CNFG to change those para meters.

❏ Use the 162Bug command ENV to change configurable 162Bug

parameters in NVRAM.

The CNFG and ENV commands are both described in the Debugging Package for Motorola 68K CISC CPUs User’s Manual. Refer to that manual for general information about their use and capabilities.

The following paragraphs present supplementary information on CNFG and ENV that is specific to the 162Bug firmware, along with the parameters that you can modify with the ENV command.

Modifying the Environment

CNFG - Configure Board Information Block

Use this command to display and configure the Board Information Block which resides within th e NVRAM. The board information block contains various elements tha t correspo nd to speci fic opera tional par ameters of the MVME162P4 board. (Note that a lthough no memory mezzanine is present on MVME1X2P4 series boards, the o n-b oard me mory is modele d as s uch for backward compatibility.)

The board structure for the MVME162P4 is as follows:

162-Bug>cnfg Board (PWA) Serial Number = " " Board Identifier = " " Artwork (PWA) Identifier = " " MPU Clock Speed = " " Ethernet Address = 0001AF000000 Local SCSI Identifier = " " Parity Memory Mezzanine Artwork (PWA) Identifier = " " Parity Memory Mezzanine (PWA) Serial Number = " "

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162Bug Firmware

Static Memory Mezzanine Artwork (PWA) Identifier = " " Static Memory Mezzanine (PWA) Serial Number = " " ECC Memory Mezzanine #1 Artwork (PWA) Identifier = " "

ECC Memory Mezzanine #1 (PWA) Serial Number = " " ECC Memory Mezzanine #2 Artwork (PWA) Identifier = " " ECC Memory Mezzanine #2 (PWA) Serial Number = " " Serial Port 2 Personality Artwork (PWA) Identifier = " " Serial Port 2 Personality Module (PWA) Serial Number = " " IndustryPack A Board Identifier = " " IndustryPack A (PWA) Serial Number = " " IndustryPack A Artwork (PWA) Identifier = " " IndustryPack B Board Identifier = " " IndustryPack B (PWA) Serial Number = " " IndustryPack B Artwork (PWA) Identifier = " " IndustryPack C Board Identifier = " " IndustryPack C (PWA) Serial Number = " " IndustryPack C Artwork (PWA) Identifier = " " IndustryPack D Board Identifier = " " IndustryPack D (PWA) Serial Number = " " IndustryPack D Artwork (PWA) Identifier = " " 162-Bug>

The parameters that ar e quoted ar e left -just ifi ed chara cter ( ASCII) stri ngs padded with space characters, and the quotes (") are displayed to indicate the size of the string. Parameters that are not quoted are considered data strings, and data strings are right-justified. The data strings are padded with zeros if the length is not met.

The Board Information Block is factory-configured before shipment. There is no need to modify block parameters unless the NVRAM is corrupted.

Refer to the MVME162P VME Embedded Controller Programmer’s Reference Guide for the actual location and other information about the Board Information Block. Refer to the Debugging Package for Motorola 68K CISC CPUs User's Manual for a CNFG description and examp les .

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ENV - Set Environment

Use the ENV command to view and/ or config ure inte ractivel y all 162 Bug operational parameters that are kept in Non-Volatile RAM (NVRAM).

Refer to the Debugging Package for Motorola 68K CISC CPUs User’s Manual for a description of the use of ENV. Additional information on registers in the MV ME162P4 t hat aff ect th ese p aramet ers appe ars in yo ur

MVME1X2P4 VME Embedded Controller Programmer’s Reference Guide.

Listed and described below are the parameters that you can configure using ENV. The default values shown are those that were in effect when this document was published.

Note In the event of difficulty with the MVME162P4, you may wish

to use env;d <CR> to restore the factory defaults as a troubleshooting aid (see Appendix B).

Configuring the 162Bug Parameters

Modifying the Environment

The parameters that can be configured using ENV are:

Table 3-3. ENV Command Parameters

ENV Parameter and Options Default Meaning of Default

Bug or System environment [B/S] B Bug mode Field Service Menu Enable [Y/N] N Do not display field service menu. Remote Start Method Switch

[G/M/B/N]

Probe System for Support e d I/O Controllers [Y/N]

Negate VMEbus SYSFAIL∗ Always [Y/N]

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B Use both methods [Global Control and Status

Register (GCSR) in the VMEchip2, and Multiprocessor Control Register (MPCR) in shared RAM] to pass and execute cross-loaded programs.

Y Accesses will be made to the appropriate

system buses (e.g., VMEbus, local MPU bus) to determine presence of supported co ntrollers.

N Negate VMEbus SYSFAIL∗ after successful

completion or entrance into the bug command monitor.

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Table 3-3. ENV Command Parameters (Continued)

ENV Parameter and Options Default Meaning of Default

Local SCSI Bus Reset on Debugger Startup [Y/N]

Local SCSI Bus Negotiations Type [A/S/N]

Industry Pack Reset on Debugger Startup [Y/N]

Ignore CFGA Block on a Hard Disk Boot [Y/N]

Auto Boot Enable [Y/N] N Auto Boot function is disabled. Auto Boot at power-up only [Y/N] Y Auto Boot is attempted at power-up reset only. Auto Boot Controller LUN 00 Specifies LUN of disk/tape controller module

Auto Boot Device LUN 00 Specifies LUN of disk/tape device currently

Auto Boot Abort Delay 15 The time in seconds that the Auto Boot

Auto Boot Default String [Y(NULL String)/(String)]

ROM Boot Enable [Y/N] N ROMboot function is disabled. ROM Boot at power-up only

[Y/N] ROM Boot Enable search of

VMEbus [Y/N] ROM Boot Abort Delay 00 The time in seconds th at the R OMboot

ROM Boot Direct Starting Address

N No local SCSI bus reset on debugger startup.

A Asynchronous negotiations.

Y IP modules are reset on debugger startup.

Y Configuration Area (CFGA) Block contents

are disregarded at boot (hard disk only).

currently supported by the Bug. Default is $0.

supported by the Bug. Default is $0.

sequence will delay before starting th e boot. The delay gives you the option of stopping the boot by use of the Break key. The time span is 0-255 seconds.

You may specify a string (filename) to pass on to the code being booted. Maximum length is 16 characters. Default is the null string.

Y ROMboot is attempted at power-up only.

N VMEbus address space will not be accessed by

ROMboot.

sequence will delay before starting th e boot. The delay gives you the option of stopping the boot by use of the Break key. The time span is 0-255 seconds.

FF800000 First location tested when the Bug searches for

a ROMboot module.

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Table 3-3. ENV Command Parameters (Continued)

ENV Parameter and Options Default Meaning of Default

ROM Boot Direct Ending Address FFDFFFFC Last location tested when the Bug searches for

a ROMboot module. Network Auto Boot Enable [Y/N] N Network Auto Boot function is disabled. Network Auto Boot at power-up

only [Y/N] Network Auto Boot Controller

LUN Network Auto Boot Device LUN 00 Specifies LUN of a disk/tape device currently

Network Auto Boot Abort Delay 5 The time in seconds that the Network Boot

Network Autoboot Configuration Parameters Pointer (NVRAM)

Memory Search Starting Address 00000000 Where the Bug begins to search for a work

Memory Search Ending Address 00100000 Top limit of the Bug’s search for a work page.

Y Network Auto Boot is attempted at power-up

reset only.

00 Specifies LUN of a disk/tape controller module

currently supported by the Bug. Default is $0.

supported by the Bug. Default is $0.

sequence will delay before starting th e boot.

The delay gives you the option of stopping the

boot by use of the Break key. The time span is

0-255 seconds.

00000000 The address where the network interface

configuration parameters are to be saved in

NVRAM; these are the parameters necessary

to perform an unattended network boot.

page (a 64KB block of memory) to us e for

vector table, stack, and variables. This must be

a multiple of the debugger work page, modulo

$10000 (64KB). In a multi-controller

environment, each MVME162P4 board could

be set to start its work page at a unique address

to allow multiple debuggers to operate

simultaneously.

If no 64KB contiguous block of memory is

found in the range specified by Memory

Search Starting Address and Memory Search

Ending Address parameters, the bug will place

its work page in the onb oard stati c RAM on th e

MVME162P4. Default Memory Search Ending

Address is the calculated size of local memory .

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Table 3-3. ENV Command Parameters (Continued)

ENV Parameter and Options Default Meaning of Default

Memory Search Increment Size 00 010 000 Multi-CPU feature used to offset the location

of the Bug work page. This must be a multiple of the debugger work page, modulo $10000 (64KB). Typically, Memory Search Increment Size is the product of CPU number and size of the Bug work page. Example: first CPU $0 (0 x $10000), second CPU $10000 (1 x $10000), etc.

Memory Search Delay Enable [Y/N]

Memory Search Delay Address FFFFD20F Default ad dress is $FFFFD20F. This is the

Memory Size Enable [Y/N] Y Memory is sized for Self-Test diagnostics. Memory Size Starting Address 00000000 Default Starting Address is $0. Memory Size Ending Address 00100000 Default Ending Address is the calculated size

N No delay before the Bug begins its s earch for a

work page.

MVME162P4 GCSR GPCSR0 as accessed through VMEbus A16 space; it assumes the MVME162P4 GRPAD (group address) and BDAD (board address within group) switches are set to "on". This byte-wide value is initialized to $FF by MVME162P4 hardware after a System or Power-On reset. In a multi162P4 environment, where the work pages of several Bugs reside in the memory of the primary (first) MVME162P4, the non-primary CPUs will wait for the data at the Memory Search Delay Address to be set to $00, $01, or $02 (refer to the Memory Requirements section in Chapter 3 for the definition of these values) before attempting to locate their work page in the memory of the primary CPU.

of local memory.

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Table 3-3. ENV Command Parameters (Continued)

ENV Parameter and Options Default Meaning of Default

Note

Memory Configuration Defaults. The default configuration for Dynamic RAM mezzanine boards will position the mezzanine with the largest memory size to start at the address selected with the ENV parameter "Base Address of Dynamic Memory". The Base Address parameter defaults to 0. The smaller sized mezzanine will follow immediately above the larger in the memory map. If mezzanines of the same size and type are present, the first (closest to the board) is mapped to the selected base ad dress. If mezzan ines of the same size but different type (parity and ECC) are present, the parity type will be mapped to the selected base address and the ECC type mezzanine will follow. The SRAM does not default to a location in the memory map that is contiguous with Dynamic RAM.

Base Address of Dynamic Memory

Size of Parity Memory 00100000 The size of the Parity type dynamic RAM

Size of ECC Memory Board 0 00000000 The size of the first ECC type memory

Size of ECC Memory Board 1 00000000 The size of the second ECC type memory

Base Address of Static Memory FFE00000 The beginning address of SRAM. The default

Size of Static Memory 00080000 The size of the SRAM type memory present.

00000000 Beginning address of Dynamic Memory

(Parity and/or ECC type memory). Must be a

multiple of the Dynamic Memory board size,

starting with 0. Default is $0.

mezzanine, if any. The default is the calculated

size of the Dynamic memory mezzanine bo ard.

mezzanine. The default is the calculated size of

the memory mezzanine.

mezzanine. The default is the calculated size of

the memory mezzanine.

is FFE00000 for the onboard 128KB SRAM,

or E1000000 for the 2MB SRAM mezzanine.

If only 2MB SRAM is present, it defaults to

address 00000000.

The default is the calculated size of the

onboard SRAM or an SRAM type mezzanine.

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Table 3-3. ENV Command Parameters (Continued)

ENV Parameter and Options Default Meaning of Default

ENV asks the following series of questions to set up the VMEbus interface for the MVME162 series modules. You should have a working knowledge of the VMEchip2 as given in the MVME1X2P4 VME Embedded Controller Programmer’s Reference Guide in order to perform this configuration. Also included in this series are questions for setting ROM and Flash access time.

The slave address decoders are used to allow another VMEbus master to access a local resource of the MVME162P4. There are two slave address decoders set. They are set up as follows:

Slave Enable #1 [Y/N] Y Yes, set up and enable Slave Address Decoder

#1.

Slave Starting Address #1 00000000 Base address of the local resource that is

accessible by the VMEbus. Default is the base of local memory, $0.

Slave Ending Address #1 000FFFFF Ending address of the local resource that is

accessible by the VMEbus. Default is the end of calculated memory.

Slave Address Translation Address #1

Slave Address Translation Select #100000000 This register defines which bits of the address

Slave Control #1 03FF Defines the access restriction for the address

Slave Enable #2 [Y/N] N Do not set up and enable Slave Address

Slave Starting Address #2 00000000 Base address of the local resource that is

Slave Ending Address #2 00000000 Ending address of the local resource that is

Slave Address Translation Address #2

00000000 This register allows the VMEbus address and

the local address to differ. The value in this register is the base address of the local resource that is associated with the starting and ending address selection from the previous questions. Default is 0.

are significant. A logical "1" indicates significant address bits, logical "0" is nonsignificant. Default is 0.

space defined with this slave address decoder. Default is $03FF.

Decoder #2.

accessible by the VMEbus. Default is 0.

00000000 Works the same as Slave Address Translation

Address #1. Default is 0.

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Modifying the Environment

Table 3-3. ENV Command Parameters (Continued)

ENV Parameter and Options Default Meaning of Default

Slave Address Translation Select #200000000 Works the same as Slave Address Translation

Select #1. Default is 0. Slave Control #2 0000 Defines the access restriction for the address

space defined with this slave address decoder.

Default is $0000. Master Enable #1 [Y/N] Y Yes, set up and enable Master Address

Decoder #1. Master Starting Address #1 02000000 Base address of the VMEbus resource that is

accessible from the local bus. Default is the

end of calculated local memory (unless

memory is less than 16MB; then this register is

always set to 01000000). Master Ending Address #1 EFFFFFFF Ending address of the VMEbus resource that is

accessible from the local bus. Default is the

end of calculated memory. Master Control #1 0D Defines the access characteristics for the

address space defined with this master address

decoder. Default is $0D. Master Enable #2 [Y/N] N Do not set up and enable Master Address

Decoder #2. Master Starting Address #2 00000000 Base address of the VMEbus resource that is

accessible from the local bus. Default is

$00000000. Master Ending Address #2 00000000 Ending address of the VMEbus resource that is

accessible from the local bus. Default is

$00000000. Master Control #2 00 Defines the access characteristics for the

address space defined with this master address

decoder. Default is $00. Master Enable #3 [Y/N] Depends on

calculated

size of local

RAM

Yes, set up and enable Master Address

Decoder #3. This is the default if the board

contains less than 16MB of calculated RAM.

Do not set up and enable the Master Address

Decoder #3. This is the default for boards

containing at least 16MB of calculated RAM.

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162Bug Firmware

Table 3-3. ENV Command Parameters (Continued)

ENV Parameter and Options Default Meaning of Default

Master Starting Address #3 00000000 Base address of the VMEbus resource that is

accessible from the local bus. If enabled, the value is calculated as one more than the calculated size of memory. If not enabled, the default is $00000000.

Master Ending Address #3 00000000 Ending address of the VMEbus resource that is

accessible from the local bus. If enabled, the default is $00FFFFFF, otherwise $00000000.

Master Control #3 00 Defines the access characteristics for the

address space defined with this master address decoder. If enabled, the default is $3D, otherwise $00.

Master Enable #4 [Y/N] N Do not set up and enable Master Address

Decoder #4.

Master Starting Address #4 00000000 Base address of the VMEbus resource that is

accessible from the local bus. Default is $0.

Master Ending Address #4 00000000 Ending address of the VMEbus resource that is

accessible from the local bus. Default is $0.

Master Address Translation Address #4

Master Address Translation Select #400000000 This register defines which bits of the address

Master Control #4 00 Defines the access characteristics for the

Short I/O (VMEbus A16) Enable [Y/N]

Short I/O (VMEbus A16) Control 01 Defines the access characteristics for the

00000000 This register allows the VMEbus address and

the local address to differ. The value in this register is the base address of the VMEbus resource that is associated with the starting and ending address selection from the previous questions. Default is 0.

are significant. A logical "1" indicates significant address bits, logical "0" is nonsignificant. Default is 0.

address space defined with this master address decoder. Default is $00.

Y Yes, Enable the Short I/O Address Decoder.

address space defined with the Short I/O address decoder. Default is $01.

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Modifying the Environment

Table 3-3. ENV Command Parameters (Continued)

ENV Parameter and Options Default Meaning of Default

F-Page (VMEbus A24) Enable [Y/N]

F-Page (VMEbus A24) Control 02 Defines the access characteristics for the

ROM Access Time Code 04 Defines the ROM access time. The default is

Flash Access Time Code 03 Defines the Flash access time. The default is

MCC Vector Base VMEC2 Vector Base #1 VMEC2 Vector Base #2

VMEC2 GCSR Group Base Address

VMEC2 GCSR Board Base Address

VMEbus Global Time Out Code 01 Controls VMEbus timeout when the

Local Bus Time Out Code 02 Controls local bus timeout. Default $02 = 256

VMEbus Access Time Out Code 02 Controls the local-bus-to-VMEbus access

Y Yes, Enable the F-Page Address Decoder.

address space defined with the F-Page address

decoder. Default is $02.

$04, which sets an access time of five clock

cycles of the local bus.

$03, which sets an access time of four clock

cycles of the local bus.

05 06 07

D2 Specifies group address ($FFFFXX00) in Short

00 Specifies base address ($FFFFD2XX) in Short

Base interrupt vector for the component

specified. Default: MC2chip = $05 , VMEchip2

Vector 1 = $06, VMEchip2 Vector 2 = $07.

I/O for this board. Default = $D2.

I/O for this board. Default = $00.

MVME162P4 is system controller. Default $01

= 64 µs.

µs.

timeout. Default $02 = 32 ms.

Configuring the IndustryPacks

ENV asks the following series of question s to set up IndustryPack modules

(IPs) on MVME162P4s. The MVME1X2P4 VME Embedded Controller Programmer’s Reference

Guide describes the base addresses and the IP register settings. Refer to that manual for information on setting base addresses and register bits.

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162Bug Firmware

IP A Base Address = 00000000? IP B Base Address = 00000000? IP C Base Address = 00000000? IP D Base Address = 00000000?

Base address for mapping IP modules. Only the upper 16 bits are significant.

IP D/C/B/A Memory Size = 00000000?

Define the memory size requirements for the IP modules:

Bits IP Register Address

31-24 D FFFBC00F 23-16 C FFFBC00E 15-08 B FFFBC00D 07-00 A FFFBC00C

IP D/C/B/A General Control = 00000000?

Define the ge neral control requirements for the IP modules:

Bits IP Register Address

31-24 D FFFBC01B 23-16 C FFFBC01A 15-08 B FFFBC019 07-00 A FFFBC018

IP D/C/B/A Interrupt 0 Control = 00000000?

Define the in terrupt contr ol requiremen ts for the IP modules, channel 0:

Bits IP Register Address

31-24 D FFFBC016 23-16 C FFFBC014 15-08 B FFFBC012 07-00 A FFFBC010

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Modifying the Environment

IP D/C/B/A Interrupt 1 Control = 00000000?

Define the in terrupt contr ol requiremen ts for the IP modules, channel 1:

Caution

Bits IP Register Address

31-24 D FFFBC017 23-16 C FFFBC015 15-08 B FFFBC013 07-00 A FFFBC011

If you have specified environmental parameters that will cause an overlap condition, a warning message will appear before the environmental parameters are saved in NVRAM. The important informa tion about each configurable ele ment in the memory map is displayed, showing where any overlap conditions exist. This allows you to quickly identify and correct an undesirable configuration before it is saved.

If an undesirable configura tion alrea dy exist s, you may wis h to res tore the factory defaults with env;d <CR>.

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162Bug Firmware

ENV warning example:

WARNING: Memory MAP Overlap Condition Exists

S-Address E-Address Enable Overlap M-Type Memory-MAP-Name $00000000 $FFFFFFFF Yes Yes Master Local Memory (Dynamic RAM) $FFE00000 $FFE7FFFF Yes Yes Master Static RAM $01000000 $EFFFFFFF Yes Yes Master VMEbus Master #1 $00000000 $00000000 No No Master VMEbus Master #2 $00000000 $00FFFFFF Yes Yes Master VMEbus Master #3 $00000000 $00000000 No No Master VMEbus Master #4 $F0000000 $FF7FFFFF Yes Yes Master VMEbus F Pages (A24/A32) $FFFF0000 $FFFFFFFF Yes Yes Master VMEbus Short I/O (A16) $FF800000 $FFBFFFFF Yes Yes Master Flash/PROM $FFF00000 $FFFEFFFF Yes Yes Master Local I/O $00000000 $00000000 No No Master Industry Pack A $00000000 $00000000 No No Master Industry Pack B $00000000 $00000000 No No Master Industry Pack C $00000000 $00000000 No No Master Industry Pack D $00000000 $00000000 No No Slave VMEbus Slave #1 $00000000 $00000000 No No Slave VMEbus Slave #2

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4Functional Description

Introduction

This chapter describes the MVME162P4 VME embedded controller on a block diagram level. The Summary of Features provides an overview of the MVME162P4, followed by a d eta il ed description of several blocks of circuitry. Figure 4-1 shows a block diagram of the overall board architecture.

Detailed descriptions of other MVME162P4 blocks, including programmable registe rs in the ASICs and peripheral c hips, can be f ound in the MVME1X2P4 Embedded Controller Programmer’s Reference Guide (part number V1 X2PFXA/PG). Refer to that manual for a functional description of the MVME162P4 in greater depth.

Summary of Features

The following table summarizes the features of the MVME162P4 VME embedded controller.

Table 4-1. MVME162P4 Features

Feature Description

Microprocessor MVME162 P4: 25MHz or 32MHZ MC68040 or MC68LC040 processor Form factor 6U VMEbus

16/32MB synchronous DRAM (SDRAM), configurable to emulate

Memory

Flash memory MVME162P4: One Intel 28F016SA 1MB or 2MB 8-bit Flash device EPROM One 32-pin JEDEC stand ard PLCC EPROM socket with 512Kb x 8 density

Real-time clock

1/4/8/16MB parity-protected DRAM or 4/8/16/32MB ECC-protected DRAM

512KB SRAM with battery backup

8KB NVRAM with RTC, battery backup, and watchdog function (SGSThomson M48T58)

4-1

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Functional Descr iption

Table 4-1. MVME162P4 Features (Continued)

Feature Description

Switches RESET and ABORT switches on front panel

Eight: Board Fail

Status LEDs

Timers

Interrupts Eight software interrupts (on versions with VMEchip2 ASIC) VME I/O VMEbus P2 connector

Serial I/O

Ethernet I/O IP interface Four IndustryPack interface channels via 3M connectors behind front panel

SCSI I/O Optional SCSI interface with DMA via P2 or LCP2 adapte r board

VMEbus interface

Controller ( Activity

Four 32-bit tick timers and watchdog timer in Petra ASIC Two 32-bit tick timers and watchdog timer in VMEchip 2 ASIC

Two EIA-232-D, EIA-530, EIA-422, or EIA-425 configurable serial ports via front panel and transition module

Optional Ethernet transceiver interface via DB15 connector on transition module

VMEbus system contro ller functions VMEbus-to-local-bus interface (A24/A32, D8/D16/D32/block transfer

[D8/D16/D32/D64]) Local-bus-to-VMEbus interface (A16/A24/A32, D8/D16/D32) VMEbus interrupter VMEbus interrupt handler Global Control/Status Register (GCSR) for interprocesso r communications DMA for fast local memory/VMEbus transfers (A16/A24/A32,

D16/D32/D64)

(SCSI), VME Activity (VME)

(FAIL), CPU Status (STAT), CPU Activity (RUN), System

SCON), LAN Activity (LAN), Fuse Status (FUSE), SCSI

Processor and Memory

The MVME162P4 is based on the MC68040/MC68LC040 microprocessor. The boards are built with 16MB or 32MB synchronous DRAM (SDRAM). Various versions of the M VME162P4 may have the SDRAM configured to model 1MB, 4MB, 8MB, or 16MB of parityprotected DRAM or 4MB, 8MB, 16MB, or 32MB of ECC-protected DRAM.

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All boards are available with 512KB of SRAM (with battery backup); time-of-day clock (with batte ry bac kup) ; an opt io nal Ether net tra nsc ei ver interface; two serial ports with EIA-232-D or EIA-530 or EIA-485/-422 interface; six ti ck timers with watchdo g timer(s); an EPROM soc ket; 1MB or 2MB Flash memory (one Flash device); four IndustryPack (IP) interfaces with DMA; optional SCSI bus interface with DMA; and an optional VMEbus interface (local bus to VMEbus/VMEbus to local bus, with A16/A24/A32, D8/D16/D32 bus widths and a VMEbus system controller).

I/O Implementation

Input/Output (I/O) s ignals on the MVME162P4 are routed to the VMEbus P2 connector. The main board is connected through a P2 adapter board and cables to the transi tion boards. The MVME162P4 supports the MVME712M and MVME712B series of transition boards (referred to in this manual as MVME712x, unless separately specified).

The MVME712x transition boards provide conf iguration headers, serial port drivers, and industry-standard connectors for various I/ O devices. Although the MVME712x series transition boards were originally designed to support MVME167 boar ds, they lend themselves readily to the MVME162P4 application a s long as you keep a few spec ial considerat ions in mind (refer to th e section o n the Ser ial Communi cations I nterfac e, later in this chapter, for details).

Summary of Features

The I/O connection for the serial ports on the MVME162P4 is also implemented with two DB25 co nnectors on the front panel. In addition, the panel has cutouts for routing of flat cables to the optional IndustryPack modules.

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Functional Descr iption

ASICs

The following ASICs are used on the MVME162P4:

❏ VMEchip2 ASIC (VMEbus interface). Provi des two ti ck timers, a

watchdog timer, programmable map decoders for the master and

slave interfaces, and a VMEbus to/from local bus DMA controller as well as a VMEbus to/from local bus non-DMA programmed access interface, a VMEbus interrupter, a VMEbus system controller, a VMEbus interrupt handler, and a VMEbus requester.

Processor-to-VMEbus transfers are D8, D16, or D32. VMEchip2 DMA transfers to the VMEbus, however, are D16, D32, D16/BLT, D32/BLT, or D64/MBLT.

❏ Petra ASIC. Combines the functions previously covered by the

MC2 chip, the MCECC chip, and the IP2 chip in a single ASIC.

– MC2 function. Provides a parity DRAM emulation. Also

supplies four tick timers and interfaces to the LAN chip, SCSI chip, serial port chip, BBRAM, EPROM/Flash, and SRAM.

– MCECC function. Provides an ECC DRAM emulation. – IP2 function. Provides control and status information for up to

four single-wide or two double- wide Indus tryPack mod ules that can be plugged into the MVME162P4 main board.

Block Diagram

The block diagram in Figure 4-1 on page 4-5 illustrates the MVME162P4’s overall architecture.

Functional Description

This section contains a functional description of the major blocks on the MVME162P4.

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Functional Description

A32/24:D64/32/16/08

VMEchip2

Interface

MC68040/MC68LC040orMC68060/MC68LC060

VMEbus

Master/Slave

VMEbus

MPU

A32/D32

IndustryPack

Functions

Chip

IP2

1/4/8/16MB Parity

Configuration-Dependent Emulations

DRAM Memory

Array

Petra ASIC

Functions

MCECC

Chip

Memory Array

512KB SRAM

w/Battery

Synchronous DRAM

4/8/16/32MB

ECC DRAM

16/32MB

Functions

MC2

Chip

8KB RAM/Clock

Battery Backed

M48T58

4 Channels

I/O

Transition Modules

Connections

Transceiver

Controller

82596CA

Ethernet

Via P2 and

Ethernet

Optional

Transition Modules

Coprocessor

53C710

SCSI

EPROM

JEDEC

Socket

32-Pin

Controller

Serial I/O

Z85230

Connections

Peripherals

Via P2 and

SCSI

DB-25 Front Panel

Transceivers

EIA-232

Transition Module

Via P2 and

2498 0003 (1-2)

1MB/2MB

Flash

Figure 4-1. MVME162P4 Block Diagram

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Functional Descr iption

Data Bus Structure

The local bus on the MVME162P4 is a 32-bit synchronous bus that is based on the MC68040 bus, and which supports burst transfers and snooping. The various local bus mast er and sl ave devices us e the local bu s to communicate. The local bus is arbitrated by pri ority type; the prio rity of

the local bus masters from highest to lowest is: 82596CA LAN, 53C710 SCSI, VMEbus, and MPU. As a general rule, any master can access any slave; not all combinat ions pass the common sense test , however. Refer to the MVME1X2P4 VME Embedded Controller Programmer’s Reference Guide and to the u ser’s guide for each device t o determine it s port size, data bus connection, and any restr ictions that appl y when accessing the device.

Microprocessor

MVME162P4 models may be ordered wi th an MC680 40 o r MC68LC040 microprocessor.

The MC68040 has on-chip instruction and dat a caches and a float ing-point processor. (A floating-point coprocessor is the major difference between the MC68040 and MC68LC040.) Refer to the MC68040 use r’s manual for more information.

MC68

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040 Cache

The MVME162P4 local bus masters (VMEchip2, processor, 53C710 SCSI controller, and 82596CA Ethernet controller) have programmable

control of the snoop/ caching mode. Th e IP DMA local bus master’s snoo p control function is govern ed by the settings of switc h S5 segments 1 and 2 (refer to IP DMA Snoop Control (S5 Pins 1/2) on page 1-18). S5 determines the val ue of t he snoop co ntrol signal fo r all IP DMA t ransf ers. This includes the IP DMA whi ch executes when the DMA control r egisters are updated while the IP DMA is operating in command chaining mode.

The MVME162P4 local bus slaves that support the snoop/caching mode are defined in the “Lo cal Bus M emory Ma p” sect ion o f the MVME1X2P4

VME Embedded Controller Programmer’s Reference Guide.

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Functional Description

Note As outlined in Table 1-4, the snoop capabilities of the

MC68xx040 processor differ f rom those of the MC68xx060 used on MVME172P4 series boards. Application software must take these differences into account.

No-VMEbus-Interface Option

In support of possible future configurations in which the MVME162P4 might be offered as an e mbedded controller witho ut the VMEbus interface, certain logic in the VMEchip2 has been duplicated in the Petra chip. (For the location of the overlapping logic, refer to Chapter 1 in the

MVME1X2P4 VME Embedded Controller Programmer’s Reference Guide.) As long as th e VMEchi p2 ASI C is pr ese nt , th e r edundant logic is

inhibited in the Petra chip. The enabling signals for these functions are controlled by software an d Petra chip hardware initialization.

Memory Options

The following memory options are available on the different versions of MVME162P4 boards.

DRAM

MVME162P4 boards are built with 16MB or 32MB synch ronous DRAM (SDRAM). Depending on build opt ions chosen at the time of manufacture, various versions of the MVME162P4 have the SDRAM configured to model 1MB, 4MB, 8MB, or 16MB of parity-protected DRAM or 4MB, 8MB, 16MB, or 32MB of ECC-protected DRAM.

The SDRAM memory array itself is always a single-bit error correcting and multi-bit error detect ion memory, irrespective of which interface model you use to access the SDRAM. When the MC2 (parity) memory controller interface is used to access the SDRAM, single-bit errors are undetectable to users and multi-bit err ors are define d to be parity errors.

Firmware will initialize the memory controller to maintain backward compatibility with MVME162FX or -LX products. If the Petra ASIC is supporting MVME162FX functionality, the parity memory controller model will be enabled by default. If the Petra ASIC is supporting

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Functional Descr iption

MVME162LX functionality, firmware will enable either the parity or the ECC memory controller model, depending on board configuration. (The board configurati on is a function of switch settings and resist or population options.)

User code can modify Petra register settings to operate in either mode.

SRAM

User code can also modify map decoder/switch settings to enable the maximum amount of memory available. The minimum SDRAM configuration is 16MB.

For specifics on SDRAM performance and for detailed programming information, refer to the chapters on MC2 a nd MCECC memory controller emulations in the MVME1X2P4 VME Embedded Controller Programmer’s Reference Guide.

The MVME162P4 implementation includes a 512KB SRAM (static RAM) option. SRAM architecture is single non-interleaved. SRAM performance is described in the sec tion on t he SRAM memory interf ace in the chapter on the MC2 memory controller emulation in the MVME1X2P4 VME Embedded Controller Progr ammer’ s Re ference Guide. An onboard battery supplies VCC to the SRAM when main power is removed. The worst-case elapsed time for battery protection is 200 days. The SRAM arrays are not parity protected.

The battery backup fu nctio n for the onb oar d SRAM is provi ded by a c ointype Panasonic CR2032 de vice (or equivalent) that supports primary and secondary power sources. In the event of a main board power failure, the CR2032 checks power sourc es a nd s wit ches to the source with the higher voltage.

If the voltage of the backup source is lower than two volts, the CR2032 blocks the second memory cyc le ; t his allows software to provide an early warning to avoid data loss. Because the second access may be blocked during a power failure, software should do at least two accesses before relying on th e data.

The MVME162P4 provides jumpers (on J22) that allow either power source of the backup batt ery to be conne cted to the VMEbus +5V STDBY pin or to one cel l of th e o nboard battery. For ex ample , the primar y syst em

4-8 Computer Group Literature Center Web Site

Motorola MVME162P-244LE, MVME162P-244LSE, MVME162P-244 Series, MVME162P4 Series, MVME162P-344 Installation And Use Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

List of Figures

List of T ables

About This Manual

Summary of Changes

Overview of Contents

Comments and Suggestions

Conventions Used in This Manual

Introduction

Getting Started

Overview of Installation Procedure

Equipment Required

Guidelines for Unpacking

ESD Precautions

Preparing the Board

MVME162P4 Configuration

VME System Controller (J1)

IP Bus Clock (J14)

SIM Selection for Serial Port B (J15)

Removal of Existing SIM

Installation of New SIM

Serial Port 1/Console Clock (J16)

Serial Port 2 Clock (J17)

IP Bus Strobe (J19)

SRAM Backup Power Source (J22)

EPROM Size (J23)

Flash Write Protection (J24)

MC2 DRAM Size (S3)

General-Purpose Readable Switch (S4 Pin 5)

IP DMA Snoop Control (S5 Pins 1/2)

IP Reset Mode (S5 Pin 3)

Flash Write Enable Mode (S5 Pin 4)

MCECC DRAM Size (S6)

Installation Instructions

IP Installation on the MVME162P4

MVME162P4 Installation

System Considerations

Serial Connections

2Startup and Operation

Introduction

Front Panel Switches and Indicators

Initial Conditions

Applying Power

Pre-Startup Checklist

Bringing up the Board

Autoboot

ROMboot

Network Boot

Restarting the System

Reset

Abort

Break

Diagnostic Facilities

Introduction

3162Bug Firmware

162Bug Overview

162Bug Implementation

Memory Requirements

Using 162Bug

Debugger Commands

Modifying the Environment

CNFG - Configure Board Information Block

ENV - Set Environment

Configuring the 162Bug Parameters

Configuring the IndustryPacks

4Functional Description

Introduction

Summary of Features

Processor and Memory

I/O Implementation

Functional Descr iption

ASICs

Block Diagram

Data Bus Structure

Microprocessor

No-VMEbus-Interface Option