Motorola MVME162P2, MVME162P-242E, MVME162P-242L, MVME162P-242, MVME162P-242LE Installation And Use Manual

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MVME162P2

VME Embedded Controller

Installation and Use

V162P2A/IH2

Edition of November 2000

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Printed in the United States of America.

Motorola

and the Motorola logo are registered trademarks of Motorola, Inc.

MC68040™ and MC68060™ are trademarks of Motorola, Inc. IndustryPack™ and IP™ are trademarks of GreenSpring Computers, Inc. All other products ment io ned i n this document are tradema rks or registered tradema rk s of

their respective holders.

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Safety Summary

The following general safety precautions must be observed during all phases of operation, service, and repair of this equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual could result in personal injury or damage to the equipment.

The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. Y ou, as the user of the product, shoul d foll ow these warni ngs and al l other sa fety pr ecauti ons nece ssary fo r the safe ope ration of the equipment in your operating environment.

Ground the Instrument.

To minimize shock hazard, the equipment chassis and enclosure must be connected to an electrical ground. If the equipment is su pplied wi th a three-c onductor A C power ca ble, the po wer cable m ust be plug ged into an a pproved three-contact electrical outlet, with the grounding wire (green/yellow) reliably connected to an electrical ground (safety ground) at the power outlet. The power jack and mating plug of the power cable meet International Electrotechnical Commission (IEC) safety standards and local electrical regulatory codes.

Do Not Operate in an Explosive Atmosphere.

Do not operate the equipment in any explosive atmosphere such as in the presence of flammable gases or fumes. Operation of any electrical equipment in such an environment could result in an explosion and cause injury or damage.

Keep Away From Live Circuits Inside the Equipment.

Operating personnel must not remove equipment covers. Only Factory Authorized Service Personnel or other qualified service personnel may remove equipment covers for internal subassembly or component replacement or any internal adjust ment. Service pe rsonnel should n ot replace compon ents with power c able connected. Under certain conditions, dangero us voltages may exist even with the power cable remo ved. T o avoid inju ries, such pers onnel should always disconnect power and discharge circuits before touching components.

Use Caution When Exposing or Handling a CRT.

Breakage of a Cathode-Ray Tube (CRT) causes a high-velocity scattering of glass fragments (implosion). To prevent CRT implosion, do not handl e the CRT and avoid rough handling o r jarring of t he equipment . Handling o f a CRT should be done only by qualified service personnel using approved safety mask and gloves.

Do Not Substitute Parts or Modify Equipment.

Do not install substitute parts or perform any unauthorized modification of the equipment. Contact your local Motorola representative for service and repair to ensure that all safety features are maintained.

Observe Warnings in Manual.

W arn ings , such as th e exa mple be low, prece de pote nt ially danger ous p rocedu res th rough out th is manu al. In str uction s contained in the warnings m ust be follow ed. You should also employ all ot her safety precautions w hich you dee m necessary for the operation of the equ ipment in your oper at ing environment.

To prevent serious injury or death from dangerous voltages, use extreme caution when handling, testing, and adjusting this equipment and its

Warning

components.

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Flammability

All Motorola PWBs (printed wiring boards) are manufactured with a flammability rating of 94V-0 by UL-recognized manufacturers.

EMI Caution

This equipment ge ner ates, uses a nd can radi ate el ectro magne tic energy . It

Caution

This product contains a lithium battery to power the clock and calendar circuitry.

Caution

may cause or be susceptible to electromagnetic interference (EMI) if not installed and used with adequate EMI protection.

Lithium Battery Caution

Danger of explosion if battery is re placed incorrect ly. Replace battery only with the same or equivalent type recommended by the equipment

manufacturer. Dispose of used batteries according to the manufacturer’s instructions.

Attention

Vorsicht

Il y a danger d’explosion s’il y a remplacement incorrect de la batterie. Remplacer uniquement avec une batterie du même type ou d’un type équivalent recommandé par le constructeur. Mettre au rebut les batteries usagées conformément aux instructions du fa bricant.

Explosionsgefahr bei unsachgemäßem Austausch der Batterie. Ersatz nur durch denselben ode r einen vom Herstel ler empfohle nen Typ. Entsorgu ng gebrauchter Batterien nach Angaben des Herstellers.

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CE Notice (European Community)

Motorola Compute r Group pro ducts wi th the CE mar king co mply with the EMC Dir ective (89/336/EEC). Compliance with this directive implies conformity to the following European Norms:

EN55022 “Limits and Methods of Meas urement of Radio Int erferen ce Chara cteri stic s of Information Technology Equipment”; this product tested to Equipment Class B

EN50082-1:1997 “Electromag netic Compatibi lit y—Gener ic Im munity St andard , Part

1. Residential, Commercial and Light Industry”

System products al so fulf ill EN60950 ( product saf ety) which i s essenti ally the r equirement for the Low Voltage Directive (73/23/EEC).

Board products are tested in a representative system to show compli ance with the above mentioned requirements. A proper installation in a CE-marked system will maintain the required EMC /safety performance.

In accordance with European Community directives, a “Declaration of Conformity” has been made and is on file within the European Union. The “Declaration of Conformity” is available on request. Please contact your sales representative.

Notice

While reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. a ssumes n o lia bility r esulti ng from any omissio ns in this docu ment, or from the use of the information obtained the rein. Motorola reserves the right to revise this document and to ma ke c hanges from time to time in the conten t hereof without obligation of Motorola to notify any person of such revision or changes.

Electronic versions of this material may be read online, downloaded for personal use, or referenced in another document as a URL to the Motorola Comput er Group website. The text itself may not b e published commerci ally in print o r electronic for m, edited, transla ted, or otherwise altered without the permiss ion of Motoro la, Inc.

It is possible th at t hi s publication may contain reference to or in for mation about Motorola products (machines and pr ograms), progra mming, or services that are not av ailable in your country. Such references or information must not be construed to mean that Motorola intends to announce such Motorola products, programming, or services in your country.

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Limited and Restricted Rights Legend

If the documentation contained herein is supplied, directly or indirectly, to the U.S. Government, the following notice shall apply unless otherwise agreed to in writing by Motorola, Inc.

Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (b)(3) of t he Rig hts i n Technical Data clause at DFARS 252.227-7013 (Nov.

1995) and of the Rights in Noncommerc ial Computer Software and Docume ntation c lause at DFARS 252.227-7014 (Jun. 1995).

Motorola, Inc. Computer Group 2900 South Diablo Way Tempe, Arizona 85282

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About This Manual

Summary of Changes.................................................................................................xvi

Overview of Contents................................................................................................xvi

Comments and Suggestions......................................................................................xvii

Conventions Used in This Manual...........................................................................xviii

CHAPTER 1 Hardware Preparation and Installation

Introduction ................................................................................................................1-1

Getting Started ...........................................................................................................1-1

Overview of Installation Procedure....................................................................1-1

Equipment Required...........................................................................................1-2

Guidelines for Unpacking...................................................................................1-3

ESD Precautions.................................................................................................1-3

Preparing the Board ............................................................ .......................................1-4

MVME162P2 Configuration..............................................................................1-5

VME System Controller (J1)..............................................................................1-7

IP Bus Strobe (J11).............................................................................................1-7

SCSI Termination (J12) ......................................................................................1-8

IP Bus Clock (J13)..............................................................................................1-9

SRAM Backup Power Source (J14).................................................................1-10

Flash Write Protection (J16).............................................................................1-11

EPROM/Flash Configuration (J20)..................................................................1-11

MC2 DRAM Size (S3) .....................................................................................1-15

General-Purpose Readable Switch (S4 Pin 5)..................................................1-16

IP DMA Snoop Control (S5 Pins 1/2)..............................................................1-18

IP Reset Mode (S5 Pin 3) .................................................................................1-19

Flash Write Enable Mode (S5 Pin 4)................................................................1-20

MCECC DRAM Size (S6)................................................................................1-21

Installation Instructions................................................. ...... ..... ................................1-22

IP Installation on the MVME162P2.................................................................1-23

MVME162P2 Installation.................................................................................1-23

System Considerations......................................................................................1-25

Serial Connections............................................................................................1-27

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CHAPTER 2 Startup and Operation

Introduction ...............................................................................................................2-1

Front Panel Switches and Indicators..................................................................2-1

Initial Conditions.......................................................................................................2-2

Applying Power.........................................................................................................2 -3

Pre-Startup Checklist.................................................................................................2-4

Bringing up the Board ...............................................................................................2-5

Autoboot............................................................................................................. 2-9

ROMboot..........................................................................................................2-10

Network Boot...................................................................................................2-11

Restarting the System..............................................................................................2-12

Reset.................................................................................................................2-12

Abort.................................................................................................................2-13

Break ................................................................................................................ 2-13

Diagnostic Facilities ................................................................................................2-14

CHAPTER 3 162Bug Firmware

Introduction ...............................................................................................................3-1

162Bug Overview......................................................................................................3-1

162Bug Implementation............................ ...... ..........................................................3-3

Memory Requirements.............................................. ...... ...................................3-4

Using 162Bug............................................................................................................3-5

Debugger Commands................................................................................................3-6

Modifying the Environment......................................................................................3-8

CNFG - Configure Board Information Block ....................................................3-9

ENV - Set Environment...........................................................................................3-11

Configuring the 162Bug Parameters................................................................ 3-11

Configuring the IndustryPacks.........................................................................3-19

CHAPTER 4 Functional Description

Introduction ...............................................................................................................4-1

Summary of Features.................................................................................................4-1

Processor and Memory........................................ ...... .........................................4-3

I/O Implementation ............................................................................................4-3

ASICs .................................................................................................................4-4

Block Diagram...........................................................................................................4-4

Functional Description ..............................................................................................4 -6

Data Bus Structure..............................................................................................4-6

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Microprocessor ...................................................................................................4-6

MC68xx040 Cache......................................................................................4-6

No-VMEbus-Interface Option............................................................................4-7

Memory Options.............................................. ...... .............................................4-7

DRAM ..................................... ...... ...... ........................................................4-7

SRAM............................................ ...... ........................................................4-8

About the Battery.........................................................................................4-9

EPROM and Flash Memory......................................................................4-11

Battery-Backed-Up RAM and Clock................................................................4-12

VMEbus Interface and VMEchip2...................................................................4-12

I/O Interfaces ....................................................................................................4-12

Serial Communications Interface..............................................................4-13

IndustryPack (IP) Interfaces......................................................................4-13

Ethernet Interface ......................................................................................4-14

SCSI Interface............................................................................................4-15

SCSI Termination......................................................................................4-15

Local Resources................................................................................................4-15

Programmable Tick Timers.......................................................................4-16

Watchdog Timer........................................................................................4-16

Software-Programmable Hardware Interrupts...........................................4-16

Local Bus Timeout ....................................................................................4-16

Local Bus Arbiter..............................................................................................4-17

Connectors........................................................................................................4-18

Remote Status and Control........................................................................4-18

CHAPTER 5 Pin Assignments

Connector Pin Assignments.......................................................................................5-1

Remote Reset Connector - J2.....................................................................................5-2

IndustryPack A and B Connectors .............................................................................5-2

Ethernet Connector - J9 .............................................................................................5-4

Serial Connector - J17................................................................................................5-4

SCSI Connector - J23.................................................................................................5-5

VMEbus Connectors (P1, P2)....................................................................................5-5

APPENDIX A Specifications

Board Specifications.................................................................................................A -1

Cooling Requirements ..............................................................................................A-2

Special Considerations for Elevated-T emperature Operation ...........................A-3

EMC Regulatory Compliance...................................................................................A-4

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APPENDIX B Troubleshooting

Solving Startup Problems......................................................................................... B-1

APPENDIX C Network Controller Data

Network Controller Modules Supported.................................................................. C-1

APPENDIX D Disk/Tape Controller Data

Controller Modules Supported................................................................................. D-1

Default Configurations......................... ....................................................................D-2

IOT Command Parameters....................................................................................... D-5

APPENDIX E Related Documentation

MCG Documents.......................................................................................................E-1

Manufacturers’ Documents.......................................................................................E-2

Related Specifications ...............................................................................................E-3

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List of Figures

Figure 1-1. MVME162P2 Board Layout...................................................................1-6

Figure 2-1. MVME162P2/Firmware System Startup................................................2-3

Figure 4-1. MVME162P2 Block Diagram.................................................................4-5

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List of T ables

T ab le 1-1. Startup Overview.............................. ..... ...... .............................................1-1

Table 1-2. MVME162P2 Configuration Settings ......................................................1-5

Table 1-3. EPROM/Flash Mapping — 128K x 8 EPROMs....................................1-13

Table 1-4. EPROM/Flash Mapping — 256K x 8 EPROMs ....................................1-13

Table 1-5. EPROM/Flash Mapping — 512K x 8 EPROMs ....................................1-14

Table 1-6. EPROM/Flash Mapping — 1M x 8 EPROMs........................................1-14

Table 1-7. EPROM/Flash Mapping —

1M x 8 EPROMs, Onboard Flash Disabled.....................................................1-14

Table 1-8. MC2 DRAM Size Settings .....................................................................1-16

Table 1-9. Switch S5 Snoop Control Encoding .......................................................1-18

Table 1-10. MCECC DRAM Size Settings..............................................................1-22

Table 2-1. MVME162P2 Front Panel Controls .........................................................2-1

T ab le 2-2. Software-Readable Switches............................. ..... ...... ............................2-6

Table 3-1. Memory Offsets with 162Bug ..................................................................3-4

T ab le 3-2. Debugger Command s........................................ .......................................3-6

Table 3-3. ENV Command Parameters....................................................................3-11

T ab le 4-1. MVME162P2 Features............................................................ ...... ...... .....4-1

Table 4-2. Local Bus Arbitration Priority ................................................................4-17

Table 5-1. Remote Reset Connector J2 Pin Assignments..........................................5-2

T ab le 5-2. IndustryPack Interconnect Signals......... ...... ...... .......................................5-3

Table 5-3. DB15 Ethernet Connector Pin Assignments.............................................5-4

Table 5-4. Serial Connector Pin Assignments ...........................................................5-4

Table 5-5. SCSI Connector J23 Pin Assignments......................................................5-6

Table 5-6. VMEbus Connector P1 Pin Assignments.................................................5-7

Table 5-7. VMEbus Connector P2 Pin Assignment...................................................5-8

Table A-1. MVME162P2 Specifications .................................................................A-1

Table B-1. Troubleshooting MVME162P2 Boards .................................................B-1

Table E-1. Motorola Computer Group Documents .................................................E-1

Table E-2. Manufacturers’ Documents ....................................................................E-2

Table E-3. Related Specifications ............................................................................ E-3

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About This Manual

MVME162P2 VME Embedded Controller Installation and Use provides instructions for hardware preparation and installation; a board-level hardware overview ; and firmwa re-rel ated genera l inform ation and st artup instructions for the MVME162P-242 series of embedded controllers,

known collectively as the ‘‘MVME162P2’’ because they are equipped with the “Petra” chip and accommodate up to two IP modules.

The “Petra” chip that dist inguishes MVME162P2 embe dded control lers is an application-specific integrated circuit (ASIC) which combines the functions previously covered by the MC2 chip, the IP2 chip, and the MCECC chip in a single ASIC. As of the publica tion date, the informati on presented in this manual applies to the following MVME162P2 models:

Model Number Characteristics

MVME162P-242L 25MHz 68LC040, 16MB SDRAM w/parity, 4 SIO, 2 DMA IP MVME162P-242LE 25MHz 68LC040, 16MB SDRAM w/ECC, 4 SIO, 2 DMA IP, Ethernet MVME162P-242LSE 25MHz 68LC040, 16MB SDRAM w/ECC, 4 SIO, 2 DMA IP,

SCSI/Ethernet MVME162P-242 25MHz 68040, 16MB SDRAM w/parity, 4 SIO, 2 DMA IP MVME162P-242E 25MHz 68040, 16MB SDRAM w/ECC, 4 SIO, 2 DMA IP, Ethernet MVME162P-242SE 25MHz 68040, 16MB SDRAM w/ECC, 4 SIO, 2 DMA IP,

SCSI/Ethernet

If the part number of your board includes a "PA" (for example: MVME162PA-242L), your board is equipped with a second-generation Petra ASIC. All other particulars of the board remain the same.

This manual is intended for anyone who designs OEM systems, adds capability to an existing compatible system, or works in a lab environment for experimental purposes. A basic knowledge of computers and digital logic is assumed. To use this manual, you may also wish to become familiar with the publications listed in the Related Documentation section in Appendix E.

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Summary of Changes

This is the second edition of MVME162P2 Installati on and Use. It supersedes the June 2000 edition and incorporates the following updates.

Date Description of Change

October 2000 In the description of the snoop control switch on page 1-18, entries in the table

concerning boards equipped with the MC68060 processor have been corrected.

October 2000 Several jumper drawings and configuration descriptions in Chapters 1 and 2

have been updated to reflect the current board layout and shipping configuration.

October 2000 In the descriptions of the MC2 and MCECC DRAM size switches on pages

1-15 and 1-21, the importance of executing env;d after modifying switch

settings has been emphasized.

Overview of Contents

Chapter 1, Hardware Preparation and Installation, provides unpacking

instructions, hardware preparation guidelines, and installation instructions for the MVME162P2 VME Embedded Controller.

Chapter 2, Startup and Operation, provides information on powering up

the MVME162P2 VME Embedded Controller after its installation in a system and describes the functionality of the switches, status indicators, and I/O ports.

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Chapter 3, 162Bug Firmware, describes the basics of 162Bug and its

architecture, describes the monitor (interactive command portion of the firmware) in detail, and gives information on using the debugger and special commands.

Chapter 4, Functional Description, describes the MVME162P2 VME

Embedded Controller on a bl ock diagram level.

Chapter 5, Pin Assignments, summarizes the pin assignments for the

various groups of interconnect signals on the MVME162P2.

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Appendix A, Specifications, lists the general specifications for the

MVME162P2 Embedded Controller. Subsequent sections of the appendix detail cooling requirements and EMC regulatory compliance.

Appendix B, Troubleshooting, includes simple troubleshooting steps to

follow in the event t hat you hav e diffic ulty with your MVME162P2 VME Embedded Controller.

Appendix C, Network Controller Data, describes the VMEbus network

controller modules that are supported by the 162Bug firmware.

Appendix D, Disk/Tape Controll er Data, de scribes th e VMEbus disk/t ape

controller modules that are supported by the 162Bug firmware.

Appendix E, Related Documentation, provides all documentation related

to the MVME162P2.

Comments and Suggestions

Motorola welcomes and appreciates your comments on its doc umentation. We want to know what y ou think about our manuals and how we can make them better. Mail comments to:

Motorola Computer Group Reader Comments DW164 2900 S. Diablo Way Tempe, Arizona 85282

You can also submit comments to the following e-mail address:

reader-comments@mcg.mot.com

In all your corres pondence , plea se li st your name, po siti on, and c ompan y. Be sure to include the title and par t number of the manual and tell how you used it. Then tell us your feelings about its strengths and weaknesses and any recommendations for improvements.

xvii

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Conventions Used in This Manual

The following typographical conventions are used in this document:

bold

is used for user inpu t that you t ype just as i t appears ; it is al so used for commands, options and arguments to commands, and names of programs, directories and files.

italic

is used for names of variables to which you assign values. Italic is also used for comments in screen dis plays and examples, and to introduce new terms.

courier

is used for system output (for example, screen displays, reports), examples, and system prompts.

<CR> represents the carriage return or Enter key.

CTRL

xviii

represents the Control key. Execute control character s by pressin g the Ctrl key and the letter simultaneously, for example, Ctrl-d.

A character precedes a data or address parameter to specify the numeric format, as follows:

$ Specifies a hexadecimal character 0x Specifies a hexadecimal number % Specifies a binary number & Specifies a decimal number

An asterisk (∗) following a signal name for si gnals that are level sig nificant denotes that the signal is true or valid when the signal is low. An asterisk (∗) following a signal name for signals that are edge significant denotes that the actions initiated by that signal occur on high to low transition.

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1Hardware Preparation and

Introduction

This chapter provides unpacking instructions, hardware preparation guidelines, and installation instructions for the MVME162P2 VME Embedded Controller.

Getting Started

This section supplies an overview of startup procedures applicable to the MVME162P2. Equipment requirements, directions for unpacking, and ESD precautions that you should take complete the section.

Overview of Installation Procedure

The following table li sts the things you will need to do to use this board and tells where to find the info rmat io n you need to perform each step. Be sure to read this entire chapter, including all Cautions and Warnings, before you begin.

Installation

Table 1-1. Startup Overview

What you need to do... Refer to...

Unpack the hardware. Guidelines for Unpacking on page 1-3. Reconfigure jumpers or swit ches

on the MVME162P 2 board as necessary.

Ensure that IP modules are properly installed on the MVME162P2 boar d.

Install the MVM E162P2 board in a chassis.

Connect a display terminal. Serial Connections on page 1-27.

Preparing the Board on page 1-4.

IP Installation on page 1-23.

MVME162P2 Installation on page 1-23.

1-1

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Hardware Preparation and Installation

Table 1-1. Startup Overview (Continued)

What you need to do... Refer to...

Connect any other equipment you will be using.

Power up the system. Applying Power on page 2-3.

Note that the firmware initializes and tests the board.

Initialize the system clock. Debugger Commands on page 3-6. Examine and/or change

environmental parameters. Program the boar d as needed for

your applications.

Connector Pin Assignments in Chapter 5. For more information on optional de vi ces and equipment , ref er

to the documentation provided with the equipm ent.

Solving Startup Problems on page B-1. Bringing Up the Board on page 2-5.

You may also wish to obtain the 162Bug Firmware User’s Manual, listed in the Relate d Documentation appendix.

Modifying the Environment on page 3-8.

Programmer’s Reference Guide, listed in the Related Documentation appendix.

Equipment Required

The following equipm ent is necessary to complete an MVME162P2 system:

❏ VME system enclosure ❏ System console terminal ❏ Operating system (and / or application software) ❏ Disk drives (and / or other I/O) and controllers

1-2 Computer Group Literature Center Web Site

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Guidelines for Unpacking

Note If the shipping carton is damaged upon receipt, request that the

carrier’s agent be present during the unpa cking and inspe ction of the equipment.

Unpack the equipment from the shipping carton. Refer to the packing list and verify that al l items are present. Save the packi ng mat erial for storing and reshipping of equipment.

Getting Started

Caution

Avoid touching areas of integrated circuitry; static discharge can damage circuits.

ESD Precautions

This section applies to all hardware installations you may perform that involve the MVME162P2 board.

Use ESD

Wrist Strap

Motorola strongly recommends the use of an antistatic wrist strap and a conductive foam pad when you install or upgrade the board. Electronic components can be extremely sensi tive to ESD. After removi ng the board from the chassis or from its protective wrapper, place the board flat on a grounded, static-free surface, component side up. Do not slide the board over any surface.

If no ESD station is available, you can av oid dama ge re sul ti ng fr om ESD by wearing an antistatic wrist strap (available at electronics st ores). Place the strap around your wrist and attach the grounding end (usually a piece of copper foil or an alligator clip) to an electrical ground. An electrical ground can be a piece of metal that literally runs into the ground (such as an unpainted met al pipe) or a metal part of a grounded electric al appliance. An appliance is grou nded if it has a thr ee-pro ng plug and i s plugged i nto a three-prong grounde d outlet . You can not use th e chassi s in which you are installing the MVME162P2 itself as a ground, because the enclosure is unplugged while you work on it.

http://www.motorola.com/computer/literature 1-3

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Hardware Preparation and Installation

Turn the system’s powe r off be fore you perform t hese proc edures. Fail ure

Warning

to turn the power off before opening the enclosure can result in personal injury or damage to the equipment. Hazardous voltage, current, and ene rgy levels are present in the chassis. Hazardous voltages may be present on power switch terminals even when the powe r switc h is off. Neve r opera te the system with the cover removed. Always replace the cover before powering up the system.

Preparing the Board

To produce the desired configuration and ensure proper operation of the MVME162P2, you may need to reconfigure hardware to some extent before installing the board.

Most options on the MVME162P2 are under software control: By setting bits in control registers after installing the module in a system, you can modify its configurat ion. (The MVME162P2 registers are described in Chapter 3 under ENV – Set Environment, and/ or in the MVME1X2P2 VME

Embedded Controller Programmer's Reference Guide as listed under

“Related Documentation” in Appendix E.) Some options, though, are not software-programmable. Such options are

either set by configuration switches or are controlled through physical installation or removal of header jumpers on the base board.

1-4 Computer Group Literature Center Web Site

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MVME162P2 Configuration

Figure 1-1 illustrates the placement of the jumper headers, connectors,

configuration switches, and various other components on the MVME162P2. Manually configurable jumper headers and configuration switches on the MVME162P2 are listed in the following table.

Table 1-2. MVME162P2 Configuration Settings

Function Factory De fault

VME System Controller (J1) on page 1-7

Preparing the Board

2-3

IP Bus Strobe (J11) on page 1-7 SCSI Termination (J12) on page 1-8 IP Bus Clock (J13) on page 1-9 SRAM Backup Power Source (J14) on page 1-10 Flash Write Protection (J16) on page 1-11 EPROM/Flash Configuration (J20) on page 1-11 MC2 DRAM Size (S3) on page 1-15 General-Purpose Readable Switch (S4 Pin 5) on page 1-16 IP DMA Snoop Control (S5 Pins 1/2) on page 1-18 IP Reset Mode (S5 Pin 3) on page 1-19 Flash Write Enable Mode (S5 Pin 4) on page 1-20 MCECC DRAM Size (S6) on page 1-21

No Jumper Jumper On

1-2

1-3, 2-4

Jumper On

5-6, 9-11, 8-10

Off-Off-Off

On-On

On On

On-Off-On

J15 (also J24, if present) is a PLD programming header for lab or factory use. It has no user function.

http://www.motorola.com/computer/literature 1-5

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Hardware Preparation and Installation

MVME162

FAIL

FUSES

ABORT

RESET

ETHERNET PORT

SCSI INTERFACE

CONSOLE 1 2 3 4

RUN

SCON

DS2 DS4

DS3DS1

J15

A1B1C1

S1 S2

R58 R75 R101

J23

J12

R157

J7J5

J13

J11

S6 S5 S3

XU1

XU2

J6J8

L10

P1 P2

A32

B32

C32

L11

A1B1C1

J14

R245

J17

BT1

16 15

J20

J16

A32

B32

C32

2783 0700

Figure 1-1. MVME162P2 Board Layout

1-6 Computer Group Literature Center Web Site

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VME System Controller (J1)

The MVME162P2 board is factory-configured in "automatic" system controller mode with a jumper across J1 pins 2 -3. In this confi guration, the MVME162P2 determines whe ther it is the system cont roller by its positi on on the bus. If the bo ard is located i n the first sl ot from the lef t, it configure s itself as the system controller. When the board is operating as system controller, the

If you want the MVME162P2 to fu nction as syste m controlle r in all cases, move the jumper to pins 1-2. If the MVME162P2 is not to be system controller under any circumstances, remove the jumper from J1.

Note On MVME162P2 boards without the option al VMEbus interface

SCON LED is turned on.

(i.e., with no VMEchip2 ASIC), the jumper may be installed or removed with no effect on n ormal operation.

Preparing the Board

123

System Controller

IP Bus Strobe (J11)

Some IP bus implementations make use of the Strobe∗ signal (pin AA19 on the Petra ASIC) a s an input to the IP mod ules from t he Petra IP 2 sector. Other IP interfaces require that the strobe be disconnected.

With a jumper installed between J11 pin s 1-2, a programmable fr equency source is connecte d to the Strobe ∗ signal on the IP bus (for details, refer to the Petra/IP2 chip programming model in the Programmer’s Reference Guide).

123

Auto System Controller

(factory configuration)

123

Not System Controller

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Hardware Preparation and Installation

If the jumper is removed from J11, the strobe line is available for a sideband type of mes saging between I P modules. The Strobe∗ signal is not connected to any active d evices on th e board, but i t may be connect ed to a pull-up resistor.

J11

IP Strobe disconnected

(Factory configuration)

SCSI Termination (J12)

The MVME162P2 provides terminators for an SCSI bus. The SCSI terminators are enabled/disabled by a jumper on header J12. The SCSI terminators may be config ured as follows.

J12

Onboard SCSI Bus Terminators disabled

J11

IP Strobe connected

J12

Onboard SCSI Bus Terminators enabled

(Factory configuration)

Note If the MVME162P2 is to be located at either end of an SCSI bus,

the SCSI bus terminators must be enabled.

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IP Bus Clock (J13)

J13 selects the speed of the IP bus clock. The IP bus clock speed may be 8MHz or it may be set synchronous to the processor bu s clock (25MHz for the MC68040 and MC68LC040). The default factory configuration has a jumper installed on pins 1-2, denoting an 8MHz clock.

If the jumper is installed on J13 pins 2-3, the IP bus clock speed matches that of the processor bus clock (25MHz), allowing the IP module to pace the MPU. Whether the setting is 8MHz or the processor bus clock speed, all IP ports operate at the same speed.

The setting of the IP32 bit in t he Control/St atus regist ers (Petra IP2 sector ,

Caution

register at offs et $1D, bi t 0) must corresp ond to that of the jumper. Th e bit is cleared (0) for 8MHz, or set (1) t o match the proce ssor bus clo ck speed. If the jumper and the CSR bi t a re not configured the same, the board may not run properly.

Preparing the Board

J13

123

Bus Clock = 8MHz

(Factory configuration)

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Bus Clock = Processor Bus Clock

J13

123

(from MPU Bus Clock)

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Hardware Preparation and Installation

SRAM Backup Power Source (J14)

Header J14 determines the so urce for onboard static RAM backup power . The MVME162P2 is factory-configured to use VMEbus +5V standby voltage as a backup power source for the SRAM (i.e., j umpers are installed across pins 1-3 and 2-4). To select the onboard battery as the backup power source, install the jumpers across pins 3-5 and 4-6.

Note For MVME162P2s without the opt ional VMEbus interface (i.e.,

without the VMEchip2 ASIC), you must select the onboard battery as the backup power source.

Removing all jumpers may temporarily disable the SRAM. Do not remove

all jumpers from J14, except for storage.

Caution

J14

Primary Source Onboard Battery

Secondary Source Onboard Battery

Primary Source VMEbus +5V STBY Secondary Source Onboard Bat ter y

J14

Backup Power Disabled

(For storage only)

Primary Source Onboard Battery

Secondary Source VMEbus +5V STBY

Primary Source VMEbus +5V STBY

Secondary Source VMEbus +5V STBY

J14

(Factory configuration)

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Flash Write Protection (J16)

When the Flash write-enable jumper is installed (factory configuration), Flash memory can be writte n to via the normal software routines. When the jumper is removed, Flash memory is not writable.

Preparing the Board

J16

Flash write-protected

EPROM/Flash Configuration (J20)

The MVME162P2 can be ordered with 2MB of Flash memory and two EPROM sockets ready for the insta llation of the EPROMs, which may be ordered separately. The EPROM locat ions are standard JEDEC 32-pin DIP sockets. The EPROM sockets accommodate four jumper-selectable

densities (128 Kbit x 8; 256 Kbit x 8; 512 Kbit x 8 — the default configuration; 1 Mbit x 8) and a lso per mit di sa bli ng o f th e Fla sh memor y.

Header J20 provides eight jumper locations to configure the EPROM sockets.

J16

Flash write-enabled

(Factory configuration)

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Hardware Preparation and Installation

J20

CONFIGURATION 1: 128K x 8 EPROMs

J20

CONFIGURATION 2: 256K x 8 EPROMs

J20

CONFIGURATION 3: 512K x 8 EPROMs

(FACTORY DEFAULT)

J20

CONFIGURATION 4: 1M x 8 EPROMs

CONFIGURATION 5: 1M x 8 EPROMs

ONBOARD FLASH DISABLED

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Preparing the Board

The next five tabl es show th e address range f or each EPROM socket in all five configurations . GPI3 (S4, switch segment 5) is a control bit in the MC2 General-Purpose Inputs register in the Petra ASIC that determines whether reset code is f et che d f rom Flash memory or from EPROMs. (For particulars on GPI3, refer to the Programmer’s Reference Guide.)

Table 1-3. EPROM/Flash Mapping — 128K x 8 EPROMs

GPI3 Address Range Device Accessed

$FF800000 - $FF81FFFF EPROM A (XU1)

Set to OFF 1

Set to ON 0

$FF820000 - $FF83FFFF EPROM B (XU2) $FFA00000 - $FFBFFFFF Onboard Flash $FF800000 - $FF9FFFFF Onboard Flash $FFA00000 - $FFA1FFFF EPROM A (XU1) $FFA20000 - $FFA3FFFF EPROM B (XU2)

Table 1-4. EPROM/Flash Mapping — 256K x 8 EPROMs

GPI3 Address Range Device Accessed

$FF800000 - $FF83FFFF EPROM A (XU1)

Set to OFF 1

Set to ON 0

$FF840000 - $FF87FFFF EPROM B (XU2) $FFA00000 - $FFBFFFFF Onboard Flash $FF800000 - $FF9FFFFF Onboard Flash $FFA00000 - $FFA3FFFF EPROM A (XU1) $FFA40000 - $FFA7FFFF EPROM B (XU2)

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Hardware Preparation and Installation

Table 1-5. EPROM/Flash Mapping — 512K x 8 EPROMs

GPI3 Address Range Device Accessed

$FF800000 - $FF87FFFF EPROM A (XU1)

Set to OFF 1

Set to ON 0

$FF880000 - $FF8FFFFF EPROM B (XU2) $FFA00000 - $FFBFFFFF Onboard Flash $FF800000 - $FF9FFFFF Onboard Flash $FFA00000 - $FFA7FFFF EPROM A (XU1) $FFA80000 - $FFAFFFFF EPROM B (XU2 )

Table 1-6. EPROM/Flash Mapping — 1M x 8 EPROMs

GPI3 Address Range Device Accessed

$FF800000 - $FF8FFFFF EPROM A (XU1)

Set to OFF 1

Set to ON 0

$FF900000 - $FF9FFFFF EPROM B (XU2) $FFA00000 - $FFBFFFFF Onboard Flash $FF800000 - $FF9FFFFF Onboard Flash $FFA00000 - $FFAFFFFF EPROM A (XU1) $FFB00000 - $FFBFFFFF EPROM B (XU2)

Table 1-7. EPROM/Flash Mapping — 1M x 8 EPROMs, Onboard Flash

Disabled

GPI3 Address Range Device Accessed

$FF800000 - $FF8FFFFF EPROM A (XU1)

Set to OFF 1

Set to ON 0

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$FF900000 - $FF9FFFFF EPROM B (XU2) Not used Onboard Flash Not used Onboard Flash $FF800000 - $FF8FFFFF EPROM A (XU1) $FF900000 - $FF9FFFFF EPROM B (XU2)

Page 33

MC2 DRAM Size (S3)

MVME162P2 boards use SDRAM (Synchronous DR AM) in place of

DRAM. The MVME162P2’s 16/32MB synchronous SDRAM is configurable to emulate either of the following memory models:

❏ 1MB, 4MB, 8MB, or 16MB shared parity-protected DRAM ❏ 4MB, 8MB, 16MB, or 32MB ECC-protected DRAM

The two memory controllers modeled in the Petra ASIC duplicate the functionality of the “parity memory controller” found in MC2 ASICs as well as that of the “single-bit error correcting/double-bit error detecting” memory controller found in MCECC ASICs. Board firmware will initialize the memory controller as appr opriate.

If the Petra ASIC is supporting MVME1X2P4 functionality, firmware will enable the parity (MC2) memory controller model. If the P etra ASIC is supporting MVME162P2 functi onality, firmware will enable either the parity or the MCECC memory controller model, depending on the board configuration. Board configuration is a function of switch settings and resistor population options.

Preparing the Board

S3 comes into play in the MC2 memory controller model. S3 is a foursegment slide switc h whose lower th ree seg ment s estab lish t he si ze of t he parity DRAM (segment 4 is not used.) Refer to the illustration and ta ble below for specifics.

ON OFF

MC2 DRAM SIZE

16MB

(factory configuration)

2734 0004

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Hardware Preparation and Installation

Table 1-8. MC2 DRAM Size Settings

Segment 1

ON ON ON 1MB OFF ON ON 4MB OFF ON OFF 8MB OFF OFF ON Disabled OFF OFF OFF 16MB

Segment 2

Segment 3

MC2 DRAM

Size

Notes As shown in the table, the Petra/MC2 interface supports parity

DRAM emulations up to 16MB. For sizes beyond 16MB, it is necesary to use the MCECC memory model.

For access to the MCECC registers, you must first disabl e the MC2 interface by setting S3 to 001 (Off/Off/On). Further details on selecting the MCECC emulation can be found under MCECC DRAM Size (S6).

If you modify the switch sett ings, you will need to exe cute env;d <CR> so that the f irmware recogniz es the new memory default s.

General-Purpose Readable Switch (S4 Pin 5)

Switch S4 is similar in func tion to the general-purpose readable jumper headers found on earlier MVME162/172 ser ie s boards. S4 provides eight software-readable switch segments. These switches can be read as bits in a register (at address $FFF4202C) in the MC2 General-Purpose Inputs register in the Petra ASIC (refer to the Programmer’s Reference Guide for details). Bit GPI7 is associated with switch segment 1; bit GPI0 is associated with switch segme nt 8. Th e bit values are read as a 0 when the switch is on, and as a 1 when the switch is off. The MVME162P2 is shipped from the factory with S4 set to all 0s (all switches set to

ON), as

diagrammed below.

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Preparing the Board

If the MVME162Bug firmware is installed, four bits are user-definable (i.e., switch segments 1-4). If the MVME162Bug fir mware is not instal led, seven bits are user-definable (i.e., segments 1-4 and segments 6-8).

Note Switch segment 5 (GPI3) is reserved to select either the Flash

memory map (switch set to (switch set to

OFF). GPI3 is not user-definable.

ON) or the EPROM memory map

OFF ON

GPI7

GPI6

GPI5

GPI4

GPI3

GPI2

GPI1

GPI0

Flash Selected

(factory configuration)

162 BUG Installed (default) User Code Installed

USER-DEFINABLE

ON=FLASH; OFF=EPROM

REFER TO DEBUG MANUAL

USER-DEFINABLE

ON=FLASH; OFF=EPROM

REFER TO DEBUG MANUAL

2735 0004

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Hardware Preparation and Installation

IP DMA Snoop Control (S5 Pins 1/2)

Segments 1 and 2 of switch S5 define the state of the snoop control bus when an IP DMA controller is local bus master . As shown in Table 1-9, S5 segment 1 controls Snoop Contr ol signal 1 on the MC68 0x0 processor. S5 segment 2 controls Snoop Control signal 0. Setting a segment to produces a logical 0; setting it to

ON OFF

OFF produces a logical 1.

Snoop inhibited (factory configuration)

2736 0004 (1-3)

S5 varies in function according to the type of processor installed. For MVME162P2 boards with an MC68040 pro cessor, settin g segments 1 and 2 of switch S5 to

OFF or leaving both segments set to ON (the factory

configuration) inhibits snooping. Enabling snooping requires one of two possible

ON/OFF combinations, according to the operation desired.

MVME172P2 boards with an MC68060 processor have different snoop functionality.

The following table lists the snoop operations represented by the settings of S5 with both types of processor. For further details, refer to the

MC68040 or MC68060 microprocessor user’s manuals listed in the Related Documentation appendix.

Table 1-9. Switch S5 Snoop Control Encoding

S5-1

(SC1)

On On Snoop disabled Snoop enabled

On Off Source dirty, sink byte/word/longword Snoop disabled Off On Source dirty, invalidate line Snoop enabled Off Off Snoop disabled (Reserved) Snoop disabled

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S5-2

(SC0)

Requested Snoop Operation MC68040 MC68060

Page 37

IP Reset Mode (S5 Pin 3)

Segment 3 of switch S5 defi nes the IP controller model (IP1 or IP2) to be emulated when the board comes up. With S5 segment 3 set to factory configuration), the board initializes in IP2 mode. With S5 segment 3 set to

In IP2 mode, IP resets occur only in response to a direct software write or to a power-up reset; the IP reset cont rol bit is not self-clearing.

In IP1 mode, the IP reset control bit clears itself after after a 1msec interval. IP resets may occur in response to a software write, a power-up reset, or a local b us reset. For details, r efer to the Programmer’s Reference

Guide listed under “Related Documentation” in Appendix E.

OFF, the board initializes in IP1 mode.

Preparing the Board

ON (the

ON OFF

IP2 reset mode (factory configuration )

2736 0004 (2-3)

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Hardware Preparation and Installation

Flash Write Enable Mode (S5 Pin 4)

Segment 4 of switch S5 define s the Flash memor y controlle r model (MC1 or MC2) to be emulated when enabling or disabling Flash memory accesses on the MVME162P2 board. With S5 segment 4 set to factory configuration), the board initializes in MC2 mode. With S5 segment 4 set to

OFF, the board initializes in MC1 mode.

ON OFF

MC2 Flash write enable mode (factory configuration )

In MC2 mode, writes to Flash memory are enabled or inhibited by a control bit at memory location $FFF42042. With the control bit set to Flash memory is write-enabled.

ON (the

2736 0004 (3-3)

In MC1 mode, writes to Flash memo ry are enabled by a me mory access to any location in the range $FFFCC000-$FFFCFFF. Writes to Flash memory are disabled by a memory access to any location in the range $FFFC8000-$FFFCBFFF. For details, refer to the Programmer’s

Reference Guide listed under “Related Documentation” in Appendix E.

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MCECC DRAM Size (S6)

MVME1X2P2 boards use SDRAM (Synchronous DRAM) in place of

DRAM. The MVME162P2’s 16/32MB synchronous SDRAM is configurable to emulate either of the following memory models:

❏ 1MB, 4MB, 8MB, or 16MB shared parity-protected DRAM ❏ 4MB, 8MB, 16MB, or 32MB ECC-protected DRAM

If the Petra ASIC is supporting MVME1X2P4 functionality, firmware will enable the parity (MC2) memory controller model. If the P etra ASIC is supporting MVME1X2P2 functionality, firmware will enable either the parity or the MCECC memory controller model, depending on the board configuration. Board configuration is a function of switch settings and resistor population options.

Preparing the Board

S6 comes into pla y in th e MCECC me mory contr oller model . S6 is a f oursegment slide switc h whose lower th ree seg ment s estab lish t he si ze of t he ECC DRAM (segment 4 is not used.) Refer to the illustration and table below for specifics.

ON OFF

16MB MCECC DRAM (factory configuration )

2737 0004

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Hardware Preparation and Installation

Table 1-10. MCECC DRAM Size Settings

Segment 1

ON ON ON 4MB ON ON OFF 8MB ON OFF ON 16MB ON OFF OFF 32MB OFF ON ON 64MB

Segment 2

Notes For the MCECC memory model to be enabled, the MC2

emulation must be disabled. You disable the MC2 memory model by setting the MC2 DRAM size select switch (S3) to 110 (Off/Off/On). Refe r to MC2 DRAM Size (S3 ) for further details.

The factory default setting for S6 is 16MB (On/Off/On). If you modify the switch settings, you will need to execute env;d <CR> so that the firmware recognizes the new memory defaults.

Installation Instructions

Segment 3

MCECC

DRAM Size

This section covers:

❏ Installation of IndustryPacks (IPs) on the MVME162P2 ❏ Installation of the MVME162P2 in a VME chassis ❏ System considerations relevant to the installation. Ensure that an

EPROM device is installed as needed. Before installing IndustryPacks, ensure that the serial ports and all header jumpers and configuration switches are set as appropriate.

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IP Installation on the MVME162P2

The MVME162P2 accommodates up to two IndustryPack (IP) modules. Install the IP modules on the MVME162P2 as follows:

1. Each IP module has two 50-pin connectors that plug into two corresponding 50-pin conn ectors on the MVME162P2: J5/J6, J7/ J8. See Figure 2-1 for the MVME162P2 connector locations.

– Orient the IP module(s) so that the tapered connector shells mate

properly. Plug IP_a int o connec tors J 5 and J6; plug IP _b into J7 and J8. If a double-sized IP is used, plug IP_ab into J5, J6, J7, and J8.

2. Two additional 50-pin connectors (J3 and J4) are provided behind the MVME162P2 front panel for external cabling connecti ons to the IP modules. There is a one-to-one correspondence between the signals on the cabling connectors and the signals on the associated IP connectors (i.e., J4 has the same IP_a signals as J5; J3 has the same IP_b signals as J7.

– Connect user-supplied 50-pin cables to J3 and J4 as needed.

(Because of the varying requirements for each different kind of IP, Motorola does not supply these cables.)

– Bring the IP cables out the narrow slots in the MVME162P2

front panel and attach them to the appropriate extern al equipment, depending on the nature of the particular IP(s).

Installation Instructions

MVME162P2 Installation

With EPROM and IP modules installed and headers or switches properly configured, proceed as follows to install the MVME162P2 in a VME chassis:

1. Turn all equipment power OFF and disconnect the power cable from the AC power source.

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Hardware Preparation and Installation

Caution

Warning

Inserting or removing modules while power is applied could result in

damage to module components.

Dangerous voltages, capable of causing death, are present in this equipment. Use extreme caution when handling, testing, and adjusting.

2. Remove the chassis cover as in st ruc te d in t he us er’s manual for th e equipment.

3. Remove the filler panel from the card slot where you are going to install the MVME162P2.

– If you intend to use the MVME162P2 as system controller, it

must occupy the leftmost card slot (slot 1). The system controller must be in slot 1 to correctly initiate the bus-grant daisy-chain and to ensure proper operation of the IACK daisy-chain driver.

– If you do not intend to use the MVME162P2 as system

controller, it can occupy any unused double-height card slot.

4. Slide the MVME162P2 into the selected card slot. Be sure the module is seated properly in the P1 and P2 connectors on the backplane. Do not damage or bend connector pins.

5. Secure the MVME162P2 in the chassis with the screws provided, making good contact wi th the transverse mou nting rails to minimize RF emissions.

6. On the chassis backplane, remove the (IACK) and slot occupied by the MVME162P2.

Note Some VME backplanes (e.g., those used in Motorola "Modular

Chassis" systems) have an autojumpering feature for automatic propagation of the IACK and BG signals. Step 6 does not apply to such backplane designs.

7. Connect the appropriate cable(s) to the panel connectors for the serial ports, SCSI port, and LAN Ethernet port.

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BUS GRANT (BG) jumpers from the header for t he card

INTERRUPT ACKNOWLEDGE

Page 43

– Note that some cables are not provided with the MVME162P2

and must be made or purchased by the user. (Motorola recommends shielded cable for all peripheral connections to minimize radiation.)

8. Connect the peripheral(s) to the cable(s).

9. Install any other required VMEmodules in the system.

10. Replace the chassis cover.

11. Connect the power cable to the AC power source and turn the equipment power ON.

System Considerations

The MVME162P2 draws power from VMEbus backplane connectors P1 and P2. P2 is also used for the upper 16 bits of data in 3 2-bit trans fers, an d for the upper 8 address lines in extended addressing mode. The MVME162P2 may not operate pr operly wi thout it s main boar d connecte d to VMEbus backplane connectors P1 and P2.

Installation Instructions

Whether the MVME162P2 operat es as a VMEbus master or as a VMEbus slave, it is c onfigured for 3 2 bits of address and 32 bits o f data (A32/D32). However, it handles A1 6 or A24 devi ces in the address ran ges indicated in the VMEchip2 chapter of the Pro grammer’s Reference Guide. D8 and/or D16 devices in the syste m must be handled by the MC680x0/ MC68LC0x0 software. For specifics, refer to the memory maps in the Programmer’s Reference Guide.

The MVME162P2 contains shar ed onboard DRAM whose base address is software-selectable. Both the onboard processor and offboard VMEbus devices see this local DRAM at base physical address $00000000, as programmed by the MVME162Bug firmware. This may be changed via software to any other base address. Refer to the Programmer’s Reference Guide for more information.

If the MVME162P2 tries to access offboard resources in a nonexistent location and is not system controller, and if the system does not have a global bus timeout, the MVME16 2P2 waits forever f or the VMEbus cycle to complete. This will cause the system to lock up. There is only one

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Hardware Preparation and Installation

situation in which th e syste m might lack th is gl obal bus timeou t: when t he MVME162P2 is not the system controller and there is no global bus timeout el sewhere in the system.

Multiple MVME162P2s may be installed in a single VME chassis. In general, hardware multiprocessor features are supported.

Note If you are installing multiple MVME162P2s in an MVME945

chassis, do not install an MVME162P2 in slot 12. The height of the IP modules may cause clearance difficulties in that slot position.

Other MPUs on the VMEbus can interrupt, disable, communicate with, and determine the opera tional status of the proc essor(s). One registe r of the GCSR (global control/s tatus regi ster) s et in the VMEchip2 ASIC i ncludes four bits that function as location monitors to allow one MVME162P2 processor to broadcas t a si gnal to any othe r MVME162P2 p rocess ors. Al l eight registers of the GCSR set are acc essib le from any loc al process or as well as from the V MEbus.

The following circuits are protected by solid-state fuses that open during overload conditions and reset themselves once the overload is removed:

❏ IndustryPack +5V (R58) ❏ IndustryPack +12V (R75) ❏ IndustryPack –12V (R101) ❏ Remote reset connector +5V (R90) ❏ SCSI terminator +5V (R157) ❏ LAN AUI +12V (R245)

FUSES LED illuminates to indicate that all fuses are functioning

The correctly. If a solid-state fuse opens, you will need to remove power for several minutes to let the f use reset to a closed or shorted condition.

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Serial Connections

The MVME162P2 uses two Zilog Z85230 serial port controllers to implement the four se rial communications interfaces. Each interface supports:

❏ CTS, DCD, RTS, and DTR control signals ❏ TXD and RXD transmit/receive data signals

Because the serial cl ocks are omitted in the MVME162P2 implementation, serial communications are strictly asynchronous. The Z85230s are interfaced as DTE (data terminal equipment) with EIA-232-D signal levels. The serial ports are routed to four RJ-45 connectors on the front panel. The MVME162P2 hardware supports asynchronous serial baud rates of 110b/s to 38.4Kb/s.

For the pin assignments of the RJ-45 connectors on the front panel, refer to Chapter 5, Pin Assignments. For additional information on the MVME162P2 serial communications interface, refer to the Z85230 Serial

Communications Controller Product Brief listed under Manufacturer’s Documents in Appendix E, Related Documentation. For additional

information on the EIA- 232-D interface, re fer to the EI A-232-D Standard .

Installation Instructions

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Hardware Preparation and Installation

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2Startup and Operation

Introduction

This chapter provide s information on poweri ng up the MVME162P2 VME Embedded Controller after its installation in a system, and describes the functionality of the switches, status indicators, and I/O ports.

For programming infor mation, cons ult the MVME1X2P 2 VME Embedded

Controller Programmer’s Reference Guide.

Front Panel Switches and Indicators

There are two switches (ABORT and RESET) and four LEDs (FAIL, RUN,

FUSES, SCON) located on the MVME162P2 front panel.

Table 2-1. MVME162P2 Front Panel Controls

Control/Indicator Function

Abort Switch (

Reset Switch (

ABORT) Sends an interrupt signal to the process or. The interrupt is normally

used to abort program execution and return control to the deb ugger firmware located in the MVME162P2 Flash memory.

The interrupter connected to the Abort switch is an edge-sensitive circuit, filtered to remove switch bounce.

RESET) Resets all onboard devices. Also drives a SYSRESET∗ signal if the

MVME162P2 is system controller. SYSRESET∗ signals may be generated by the Reset switch, a power-up reset, a watchdog timeout, or by a control bit in the Local Control/Status Reg ister (LCSR) in the VMEchip2 ASIC. For further details, refer to Chapter 4, Functional Description.

2-1

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Startup and Operation

Table 2-1. MVME162P2 Front Panel Controls

Control/Indicator Function

FAIL LED (DS1, red) Board failure. Lights if a fault occurs on the MVME162P2 board. RUN LED (DS2, green) CPU activity. Indicates that one of the local bus masters is

executing a local bus cycle.

FUSES LED (DS3, green) Fuse OK. Indicates that +5Vdc, +12Vdc, and –12Vdc power is

available to the LAN and SCSI interfaces and IP connectors.

SCON LED (DS4, green) System controller. Lights when the VMEchip2 ASIC is functioning

as VMEbus system controller.

Initial Conditions

After you have verified that all necessary hardware preparation has been done, that all connections have been made correctly, and that the installation is compl ete, yo u can power up the sys tem. Apply ing power to the system (a s well as resetting it) trigg ers an initiali zation of the

MVME162P2’s MPU, hardware, and firmware along with the rest of the system.

The Flash-resident fi rmware initializes the devices on the MVME162P2 board in preparation for booting the operating system. The firmware is shipped from the factory with a set of defaul ts appropr iate to the boa rd. In most cases there is no need to modify the firmware configuration before you boot the operating sys tem. For specifics in this regard, refer to Chapter 3 and to the user documentation for the MVME162Bug firmware.

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Applying Power

When you power up ( or when you re set) the sys tem, the firmwar e executes some self- checks and proceeds to the hardware initializa tion. The system startup flows in a predetermined sequence, following the hierarchy inherent in the processor and the MVME162P2 hardware. The figure below charts the flow of the basic initialization sequence that takes p lace during system startup.

STARTUP

INITIALIZATION

POST

Power-up/reset initialization

Initialization of devices on the MVME162P2 module/system

Power-On Self-Test diagnostics

BOOTING

MONITOR

Firmware-configured boot mechanism, if so configured. Default is no boot.

Interactive, command-driven on-line debugger, when terminal connected.

Figure 2-1. MVME162P2/Firmware System Startup

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Pre-Startup Checklist

Before you power up the MVME162P2 sy stem, be sure that the fol lowing conditions exist:

1. Jumpers and/or configuration switches on the MVME162P2 VME Embedded Controller and associated equipment are set as required for your particular application.

2. The MVME162P2 board is installed and cabled up as appropriate for your particular chassis or system, as outlined in Chapter 1.

3. The terminal that you pla n to use as the system console i s connected to the console port (serial port 1) on the MVME162P2 module.

4. The terminal is set up as follows:

– Eight bits per charac ter – One stop bit per character – Parity disabled (no parity protect ion) – Baud rate 9600 baud (the default baud rate of many serial ports

at power-up)

5. Any other device that you wish to use, such as a host computer system and/or peripheral equipment, is cabled to the appropriate connectors.

After you comple te the ch ecks lis ted above, you are ready to power up th e system.

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Bringing up the Board

The MVME162P2 comes with MVME162Bug fi rmware installed. For the firmware to operate properly with the board, you must follow the steps below.

Caution

Inserting or removing boards with power applied may damage board components.

Turn all equipment pow er OFF. Refe r to MVME162P2 Configuration on

page 1-5 and verify that jumpers and switches are configured as necessary

for your particular application.

1. Configuration switch S4 on the M VME162P2 contains eight segments, which all affect the operation of the firmware. They are read as a regist er ( at l ocati on $FFF4 202C) i n the Petr a MC2 sect or. (The MVME1X2P2 VME Embedded Controller Programmer’s Reference Guide has additional information on the Petra MC2 emulation.) The bit values are read as a 0 when the corresponding switch segment is set to

OFF.

The defaul t configuration for S4 has S4 set to a ll 0s (all switch segments set to lower order bits (GPI0 to GPI3, switch segments 5-8). Table 2-2 describes the bit assignments on S4.

ON). The 162Bug firmware reser ves/defines the four

ON, or as a 1 when that segm ent is set to

2. Configure header J1 as appropriate fo r the desired system contr oller functionality (alwa ys system contro ller, neve r system cont roller , or self-regulating) on the MVME162P2.

3. Header J11 enables or disables the IP bus strobe function on the MVME162P2. The factory configuration puts no jumper on J11, disabling the Strobe∗ signal to the Petra /IP2 chip. Verify that this setting is appropriate for your applicat ion.

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Startup and Operation

Bit No. S4 Segmen t Function

GPI0 8 When set to 1 (high) , i ns t ructs th e debugger to use local static RAM for

GPI1 7 When set to 1 (high), instructs the de bugger to use the default

GPI2 6 Reserved for future use. GPI3 5 When set to 0 (low), informs the debugger that it is executing out of

GPI4 4 Open to your application. GPI5 3 Open to your application. GPI6 2 Open to your application. GPI7 1 Open to your application.

Table 2-2. Software-Readable Switches

its work page (variables, stack, vector tables, etc.).

setup/operation parameters in ROM instead of the user se tup/operation parameters in NVRAM. The effect is the same as pressing the

ABORT switches simultaneously.

and This feature can be helpful in the event the user setup is corrupted or

does not meet a sanity check. Refer to the ENV command description for the Flash/ROM defaults.

Flash memory. When set to 1 (high), it informs the debugger that it is executing out of the PROM.

RESET

4. Header J12 enables/disables the SCSI terminators provided on the MVME162P2. If the board i s to be locat ed at eithe r end of an SCSI bus, the SCSI bus terminators must be enabled. The factory configuration has a jumper installed on J12, enabling SCSI termination . Verify that this setting is appropriate for your application.

5. Header J13 configures the IP bus clock for either 8MHz or the processor bus clock speed (25MHz for the MC68040 and MC68LC040). The factory configuration has a jumper installed on J13 pins 1-2, denoting an 8MHz clock. Verify that this setting is appropriate for your application.

6. The jumpers on header J14 establish the SRAM backup power source on the MVME162P2. The factory configuration uses VMEbus +5V standby voltage as the primary and s econdary powe r

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Bringing up the Board

source (the onboard battery is disconnected). Verify that this configuration is appropriate for your application.

7. Header J16 defines the state of Flash memor y write protec tion. The factory configuration has the jumper installed, permitting writes to Flash. Verify that this setting is appropriate for your application.

8. The EPROM/Flash configuration header, J20, should be jumpered between pins 5-6, 9-11, and 8-10. This sets it up for a 512Kbit x 8 EPROM density, the factory default.

9. Verify that the setting s o f c onf iguration switches S3 (MC2 DRAM size), S5 (IP DMA snoop control, IP Reset mode, and Flash Write Enable mode), and S6 (MCECC DRAM size) are appropriate for your memory controller emulation.

10. Refer to the setup procedu re for your particular chassis or system for details concerning the installation of the MVME162P2.

11. Connect the terminal to be used as the 162Bug system console to the default EIA-232-D port at Serial Port 1 on the front panel of the MVME162P2 . Set the terminal up as follows:

– Eight bits per charac ter – One stop bit per character

– Parity disabled (no parity) – Baud rate 9600 baud (the power-up default) After power-up, you can reconf igure the baud rate of the de bug port

by using the 162Bug Port Format (PF) command.

Note Whatever the baud rate, some f orm of hardware handshaking

— either XON/XOFF or via t he RTS/CST line — is desira ble if the system supports it. If you get garbled messages and missing characters, you should check the terminal to make sure that handshaking is enabled.

12. If you have equipment (such as a host computer system and/or a serial printer) to connect to the other EIA-232-D port connectors, connect the appropri ate ca ble s and conf igure t he port (s) as deta iled

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Startup and Operation

by programming the MVME162P2 Z85230 Serial Communicati ons Controllers (SCCs) or by using the 162Bug PF command.

13. Power up the system. 162Bug executes some self-checks and

in Step 11 above. After power-up, you can reconfigure the port(s)

displays the debugger prompt

162-Bug> if the firmware is in Board

mode. However, if the ENV command has placed 162Bug in System

mode, the system performs a self-test and tries to aut oboot. Refe r to the ENV and MENU commands (Table 3-2).

If the confidence test fails, the test is aborted when the first fault is encountered. If possible, an appropriate message is displayed, and control then returns to the menu.

14. Be fore using the MV ME162P2 after the initial installation, set the date and time using the following command line structure:

162-Bug> SET [mmddyyhhmm]|[<+/-CAL>;C]

For example, the followi ng command line starts the real -time clock and sets the date and time to 10:37 a.m., November 7, 2000:

162-Bug> SET 1107001037

The board’s self-tests and operating systems require that the realtime clock be running.

Note If you wish to execute the debugger out of Flash and Flash

does not contain 162 Bug, you may copy the EPROM version of 162Bug to Flash memory. To c opy the EPROM version of 162Bug to Flash memory, firs t verify that a jumper is in pla ce on J16 to enable Fl ash writes, set switch S4 seg ment 5 to and make sure that 162Bug is in Bug mode. Then copy the EPROM contents to Flash memory with the PFLASH command as follows:

162-Bug> PFLASH FF800000:80000 FFA00000

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ON,

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Bringing up the Board

Autoboot

Then remove the jumper from J16 (if you wish to disable subsequent Flash writes ) and slide switch S4 segment 5 back to

OFF. (162Bug always executes f rom memory location FF800000;

the setting of S4 determin es whether that location is in EPROM or Flash.)

Autoboot is a software routine that is contained in the 162Bug Flash/EPROM to provide an independent mechanism for booting an operating system . This autoboot routine automatically scan s for controllers and devices in a specified sequence until a valid bootable device containing a boot media is found or the lis t is exhausted. If a valid bootable device is found, a boot from that device is starte d. The controller scanning sequence goes from the lowest controller Logical Unit Number (LUN) detected to the highe st LUN detected. Controllers , devices, and their LUNs are listed in Appendix D.

At power-up, Autoboot is enabled and (provided that the drive and controller numbers encountered are valid) the following message is displayed upon the system console:

Autoboot in progress... To abort hit <BREAK>

A delay follows this message so that you can abort the Autoboot proces s if you wish. Then the actual I/O begins: the program designated within the volume ID of the media specified is loaded into RAM and control passes to it. If you want to gain control without Autoboot during this time, however, you can press the <BREAK> key or the software

RESET switches.

ABORT or

The Autoboot process is controlled by parameters contained in the ENV command. These parameters allow the selection of specific boot devices and files, and allow programming of the Boot delay. Refer to the ENV command description in Chapter 3 for more details.

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Startup and Operation

Caution

Although you can use streaming tape to autoboot, the same power supply must be connected to the tape drive, the controller, and the MVME162P2. At power-up, the tape controller will position the streaming ta pe to the load point where the volume ID can correctly be read and used.

However, if the MVME162P2 loses power but the controller does not, and the tape happens to be at load point, the necessary command se quences (att ach a nd rewind) cannot be given to the controller and the autoboot will not succeed.

ROMboot

As shipped from the factory, 162Bug occupies an EPROM installed in XU2. This leaves the remaining EPROM socket (XU1) and the Flash memory available for your use.

Note You may wish to contact your Motorola sales office for

assistance in using these resources.

The ROMboot function is configured/enabled via the ENV command (refer to Chapter 3) and is executed at power-up (optionally also at reset).

You can also execute the ROMboot function via the RB command, assuming there is valid code in the memory devi ces (or optionally elsewhere on the board or VMEbus) to support it. If ROMboot code is installed, a user-written routine is given control (if the routine meets the format requi rements).

One use of ROMboot might be resetting the SYSFAIL∗ line on an unintelligent controller module. The NOR B command disab l es the function.

For a user’s ROMboot module to gain control through the ROMboot linkage, four conditions must exist:

❏ Power has just been applied (but the ENV command can change this

to also respond to any reset).

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Bringing up the Board

For complete details on using the ROMboot function, refer to the Debugging Package for Motorola 68K CISC CPUs User’s Manual.

Network Boot

Network Auto Boot is a software routine in the 162Bug Flash/EPROM which provides a mechanism for booting an operating system using a network (local Ethernet interface) as the boot device. The Network Auto Boot routine automa tically scans for contr ollers and device s in a spec ified sequence until a vali d bootable device containing boot media is found or until the list is exhausted. If a valid bootable device is found, a boot from that device is started. The controller scanning sequence goes from the lowest controller Logical Unit Number (LUN) d etected to the highest LUN detected. (Refer to Appendix C for defaul t LUNs.)

❏ Your routine is located within the MVME162P2 Flash/PROM

memory map (but the ENV command can change this to any other portion of the onboard memory, or even offboard VMEbus memory).

❏ The ASCII string "BOOT" is f ound i n the speci fied me mory ra nge. ❏ Your routine pass es a checksum tes t, which ensu res that this routine

was really intended to receive control at powerup.

At power-up, Network Boot is enabled and (provided that the drive and controller numbers encountered are valid) the following message is displayed upon the system console:

Network Boot in progress... To abort hit <BREAK>

After this mess age , t her e is a delay to let you abort th e Au to Boot process if you wish. Then the actual I/O is begun: the program designated within the volume I D of the media specified is lo aded into RAM and control passes to it. If you wa nt t o ga in control without Network Boot during this time, however, you can pr ess the <BREAK> key or use the software

ABORT or RESET switches.

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Startup and Operation

Network Auto Boot is controlled by parameters contained in the NIOT and ENV commands. These parameters allow the selection of specific boot devices, systems, and files, and allow programmin g of the Boot delay. Refer to the ENV command description in Chapter 3 for more details.

Restarting the System

You can initialize the system to a known state in three different ways: Reset, Abort, and Break. Each method has characteristics which make it more suitable than the others in certain situations.

A special debugger function is accessible during resets. This feature instructs the debugger to use the default setup/operation parameters in ROM instead of your own setup/operation parameters in NVRAM. To activate this function, you press the same time. This feature can be helpful in the event that your setup/operation parameters are corrupted or do not meet a sanity check. Refer to the ENV command description in Chapter 3 for the ROM defaults.

Reset

RESET and ABORT switches at the

Powering up the MVME162P2 initiates a system reset. You can also initiate a reset by pressing and quick ly releasing the MVME162P2 front panel, or re set the board in software.

For details on resett ing the MVME162 P2 board thr ough software, r efer to the MVME1X2P2 VME Embedded Controller Programmer’s Reference Guide.

Both “cold” and “warm” r eset modes are a vaila ble. By defaul t, 162Bug is in “cold” mode. During cold resets, a tot al system initiali zation takes place, as if the MVME162P2 had just been powered up. All static variables (including disk device and controller parameters) are restored to their default states. The breakpoint table and offset registers are cleared. The target registers are invalidated. Input and output character queues are cleared. Onboard devices (timer, serial ports, etc.) are reset, and the two serial ports are reconfigured to their default state.

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RESET switch on the

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Restarting the System

Abort

During warm resets, the 162Bug variables a nd tables are p reserved, as well as the target state registers and breakpoints.

Note that when the MVME162P2 comes up in a cold reset, 162Bug runs in Board mode. Using the Environment ( ENV) or MENU commands can make 162Bug run in System mode. Refer to Chapter 3 for specifics.

You will need to reset your system if the processor ever halts, or if the 162Bug environment is ever lost (vector table is destroyed, stack corrupted, etc.).

Aborts are invoked by pressing and releasing the ABORT switch on the MVME162P2 front panel. When you invoke an abort while executing a user program (running target code), a snapshot of the processor state is stored in the target registers. This characteristic makes aborts most appropriate for terminating user programs that are being debugged.

If a program gets caught in a loop, for instance, aborts should be used to regain control. The target PC, register contents, etc., help to pinpoint the malfunction.

Pressing and releasi ng the which may interrupt the processor if enabled. The target registers, reflecting the mac hine state at the time the displayed on the screen. Any breakpoints installed in your code are removed and the breakpoint table remains intact. Control returns to the debugger.

ABORT switch generates a local board condition

ABORT switch was pressed, are

Break

Pressing and releasing the <BREAK> key on the terminal keyboard

generates a "power break”. Breaks do not produce interrupts. The only time that breaks are recognized is while characters are being sent or received by the console port. A break removes any breakpoints in your code and keeps the breakpoint table intact. If the function was entered using SYSCALL, Break also takes a snapshot of the machine state. This machine state is then accessible to you for diagnostic purposes.

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In many cases, you may wish to ter minate a de bugger command before i ts completion (for example , during the display of a large block of memory). Break allows you to terminate the command.

Diagnostic Facilities

The 162Bug package includes a set of hardware diagnostics for testing and troubleshooting the MVME162P2. To use the diagnostics, switch directories to the diagnostic directory.

If you are in the debugger directory, you can switch to the diagnostic directory with the debugger command Switch Directories (SD). The diagnostic prompt for Motorola 68K CISC CPUs User’s Manual for complete descriptions of the diagnostic routines available and instructions on how to invoke them. Note that some diagnostics depend on restart defaults that are set up only in a particular restart mode. The documentation for such diagnostics includes restart information.

162-Diag> appears. Refer to the Debugging Package

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Introduction

The 162Bug firmware i s the layer of software just above the hardware . The firmware supplies the appropriate initialization for devices on the MVME162P2 board upon power-up or reset.

This chapter descri bes the basic s of 162Bug and its a rchitectur e, describes the monitor (interactive c ommand portion of the firmware) in detail, and gives information on using the debugger and special commands. A list of 162Bug commands appears at the end of the chapter.

For complete user information about 162Bug, refer to the Debugging

Package for Motorola 68K CISC CPUs User’s Manual and to the MVME162Bug Diagnostics User’s Manual, listed under Related Documentation.

3162Bug Firmware

162Bug Overview

The firmware for the M68000-based (68K) series of board and system level products has a c ommon ge nealogy, deriving from the Bug firmware currently used on all Motorola M68000-based CPUs. The M68000 firmware version implemented on the MVME162P2 MC68040- or MC68LC040-based embedded contro ll er is known as MVME162Bug, or 162Bug. It includes diagnostics for testing and configuring IndustryPack modules.

162Bug is a powerful evaluation and debugging tool for systems built around MVME162P2 CISC-based micr ocomputers. Facilities are available for loading and executing user programs under com plete operator control for system evaluation. The 162Bug firmware provides a high degree of functionality, user friendliness, portability, and ease of maintenance.

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162Bug Firmware

162Bug includes:

❏ Commands for display and modification of memory

❏ Breakpoint and tracing capabilities ❏ A powerful assembler/dis assembler useful for patching programs ❏ A “self-test at po wer- up” feature which verifies the integrity of t he

system

In addition, the TRAP #15 syst em calls make various 162Bug rou tines that handle I/O, data conversion, and string functions available to user programs.

162Bug consists of three parts:

❏ A command-driven user-interactive software debugger, described

in this chapter . It is re fe rred to her e as “ th e debugg er” or “162Bug ”.

❏ A command-driven diagnostic package for the MVME162P2

hardware, referred to here as “the diagnostics”.

❏ A user interface or debug/diagnostics monitor that accepts

commands from the system console terminal.

When using 162Bug, you operate out of either the debugger directory or the diagnostic directory.

❏ If you are in the deb ugger director y, the debugger prompt 162-Bug>

is displayed and you have all of the debugger commands at your disposal.

❏ If you are in the diagnostic directory, the diagnostic prompt 162-

Diag> is displayed and you have all of the diagnostic commands at

your disposal as well as all of the debugger commands.

Because 162Bug is command-driven, it performs its vari ous operati ons in response to user commands entered at the keyboard. When you enter a command, 162Bug executes the command and the prompt reappears. However, if you enter a command that causes executi on of user target code (for example, GO), then cont rol may or may not return to 162Bug, depending on the outcome of the user program.

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If you have used one or more of Motorol a’s other debugging packages, you will find the CISC 162Bug very similar. Some effort has also been made to improve th e consistency of interactive commands. F or example, delimiters between commands and arguments may be commas or spaces interchangeably.

162Bug Implementation

Physically, 162Bug is contained in a single 27C040 DIP EPROM i nstalled in socket XU2, providing 512KB (128K longwords) of storage. Optionally, the 162Bug firmware can be loaded and executed in a 28F016SA Flash memory chip. The executable code is checksummed at every power-on or reset firmware entry, and the result (which includes a precalculated chec ksum cont ained in the memory de vices) is t ested for a n expected zero. Users are cautioned against modification of the memory devices unless precautions for re-checksumming are taken.

Note MVME162P2 boards ordered without the VMEbus interface

are shipped with Flash m emory blank (the factory uses the VMEbus to program the Flash memory wit h debugger code). To use the 162Bug package, be sure that switch S4 segment 5 is configured to select the EPROM memory map.

162Bug Implementation

If you subsequently wish to run the debugger from Flash memory, you must first initialize Flash memory with the PFLASH command, then reconfigure S4. Refer to Step 14 (Note) under Bringing up the Board on page 2-5 for further details.

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Memory Requirements

The program portion of 162Bug is approximately 512KB of code,

consisting of download, de bugger, and diagno stic packages and contained entirely in Flash memory or EPROM.

The 162Bug firmware ex ecutes from address $FF800000 whether i n Flash or EPROM. If you set switch S4 segment 5 to

ON, the address spaces of the

Flash and EPROM are swapped. For MVME162P-242 series boards (MVME162P2), the factory ship configuration except in the no-VMEbus case has switch S4 segment 5 set to

OFF (162Bug operating out of Flash).

The 162Bug initial stack completely changes 8KB of SRAM memory at addresses $FFE0C000 through $FFE0DFFF, at power-up or reset.

Table 3-1. Memory Offsets with 162Bug

Type of Memory Present Default DRAM

4/8/16/32MB synchr onous DRAM (SDRAM) . Appears as parity memory at 1/8/16MB, ECC at 32MB.

The synchronous DRAM can be modeled as ECC or parity type, as indicated above.

The 162Bug requires 2KB of NVRAM for stor age of board conf iguration, communication, and booting parameters. This storage area begins at $FFFC16F8 and ends at $FFFC1EF7.

162Bug requires a minimum of 6 4KB of contiguous rea d/write memory to operate. The ENV command controls where this block of memory is located. Regardless of where the onboard RAM is located, the first 64KB is used for 162Bug stack and static variable space and the rest is reserved as user space. Whenever the MVME162P2 is reset, the target PC is initialized to the address correspon ding to t he beginni ng of th e user sp ace, and the target stack pointers are initialized to addresses within the user space, with the targ et Interrupt Stack Pointer (ISP) set to the to p of the user space.

Default SRAM

Base Address

$00000000 $FFE00000

Base Address

(onboard SRAM)

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Using 162Bug

162Bug is command-driven; it perfor ms its various o perations i n response to commands that you enter a t the k eyboard. Whe n the appears on the terminal screen, the debugger is ready to accept debugger commands. When the debugger is ready to accept diagnostics commands.

To switch from one mode to the other, enter SD (Switch Directories). To examine the commands in the directory that you are currently in, use the Help command (HE).

What you key in is stored in an internal buff er. Execution begi ns only after the carriage return is entered. This allows you to correct entry errors, if necessary, with the control characters de scribed in the Debugging Package for Motorola 68K CISC CPUs User’s Manual, Chapter 1.

After the debugger executes the command you have entered, the prompt reappears. However, if the command ca uses exe cution of user targ et code (for example GO), then control may or may not return to the debugger, depending on what the user program does.

Using 162Bug

162-Bug> prompt

162-Diag> prompt appears on the screen, the

For example, if a bre akpoint has bee n specified, t hen contro l returns to t he debugger when the br eakpoint is enc ountered during e xecution of the user program. Alternativel y, the user program could return to the debugger by means of the System Call Handler routine RETURN (described in the Debugging Package for Motorola 68K CISC CPUs User’s Manual, Chapter 5, listed in Appendix E, Related Documentation).

A debugger command is made up of the following parts:

❏ The command name, either uppercase or lowercase (e.g., MD or

md).

❏ A port number (if the c ommand is set up to work with more than one

port).

❏ Any required arguments, as specified by the command. ❏ At least one space before the first argument. Precede all other

arguments with either a space or a comma.

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❏ One or more options. Precede an option or a string of options with

a semicolon (;). If no option is entered, the command’s default option conditions are used.

Debugger Commands

The 162Bug debugger commands are summarized in the following table. The commands are described in detail in the Debugging Package for Motorola 68K CISC CPUs User’s Manual.

Table 3-2. Debugger Commands

Command Description

AB Automatic Bootstrap Operating System NOAB No Autobo ot AS One Line Assembler BC Block of Memory Compare BF Block of Memor y Fill BH Bootstrap Operating System and Halt BI Block of Memory Initialize BM Block of Memory Move BO Bootstrap Operating System BR Breakpoint Insert NOBR Breakpoint Delete BS Block of Memory Search BV Block of Memory Verify CM C oncu rren t Mode NOCM No Concurrent Mode CNFG Configure Board Information Block CS Checksum DC Data Conversion DMA DMA Block of Memory Move DS One Line Disassembler DU Dump S-records ECHO Echo String ENV Set Environment to Bug/Operating System

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Table 3-2. Debugger Commands (Continued)

Command Description

GD Go Direct (Ignore Breakpoints) GN Go to Next Instruction GO Go Execute User Program GT Go to Temporary Breakpoint HE Help IOC I/O Control for Disk IOI I/O Inquiry IOP I/O Physical (Direct Disk Access) IOT I/O "Teach" for Configuring Disk Controller IRQM Interrupt Request Mask LO Load S-records from Host MA Macro Define/Display NOMA Macro Delete MAE Macro Edit MAL Enable Macro Expansion Listing NOMAL Disable Macro Expansion Listing MAW Save Macros MAR Load Macros MD Memory Display MENU Menu MM Memory Modify MMD Memory Map Diagnostic MS Memory Set MW Memory Write NAB Automatic Network Boot Operating System NBH Network Boot Operating System and Halt NBO Network Boot Operating System NIOC Network I/O Control NIOP Network I/O Physical NIOT Network I/O Teach NPING Network Ping OF Offset Registers Display/Modify PA Printer Attach

Debugger Commands

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Table 3-2. Debugger Commands (Continued)

Command Description

NOPA Printer Detach PF Port Format NOPF Port Detach PFLASH Program FLASH Memory PS Put RTC Into Power Save Mode for Storage RB ROMboot Enable NORB ROMboot Disable RD Reg ister Display REMOTE Connect the Remote Modem to CSO RESET Cold/Warm Reset RL Read Loop RM Register Modify RS Register Set SD Switch Directories SET Set Time and Date SYM Symbol Table Attach NOSYM Symbol Table Detach SYMS Symbol Table Display/Search T Trace TA Terminal Attach TC Trace on Change of Control Flow TIME Display Time and Date TM Transparent Mode TT Trace to Temporary Breakpoint VE Verify S-Records Against Memory VER Display Revision /Version WL Write Loop

Modifying the Environment

You can use the factory-installed debug monitor, 162Bug, to modify certain parameters contained in the MVME162P2’s Non-Volatile RAM (NVRAM), also known as Battery Backed-Up RAM (BBRAM).

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Modifying the Environment

❏ The Board Information Block in NVRAM contains various entries

that define operating parameters of the board hardware. Use the 162Bug command CNFG to change those para meters.

❏ Use the 162Bug command ENV to change configurable 162Bug

parameters in NVRAM.

The CNFG and ENV commands are both described in the Debugging Package for Motorola 68K CISC CPUs User’s Manual, listed in Appendix E, Related Documentation. Refer to that manual for general information about their use and capabilities.

The following paragraphs present supplementary information on CNFG and ENV that is specific to the 162Bug firmware, along with the parameters that you can modify with the ENV command.

CNFG - Configure Board Information Block

Use this command to display and configure the Board Information Block which resides within th e NVRAM. The board information block contains various elements tha t correspo nd to speci fic opera tional par ameters of the MVME162P2 board. (Note that although no memory mezzanine is present on MVME1X2P2 serie s boar ds, th e on-b oar d memory is mode led as such for backward compatibility.)

The board structure for the MVME162P2 is as follows:

162-Bug>cnfg Board (PWA) Serial Number = " " Board Identifier = " " Artwork (PWA) Identifier = " " MPU Clock Speed = " " Ethernet Address = 0001AF200000 Local SCSI Identifier = " " Parity Memory Mezzanine Artwork (PWA) Identifier = " " Parity Memory Mezzanine (PWA) Serial Number = " " Static Memory Mezzanine Artwork (PWA) Identifier = " " Static Memory Mezzanine (PWA) Serial Number = " " ECC Memory Mezzanine #1 Artwork (PWA) Identifier = " " ECC Memory Mezzanine #1 (PWA) Serial Number = " " ECC Memory Mezzanine #2 Artwork (PWA) Identifier = " "

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ECC Memory Mezzanine #2 (PWA) Serial Number = " " Serial Port 2 Personality Artwork (PWA) Identifier = " " Serial Port 2 Personality Module (PWA) Serial Number = " "

IndustryPack A Board Identifier = " " IndustryPack A (PWA) Serial Number = " " IndustryPack A Artwork (PWA) Identifier = " " IndustryPack B Board Identifier = " " IndustryPack B (PWA) Serial Number = " " IndustryPack B Artwork (PWA) Identifier = " " IndustryPack C Board Identifier = " " IndustryPack C (PWA) Serial Number = " " IndustryPack C Artwork (PWA) Identifier = " " IndustryPack D Board Identifier = " " IndustryPack D (PWA) Serial Number = " " IndustryPack D Artwork (PWA) Identifier = " " 162-Bug>

The parameters that ar e quoted ar e left -just ifi ed chara cter ( ASCII) stri ngs padded with space characters, and the quotes (") are displayed to indicate the size of the string. Parameters that are not quoted are considered data strings, and data strings are right-justified. The data strings are padded with zeros if the length is not met.

The Board Information Block is factory-configured before shipment. There is no need to modify block parameters unless the NVRAM is corrupted.

Refer to the MVME1X2P2 VME Embedded Controller Programmer’s Reference Guide for the actual location and other information about the Board Information Block. Refer to the Debugging Package for Motorola 68K CISC CPUs User's Manual for a CNFG description and examp les .

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ENV - Set Environment

Use the ENV command to view and/ or config ure inte ractivel y all 162 Bug operational parameters that are kept in Non-Volatile RAM (NVRAM).

Refer to the Debugging Package for Motorola 68K CISC CPUs User’s Manual for a description of the use of ENV. Additional information on registers in the MV ME162P2 t hat aff ect th ese p aramet ers appe ars in yo ur

MVME1X2P2 VME Embedded Controller Programmer’s Reference Guide.

Listed and described below are the parameters that you can configure using ENV. The default values shown are those that were in effect when this document was published.

Note In the event of diffi culty with the MVME162P2, you may

wish to use env;d <CR> to restore the factory defaults as a troubleshooting aid (see Appendix B).

ENV - Set Environment

Configuring the 162Bug Parameters

The parameters that can be configured using ENV are:

Table 3-3. ENV Command Parameters

ENV Parameter and Options Default Meaning of Default

Bug or System environment [B/S] B Bug mode Field Service Menu Enable [Y/N] N Do not display field service menu. Remote Start Method Switch

[G/M/B/N]

Probe System for Support e d I/O Controllers [Y/N]

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B Use both methods [Global Control and Status

Register (GCSR) in the VMEchip2, and Multiprocessor Control Register (MPCR) in shared RAM] to pass and execute cross-loaded programs.

Y Accesses will be made to the appropriate

system buses (e.g., VMEbus, local MPU bus) to determine presence of supported co ntrollers.

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Table 3-3. ENV Command Parameters (Continued)

ENV Parameter and Options Default Meaning of Default

Negate VMEbus SYSFAIL∗ Always [Y/N]

Local SCSI Bus Reset on Debugger Startup [Y/N]

Local SCSI Bus Negotiations Type [A/S/N]

Industry Pack Reset on Debugger Startup [Y/N]

Ignore CFGA Block on a Hard Disk Boot [Y/N]

Auto Boot Enable [Y/N] N Auto Boot function is disabled. Auto Boot at power-up only [Y/N] Y Auto Boot is attempted at power-up reset only. Auto Boot Controller LUN 00 Specifies LUN of disk/tape controller module

Auto Boot Device LUN 00 Specifies LUN of disk/tape device currently

Auto Boot Abort Delay 15 The time in seconds that the Auto Boot

Auto Boot Default String [Y(NULL String)/(String)]

ROM Boot Enable [Y/N] N ROMboot function is disabled. ROM Boot at power-up only

[Y/N] ROM Boot Enable search of

VMEbus [Y/N] ROM Boot Abort Delay 00 The time in seconds th at the R OMboot

N Negate VMEbus SYSFAIL∗ after successful

completion or entrance into the bug command monitor.

N No local SCSI bus reset on debugger startup.

A Asynchronous negotiations.

Y IP modules are reset on debugger startup.

Y Configuration Area (CFGA) Block contents

are disregarded at boot (hard disk only).

currently supported by the Bug. Default is $0.

supported by the Bug. Default is $0.

sequence will delay before starting th e boot. The delay gives you the option of stopping the boot by use of the Break key. The time span is 0-255 seconds.

You may specify a string (filename) to pass on to the code being booted. Maximum length is 16 characters. Default is the null string.

Y ROMboot is attempted at power-up only.

N VMEbus address space will not be accessed by

ROMboot.

sequence will delay before starting th e boot. The delay gives you the option of stopping the boot by use of the Break key. The time span is 0-255 seconds.

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ENV - Set Environment

Table 3-3. ENV Command Parameters (Continued)

ENV Parameter and Options Default Meaning of Default

ROM Boot Direct Starting Address

ROM Boot Direct Ending Address FFDFFFFC Last location tested when the Bug searches for

Network Auto Boot Enable [Y/N] N Network Auto Boot function is disabled. Network Auto Boot at power-up

only [Y/N] Network Auto Boot Controller

LUN Network Auto Boot Device LUN 00 Specifies LUN of a disk/tape device currently

Network Auto Boot Abort Delay 5 The time in seconds that the Network Bo ot

Network Autoboot Configuration Parameters Pointer (NVRAM)

Memory Search Starting Address 00000000 Where the Bug begins to search for a work

FF800000 First location tested when the Bug searches for

a ROMboot module.

Y Network Auto Boot is attempted at power-up

reset only.

00 Specifies LUN of a disk/tape controller module

currently supported by the Bug. Default is $0.

supported by the Bug. Default is $0.

sequence will delay before starting th e boot. The delay gives you the option of stopping the boot by use of the Break key. The time span is 0-255 seconds.

00000000 The address where the network interface

configuration parameters are to be saved in NVRAM; these are the parameters necessary to perform an unattended network boot.

page (a 64KB block of memory) to us e for vector table, stack, and variables. This must be a multiple of the debugger work page, modulo $10000 (64KB). In a multi-controller environment, each MVME162P2 board could be set to start its work page at a unique address to allow multiple debuggers to operate simultaneously.

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Table 3-3. ENV Command Parameters (Continued)

ENV Parameter and Options Default Meaning of Default

Memory Search Ending Address 00100000 Top limit of the Bug’s search for a work page.

If no 64KB contiguous block of memory is found in the range specified by Memory Search Starting Address and Memory Search Ending Address parameters, the bug will place its work page in the onb oard stati c RAM on th e MVME162P2. Default Memory Search Ending Address is the calculated size of local memory .

Memory Search Increment Size 00010000 Multi-CPU feature used to offset the location

of the Bug work page. This must be a multiple of the debugger work page, modulo $10000 (64KB). Typically, Memory Search Increment Size is the product of CPU number and size of the Bug work page. Example: first CPU $0 (0 x $10000), second CPU $10000 (1 x $10000), etc.

Memory Search Delay Enable [Y/N]

Memory Search Delay Address FFFFD20F Def a ult address is $FFFFD20F. This is the

Memory Size Enable [Y/N] Y Memory is sized for Self-Test diagnostics. Memory Size Starting Address 00000000 Default Starting Address is $0.

N No delay before the Bug begins it s s earch fo r a

work page.

MVME162P2 GCSR GPCSR0 as accessed through VMEbus A16 space; it assumes the MVME162P2 GRPAD (group address) and BDAD (board address within group) switches are set to "on". This byte-wide value is initialized to $FF by MVME162P2 hardware after a System or Power-On reset. In a multi162P2 environment, where the work pages of several Bugs reside in the memory of the primary (first) MVME162P2, the non-primary CPUs will wait for the data at the Memory Search Delay Address to be set to $00, $01, or $02 (refer to the Memory Requirements section in Chapter 3 for the definition of these values) before attempting to locate their work page in the memory of the primary CPU.

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ENV - Set Environment

Table 3-3. ENV Command Parameters (Continued)

ENV Parameter and Options Default Meaning of Default

Memory Size Ending Address 00100000 Default Ending Address is the calculated size

of local memory.

Note

Memory Configuration Defaults. The default configuration for Dynamic RAM mezzanine boards will position the mezzanine with the largest memory size to start at the address selected with the ENV parameter "Base Address of Dynamic Memory". The Base Address parameter defaults to 0. The smaller sized mezzanine will follow immediately above the larger in the memory map. If mezzanines of the same size and type are present, the first (closest to the board) is mapped to the selected base ad dress. If mezzan ines of the same size but different type (parity and ECC) are present, the parity type will be mapped to the selected base address and the ECC type mezzanine will follow. The SRAM does not default to a location in the memory map that is contiguous with Dynamic RAM.

Base Address of Dynamic Memory

Size of Parity Memory 00100000 The size of the Parity type dynamic RAM

Size of ECC Memory Board 0 00000000 The size of the first ECC type memory

Size of ECC Memory Board 1 00000000 The size of the second ECC type memory

Base Address of Static Memory FFE00000 The beginning address of SRAM. The default

Size of Static Memory 00080000 The size of the SRAM type memory present.

00000000 Beginning address of Dynamic Memory

(Parity and/or ECC type memory). Must be a multiple of the Dynamic Memory board size, starting with 0. Default is $0.

mezzanine, if any. The default is the calculated size of the Dynamic memory mezzanine bo ard.

mezzanine. The default is the calculated size of the memory mezzanine.

is FFE00000 for the onboard 128KB SRAM, or E1000000 for the 2MB SRAM mezzanine. If only 2MB SRAM is present, it defaults to address 00000000.

The default is the calculated size of the onboard SRAM or an SRAM type mezzanine.

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Table 3-3. ENV Command Parameters (Continued)

ENV Parameter and Options Default Meaning of Default

ENV asks the following series of questions to set up the VMEbus interface for the MVME162 series modules. You should have a working knowledge of the VMEchip2 as given in the MVME1X2P2 VME Embedded Controller Programmer’s Reference Guide in order to perform this configuration. Also included in this series are questions for setting ROM and Flash access time.

The slave address decoders are used to allow another VMEbus master to access a local resource of the MVME162P2. There are two slave address decoders set. They are set up as follows:

Slave Enable #1 [Y/N] Y Yes, set up and enable Slave Address Decoder

#1.

Slave Starting Address #1 00000000 Base address of the local resource that is

accessible by the VMEbus. Default is the base of local memory, $0.

Slave Ending Address #1 000FFFFF Ending address of the local resource that is

accessible by the VMEbus. Default is the end of calculated memory.

Slave Address Translation Address #1

Slave Address Translation Select #100000000 This register defines which bits of the address

Slave Control #1 03FF Defines the access restriction for the address

Slave Enable #2 [Y/N] N Do not set up and enable Slave Address

Slave Starting Address #2 00000000 Base address of the local resource that is

Slave Ending Address #2 00000000 Ending address of the local resource that is

Slave Address Translation Address #2

00000000 This register allows the VMEbus address and

the local address to differ. The value in this register is the base address of the local resource that is associated with the starting and ending address selection from the previous questions. Default is 0.

are significant. A logical "1" indicates significant address bits, logical "0" is nonsignificant. Default is 0.

space defined with this slave address decoder. Default is $03FF.

Decoder #2.

accessible by the VMEbus. Default is 0.

00000000 Works the same as Slave Address Translation

Address #1. Default is 0.

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ENV - Set Environment

Table 3-3. ENV Command Parameters (Continued)

ENV Parameter and Options Default Meaning of Default

Slave Address Translation Select #200000000 Works the same as Slave Address Translation

Select #1. Default is 0.

Slave Control #2 0000 Defines the access restriction for the address

space defined with this slave address decoder. Default is $0000.

Master Enable #1 [Y/N] Y Yes, set up and enable Master Address

Decoder #1.

Master Starting Address #1 02000000 Base address of the VMEbus resource that is

accessible from the local bus. Default is the end of calculated local memory (unless memory is less than 16MB; then this register is always set to 01000000).

Master Ending Address #1 EFFFFFFF Ending address of the VMEbus resource that is

accessible from the local bus. Default is the end of calculated memory.

Master Control #1 0D Defines the access characteristics for the

address space defined with this master address decoder. Default is $0D.

Master Enable #2 [Y/N] N Do not set up and enable Master Address

Decoder #2.

Master Starting Address #2 00000000 Base address of the VMEbus resource that is

accessible from the local bus. Default is $00000000.

Master Ending Address #2 00000000 Ending address of the VMEbus resource that is

accessible from the local bus. Default is $00000000.

Master Control #2 00 Defines the access characteristics for the

address space defined with this master address decoder. Default is $00.

Master Enable #3 [Y/N] Depends on

calculated

size of local

RAM

Yes, set up and enable Master Address Decoder #3. This is the default if the board contains less than 16MB of calculated RAM.

Do not set up and enable the Master Address Decoder #3. This is the default for boards containing at least 16MB of calculated RAM.

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Table 3-3. ENV Command Parameters (Continued)

ENV Parameter and Options Default Meaning of Default

Master Starting Address #3 00000000 Base address of the VMEbus resource that is

accessible from the local bus. If enabled, the value is calculated as one more than the calculated size of memory. If not enabled, the default is $00000000.

Master Ending Address #3 00000000 Ending address of the VMEbus resource that is

accessible from the local bus. If enabled, the default is $00FFFFFF, otherwise $00000000.

Master Control #3 00 Defines the access characteristics for the

address space defined with this master address decoder. If enabled, the default is $3D, otherwise $00.

Master Enable #4 [Y/N] N Do not set up and enable Master Address

Decoder #4.

Master Starting Address #4 00000000 Base address of the VMEbus resource that is

accessible from the local bus. Default is $0.

Master Ending Address #4 00000000 Ending address of the VMEbus resource that is

accessible from the local bus. Default is $0.

Master Address Translation Address #4

Master Address Translation Select #400000000 This register defines which bits of the address

Master Control #4 00 Defines the access characteristics for the

Short I/O (VMEbus A16) Enable [Y/N]

Short I/O (VMEbus A16) Control 0 1 Defines the access characteristics for the

00000000 This register allows the VMEbus address and

the local address to differ. The value in this register is the base address of the VMEbus resource that is associated with the starting and ending address selection from the previous questions. Default is 0.

are significant. A logical "1" indicates significant address bits, logical "0" is nonsignificant. Default is 0.

address space defined with this master address decoder. Default is $00.

Y Yes, Enable the Short I/O Address Decoder.

address space defined with the Short I/O address decoder. Default is $01.

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ENV - Set Environment

Table 3-3. ENV Command Parameters (Continued)

ENV Parameter and Options Default Meaning of Default

F-Page (VMEbus A24) Enable [Y/N]

F-Page (VMEbus A24) Control 0 2 Defines the access characteristics for the

ROM Access Time Code 04 Defines the ROM access time. The default is

Flash Access Time Code 03 Defines the Flash access time. The default is

MCC Vector Base VMEC2 Vector Base #1 VMEC2 Vector Base #2

VMEC2 GCSR Group Base Address

VMEC2 GCSR Board Base Address

VMEbus Global Time Out Code 01 Controls VMEbus timeout when the

Local Bus Time Out Code 02 Controls local bus timeout. Default $02 = 256

VMEbus Access Time Out Code 02 Controls the local-bus-to-VMEbus access

Y Yes, Enable the F-Page Address Decoder.

address space defined with the F-Page address decoder. Default is $02.

$04, which sets an access time of five clock cycles of the local bus.

$03, which sets an access time of four clock cycles of the local bus.

05 06 07

D2 Specifies group address ($FFFFXX00) in Short

00 Specifies base address ($FFFFD2XX) in Short

Base interrupt vector for the component specified. Default: MC2chip = $05 , VMEchip2 Vector 1 = $06, VMEchip2 Vector 2 = $07.

I/O for this board. Default = $D2.

I/O for this board. Default = $00.

MVME162P2 is system controller. Default $01 = 64 µs.

µs.

timeout. Default $02 = 32 ms.

Configuring the IndustryPacks

ENV asks the following series of question s to set up IndustryPack modules

(IPs) on MVME162P2s. The MVME1X2P2 VME Embedded Controller Programmer’s Reference

Guide describes the base addresses and the IP register settings. Refer to that manual for information on setting base addresses and register bits.

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IP A Base Address = 00000000? IP B Base Address = 00000000? IP C Base Address = 00000000? IP D Base Address = 00000000?

Base address for mapping IP modules. Only the upper 16 bits are significant.

IP D/C/B/A Memory Size = 00000000?

Define the memory size requirements for the IP modules:

Bits IP Register Address

31-24 D FFFBC00F 23-16 C FFFBC00E 15-08 B FFFBC00D 07-00 A FFFBC00C

IP D/C/B/A General Control = 00000000?

Define the ge neral control requirements for the IP modules:

Bits IP Register Address

31-24 D FFFBC01B 23-16 C FFFBC01A 15-08 B FFFBC019 07-00 A FFFBC018

IP D/C/B/A Interrupt 0 Control = 00000000?

Define the in terrupt contr ol requiremen ts for the IP modules, channel 0:

Bits IP Register Address

31-24 D FFFBC016 23-16 C FFFBC014 15-08 B FFFBC012 07-00 A FFFBC010

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ENV - Set Environment

IP D/C/B/A Interrupt 1 Control = 00000000?

Define the in terrupt contr ol requiremen ts for the IP modules, channel 1:

Bits IP Register Address

31-24 D FFFBC017 23-16 C FFFBC015 15-08 B FFFBC013 07-00 A FFFBC011

If you have specified environmenta l parameter s that will cause an overl ap

Caution

condition, a warning message will appear before the environmental parameters are saved in NVRAM. The important information about each configurable eleme nt in the memo ry map is displayed, sh owing where any overlap condition s exist. This allows you t o quickly identi fy and correct an undesirable configur ation before it is saved.

If an undesirable configura tion alrea dy exist s, you may wis h to res tore the factory defaults with env;d <CR>.

ENV warning example:

WARNING: Memory MAP Overlap Condition Exists

S-Address E-Address Enable Overlap M-Type Memory-MAP-Name $00000000 $FFFFFFFF Yes Yes Master Local Memory (Dynamic RAM) $FFE00000 $FFE7FFFF Yes Yes Master Static RAM $01000000 $EFFFFFFF Yes Yes Master VMEbus Master #1 $00000000 $00000000 No No Master VMEbus Master #2 $00000000 $00FFFFFF Yes Yes Master VMEbus Master #3 $00000000 $00000000 No No Master VMEbus Master #4 $F0000000 $FF7FFFFF Yes Yes Master VMEbus F Pages (A24/A32) $FFFF0000 $FFFFFFFF Yes Yes Master VMEbus Short I/O (A16) $FF800000 $FFBFFFFF Yes Yes Master Flash/PROM $FFF00000 $FFFEFFFF Yes Yes Master Local I/O $00000000 $00000000 No No Master Industry Pack A $00000000 $00000000 No No Master Industry Pack B $00000000 $00000000 No No Master Industry Pack C

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$00000000 $00000000 No No Master Industry Pack D $00000000 $00000000 No No Slave VMEbus Slave #1 $00000000 $00000000 No No Slave VMEbus Slave #2

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4Functional Description

Introduction

This chapter describes the MVME162P2 VME embedded controller on a block diagram level. The Summary of Features provides an overview of the MVME162P2, followed by a d eta il ed description of several blocks of circuitry. Figure 4-1 shows a block diagram of the overall board architecture.

Detailed descriptions of other MVME162P2 blocks, including programmable registe rs in the ASICs and peripheral c hips, can be f ound in the MVME1X2P2 VME Embedded Controller Programmer’s Reference Guide (part number VME1X2P2A/PG). Refer to that manual for a functional description of the MVME162P2 in greater depth.

Summary of Features

The following table summarizes the features of the MVME162P2 VME embedded controller.

Table 4-1. MVME162P2 Features

Feature Description

Microprocessor MVME162P2: 25MHz MC68040 or MC68LC040 processor Form factor 6U VMEbus

16/32MB synchronous DRAM (SDRAM), configurable to emulate

Memory

Flash memory MVME162P2: One Intel 28F016SA 1MB or 2MB 8-bit Flash device EPROM Two 32-pin JEDEC standard PLCC EPROM sockets

Real-time clock

1/4/8/16/MB parity-protect ed DRAM or 4/8/16/32MB ECC-protected DRAM

512KB SRAM with battery backup

8KB NVRAM with RTC, battery backup, and watchdog function (SGSThomson M48T58)

4-1

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Functional Descr iption

Table 4-1. MVME162P2 Features (Continued)

Feature Description

Switches RESET and ABORT switches on front panel Status LEDs

Timers

Interrupts Eight software interrupts (on versions with VMEchip2 ASIC) VME I/O VMEbus P2 connector Serial I/O Four EIA-232-D serial ports via front panel

Ethernet I/O

IP interface SCSI I/O Optional SCSI interface with DMA via front panel

VMEbus interface

Four: Board Fail Fuse Status (

Four 32-bit tick timers and watchdog timer in Petra ASIC Two 32-bit tick timers and watchdog timer in VMEchip 2 ASIC

Optional Ethernet transceiver interface with DMA via DB15 connector on front panel

T wo Indu stryPack interf ace channels with DMA via 3M connecto rs behind front panel

VMEbus system contro ller functions VMEbus-to-local-bus interface (A24/A32, D8/D16/D32/block transfer

[D8/D16/D32/D64]) Local-bus-to-VMEbus interface (A16/A24/A32, D8/D16/D32) VMEbus interrupter VMEbus interrupt handler Global Control/Status Register (GCSR) for interprocesso r communications DMA for fast local memory/VMEbus transfers (A16/A24/A32,

D16/D32/D64)

(FAIL), CPU Activity (RUN), System Controller (SCON),

FUSES)

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Processor and Memory

The MVME162P2 is based on the MC68040/MC68LC040 microprocessor. Th e boar ds ar e buil t wit h 16MB or 32MB sha red DRAM (SDRAM). Various versions of the MVM E162P2 have the SDRAM configured to model 1MB, 4MB, 8MB, or 16MB of parity-protected DRAM or 4MB, 8MB, 16MB, or 32MB of ECC-protected DRAM.

All boards are available with 512KB of SRAM (with battery backup); time-of-day clock (with batte ry bac kup) ; an opt io nal Ether net tra nsc ei ver interface; four serial po rts with EIA-23 2-D interface; six tick time rs with watchdog timer(s); two EPROM sockets; 1MB or 2MB Flash memory (one Flash device); two IndustryPack (IP) interfaces with DMA; optiona l SCSI bus interface with DMA; and an optional VMEbus interface (local bus to VMEbus/VMEbus to local bus, with A16/A24/A32, D8/D16/D32 bus widths and a VMEbus system controller).

I/O Implementation

Peripheral input/output (I/O) signals on the MVME162P2 are routed through the front panel.

Summary of Features

The I/O connections for the four serial ports are implemented with four RJ45 connectors on the fr ont panel. In addition, the panel has cutouts for routing of flat cables to the optional IndustryPack modules.

SCSI devices are interf aced via an industry-standard 68-pin panel connector. The Ethernet interface uses a DB15 connector.

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Functional Descr iption

ASICs

The following ASICs are used on the MVME162P2:

❏ VMEchip2 ASIC (VMEbus interface). Provi des two ti ck timers, a

watchdog timer, programmable map decoders for the master and

slave interfaces, and a VMEbus-to/ from-loca l-bus DMA cont rolle r as well as a VMEbus-to/from-local-bus non-DMA programmed access interface, a VMEbus interrupter, a VMEbus system controller, a VMEbus interrupt handler, and a VMEbus requester.

Processor-to-VMEbus transfers are D8, D16, or D32. VMEchip2 DMA transfers to the VMEbus, however, are D16, D32, D16/BLT, D32/BLT, or D64/MBLT.

❏ Petra ASIC. Combines the functions previously covered by the

MC2 chip, the MCECC chip, and the IP2 chip in a single ASIC.

– MC2 function. Provides a parity DRAM emulation. Also

supplies four tick timers and interfaces to the LAN chip, SCSI chip, serial port chip, BBRAM, EPROM/Flash, and SRAM.

– MCECC function. Provides an ECC DRAM emulation. – IP2 function. Provides control and status information for up to

two single-wide or one double-wide IndustryPack module, which can be plugged into the MVME162P2 main board.

Block Diagram

The block diagram in Figure 4-1 on page 4-5 illustrates the MVME162P2’s overall architecture.

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Block Diagram

A32/24:D64/32/16/08

VMEchip2

Interface

MC68040/MC68LC040orMC68060/MC68LC060

VMEbus

Master/Slave

VMEbus

MPU

A32/D32

IndustryPack

Functions

Chip

IP2

Configuration-Dependent Emulations

4/8/16MB Parity

DRAM Memory

Array

Petra ASIC

Functions

MCECC

Chip

Memory Array

512KB SRAM

w/Battery

Synchronous DRAM

ECC DRAM

16/32MB

32MB

Functions

MC2

Chip

8KB RAM/Clock

Battery Backed

M48T58

2 Channels

I/O

Transceiver

DB15 Front

Controller

82596CA

Ethernet

Connector

Ethernet

Panel

Optional

Coprocessor

53C710

SCSI

EPROM

JEDEC

Socket

32-Pin

Dual Z85230

Controllers

Serial I/O

68-Pin Front

Panel SCSI

Peripherals

Connector

SCSI

Transceivers

EIA-232

Panel

RJ45 Front

4 Serial Ports

2498 0003 (2-2)

1MB/2MB

Flash

Figure 4-1. MVME162P2 Block Diagram

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Functional Descr iption

Functional Description

This section contains a functional description of the major blocks on the MVME162P2.

Data Bus Structure

The local bus on the MVME162P2 is a 32-bit synchronous bus that is based on the MC68040 bus, and which supports burst transfers and snooping. The various local bus mast er and sl ave devices us e the local bu s to communicate. The local bus is arbitrated by pri ority type; the prio rity of the local bus masters from highest to lowest is: 82596CA LAN, 53C710 SCSI, VMEbus, and MPU. As a general rule, any master can access any slave; not all combinat ions pass the common sense test , however. Refer to the MVME1X2P2 VME Embedded Controller Programmer’s Reference Guide and to the u ser’s guide for each device t o determine it s port size, data bus connection, and any restr ictions that appl y when accessing the device.

Microprocessor

MVME162P2 models may be ordered wi th an MC680 40 o r MC68LC040 microprocessor.

The MC68040 has on-chip instruction and dat a caches and a float ing-point processor. (A floating-point coprocessor is the major difference between the MC68040 and MC68LC040.) Refer to the MC68040 use r’s manual for more information.

MC68

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040 Cache

The MVME162P2 local bus masters (VMEchip2, processor, 53C710 SCSI controller, and 82596CA Ethernet controller) have programmable

control of the snoop/ caching mode. Th e IP DMA local bus master’s snoo p control function is govern ed by the settings of switc h S5 segments 1 and 2 (refer to IP DMA Snoop Control (S5 Pins 1/2) on page 1-18). S5 determines the val ue of t he snoop co ntrol signal fo r all IP DMA t ransf ers. This includes the IP DMA whi ch executes when the DMA control r egisters are updated while the IP DMA is operating in command chaining mode.

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The MVME162P2 local bus slaves that support the snoop/caching mode

are defined in the “Lo cal Bus M emory Ma p” sect ion o f the MVME1X2P2

VME Embedded Controller Programmer’s Reference Guide.

Note As outlined in Table 1-9, the snoop capabilit ies of the

MC68xx040 processor d iffer f rom th ose of t he MC68 xx0 60 used on MVME172P2 series boards. Application software must take these differences into account.

No-VMEbus-Interface Option

In support of possible future configurations in which the MVME162P2 might be offered as an e mbedded controller witho ut the VMEbus interface, certain logic in the VMEchip2 has been duplicated in the Petra chip. (For the location of the overlapping logic, refer to Chapter 1 in the

MVME1X2P2 VME Embedded Controller Programmer’s Reference Guide.) As long as th e VMEchi p2 ASI C is pr ese nt , th e r edundant logic is

inhibited in the Petra chip. The enabling signals for these functions are controlled by software an d Petra chip hardware initialization.

Functional Description

Memory Options

The following memory options are available on the different versions of MVME162P2 boards.

DRAM

MVME162P2 boards are built with 16MB or 32MB shared DRAM (SDRAM). Depending on build opt ions chosen at the time of manufacture, various versions of the MVME162P2 have the SDRAM configured to model 1MB, 4MB, 8MB, or 16MB of parity-protected DRAM or 4MB, 8MB, 16MB, or 32MB of ECC-protected DRAM.

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Functional Descr iption

The SDRAM memory array itself is always a single-bit error correcting and multi-bit error detect ion memory, irrespective of which interface model you use to access the SDRAM. When the MC2 (parity) memory controller interface is used to access the SDRAM, single-bit errors are undetectable to users and multi-bit err ors are define d to be parity errors.

SRAM

Firmware will initialize the memory controller to maintain backward compatibility with MVME162LX or -FX products. If the Petra ASIC is supporting MVME162FX functionality, the parity memory controller model will be enabled by default. If the Petra ASIC is supporting MVME162LX functionality, firmware will enable either the parity or the ECC memory controller model, depending on board configuration. (The board configurati on is a function of switch settings and resist or population options.)

User code can modify Petra register settings to operate in either mode. User code can also modify map decoder/switch settings to enable the maximum amount of memory available. The minimum SDRAM configuration is 16MB.

For specifics on SDRAM performance and for detailed programming information, refer to the chapters on MC2 a nd MCECC memory controller emulations in the MVME1X2P2 VME Embedded Controller Programmer’s Reference Guide.

The MVME162P2 implementation includes a 512KB SRAM (static RAM) option. SRAM architecture is single non-interleaved. SRAM performance is described in the sec tion on t he SRAM memory interf ace in the chapter on the MC2 memory controller emulation in the MVME1X2P2 VME Embedded Controller Progr ammer’ s Re ference Guide. An onboard battery supplies VCC to the SRAM when main power is removed. The SRAM arrays are not parity protected.

The battery backup fu nctio n for the onb oar d SRAM is provi ded by a c ointype Panasonic CR2032 de vice (or equivalent) that supports primary and secondary power sources. In the event of a main board power failure, the CR2032 checks power sourc es a nd s wit ches to the source with the higher voltage.

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Functional Description

If the voltage of the backup source is low er than two volts, the CR203 2 blocks the second memory cyc le ; t his allows software to provide an early warning to avoid data loss. Because the second access may be blocked during a power failure, software should do at least two accesses before relying on th e data.

The MVME162P2 provides jumpers (on J14) that allow either power source of the CR2032 to be conne cted to the VMEbus +5V STDBY pin or to one cell of the o nboard battery. For exa mple, the primary syst em backup source may be a battery connected to the VMEbus +5V STDBY pin and the secondary source may be the onboard battery. If the system source should fail or the board is removed from the chassis, the onboard battery takes over.

For proper SRAM operation , some j umper combi na ti on must be ins tall ed

Caution

About the Battery

on the Backup Power Source Select header (refer to the jumper information in Chapt er 1). If one of the j umpers is s et to select t he batter y, a battery must be installed on the MVME162P2. The SRAM may malfunction if inputs to the CR2032 are left unconnected.

The SRAM is controlled by the Petra MC2 sector, and the access time is programmable. Refer to the descri ption of the Petra MC2 emulati on in the

MVME1X2P2 VME Embedded Controller Programmer’s Reference Guide for more detail.

The power source for the onboard SRAM is a coin-type Panasonic CR2032 device (or equivalent) with two lithium cells. The battery is socketed for easy removal and replacement. Small capacitors are provided so that the battery can be quickly replaced without data loss.

The service life of the battery is very dependent on the ambient temperature of the board and the power-on dut y cycle. The lithium bat tery supplied on the MVME162P2 s hould provi de at lea st two yea rs of back up time with the board powered off and with an ambient temperature of 40° C. If the power-on duty cycle is 50% (the boa rd is powered on half of the time), the battery lifetime is four years. At lower ambient temperatures, the backup time is correspondingly longer.

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Functional Descr iption

If you intend to place the board in storage, putting the M48T58 in powersave mode by stopping the oscillator will prolong battery life. This is especially important at high ambient temperatures. To enter power-saving mode, execute the 162Bug PS command (ref er to Debugger Commands in Chapter 3) or its equivalent applicati on-specific command. When restoring the board to service, execute the 162Bug SET command (set

mmddyyhhmm) after installation to restart the oscillator and initialize the clock.

The MVME162P2 is shipped with the battery disconnected (i.e., with VMEbus +5V standby voltage selected as both primary and secondary power source). In order to use the battery as a power source, whether primary or secondary, it is necessary to reconfigure the jumpers on J14 before installi ng the board. Refer to SRAM Backup Power Source (J14) on

page 1-10 for available jumper configurations.

The power leads from the battery are exposed on the solder side of the board. The board sh ould not be plac ed on a con ductive surfac e or store d in a conductive bag unless the battery is removed.

Lithium batteries incorporate inflammable materials such as lithium and

Warning

organic solvents. If lithium batteries are mistreated or handled incorrectly, they may burst open and ignite, possibly resulting in injury and/or fire. When dealing with lith ium batteries, carefully fol low the precautions listed below in order to prevent accidents.

❏ Do not short circuit. ❏ Do not disassemble, deform, or apply excessive pressure. ❏ Do not heat or incinerate. ❏ Do not apply solder directly. ❏ Do not use different models, or new and old batteries together. ❏ Do not charge. ❏ Always check proper polarity.

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Functional Description

To remove the battery from the module, carefully pry the battery from its socket.

Before installing a new battery, ensure that the battery pins are clean. Note the battery pol arit y and press the bat tery into th e soc ket. W hen t he bat tery is in the socket, no soldering is required.

EPROM and Flash Memory

The MVME162P2 implementation include s 1MB or 2MB Flash memor y. Flash memory is a single Intel device (28F016SA on the MVME162P2) organized in a 1MB x 8 or 2Mb x 8 configuration. For information on programming Flash, refer to the Intel documents listed under Manufacturer’s Documents in the Related Documentation appendix.

The Flash write enable signal is con t rolled by:

❏ A bit in the Flash Access Time Control register in the Petra ASIC ❏ A board-level configuratio n jumper (J 16) and conf igura tion swit ch

(S5, segment 4) which determine the statu s of Flash write prot ection on the board

Refer to the MVME1X2P2 VME Embedded Controller Programmer’s Reference Guide for specifics.

The EPROM locations a re standard JEDEC 32-pin PLCC sockets that accommodate three jumper-selectable densities (256 Kb x 8; 512 Kb x 8, the factory default; 1 Mb x 8). The setting of a configuration switch (line GPI3, segment 5 on S4), allows r eset c ode to be fetch ed eit her fr om Flash memory (S4 segment 5 set to

ON).

OFF) or from EPROMs (S4 segment 5 se t to

Note that MVME162P2 models orde red without the VMEbus interface are shipped with Flash memory blank (the factory uses the VMEbus to program the Flash memory with debugger code). To use the debugger firmware, be sure that configuration switch S4 is set for the EPROM memory map. Refer to chapters 1 and 3 for further details.

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Functional Descr iption

Battery-Backed-Up RAM and Clock

An M48T58 RAM and clock chip is used on the MVME162P2. This chip provides a time-of-day clock, oscillator, crystal, power fail detection, memory write protection, 8KB of RAM, and a battery in one 28-pin package. The clock provides seconds, minutes, hours, day, date, month,

and year in BCD 24- hour for mat. Cor recti ons f or 28- , 29- (lea p year ), and 30-day months are made automat ically. No interr upts are gener ated by the clock. Although the M48T58 is an 8-bit devi ce, t he int erfa ce pr ovi ded by the Petra chip supports 8-, 16-, and 32-bit accesses to the M48T58. Refer to the description of the Petra MC2 function in the MVME1X2P2 VME Embedded Controller Progra mmer’s Reference Guid e and to the M48 T58 data sheet for detailed programming guidance and battery life information.

VMEbus Interface and VMEchip2

The VMEch ip2 ASIC provides the local-bus-to-VMEbus interface, the VMEbus-to-local-bus interface, and the DMA controller functions of the local VMEbus. The VMEchip2 also provides the VMEbus system controller functions. Refer to the VMEchip2 description in the

MVME1X2P2 VME Embedded Controller Programmer’s Reference Guide for detailed programming information.

Note that the Abort switch logic in the VMEchip2 is not used. The GPI inputs to the VMEchip2 which are located at $FFF40088 bits 7-0 are not used. Instead, the Abort switch interrupt is integrated into the Petra MC2 sector at locati on $FFF42043. The GPI i nputs ar e integrat ed into t he Petra MC2 sector at location $FFF4202C, bits 23-16.

I/O Interfaces

The MVME162P2 provides onboard I/O for many system applications. The I/O functions include serial ports, IndustryPack (IP) interfaces, and optional interfaces for LAN Ethernet transceivers and SCSI mass storage devices.

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Serial Communications Interface

The MVME162P2 uses two Zilog Z85230 serial port controllers to implement the four se rial communications interfaces. Each interface supports CTS, DCD, RTS, and DTR control signals, as well as the TXD and RXD transmit/receive data signals.

Functional Description

Because the serial cl ocks are omitted in the MVME162P2 implementation, serial communications are strictly asynchronous. The MVME162P2 hardware supports serial baud rates of 110b/s to 38.4Kb/s.

The Z85230 supplies an interrupt vector during interrupt acknowledge cycles. The vector is modified based upon the interrupt source within the Z85230. Interrupt request levels are programmed via the Petra MC2 function (the MC2 emulation can handle up to four Z85230 chips). Refer to the Z85230 data sheet list ed list ed under Manu factu rer’s Documents in the Related Documentation appendix, and to the MC2 programming model in the MVME1X2P2 VME Embedded Controller Programmer’s Referen ce Guide, for information.

The Z85230s are interfaced as DTE (data terminal equipment) with EIA232-D signal levels. The four serial ports are routed to four RJ45 connectors on the MVME162P2 front panel.

IndustryPack (IP) Interfaces

The IP2 function in the Petra ASIC supports four IndustryPack (IP) interfaces; the MVME162P2 board itself accommodates up to two IP modules. The IP modules are accessible from the front panel. The IP2 function as implemented on the MVME162P2 also includes two DMA channels (one for each IP, o r two for a doubl e-wide IP), 32 or 30MHz (32 MHz for MC68LC0x0 or 30 MHz for MC680x0) or 8MHz IndustryPack clock selection (jumper selectable), and one programmable timebase strobe which is connected to the two interfaces. Refer to the IP2 Programming Model in the MVME1X2P2 VME Embedded Controller Programmer's Reference Guide for details of the IP interface. Refer to Chapter 5, Pin Assignments for the pin assignments of the IP connector s.

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Functional Descr iption

Notes MVME162P2 boards do not monitor power supply +5 Vdc

power and assert IP reset if the power falls too low. Instead, IP reset is handled by the ENV command of the 162Bug debugger, as described in Chapter 3. The IP re set is also driven activ e by the power-up reset signal.

Ethernet Interface

The MVME162P2 uses the Int el 82596CA LAN coprocessor to i mplement the optional Ethernet transceiver interface. The 82596CA accesses local RAM using DMA operations to perform its normal function s. Because the 82596CA has small internal buffers and the VMEbus has an undefined latency period, buffer overrun may occur if the DMA is programmed to access the VMEbus. Therefore, the 82596CA should not be programmed to access the VMEbus.

Every MVME162P2 that is built wit h an Ethernet inter face is assi gned an Ethernet Station Address . The add res s is $0001AF2xxxxx, where xxxxx is the unique 5-nibble number assigned to the board (i.e., every MVME162P2 has a different value for xxxxx).

Each board has an Ethernet Station Address displayed on a label attached to the VMEbus P2 connector. In addition, the six bytes including the Ethernet address are stored in the BBRAM configuration area. That is, 0001AF2xxxxx is stored in the BBRAM. The upper fo ur bytes (0001AF2x) are read at $FFFC1F2C; the lower two bytes (xxxx) are read at $FFFC1F30. The MVME162 debugger has t he capability to ret rieve or set the Ethernet address.

Two IP modules plugged into the s ame MVME162P2 boa rd can not use the Str obe∗ signal unless the jumper is removed from J11 . This will disconnect the Stro be∗ outpu t from the Pet ra/IP2 ASIC.

If the data in BBRAM is lost, use the number on the label on backplane connector P2 to restore it.

The Ethernet transceiver interface is located on the MVME162P2 main board, and the industry-standard DB15 connector is located on its front panel.

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Support functions fo r the 82596CA LAN co proc essor are p rovide d by th e Petra MC2 sector. Refer to the 82596CA user’s guide and to the descripti on of the MC2 function in the MVME1X2P2 VME Embedded Controller Programmer’s Reference Guide for detailed programming information.

SCSI Interface

The MVME162P2 may have provision for mass storage subsystems through the industry-standard SCSI bus. These subsystems may include hard and floppy dis k drives, streaming tape drives, and other ma ss storag e devices. The optional SCSI interface is implemented using the NCR 53C710 SCSI I/O controller.

Support functions for the 53C710 are provided by the Petra MC2 sector. Refer to the NCR 53C710 user’s guide and to the description of the MC2 function in the MVME1X2P2 VME Embedded Controller Programmer’s Reference Guide for detailed programming information.

SCSI Termination

It is important that the SCSI bus be properly terminated at both ends.

Functional Description

In the case of the MVME162P2, terminators for the SCSI bus are present on the main board. The SCSI terminators are enabled or disabled by a jumper on header J12. If the SCSI bus e nds at t he MVME162P2, a jumper must be installed at J12.

FUSES LED on the MVME162P2 front panel monito rs +5V power to

The the SCSI bus TERM power line in addition to LAN power and IndustryPack power; the

FUSES LED illuminates when all fuses on the

MVME162P2 are operational. (The fuses are solid- state circuit breakers that reset when th e short which trips them is removed.) Bec ause any device on the SCSI bus can provide power to the TERM power line, the

FUSES

LED does not directly indicate the condition of the fuse.

Local Resources

The MVME162P2 incl udes many r esourc es for the loca l pro cessor. Th ese include tick timers, software-programmable hardware interrupts, a watchdog timer, and a local bus timeout.

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Functional Descr iption

Programmable Tick Timers

Six 32-bit pro grammable t ick timers wi th 1µs resolut ion are available: two in the VMEch ip2 ASIC and four in the Petra/MC2 chip. The tick timers may be programmed to generate peri odic interrupt s to the pro cessor. Refer to the VMEchip2 and Petra/MC2 descriptions in the MVME1X2P2 VME

Watchdog Timer

Embedded Controller Programmer’s Reference Guide for detailed programming information.

A watchdog timer function is provided in both the Petra/MC2 chip and the VMEchip2 ASIC. When the watchdog ti mer is enabled, it must be reset by software wit hin the programmed interva l or it times out. The watchdog timer can be programmed to g enerate a SYS RESET signal, a local reset signal, or a board fail signal if it times out. Refer to the VMEchip2 and Petra/MC2 descriptions in the MVME1X2P2 VME Embedded Controller Programmer’s Reference Guide for detailed programming information.

The watchdog timer logic is duplicated in the VMEchip2 and Petra/MC2 ASICs. Because the watchdog timer function in the VMEchip2 is a superset of that function in the Petra/MC2 chip (system reset function), the timer in the VMEchip2 i s t o be used in all ca ses exc ept fo r vers io ns of th e MVME162P2 which do not include the VMEbus interface (i.e., boards ordered with a "No VMEbus Interface" option).

Software-Programmable Hardware Interrupts

The VMEchip2 ASIC supplies eight software-programmable hardware interrupts. These interrupts allo w software t o create a hardware interrupt. Refer to the VMEchip2 description in the MVME1X2P2 VME Embe dded Controlle r Programmer’s Reference Guide for detailed programming information.

Local Bus Timeout

The MVME162P2 provides timeout fu nctions in the VMEchip2 ASIC and the Petra/MC2 chip for the l ocal bus. When the timer is enab led and a local bus access times out, a Transfer Error Acknowledge (TEA) signal is sent to the local bus master . The timeout value is selectable by software for 8

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µsec, 64 µsec, 256 µsec, or infinity. The local bus timer does not operate during VMEbus bound cycles. VMEbus bound cycles are timed by the VMEbus access timer and the VMEbus global timer. Refer to the VMEchip2 and Petra/MC2 descriptions in the MVME1X2P2 VME Embedded Controller Programmer’s Reference Guide for detailed programming information.

The access timer logic is duplicated in the VMEchip2 and Petra/MC2 ASICs. Because the local bus timer in the VMEchip2 can detect an offboard access and th e Petra/MC2 local bus timer cannot, th e timer in the VMEchip2 ASIC is used in all cases except for versions of the MVME162P2 which do not include the VMEbus interface (i.e., boards ordered with a "No VMEbus Interface" option).

Local Bus Arbiter

The local bus arbiter implements a fixed priority (see Table 4-2).

Table 4-2. Local Bus Arbitration Priority

LAN 0 Highest Industry Pack DMA 1 SCSI 2 ... VMEbus 3 Next Lowest MC680x0/MC68LC0x04Lowest

Functional Description

Device Priority Note

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Functional Descr iption

Connectors

The MVME162P2 has two 96-position DIN connectors: P1 and P2. P1 rows A, B, C, and P2 row B provide the VMEbus interconnection. P2 rows A and C are not used.

Remote Status and Control

The serial ports on the MVME162P2 are connected to four 8-pin RJ45 female connectors ( J17) on the front panel. The two IP modules connect to the MVME162P2 by two pairs of 50- pin connectors. Two addi tional 50pin connectors behind the front panel are for external connections to IP signals. The Ethernet LAN connector (J9) is a 15-pin socket connector mounted on the front panel. The SCSI connector (J23) is a 68-pin socket connector mounted on the front panel.

Pin assignments for the connectors on the MVME162P2 are listed in Chapter 5.

The remote reset connector, J2, is a 20-pin connector located behind the front panel of the MVME162P2. It provides system designers with flexibility in accessing critical indicator and reset functions. When the board is enclosed in a chassis and the front panel is not visible, this connector allows the Reset, Abort, and LED functions to be extended to the control panel of the system, where they are visible. Alternatively, it allows a system designe r to construct a be located remotely fr om the MVME162P2.

RESET/ABORT/ LED panel that can

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Motorola MVME162P2, MVME162P-242E, MVME162P-242L, MVME162P-242, MVME162P-242LE Installation And Use Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

List of Figures

List of T ables

About This Manual

Summary of Changes

Overview of Contents

Comments and Suggestions

Conventions Used in This Manual

Introduction

Getting Started

Overview of Installation Procedure

Equipment Required

Guidelines for Unpacking

ESD Precautions

Preparing the Board

MVME162P2 Configuration

VME System Controller (J1)

IP Bus Strobe (J11)

SCSI Termination (J12)

IP Bus Clock (J13)

SRAM Backup Power Source (J14)

Flash Write Protection (J16)

EPROM/Flash Configuration (J20)

MC2 DRAM Size (S3)

General-Purpose Readable Switch (S4 Pin 5)

IP DMA Snoop Control (S5 Pins 1/2)

IP Reset Mode (S5 Pin 3)

Flash Write Enable Mode (S5 Pin 4)

MCECC DRAM Size (S6)

Installation Instructions

IP Installation on the MVME162P2

MVME162P2 Installation

System Considerations

Serial Connections

2Startup and Operation

Introduction

Front Panel Switches and Indicators

Initial Conditions

Applying Power

Pre-Startup Checklist

Bringing up the Board

Autoboot

ROMboot

Network Boot

Restarting the System

Reset

Abort

Break

Diagnostic Facilities

Introduction

3162Bug Firmware

162Bug Overview

162Bug Implementation

Memory Requirements

Using 162Bug

Debugger Commands

Modifying the Environment

CNFG - Configure Board Information Block

ENV - Set Environment

Configuring the 162Bug Parameters

Configuring the IndustryPacks

4Functional Description

Introduction

Summary of Features

Processor and Memory

I/O Implementation

ASICs

Block Diagram

Functional Descr iption

Data Bus Structure

Microprocessor

No-VMEbus-Interface Option

Memory Options

DRAM

SRAM

About the Battery