Motorola MVME162LX-202, MVME162LX 200 Series, MVME162LX-200, MVME162LX-201, MVME162LX-210 Installation And Use Manual

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MVME162LX 200/300 Series

Embedded Controller

Installation and Use

V162LX2-3A/IH3

Notice

While reasonable efforts have been made to assure the accu r acy of this document, Motorola, Inc. assum es no li abilit y resu lting f rom any omi ssions in t his d ocument, or from the use of the information obtained therein. Motorola reserves the right to revis e this document and to make change s from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes.

No part of this mate rial may be reproduced or copied in any tangible medium, or stored in a retrieval system, or transmitted in any form, or by any means, radio, electronic, mechanical, photocopying, recording or facsimile, or otherwise, without the prior written permission of Motorola, Inc.

It is possible that this publ icat ion may conta in referenc e to, or inf ormation about Motorola products (machines and programs), programming, or services that are not announced in your country. Such references or information must not be construed to mean that Mo torola intends to announce such Motorola produc ts, programming, or services in your country.

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Motorola, Inc.

Computer Group

2900 South Diablo Way

T empe, Arizona 85282

Preface

The MVME162LX 200/300 Series Embedded Contr oller Installation and Use Manual provides a board- level description of the MVME162LX Embedded Controller. It contains a general overview of the product along with a list of hardware features and a detailed functional description.

The information containe d in this manual applies to the MVME162LX-2xx and MVME162LX-3xx (200 and 300 series) models that are curre ntly shipping as of the publication date of this manual.

Motorola All other product s mentioned in this document are trademarks or registered trademarks of

their respecti ve holder s.

and the Motorola symbol are registered trademarks of Motorola, Inc.

Printed in the United State s of America

November 1998

Safety Summary

Safety Depends On You

The following general safety precautions must be observed during all phases of operation, service, and repair of this equipment. Failure to comp ly with the se preca utions or with spec ific wa rnings elsew here in this manua l violate s safety standards of design, manufacture, and intended use of the equipment. Motorola, Inc. assumes no liability for the customer’s failure to comply with these requirements.

The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You, as the user of the product, should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment.

Ground the Instrument.

To minimize shock hazard, the equipment chassis and enclosure must be connected to an electrical ground. The equipment is supplied with a three-conductor AC power cable. The power cable must be plugged into an approved three-contac t el ectrical outlet. The power jack an d m atin g plug of the p owe r c able me et I nternational Ele ctro tech nica l Commission (IEC) safety standards.

Do Not Operate in an Explosive Atmosphere.

Do not operate the equipment in the presence of flammable gases or fumes. Operation of any electrical equipment in such an environment constitutes a definite safety hazard.

Keep Away From Li ve Ci rc ui ts.

Operating personnel must not remove equipment covers. Only Factory Authorized Service Personnel or other qualified maintenance personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment. Do not replace components with power cable connected. Under certain conditions, dangerous voltages may exist even with the power cable removed. To avoid injuries, always disconnect power and discharge circuits before touching them.

Do Not Service or Adjust Alone.

Do not attempt intern al service or adjustment unle ss another person capabl e of rendering first aid and res usci t atio n is present.

Use Caution When Exposing or Handling the CRT.

Breakage of the Cathode-Ray Tube (CRT) causes a high-velocity scattering of glass fragments (implosion). To prevent CRT implosion, avoid rough handling or jarring of the equipment. Handling of the CRT should be done only by qualified maintenance personnel using approved safety mask and gloves.

Do Not Substitute Parts or Modify Equipment.

Because of the danger of introducing additional hazards, do not install substitute parts or perform any unauthorized modification of the equipment. Co ntac t your local Motorola representative for s ervi c e and repair to ensure that sa fet y features are maintained.

Dangerous Procedure Warnings.

Warnings, such as th e exa mple below, p rece de potentially dangerous procedu res th roug hout this manual. Instructions contained in the warnings must be followed. You should also employ all other safety precautions which you deem necessary for the operation of the equipment in your operating environment.

Dangerous voltages, capable of causing death, are present in

WARNING

this equipment. Use extreme caution when handling, testing, and adjusting.

All Motorola printed wiring boards (PWBs) are manufactured by UL-recognized manufacturers, with a fla mmability rating of 94V-0.

This equipment generate s, use s, and can radiate electro-

WARNING

European Notice: Board produc ts with the CE marking comply with the EMC Directive (89/336/EEC ). Marking a system with the CE symbol indicates compliance of that Motorola system to the applicable directives of the European Community. A system with the CE marking meets or exceeds the following technical standards:

magnetic energy. It may cause or be suscept ible to electromagnetic interference (EMI) if not installed and used in a cabinet with adequate EMI protec tion.

EN55022 (CISPR 22): Limits and Methods of Measurement of Radio Interference Characteristics of Information Tech nology Equipment. Tested to Equipment Class B.

EN50082-1, 1992: Electromagnetic Compatibility -- Generic Immunity Standard, Part 1: Residential, Commercial and Light Industry.

IEC801-2: Electromagnetic Compatibility for Industrial Process Measurement and Control Equipment , Par t 2: Electrostatic Discharge Requirements.

IEC801-3: Electromagnetic Compatibility for Industrial Process Measurement and Control Equipment, Part 3: Radiate d Electromagnetic Field Requirements.

IEC801-4: Electromagnetic Compatibility for Industrial Process Measurement and Control Equipment, Part 4: Electrical Fast Transi ent/Burst Requirements.

The product also fulfill s EN60950 (product safety) which is essentially the requirement for the Low Voltage Directive (73/23/EEC).

In accordance with European Community directives, a “Declaration of Conformity” has been made and is on file at Motorola, Inc. - Computer Group, 27 Market Street, Maidenhead, United Kingdom, SL6 8AE.

This board produc t was teste d in a repr esentative syst em to show compl iance with the above mentioned requirements . A proper installation in a CE-marked system will maintain the required EMC/safety performance.

CHAPTER 1 Board Level Hardware Description

Introduction................................................................................................................1-1

Overview............................ ........................................................................... ......1-1

Related Documentation.......................................................................................1-2

Models Available ................................................................................................1-3

Docume n t Requirem en t s...... ... .. .......... .. ... ................... ... .. ................... ... .. ...........1-4

Available Software..............................................................................................1-5

Requir e d Eq u i pm en t .......... ................... ... .. .......... .. ... ................... ... .. ..................1-5

Features...... ................... .. ... ................... ... .. .................... .. .. .......... ... .. .................. 1 -5

Specif i ca ti o n s. ... .. .......... .. ... ................... ... .. .................... .. .. .................... .. ... ........1 - 7

Cooling Requirements........................................................................................1-8

Special Considerations for Elevated-Temperature Operation ............................1-9

Manual Terminology.........................................................................................1-10

Block D ia g ra m .. .. ................... ... .. .................... .. ... ................... .. ... .......... .. .. .............. 1-11

Functional Description.............................................................................................1-12

Switches and LEDs...........................................................................................1-12

ABORT Switch..........................................................................................1-12

RESET Switch...........................................................................................1-12

Front Panel Indicators................................................................................1-13

Data Bus Structure............................................................................................1-13

MC68040 or MC68LC040 CPU.......... .......... ...................................................1-14

MC68XX040 Cache............ ........................ ............ ............ ......................1-14

No VMEbus Interface Option...........................................................................1-14

Memo ry O p ti on s .... .. .......... .. ... ................... ... .. ................... ... .. .................... .. ... .1-15

DRAM Options..........................................................................................1-15

SRAM Options ..........................................................................................1-15

SRAM Batteries.........................................................................................1-17

EPROM and Flash Memory ......................................................................1-18

Battery Backed Up RAM and Clock ................................................................1-18

VMEbus Interface and VMEchip2...................................................................1-19

I/O Inter faces ......... .. .......... .. ... ................... ... .. ................... ... .. .................... .. ... .1-19

Serial Communications Interface ..............................................................1-19

IndustryPack (IP) Interfaces ......................................................................1-20

Ethernet Interface ......................................................................................1-20

SCSI Interface............................................................................................1-21

SCSI Termination......................................................................................1-21

vii

Loca l Re s o u rces ... .. ... ......... ... .. .................... .. ... ................... .. ... ................... ... .. 1- 2 2

Progr ammable Tick Timers. .. ... ......... ... .. .......... .. ... ................... ... .. ............ 1-2 2

Watchdog Timer........................................................................................1-22

Software-Programmable Hardware Interrupts ..........................................1-23

Loca l Bu s Ti m e ou t.......................... .. ... ......... ... .. .................... .. ... ..............1 -2 3

Loca l Bu s A r bi t er ... .......... .. ... ................... ... .. .................... .. .. .................... .. ... .. 1-2 4

Conn ect o r s..... .. .. .................... .. ... ................... ... .. ................... ... .. .................... .. 1- 2 4

Memory Maps.......................................................................................................... 1-25

Loca l Bu s M emory Map........ .. ... ................... ... .. .......... .. ... ................... .. ... .......1-25

Norma l A d d re ss R an g e .. .. ... ................... ... .. .......... .. ... ................... .. ... ....... 1-25

Detailed I/O Memory Maps .... ... .. .................... .. .. .................... .. ... ................... 1- 3 1

IPIC Overall Memory Map ....................................................................... 1-41

BBRAM, TOD Clock Memory Map........................................................1-46

Interrupt Acknowledge Map .....................................................................1-49

VMEbus Memory Map ....................................................................................1-49

VMEbus Accesses to the Local Bus .........................................................1-49

VMEbus Short I/O Memory Map ............................................................. 1-49

Software Initialization .............................................................................................1-50

Multi-MPU Programming Considerations....................................................... 1-50

Local Reset Operation......................................................................................1-50

EMC Compliance.............................................................................................1-51

CHAPTER 2 Hardware Preparation and Installation

Introduction ...............................................................................................................2-1

Unpacking Instructions.............................................................................................. 2-1

Hard w ar e Pr ep a r at io n....... .. ... ......... ... .. .................... .. .. .................... .. ... ................... .. 2- 1

System Controller Select Header (J1)................................................................ 2-2

General-Purpose Readable Jumpers Header (J11)............................................. 2-4

EPROM/Flash Configuration Header (J12) .......................................................2-5

SRAM Backup Power Source Select Headers (J13, J1) .................. ..................2-9

SCSI Terminator Enable Header (J14)............................................................. 2-10

Memory Mezzanine Options............................................................................2-11

Installation Instructions ...........................................................................................2-12

IP Installation on the MVME162LX ................................................................2-12

MVME162LX Module Installation................. ............ ............ ........................ .2-13

System Considerations..................................................................................... 2-14

................................................................................................................................. 2-18

viii

CHAPTER 3 Debugger General Information

Overview....................................................................................................................3-1

Description of 162Bug...............................................................................................3-1

162Bug Implementation.............................................................................................3-2

Installation and Start-up.............................................................................................3-3

Autoboot ....................................................................................................................3-6

ROMboot ...................................................................................................................3-7

Netwo r k Boo t...... .. ... ................... ... .. .................... .. .. .................... .. ... ......... ... .. ...........3-8

Restarting the System ................................................................................................3-9

Reset....................................................................................................................3-9

Abort .................................................................................................................3-10

Break.................................................................................................................3-10

SYSFAIL* Asse r ti o n/ N e ga ti o n ..... .......... .. ... ................... .. ... ................... ... .. ....3- 1 0

MPU Clock Speed Calculation.........................................................................3-11

Memo ry Requirem en t s....... .. .. .................... .. ... ......... ... .. .................... .. ... ..................3-11

T erminal Input/Output Control ................................................................................3-12

Disk I/O S u p po rt . .. .................... .. ... ................... ... .. ................... ... .. .......... .. ... ...........3-13

Blocks Versus Sectors.......................................................................................3-13

Device Probe Function......................................................................................3-14

Disk I/O via 162Bug Commands......................................................................3-14

IOI (Input/Output Inquiry)........................... .............. .. ......................... .. ...3-14

IOP (Physical I/O to Disk).........................................................................3-15

IOT (I/O Teach).........................................................................................3-15

IOC (I/O Co n t r ol) .. .. ... ................... ... .. .......... .. ... ................... ... .. ................ 3 -1 5

BO (Bootstrap Operating System).............................................................3-15

BH (Bootstrap and Halt)............................................................................3-15

Disk I/O via 162Bug System Calls................ ....................................... .. ..........3-15

Default 162Bug Cont roller and Device Parameters..................... ............ ........3-17

Disk I/O Error Codes ........................................................................................3-17

Netwo r k I/O Su p po r t....... ... ......... ... .. .................... .. .. .................... .. ... ................... ... .3-18

Intel 82596 LAN Coproces so r Eth erne t Driver....................... ............. ............3-18

UDP/IP Protocol Modules ................................................................................3-18

RARP/ARP Protocol Modules .........................................................................3-19

BOOTP Protocol Module.................................................................................3-19

TFTP Protocol Module .....................................................................................3-19

Network Boot Control Module .........................................................................3-19

Network I/O Error Codes..................................................................................3-19

Multiprocessor Support......................................... ............... .. ............... .. ............... ..3-2 0

Multiprocessor Control Register (MPCR) Method ..........................................3-20

GCSR Method...................................................................................................3-22

Diagn os ti c F ac il it i es... ... ......... ... .. .................... .. ... ................... .. ... ................... ... .. ....3-23

Manuf ac tu r i ng Test Proce s s ... ... .. .......... .. ... .......... .. .. .................... .. ... ................... ... . 3 - 23

CHAPTER 4 Using The 162Bug Debugger

Entering Debugger Command Lines ......................................................................... 4-1

Synt ac ti c Variables . ... ................... ... .. .......... .. ... ................... .. ... ................... ... .. .. 4-2

Expre s si o n as a P ar a meter.................... .. ... ................... .. ... ................... ... .. .. 4 - 3

Address as a Parameter ............................................................................... 4-4

Address Formats..........................................................................................4-4

Offse t R eg isters........................ .. .. .......... ... .. ................... ... .. .................... .. .. 4- 6

Port Numbers......................................................................................................4-8

Entering and Debugging Programs.............. ......................... .. ......................... .. ........4-9

Calling System Utilities from User Programs........................................................... 4-9

Preserving the Debugger Operating Environment...................................................4-10

162Bug Vector Table and Workspace...............................................................4-10

Hard w ar e Fu n ct io n s .... ... .. ................... ... .. .................... .. ... ................... .. ... ....... 4-11

Exce pt io n Vectors Used by 1 6 2B u g.. ................... ... .. .................... .. ... .............. 4-11

Using 162Bug Target Vector Table...... .. ......................... .. .............. .........4-12

Creating a New Vector Table....................................................................4-13

162Bug Generalized Ex ce ption Handler................... ........................ ........4-15

Floating Point Support.............................................................................................4-17

Single Precision Real........................................................................................4-18

Double Precisio n Rea l........................... ............ ........................ ............ ...........4-18

Extended Precision Real...................................................................................4-18

Packed Decimal Real........................................................................................4-19

Scientific Notation............................................................................................ 4-19

The 162Bug Debugger Command Set........................................... ........... ............ ...4-20

................................................................................................................................. 4-24

APPENDIX A Configure and Environment Commands

Configure Board Information Block......................................................................... A-1

Set Env i ron m e n t to Bu g / O pe r at in g S y ste m ... ................... ... .. .................... .. .. ........... A-3

Configuring the IndustryPacks.............. ............ ........................ ............ ..........A-16

APPENDIX B Disk/Tape Controller Data

Disk/Tape Controller Modules Supported................................................................ B-1

Disk/Tape Controller Default Configurations .......................................................... B-2

IOT Command Parameters for Supported Floppy Types.......... ............................... B-5

APPENDIX C Network Controller Data

Netwo r k Con t r o ll er M od u l es S u pp o rt e d. ... .. .......... .. ... ................... ... .. .................... ..C-1

APPENDIX D Serial Interface Connections

EIA-23 2- D In terconnections........................ ... .. .................... .. .. .......... ... .. .................D-1

APPENDIX E Network Port Connections

Ethernet Interconnections .........................................................................................E-1

APPENDIX F SCSI Bus Connections

SCSI Interconnect ions........ .............. ............. .............. .. ......................... .. ................ F-1

APPENDIX G Mezzanine Board Connectors

Mezzanine Connector J15 Signals............................................................................G-1

Mezzanine Connector J16 Signals............................................................................G-6

Mezzanine Board Dimensions ................................................................................G-11

APPENDIX H Troubleshooting CPU Boards

Solvi n g St ar tu p Pr ob l ems ...... ... .......... .. .. .................... .. ... ................... ... .. .................H-1

APPENDIX I Input/Output Connections

IndustryPack Logic Interface Interconnections ......................................................... I-1

IndustryPack I/O Interconnections ............................................................................ I-4

Remote Reset/LED Interconnection ..........................................................................I-5

VME Bus Interconnection ......................................................................................... I-6

Connector P1 Interconnect Signals.....................................................................I-6

Connector P2 Interconnect Signals...................................................................I-10

APPENDIX J Related Documentation

Motorola Documentation........................................................................................... J-1

Non-Mo t o ro l a D o cu mentatio n.. .. .................... .. ... ................... .. ... ................... ... .. ...... J-2

Support Information...................................................................................................J-3

FIGURES

Figure 1-1. MVME162LX Block Diagram ............................................................. 1-11

Figure 2-1. MVME162LX Switch, Header, Connector, Fuse, and LED Locations..2-3

Figure 2-2. DB25-DTE-to-RJ45 Adapter................................................................ 2-16

Figure 2-3. DB25-DCE-to-RJ45 Adapter................................................................2-17

Figure 2-4. Typical RJ45 Serial Cable..................................................................... 2-17

Figure D-1. Serial Interface Connections................................................................. D-2

Figure D-2. DB25-DTE-to-RJ45 Adapter................................................................ D-3

Figure D-3. DB25-DCE-to-RJ45 Adapter................................................................ D-3

Figure D-4. Typical RJ45 Serial Cable ....................................................................D-4

Figure G-1. Mezzanine Board Dimensions (Parity DRAM)..................................G-11

Figure G-2. Mezzanine Boar d Dimensions (SRAM and ECC DRAM)......... ........G-12

TABLES

Table 1-1. MVME162LX Embedded Controller Models ......................................... 1-3

Table 1-2. MVME162LX Specifications...................................................................1-7

Table 1-3. Local Bus Arbitration Priority................................................................1-24

Table 1-4. Local Bus Memory Map......................................................................... 1-26

Table 1-5. Local I/O Devices Memory Map ........................................................... 1-28

Table 1-6. VMEchip2 Memory Map - LCSR Summary (Sheet 1 of 2) ............ ......1-32

Table 1-7. MCchip Register Map ............................................................................ 1-36

Table 1-8. MCECC Internal Register Memory Map .............................................. 1-37

Table 1-9. Z85230 SCC Register Addresses............................................ ...............1-39

Table 1-10. 82596CA Ethernet LAN Memory Map................................... ............ .1-39

Table 1-11. 53C710 SCSI Memory Map.......... ............ ...........................................1-40

Table 1-12. IPIC Overall Memory Map...................................................................1-41

Table 1-13. IPIC Memory Map—Control and Status Registers .............................1-42

Table 1-14. MK48T08 BBRAM/TOD Clock Memory Map ...................................1-43

Table 1-15. BBRAM Configuration Area Memory Map .............. ................. ........1-44

Table 1-16. TOD Clock Memory Map .................................................................... 1-45

Table 2-1. EPROM/Flash Mapping - 128K x 8 EPROMs ........................................2-6

Table 2-2. EPROM/Flash Mapping - 256K x 8 EPROMs ........................................2-6

Table 2-3. EPROM/Flash Mapping - 512K x 8 EPROMs ........................................2-7

Table 2-4. EPROM/Flash Mapping - 1M x 8 EPROMs............................................2-7

Table 2-5. EPROM/Flash Mapping - 1M x 8 EPROMs, On-Board Flash Dis abled.2-8

Table 4-1. Debugger Address Parameter Formats.....................................................4-5

Table 4-2. Exception Vectors Used by 162Bug....................................................... 4-11

xii

T able 4-3. Debugger Commands ............................................................................4-20

Table A-1. ENV Command Parameters ..................................................................A-4

Table D-1. Connector J17 Interconnect Signals ........................................ ........... ...D-1

Table E-1. Ethernet Connector J9 Interconnec t Si gnals ...... ............ .......................E-1

Table F-1. SCSI Connector J 10 Interconnect Signals ............. ............................... F-1

Table G-1. Mezzanine Connector J15 Interconnect Signals ...................................G-1

Table G-2. Mezzanine Connector J16 Interconnect Signals ...................................G-6

Table H-1. Troubleshooting MVME162LX Boards ...............................................H-1

Table I-1. Industr yP ac k Interconnect Signals ...................... ....................................I-1

Table I-2. Remote Reset/LED interconnect Signals .................................................. I-5

Table I-3. Connector P 1 Interconnect Signals .............. .............. .. ......................... ..I-6

Table I-4. Connector P 2 Interconnect Signals...................................................... ... I-10

xiii

xiv

1Board Level Hardware

Introduction

This chapter provides a board-level hardware description of the MVME162LX Embedded Controller. It co ntains a general overview of the product along with a list of hardware features and a detailed functional

description. The controller’s front panel switches and indicators are included in th e functional description. Additionally, a section on memory maps is provided at the end of this chapter to familiarize you with the controller’s memory ad dresses and the corresponding devices accesse d.

All of the controller’s pr ogrammable registers that reside in ASICs are covered in the MVME162LX Embedded Controller Programmer’s Reference Guide.

Overview

The MVME162LX Embedded Contr oller is ba sed on the MC68040 or the MC68LC040 microprocessor. The MC68040 microprocessor has a floating-point ( math) coprocessor and the MC68LC040 does not.

Various versions of the contr oller contain the following:

Description

❏ 1 or 4 MB of parity-protected DRAM ❏ 4, 8, 16, or 32 MB of ECC-protected DRAM ❏ 128 KB of SRAM (with battery backup) ❏ Time of day clock (with battery backup) ❏ An optional LAN Ethernet transce ive r interface ❏ Four serial ports with an EIA-232- D interface ❏ Six tick timers with watchdog timer(s) ❏ Four EPROM sockets ❏ 1 MB flash memory (one flash device)

❏ Two IndustryPack (IP) inte rfa ces ❏ An optional SCSI bus interface with DMA ❏ An optional VMEbus interface (local bus to VMEbus/VMEbus to

local bus, with A16/A24/A32, D8/D16/D32 bus widths and a VMEbus system controller)

1-1

Board Level Hardware Descript ion

Input/Output (I/O) signals are routed through industry standar d connectors

on the controller’s front panel. This includes the I/O for the serial ports, which is provided by four RJ45 connectors.

The VME bus int er face is provided by an ASIC called the VMEchip2. It contains two tick timers, a watchdog timer, programmable map decoders for the master and slave interfaces, a VMEbus to/from local bus DMA controller, a VMEbus to/from local bus non-DMA programmed access interface, a VMEbus interrupter, a VMEbus sys tem controlle r, a VMEbu s interrupt handler, and a VMEbus requester.

Processor-to-VMEbus tra nsfers can be D8, D16, or D32. VMEchip2 DMA tran sfers to the VM Ebus, however, can be D16, D32, D16/BLT, D32/BLT, or D64/MBLT.

The MCchip ASIC provides four t ick timers, the interface to the LAN chip, SCSI chip, serial port chip, BBRAM, EPROM/Flash, DRAM and SRAM.

The MCECC memory controller ASIC provides the programmable interface for the ECC-protected 16 MB DRAM mezzanine board.

The IndustryPack Interface Controller (IPIC) ASIC provides control and status information for up to two single size IndustryPacks (IPs) or one double size IP that can be plugged into the controller’s PCB.

Models Available

As of the publication date of this manual, the MVME162LX Embedded Controller is avail able in a number of models shown in Table 1-1.

Table 1-1. MVME162LX Embedded Controller Models

Model Description

-200 MC6 8 L C040 25 MHz mic r o processor, 1 MB DRAM, 128 KB SRAM,1 MB Flash memory, 2 IndustryPack sites

-201 MC6 8 L C040 25 MHz mic r o processor, 1 MB DRAM, 128 KB SRAM,1 MB Flash memory, 2 IndustryPack sites, 4 serial ports

-202 MC6 8 L C040 25 MHz mic r o processor, 1 MB DRAM, 128 KB SRAM,1 MB Flash memory, 2 IndustryPack sites, 4 serial ports

-210 MC6 8 L C040 25 MHz mic r o processor, 4 MB DRAM, 1 28 KB S RAM, 1 MB Flash memory, 2 IndustryP ac k sites, 4 serial ports

-211 MC68 L C 040 25 MHz micr o p r ocessor, 4 MB DRA M , 1 28 KB S R AM, 1 MB Flash memory, 2 IndustryP ac k sites, 4 serial ports, SCSI

-212 MC6 8 L C040 25 MHz mic r o processor, 4 MB DRAM, 1 28 KB S RAM, 1 MB Flash memory, 2 IndustryP ac k sites, 4 serial ports, Ethernet

Introduction

-213 MC6 8 L C040 25 MHz mic r o processor, 4 MB DRAM, 1 28 KB S RAM, 1 MB Flash memory, 2 IndustryP ac k sites, 4 serial ports, SCSI & Ethernet

-216 MC6 8 L C040 25 MHz mic r o processor, 4 MB DRAM, 1 28 KB S RAM, 1 MB Flash memory, 2 IndustryP ac k sites, Ethernet, No VME

-220 MC68040 25 MHz microprocessor , 4 MB DRAM, 128 KB SRAM, 1 MB Flash memory, 2 IndustryP ac k sites, 4 serial ports

-222 MC68040 25 MHz microprocessor , 4 MB DRAM, 128 KB SRAM, 1 MB Flash memory, 2 IndustryP ac k sites, 4 serial ports, Ethernet

-223 MC68040 25 MHz microprocessor , 4 MB DRAM, 128 KB SRAM, 1 MB Flash memory, 2 IndustryP ac k sites, 4 serial ports, SCSI & Ethernet

-233 MC6 8 L C040 25 MHz mic r o processor, 4 MB EC C DRAM , 128 KB SRAM, 1 MB Flash memory, 2 Indust ryPac k sit es, 4 ser ial por ts, SCSI & Ethernet

http://www.mcg.mot.com/literature 1-3

Board Level Hardware Descript ion

Table 1-1. MVME162LX Embedded Controller Models (Continued)

Model Description

-243 MC68040 25 MHz mic r oprocessor, 4 MB ECC DRAM, 128 KB SRAM, 1 M B Flash memory, 2 IndustryPack sites, 4 serial ports, SCSI & Ethernet

-253 MC68LC040 25 MHz microprocess or, 16 MB ECC DRAM, 128 KB SRAM, 1 MB Flash memory, 2 IndustryPack sites, 4 seria l ports , SCSI & Ethernet

-262 MC68040 25 MHz microprocessor, 16 MB ECC DRAM, 128 KB SRAM, 1 MB Flash memory, 2 IndustryPack sites, 4 seria l ports , Ethernet

-263 MC68040 25 MHz microprocessor, 16 MB ECC DRAM, 128 KB SRAM, 1 MB Flash memory, 2 IndustryPack sites, 4 seria l ports , SCSI & Ethernet

-322 MC68LC040 25 MHz microprocess or, 8 MB ECC DRAM, 128 KB SRAM, 1 MB Flash memory, 2 IndustryPack sites, 4 seria l ports , Ethernet

-323 MC68LC040 25 MHz microprocess or, 8 MB ECC DRAM, 128 KB SRAM, 1 MB Flash memory, 2 IndustryPack sites, 4 seria l ports , SCSI & Ethernet

-333 MC68040 25 MHz mic r oprocessor, 8 MB ECC DRAM, 128 KB SRAM, 1 MB Flash memory, 4 seria l ports , SCSI & Ethernet

-353 MC68040 25 MHz microprocessor, 32 MB ECC DRAM, 128 KB SRAM, 1 MB Flash memory, 4IndustryPack sites, 4 serial ports, SCSI & Ethernet

Document Requirements

The controller is designed to conform to the requirements of the following documents:

❏

VMEbus S pecification (IEEE 1014-87)

❏

EIA-232-D Serial Interface Specification, EIA

❏

SCSI Specification, ANSI

❏

IndustryPack S pecification, GreenSpring

1-4 Computer Group Literature Center Web Site

Available Software

Ava il ab le s of tware for t he co n tro l ler in cludes th e on - bo ar d de bu g ge r/m o n it or firmware, VMEexec d river packages for v ar ious IndustryPack modules, and numerous third-party applications for MC680 local Motoro la sales office or distribution for more information.

Required Equipment

he following equipment is required to complete an M VME162LX system:

❏

System console terminal

❏

Disk drives and controllers

❏

Operating syste m

As mention ed earlier, transition modules are unnecessary, as the controller incorporates industry-standard SCSI, Ethernet, and RJ45 serial connectors on its front panel.

Features

Introduction

0-based systems. Contact your

General featur es of the MVME162LX Embedded C ontroller are sho wn in the following table:

Feature Description Models

Microprocessor MC68LC040 See Table 1-1

MC68040 See Table 1-1

Memory 1 or 4 MB of parity-protected DRAM See Table 1-1

4, 8, 16, or 32 MB of ECC-protected DRAM See Table 1-1 128 KB of SRAM (with battery ba ckup) All models 1 MB of Flash memory All models

Real-time clock 8KB NVRAM with RTC and battery ba ckup

(SGS-Thomson M48T18) Switches Status LEDs Four: Tick timers Four programmable 32-bit timers All models

http://www.mcg.mot.com/literature 1-5

RESET and ABORT All models

FAIL, RUN, SCON, and FUSES All models

All models

Board Level Hardware Descript ion

Feature Description Models

Watchdog timer Provided in MCchip ASIC (VMEchip2) All models Serial I/O EIA-232-D DTE serial interface with four

serial ports (Zilog Z85230 controller chips)

SCSI I/O Optional Small Computer Systems Interface

(SCSI) bus interface with 32-bit local bus burst Direct Memory Access (DMA) (NCR 53C710 controller)

Ethern et I/O Optional LAN Ethernet transceiver interface

with 32-bit local bus DMA (Intel 82596CA controller)

IndustryPack Interfaces

VMEbus interface (Optional)

NOTE: This option is a

factory install ed and cannot be added in the field.

2 or 4 IndustryPack Interface sites See Table 1-1

VMEbus system controlle r All models VMEbus requester VMEbus interrupter VMEbus interrupt handler Eight software interrupts Programmable map decoders for the master

and slave interfaces VMEbus to local bus interface (A24/A32,

D8/D16/D32 (D8/D16/D32/D64 BLT) (BLT = Block Transfer)

See Table 1- 1

Local-bus-to-VMEbus in terface (A16/A24/A32, D8/D16/D32)

Two 32- bit programma ble Tick Timers a nd a programmable Watchdog Timer (in the VMEchip2 ASIC) for periodic interrupts

Global CSR for interprocessor communications

DMA for fast local memory - VMEbus transfers (A16/A24/A32, D16/D32 [D16/D32/D64 BLT])

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Specifications

Table 1-2 lists the specifications for an MVME162LX Embedded Controller without IndustryPacks.

Characteristics Specifications

Introduction

Table 1-2. MVME162LX Specifications

Power requirements (with EPROMs; without IPs )

Oper at in g temperatur e 0° to 70° C ex i t ai r wi th for c ed air co o li n g

Storage temperature -40° to +85° C

Relative humidit y 5% to 90% (noncondensing)

Physical dimensions PC board with mezzanine

module only

Height Depth Thickness

PC bo a r d with co nn ector s and front panel

Height Depth Thickness

+5Vdc (± 5%), 3.5 A typical, 4.5 A maximum +12 Vdc (± 5%), 100 mA maximum

-12 Vdc (± 5%), 100 mA maximum

(see NOTE)

Double-high VMEboard

9.20 inches (233 mm)

6.30 inches (160 mm)

0.66 inch (17 mm)

10.3 inches (262 mm)

7.4 inches (188 mm)

0.80 inch (20 mm)

Note: Refer to the sections on the followi ng pag es for information

on Cooling Requirements and Special Requirements for

Elevated-Temperature Operation.

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Board Level Hardware Descript ion

Cooling Requirements

The Motorola MVME162LX Embe dded Contr oller is de sign ed and te sted

to operate reliably with an incoming air temperature range of 0° to 55° C (32° to 131° F). This is accomplished with forced air coolin g at a velocity typically achieva ble by a 100 CFM axi al fan. Temper ature quali fi cation is performed in a standard Motorola VME system chassis. 25 wat t load boards are inserted in two card slots (one on each side ), adjacent to the board under test, to simulate a high power density system configuration. An assembly of three axial fans, rated at 100 CFM per fan, is placed directly under the VME card cage. The incoming air temperature is measured between the fan assembly and the card cage, where the incoming airstream first encounters the controller under test. Test softwa re is executed as the controller is subje cted to ambient temperature variations. Case temperatures of critical, high power density integrated circui ts are monitored to ensure the component vendor ’s specifications are not exceeded.

While the exact amount of air flow required for cooling depends on the ambient air temperat ure and the type, number, and location of boards and other heat sourc es; adequate cooling c an usually be achieved with 1 0 CFM and 490 LFM flowing over the contr oller . Less ai r fl ow is requir ed to c ool the controller in environments having lower maximum ambient temperatures. Under more f avorable thermal condit ions, it may be possible to operate the controller reliably at higher than 55° C with increased air flow. It is important to note that ther e are several factors (i n addition to the rated CFM of the fan), which deter mine the actual volum e and speed of air flowing over the controller .

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Introduction

Special Considerations for Elevated-Temperature Operation

This section provide s information pertine nt to users whose application s for the MVME162LX Embedded Controller may subject it to high temperatures.

The controller’s design uses commercial grade devices. Therefore, it can operate within an air temperature range of 0° C to 70° C. There are many factors that affect the ambient temperature felt by components on the controller: inlet air temperature; air flow characteristics; number, types, and locations of IndustryPack modules; power dissipation of adjacent boards in the system, etc.

A temperature profile of an MVME162LX Embedded Controll er (MVME162-223) was developed in an MVME945 12-slot VME chassis. This board was loaded with one GreenSpring IP-Dual P/T module (position a) and one GreenSprin g IP-488 module (position b). One twentyfive-watt lo ad board was install ed adjacent t o e ach side of the boa rd und er test. The exit air velocity was approximately 200 LFM between the controller and the IP-Dua l P/T module . Unde r these conditions, a 10° C rise between the inlet and exit air was observed. At 70° C exit air temperature (60° C inlet air), the junction temperatures of devices on the controller were calculated (from the measured case temperatures) and did not exceed 100° C.

The following are some steps that the user can take to help make elevated temperature operation possible:

1. Position the MVME162LX Embedded Controller in the chassis for maximum air flow over the component side of the board.

2. Avoid placing boards with high power dissipation adjacent to the controller.

3. Use low power IndustryPack modules only.

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Board Level Hardware Descript ion

Manual Terminology

Throughout this m anual, a convention is used which precedes data and addr ess parameters by a character identifying the numeric format as follows:

$ dolla r specifi es a he x ad e ci m a l ch ar a cter % percent specifies a binary number & ampersand specifies a decimal number

For examp le, "12" is the decimal number twelve, and "$12" is the de cimal number eighteen. Unless otherwise specified, all address references are in hexadecimal.

An asterisk (*) following the signal name for signals which are level significant denotes that the signal is true or v alid when the signal is low .

An asterisk (*) following the signal nam e for signals which are edge significant denotes that the actions initiated by that signa l occur on high to low transitio n.

In this manual, assertion a nd nega tion are u sed to spe cify forcing a signal to a particular state. In particular, assertion and assert refer to a signal that is active or true; negation a nd negate indicate a signa l that is inactive or false. T hese terms are used ind ependently of the voltage level (high or low) that they represent.

Data and address sizes are defined as follows:

❏

A byte is eight bits, numbered 0 through 7, with bit 0 being the least significant.

❏

A word is 16 bits, numbered 0 through 15, with bit 0 being the least significant.

❏

A longword is 32 bits, numbered 0 through 31, with bit 0 being the least significant.

The terms "contr ol bit" and "status bit" are use d exte nsively in this document. The term control bit is used to describe a bit in a register that can be set and cleared under software control. The term "true" is used to indicate that a bit is in the state that enables the function it controls. The term "false" is used to indicate that the bit is in the state that disables the function it controls. In all tables, the terms 0 and 1 are used to describe the actual value that should be written to the bit, or the value that it yields when read. The term status bit is used to describe a bit in a register that reflects a specific cond ition. Th e status bit can be read b y software to determ ine operational or exception conditions.

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Block Diagram

Block Diagra m

1MB

FLASH

Optional

Panel

RJ-45 Front

4 Serial Ports

SCSI

OptionalOptional

Ethernet

EIA-232

Transceivers

Connector

Peripherals

Panel SCSI

68-pin Front

Panel

Connector

Transceiver

DB-15 Front

I/O

2 Channels

IndustryPack

Dual 85230

Four 32-pi n

53C710

i82596CA

IPchip

Serial

I/O Contr o llers

MCchip

Sockets

EPROM

SCSI

Coprocessor

Ethernet

Controller

A32/D32

Interface

IndustryPack

8KB

MK48T08

Battery Backed

2MB SRAM

16MB E CC

1 or 4MB P a rity

128KB SRAM

Memory Array

DRAM Memory

1211 9310

w/Battery

Memory Array

w/Battery

Array

Configuration Dependent

Array

MPU

25 MHz

MC68LC040

VMEbus

Master/Slave

A32/24:D64/32/16/08

VMEbus

Interface

VMEchip2

Optional MC68040

Figure 1-1. MVME162LX Block Diagram

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Board Level Hardware Descript ion

Functional Description

This section contains a functiona l description of the MVME162LX Embedded Controller.

Switches and LEDs

The controller’s front panel has an ABORT and RESET swit ch and four light-emitting diode (LED) indicators (FAIL, RUN, SCON, FUSES).

ABORT Switch

RESET Switch

When enabled by software, the user-programmable leve l. I t is norma lly used to abort program execution and return to the 162Bug debugger firmware locat ed in the controller’s EPROMs and flash memory.

The

ABORT switch interrupter in the MCchip ASIC is an edge-sensitive

interrupter connect ed to the ABORT switch. This interrupte r is filtered to remove switch bounce.

Note:

The RESET switch r esets all onboard devices; it also drives SYSRESET* if the MVME162LX is operating as system controller. The RESET switch may be disabled by software.

The VMEchip2 includes both a global and a local reset driver. When the VMEchip2 operates as the VMEbus system controller, the reset driver provides a global system reset by asserting the VMEbus signal SYSRESET*. A SYSRESET* may be generated by the power-up reset, a watchdog timeout, or by a control bit in the LCSR (local control/status register) in the VMEchip2. SYSRESET* remains asserted for at least 200 msec, as required by the VMEbus specification.

For an MVME162LX without the VMEbus option (no VMEchip2), the LCSR control bit is not available to reset the module. In this case, the watchdog timer is allowed to time out to reset the controller.

ABORT switch generates an interrupt at a

RESET switch, a

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Similarly, the VMEchip2 provides an input signal and a control bit to initiate a local res et operatio n. By setting a control bit , software can maintain a b oard in a reset state, disabling a faulty board from participating in normal system operation . The lo cal res et dri ver i s ena bled e ven wh en th e VME chip 2 is n ot the system controller. A local reset may be generated by the RESET switch, a power-up reset, a watchdog timeout, a VMEbus SYSRESET*, or by a control bit in the global control/status register (GCSR).

Front Panel Indicators

Functional Description

There are four LEDs on the MVME162LX front pa nel : and FUSES.

❏ FAIL LED (red). Light s when the BRDFAIL* si gnal line is active or

when the processor is halted. Part of DS1.

❏ RUN LED (green or amber). Lights when the local bus TIP* signal

line is low. This indicates one of the loca l bus master s is executing a local bus cycle. Part of DS1.

❏ SCON LED (green). Lights when the VMEchip2 in the

MVME162LX is the VMEbus system controller. Part of DS2.

❏ FUSES LED (green). Lights when +5 Vdc, +12 Vdc, and -12 Vdc

power is ava ilable to t he LAN, IP, and SCSI interfaces. Part of DS2.

Data Bus Structure

The local bus on the MVME162LX Embedded Controller is a 32-bit synchronous bus that is based on the MC68040 bus, and supports burst transfers and snooping. The var ious local bus maste r and slave devi ces use the local bus to communicate. The local bus is arbitrated by priority type arbiter and the priori ty of the loc al bus masters from highest to lowest is: 82596CA LAN, 53C710 SCSI, VMEbus, and MPU. In the general case, any master can access any slave; however, not all combinations pass the common sense test. Refer to the MVME162LX Embedded Controller Programmer’s Reference Guide to determine its port size, data bus connection, and any restrictions that apply when accessing the device.

FAIL, RUN, SCON,

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Board Level Hardware Descript ion

MC68040 or MC68LC040 CPU

The MC68040 or MC68LC040 processor is used on the MVME162LX. The MC68040 has on-chip instruc tion and data cache s and a floating point process or . The majo r diff eren c e be twe en the tw o pro ce sso rs is that the MC68040 has a floating point coprocessor. Refer to the M68040 user’s manual for additional information.

MC68

040 Cache

The MVME162LX local bus maste rs (VMEchip2, MC68XX040, 5 3C710 SCSI controller, and 82596CA Ethernet controller) have programmable control of the snoop/caching mode. The MVME162LX local bus slaves which support MC68XX040 bus snooping are defined in the Local Bus Memory Map table later in this chapter.

No VMEbus Interface Option

The MVME162LX can be operated as a n embedded controlle r without the VMEbus interface. To su pport thi s featur e, certain logic in the VMEchip2 has been duplicated in the MCchip. This logic is inh ibited in the MCchip if the VMEchip2 is present. The enabl es for the se f unctions ar e control led by software and MCchip hardware initialization.

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Memory Options

The following memory options are used on the different versions of MVME162LX Embedded Controller boards.

DRAM Options

The controller of fers vari ous DRAM options (see Table 1-1) : either 1 MB or 4 MB of parity-protec ted DRAM, or 4, 8, 16, or 32 MB ECC DRAM on a mezzanine boa rd. Parity protecti on ca n be ena bled wi th i nterrupt s or b us exception when a pa rity error is detected. DRAM performance is specified in the MVME162LX Embedded Controller Programmer’s Reference Guide in the section on the DRAM Memory Controller in the MCchip Programming Model.

The DRAM map decoder can be programmed to accommodate different base address(es) and sizes of mezzanine boards. The onboard DRAM is disabled by a local bus reset and must be programmed before the DRAM can be accessed. Refer to the MCchip and MCECC descriptions in the MVME162LX Embedded Controller Programmer’s Reference Guide for detailed programmin g inform ation.

Functional Description

Most DRAM devices require some number of access cycles befo re the DRAMs are fully operational. Normally this requirement is met by the onboard refresh circ uitr y and normal DRAM initialization. However, software should insure a minimum of 10 initialization cycles are performe d to ea ch bank of RA M .

SRAM Options

The controller provi des 128 KB of 32-bit-wide onboard static RAM in a single non-interleaved architecture with onboard battery backup.

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Board Level Hardware Descript ion

The battery backup function for the onboa rd SRAM is provided by a Dallas DS1210S device that supports primary and secondary power sources. In the event of a main board power failure , the DS1210S checks power sources and switches to the source with the higher voltage.

If the voltage of the backup source is less than two volts, the DS1210S blocks the second memory cycle; this allows software to provide an early warning to avoid data loss. Because the second access may be blocked during a power failure, software should do at least two accesses before relying on the data.

The controller provi des jumpers (on J13) tha t allow eit her power source of the DS1210S to be connected to the VMEbus +5V STDBY pin or to one cell of the onboard battery. For example , the primary system backup source may be a battery connected to the VMEbus +5V STDBY pin and the secondary source may be the onboard battery. If the system source should fail or the board is removed from the chassis, the onboard battery takes over.

Further details on SRAM configuration and specifics on SRAM performance can be f ound in the sec tion on the SRAM Memory Cont roller in the MCchip Programming Model in the MVME162LX Embedded Controller Programmer’s Refe rence Guide. The SRAM arrays are not parity protected.

Caution

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For proper operation of the SRAM, some jumper combination must be installed on the respective Backup Power Source Select Header. Refer to the jumper information in Chapter 2. If one of the jumpers is used to select the battery, the battery mus t be i nsta l led on the MVME162LX. The SRAM may malfunction if inputs to the DS1210S are left unconnected.

The SRAM is controlled by the MCchip, and the access time is programmable. Refer to the MCchip descrip tion in the MVME162LX Embedded Controller Programmer’s Reference Guide for additional information.

SRAM Batteries

Lithium batterie s incorporate inflammable materials such

Caution

as lithium and organic solvents. If lithium batteries are mistreated or handled incorrectly, they may burst open and ignite, possible resulting in injury and/or fire.

When dealing with lithium batteries, carefully follow the precautions listed below in order to prevent accidents.

Functional Description

❏ Do not short ci rc ui t. ❏ Do not disassemble, deform, or apply excessive pressure. ❏ Do not heat or incinerate. ❏ Do not apply solder directly. ❏ Do not use different models, or new and old batteries together. ❏ Do not char ge. ❏ Always check proper polarity.

The power source for the o nboard SRAM is a RAYOVAC FB1225 batter y with two BR1225 type lithium cells. The battery is socketed for easy removal and replacement . The power source for the mezzanine SRAM is a Sanyo CR2430 battery. Small capacitors are provided so that the batteries can be quickl y repla ced without data loss.

The lifetime of the batte ries is very de pendent on the ambi ent temper ature of the board and the power-on duty cycle. The lit hium batteries supplied on the controller and on the SRAM mezzanine module should provide at least two years of backup time with the board powered off and with an ambient temperatu re of 40

° C. If the power-on duty cyc le is 50% (the board

is powered on half of th e time), the battery lifetime is f our ye ars. At lower ambient temperature s, the backup time is significantly longer and may approach the shelf life of the batte ry.

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Board Level Hardware Descript ion

When a controller is stored, the battery should be disconnected to prolong battery life. This is especially important at high ambient temperatures. The controller is shipped with the batteries disconnected (with VMEbus +5V standby voltage selected as both primary and secondary power source). If you intend to use the battery as a power source, whether primary or secondary, it is necessary to reconfigure the jumpers on J13 before installing the module.

The power leads from the battery are exposed on the sold er side of the board. The board should not be placed on a conductive surface or stored in a conduc tive ba g unless the battery is removed.

To remove the battery from the module, carefully pull the battery from the socket. Before installing a new battery, ensure that the battery pi ns are clean. Note the battery polarity and press the battery into the socket. When the battery is in the socket, no soldering is required.

EPROM and Flash Memory

The MVME162LX Embedded Controller comes with 1 MB of flash memory and four EPROM sockets ready for the installation of EPROMs, which may be ordered separately. Flash memory is a single Intel 28F008SA device organized in a 1Mbit x 8 configuration. The EPROM locations are standard JEDEC 32-pin DIP sock ets accommodating four jumper-selectable densities (128 Kbit x 8; 256 Kbit X 8; 512 Kbit x 8; 1 Mbit x8). A jumper setting (GPIO3, pins 7-8 on J11), allo ws reset code to be fetched eit her from flash memory (GPIO3 installed) or from EPROMs (GPIO3 removed ).

Battery Backed Up RAM and Clock

An MK48 T08 RAM an d clo ck ch ip is used on th e MVM E162L X. Th is ch ip provides a time-of-day clock, oscillator, crystal, power fail detection, memory write protection, 8KB of RAM, and a battery in one 28-pin package. The clock provides seconds, minutes, hours, day, date, month, and year in BCD 24-hour format. Corrections for 28-, 29- (leap year), and 30day months are automatically made. No interrupts are genera ted by the clock. Although the MK48T08 is an 8 bi t device, the interface provided by the MCchip supports 8-, 16-, and 32 -bit accesses to the MK48T08. Refer to the MCc hip in th e

Reference Guide

programming and battery life information.

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MVME16 2LX Embedded Contr ol ler Programmer’s

and to the MK48T08 data sheet for additional

VMEbus Interface and VMEchip2

The local bus to VMEbus inter face, VMEbus to local bus inter face, and the DMA controller functions of the local VMEbus are provi ded by the VMEchip2. The VMEchip2 can also provide the VMEbus system controller funct ions. Refer to the VMEchip2 in the MVME162LX Embedded Controller Progra mmer’s Reference Guide for additional programming information.

Note that the ABORT switch logic in the VMEchip2 is not used. The GPI inputs to the VMEchip2 which are located at $FFF40088 bits 7-0 are not used. The ABORT switch interrupt is inte grated int o the MCchip ASIC at location $FFF42043. Th e GPI inputs are inte grated into the MCchip ASIC at location $FFF4202C bits 23-1 6.

I/O Interfaces

The MVME162LX provides onboa rd Input/Ou tput ( I/O) f or many sy stem applications. The I/O functions include serial por ts and optional interfaces for IndustryPack (IP ) modules, LAN Ethernet transceivers, and SCSI mass storage devices.

Functional Description

I/O signals are routed thr ough industry-standard connectors on the

controller’s f ront panel; no adapter boards or transition modules are necessary. I/O connections on the controller’s front panel include an optional 68-pin SCSI connector , an optional DB15 Ethernet connector, and four 8-pin RJ45 seria l connectors. In addition , the panel has cutouts for routing of flat cables to the optional IndustryPack modules.

Serial Communications Interface

The MVME162LX uses two Zilog Z85230 serial port control le rs to implement the four serial communica tions interfaces. Each interface supports CTS, DCD, RTS, and DTR control signals, as well as the TXD and RXD transmit/receive data signals. Because the serial clocks are omitted in the controlle r’s de sign, serial communications are strictly asynchronous. The controller’s hardware supports serial baud rates of 110b/s to 38.4Kb/s.

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Board Level Hardware Descript ion

The Z85230 supplies an interrupt vector during interrupt acknowledge cycles. The vector is modified based upon the interrupt source within the Z85230. Interrupt request levels are programmed via the MCchip.

The Z85230s are interfaced as DTE (data terminal equipment) with EIA232-D signal levels. The four serial por ts are routed to four RJ45 telephone connectors on the MVME162LX front panel.

Refer to the Z85230 data sheet a nd to t he MCchip Progr amming Model i n the MVME162LX Embedded Controller Programmer’s Reference Guide for additional information.

IndustryPack (IP) Interfaces

Up to two IndustryPack (IP) modules may be installed on the MVME162LX Embedded Controller as an optio n. The interfac e between the IPs and the MVME162LX is the IndustryPack Interface Controller (IPIC) ASIC. Access to the IPs is provided by two 3M connect ors located

behind the controller’s f ront panel. Refer to the chapter on the IP IC in the MVME162LX Embedded Contr oller

Programmer’s Reference Guide for additional information on the IP interface.

Ethernet Interface

The MVME162LX Embedded Control ler uses the 82596CA controller to implement the Ethe rnet transc eiver inter face. The 82596CA accesses l ocal RAM using DMA operations to perform its normal func tions. Because the 82596CA has small internal buffers and the VMEbus has an undefined latency period, buffer overrun may occur if the DMA is programmed to access the VMEbus. Therefore, the 82596CA should not be programmed to access the VMEbus.

Every MVME162LX that has the Ethernet interface is assigned an Ethernet Station Addre ss. The addr ess is $08003E2XXXXX where XXXXX is the unique 5-nibble number assigned to the board (every MVME162LX has a differe nt va lue for XXXXX).

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SCSI Interface

Functional Description

Each board has an Et hernet Station Address displayed on a label attached to the VMEbus P2 connector. In addition, the six bytes including the Ethernet addres s are store d in th e configura tion area of the BBRAM. That is, 08003E2XXXXX is stored in the BBRAM. At an address of $FFFC1F2C, the upper four bytes (08003E2X) can be read. At an address of $FFFC1F30, the lower two bytes (XXXX) can be read. The MVME162 debugger has the capabili ty to retr ieve or set the Ethernet address.

If the data in the BBRAM is lost, the user should use the number on the label on backplane connector P2 to restore it. The Ethernet transceiver

interface i s locate d on th e control ler’s main cir cuit bo ard, an d the ind ustry standard connector is loc at ed on its front panel.

Support functions for the 82596CA are provide d by the MCchip ASIC. Refer to the 82596CA user's guide and to the MCchip in the MVME162LX

Embedded Controller Progra mmer’s Reference Guide for additional programming information.

The controller suppor ts mass storage subsystems through the industrystandard SCSI bus. These subsystems may include hard and floppy disk drives, streaming tape drives, and other mass storage devices. The SCSI interface is implemen te d using the NCR 53C710 SCSI I/O controller.

Support functions for the 53C710 are provi ded by the MCchi p ASIC. The

SCSI connector is located on the controller’s front panel. Refer to the NCR 53C710 user's guide and to the MCchip in the

MVME162LX Embedded Controller Programmer’s Reference Guide for additional progr amming information.

SCSI T e rminat ion

The individual config uring the system must ensure that the SCSI bus is properly termi nated at both ends. SCSI bus te rminators are located on the controller. The SCSI terminators are enabled/disabled by a jumper on header J14. If the SCSI bus ends at the controlle r, then a jumper must be installed between J14 pins 1 and 2.

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Board Level Hardware Descript ion

The controller provides +5 Vdc to the SCSI bus TERMPWR signal through fuse F4, located near J7. The FUSES LED (part of DS2) on the MVME162LX front panel monitors the SCSI bus TERMPWR signal in addition to LAN power; with the controller connecte d to an SCSI bus, the FUSES LED lights when SCSI terminator power is present.

Because any device on the SCSI bus can provide TERMPWR, the FUSES LED does not dir ectly indicate the condition of the f use. If the LED is not lit during SCSI bus operation, the fuse should still be checked.

Local Resources

The MVME162LX Embedded Contr oller inc lu des many resources for the local processor. These incl ude tick timers, software-programmable hardware interrupts , a watchdog timer, and a local bus timeout.

Programmable Tick Timers

Four 32-bit programmable tick timers with a 1 µs resolution are pro vided in the MCchip and two 32-bi t programmable tick timer s are provided in the optional VMEchip2. The tick timers can be programmed to generate periodic interrupts to the processor.

Refer to the VMEchip2 and MCchip in the MVME162LX Embedded Controller Programmer’s Refe rence Guide for additional programming information.

Watchdog Timer

A watchdog timer is provided in both the MCchip and the optional VMEchip2. The timers operate independently but in parallel. When the watchdog tim ers are enab l ed, they must be reset by software within the programmed time or they will time out. The watchdog timers can be programmed to generate a SYSRESET signal, local reset signal , or board fail signal if they time out.

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The watchdog timer logic is duplicated in the VMEchip2 and MCchip ASICs. Because the watchdog timer function in the VMEchip2 is a superset of that function in the MCchip (system reset function), the timer in the VMEchip2 is used in all cases except for the version of the MVME162LX which does not include the VMEbus interface ("No VMEbus Interface" option).

Refer to the VMEchip2 and the MCchip in the MVME162LX Embedded Controller Programmer’s Reference Guide for additional programming information.

Software-Programmable Hardware Interrupts

Eight software-pr ogrammable hardware interrupts are provided by the VMEchip2. These interrupt s allow software to create a hardware inte rrupt. Refer to the VMEchip2 in the MVME162LX Embedded Controller Programmer’s Referenc e Guide for additional pr ogramming informatio n.

Local Bus Timeout

The MVME162LX Embedded Controller provides timeout fu nctions in the VMEchip2 and the MCchip for the local bus. When the timer is enabled and a local bus access times out, a Transfer Error Acknowledge (TEA) signal is sent to the local bus master. The timeout value is selectable by softwa re for 8 µsec, 64 µsec, 256 µsec, or infinite. The local bus timer does not operate during VMEbus boun d cycles. VMEbus bound cycles are timed by the VMEbus access timer and the VMEbus global timer. The MCchip also provides local bus timeout logic for controllers without the optional VMEbus inte rface (without the VMEchip2).

Functional Description

The access timer logic is dupl icated in the VMEchip2 and MCchip ASICs. Because the local bus timer in the VMEchip2 can detect an offboa rd access and the MCchip local bus timer cannot, the timer in the VMEchip2 is used in all cases except for the version of the controller which does not inc lude the VMEbus interface ("No VME bus Inte rfa ce o ption").

Refer to the VMEchip2 and the MCchip in the MVME162LX Embedded Controller Programmer’s Reference Guide for additional programming information.

http://www.mcg.mot.com/literature 1-23

Board Level Hardware Descript ion

Local Bus Arbiter

The local bus arbiter im plements a fi xed priori ty which is de scribe d in the following table.

Table 1-3. Local Bus Arbitration Priority

Device Priority Note

LAN 0 Highest SCSI 1 ...

VMEbus 2 Next Lowest

MC68XX040 3 Lowest

Connectors

The MVME162LX Embedded Controller has two 96-position DIN connectors: P1 and P2. P1 rows A, B, C, and P2 row B provide the VMEbus interconnection. P2 rows A and C are not used. The MVME162LX has a 20-pin c onnector J2 mounted be hind the fr ont panel. When the MVME162LX board is enclosed in a chassis and the front panel is not visible, this connector allows the reset, abort and LED functions to be extended to the control panel of the system, where they are visible.

The serial ports on the controller are connected to four 8- pin RJ45 female connectors (J17) on the front panel. The two IPs connect to the controller by two pairs of 50- pin connectors. The two 50-pin connectors behind the front panel are for external connections to IP signals. The memory mezzanine board is plugged into two 100-pin connectors. The Ethernet LAN connector is J9, a 15-pin socket connector mount ed on the front panel. The SCSI connector is J10, a 68-pin socket connector is also mounted on the front panel.

1-24 Computer Group Literature Center Web Site

Memory Maps

There are two points of view for memory maps:

1. The mapping of all resources as viewed by local bus masters (local bus memory map).

2. The mapping of onboard resources as viewed by external masters (VMEbus memory map).

The memory and I/ O maps which a re des cribed in t he next t hree ta bles are correct for all local bus masters. There is some address translation capability in the VMEchip2. This all ows multiple MVME162LXs on the same VMEbus with different virtual loca l bus maps as viewed by dif ferent VMEbus masters.

Local Bus Memory Map

The local bus memory map is split into different address spaces by the transfer type (TT) sign als . The local resour ces respond to the normal access and interrupt acknowledge codes.

Memory Maps

Normal Address Range

The memory map of devices that respond to the normal address range is shown in the following tables. The normal address range is defined by the Transfer Type (TT) signals on the local bus. On the MVME162LX Embedded Controller, Transfer Types 0, 1, and 2 define the normal address range. Table 1-4 is the entire map from $00000000 to $FFFFFFF F. Man y are as of th e map are us er-p r ogr ammable, and suggested uses are shown in the table. The cache inhibit function is programmable in the MC68XX040 MMU. The onboard I/O space must be marked cache inhibit and serialized in its page table. Table 1-5 further defines the map for the local I/O devices.

http://www.mcg.mot.com/literature 1-25

Board Level Hardware Descript ion

Table 1-4. Local Bus Memory Map

Address Range Devices Accessed Port

Programmable DRAM on Parity

Mezzanine

Programmable DRAM on ECC

Mezzanine Programmable On-Board SRAM Programmable SRAM on M ezzanine Programmable VMEb us A32/A24 Programmable IP_a Memory Programmable IP_b Memory $FF800000-$FF9FFFFF Flash/EPROM $FFA00000-$FFBFFFFF EPROM/Flash $FFC00000-$FFDFFFFF Not Decoded $FFE00000-$FFE1FFFF On-Board SRAM

Default $FFE80000-$FFEFFFFF Not Decoded

Size Software

Width

D32 1MB-4MB

D32 16MB

D32 128KB D32 2MB

D32/D16 --

D32-D8 64KB-8MB D32-D8 64KB-8MB

D32 2MB D32 2MB D32 2MB D32 128KB

-- 512KB

Notes

Cache

Inhibit

N2, 7

N2, 7 Y/N 4 Y/N 2, 4 Y/N 2, 4

N1, 5

$FFF00000-$FFFEFFFF Local I/O Devices

(Refer to next table)

$FFFF0000-$FFFFFFFF VMEbus A16

1-26 Computer Group Literature Center Web Site

D32-D8 878KB

D32/D16 64KB

Y/N 2, 4

Memory Maps

Notes 1. Devices mapped at $FFF80000-$FFF9FFFF also appear at

$00000000- $001FFFFF when the ROM0 bit in the MCchip EPROM control registe r is hi gh (ROM0=1). ROM0 is set to 1 after each reset . The ROM0 bit must be cleared bef ore other resources (DRAM or SRAM) can be map ped in t his ran g e ($00000000 - $001FFFFF).

2. The EPROM/Flash memory map is also controlled by the EPROM size and by control bit V19 in the MCchip ASIC. Refer to the EPROM/Flash configuration ta bles in the

MVME162LX Embedded Controller Programmer’s Reference Guide for additional information.

3. This area is user-programmable. The DRAM and SRAM decoder is progr ammed in the MCchip, t he local- to-VMEbus decoders are pro g ram m ed in the V MEchip2, and the IP memory space is programmed in the IPIC.

4. Size is approximate.

5. Cache inhibit depends on the devices in the area mapped.

6. The EPROM and Flash are dynamically sized by the MCchip ASIC from an 8-bit private bus to the 32-bit MPU local bus.

7. These areas are not decoded unless one of the programmable decoders i s initializ ed to decode th is space . If they are not decoded and the local timer is e nabled, an acce ss to this address range will generate a local bus timeout.

8. SRAM is 128 KB.

http://www.mcg.mot.com/literature 1-27

Board Level Hardware Descript ion

The following table focuses on the ‘‘Local I/O Devices’’ portion of the local bus ma in me mo ry ma p .

Note Th e IPIC ch ip on th e MVME162LX supports up to four

IndustryPack ( IP) interfaces, designated IP_a through IP_d. The MVME162LX itself accommodates two IPs: IP_a and IP_b. In the following map, the segments a pplica ble to IP_c and IP_d are not used in the controller.

Table 1-5. Local I/O Devices Memory Map

Address Range Devices Accessed Port

Width

$FFF00000 - $FFF3FFFF Reserved - - 256 KB 4 $FFF40000 - $FFF400FF VMEchip2 (LCSR) D32 256 B 1, 3 $FFF40100 - $FFF401FF VMEchip2 (GCSR) D32-D8 256 B 1, 3 $FFF40200 - $FFF40FFF Reserved - - 3.5 KB 4, 5 $FFF41000 - $FFF41FFF Reserved - - 4 KB 4 $FFF42000 - $FFF42FFF MCchip D32-D8 4 KB 1 $FFF43000 - $FFF430FF MCECC #1 D8 256 B 1 , 9 $FFF43100 - $FFF431FF MCECC #2 D8 256 B 1 , 9 $FFF43200 - $FFF43FFF MCECCs (repeated) - - 3.5 KB 1, 5, 9 $FFF44000 - $FFF44FFF Reserved - - 8 KB 4 $FFF45000 - $FFF45800 SCC #1 (Z85230) D8 2 KB 1, 2 $FFF45801 - $FFF45FFF SCC #2 (Z85230) D8 2 KB 1, 2 $FFF46000 - $FFF46FFF LAN (82596CA) D32 4 KB 1, 6 $FFF47000 - $FFF47FFF SCSI (53C710) D32-D8 4 KB 1 $FFF48000 - $FFF57FFF Reserved - - 64 KB 4 $FFF58000 - $FFF5807F IPIC IP_a I/O D16 128 B 1

Size Notes

$FFF58080 - $FFF580FF IPIC IP_a ID D16 128 B 1 $FFF58100 - $FFF5817F IPIC IP_b I/O D16 128 B 1 $FFF58180 - $FFF581FF IPIC IP_b ID Read D16 128 B 1

1-28 Computer Group Literature Center Web Site

Table 1-5. Local I/O Devices Memory Map (Continued)

Memory Maps

Address Range Devices Accessed Port

Width

$FFF58200 - $FFF5827F IPIC IP_c I/O D16 128 B 8 $FFF58280 - $FFF582FF IPIC IP_c ID D16 128 B 8 $FFF58300 - $FFF5837F IPIC IP_d I/O D16 128 B 8 $FFF58380 - $FFF583FF IPIC IP_d ID Read D16 128 B 8 $FFF58400 - $FFF584FF IPIC IP_ab I/O D32-D16 256 B 1 $FFF58500 - $FFF585FF IPIC IP_cd I/O D32-D16 256 B 8 $FFF58600 - $FFF586FF IPIC IP_ab I/O Repeated D32-D16 256 B 1 $FFF58700 - $FFF587FF IPIC IP_cd I/O Repeated D32-D16 256 B 8 $FFF58800 - $FFF5887F Reserved - - 128 B 1 $FFF58880 - $FFF588FF Reserved - - 128 B 1 $FFF58900 - $FFF5897F Reserved - - 128 B 1 $FFF58980 - $FFF589FF Reserved - - 128 B 1 $FFF58A00 - $FFF58A7F Reserved - - 128 B 1 $FFF58A80 - $FFF58AFF Re served - - 128 B 1 $FFF58B00 - $FFF58B7F Reserved - - 128 B 1 $FFF58B80 - $FFF58BFF Reserved - - 128 B 1

Size Notes

$FFF58C00 - $FFF58CFF Reserved - - 256 B 1 $FFF58D00 - $FFF58DFF Re served - - 256 B 1 $FFF58E00 - $FFF58EFF Reserved - - 256 B 1 $FFF58F00 - $FFF58FFF Reserved - - 256 B 1 $FFFBC000 - $FFFBC01F IPIC Registers D32-D8 2 KB 1 $FFFBC800 - $FFFBC81F Reserved - - 2 KB 1 $FFFBD000 - $FFFBFFFF Reserved - - 12 KB 4 $FFFC0000 - $FFFC7FFF MK48T08 (BBRAM,

TOD Clock)

$FFFC8000 - $FFFCBFFF MK48T08 & Disable

Flash w r it es

http://www.mcg.mot.com/literature 1-29

D32-D8 32 KB 1

D32-D8 16 KB 1, 7

Board Level Hardware Descript ion

Table 1-5. Local I/O Devices Memory Map (Continued)

Address Range Devices Accessed Port

Width

$FFFCC000 - $FFFCFFFF MK48T08 & Enable

Flash w rites

$FFFD0000 - $FFFEFFFF Reserved - - 128 KB 4

D32-D8 16 KB 1, 7

Size Notes

Notes 1. For a complete descript ion of the register bits, refer to the

data sheet for the specific chip. For a more detailed memory map, refer to the following detailed peripheral device memory m ap s

2. The SCC is an 8-bit device located on an MCchip private data bus. Byte access is required.

3. Writes to the LCSR in the VMEchip2 must be 32 bits. LCSR writes of 8 or 16 bits terminate with a TEA signal. Writes to the GCSR may be 8, 16 or 32 bits. Reads to the LCSR and GCSR may be 8, 16 or 32 bits. B yte reads should be used to read the interrupt vector.

4. This area does not return an acknowledge signal. If the local bus timer is enabled, the acce ss times out and is terminated by a TEA signal.

5. Size is approximate.

6. Port commands to the 82596 CA must be written a s two 16bit writes: upper word first and lower word second.

7. Refer to the Fla sh and EPRO M In te rfa ce se cti on i n the MCchip description in Chapter 3.

8. Not used.

9. To use this area, the ECC mezzanine board must be installed. If it is not installed, no acknowledge signal is returned; if the local bus timer is enabled, the access times out and is terminated by a TEA signal.

1-30 Computer Group Literature Center Web Site

Detailed I/O Memory Maps

The following tables provide detailed memory maps for the VMEchip2, MCchip, the MCECC memory controller chip, the Zilog Z85230, the Int el 82596CA controller, the NCR 53C710 contro ller, the IPIC chip, and the MK48T08 BBRAM/TOD Clock.

Tables X-X - XX define the programming model for the Local Control and Status Regist ers (LCSR) in the VMEchi p2. The local bu s m ap decoder for the LCSR is included in t he VMEchip2. The base address of the LCSR is $FFF40000 and the registers are 32-bi ts wide. Byte, two-byte, and four-byte re ad oper ations are pe rmitte d: however, byte and two-byt e write operations are not permitted. Byte and two-byte write operations return a TEA signal to the loc al b us. Read-modify- write opera tions sho uld b e use d to modify a byte or a two-byte of a register.

Each register defini tion includes a table with 5 lines:

❏ Line 1 is the base address of the register and the number of bits

defined in the table.

❏ Line 2 shows the bits defined by this table.

Memory Maps

❏ Line 3 defines t he name of th e regist er or the name of the bits in the

❏ Line 4 defines the operatio ns possible on the register bits as follows:

R This bit is a read-only status bit. R/W This bit is readable and writable. W/AC This bit can be set and it is automatically cleared. This bit can

also be read.

C Writing a one to this bit clears this bit or another bit. This bit

reads ze ro .

S Writing a one to this bit sets this bit or another bit. This bit

reads ze ro .

❏ Line 5 defines the state of the bit following a reset as follows:

P The bit is affected by powerup reset. S T h e bi t is affected by SY SR ESET. L The bit is a ffect ed by local re s et . X The bit is not affected by reset.

http://www.mcg.mot.com/literature 1-31

Board Level Hardware Descript ion

Table 1-6. VMEchip2 Memory Map - LCSR Summary (Sheet 1 of 2)

VMEc hip2 LCSR Base Addr ess = $FFF40000 OFFSET:

16171819202122232425262728293031

SLAVE ENDING ADDRESS 1

ADDER

SLAVE ENDING ADDRESS 2

SLAVE ADDRESS TRANSLA TION ADDRESS 1

SLAVE ADDRESS TRANSLA TION ADDRESS 2

SNP

WP2SUP2USR2A322A24

BLK

BLK2PRGM2DATA

D64

16171819202122232425262728293031

MASTER ENDING ADDRESS 1

MASTER ENDING ADDRESS 2

MASTER ENDING ADDRESS 3

MASTER ENDING ADDRESS 4

MASTER ADDRESS TRANSLATION ADDRESS 4

MAST

D16

MAST

GCSR GROUP SELECT

MAST

D16

BOARD SELECT

GCSR

MASTER AM 3MASTER AM 4

MAST

16171819202122232425262728293031

WAIT

RMW

ROM

ZERO

SNP MODE

SRAM

SPEED

DMA TB

DMA CONTROLLER

TICK

2/1

TICK

IRQ 1

CLR

IRQ

STAT

VMEBUS

INTERRUPT

LEVEL

VMEBUS INTERRUPT VECTOR

DMA CONTROLLER

This sh eet continues on facing page.

1-32 Computer Group Literature Center Web Site

ADDER

MAST

D16

IO2ENIO2

ARB

ROBN

DMA

TBL INT

MAST

DHB

DMA LB

SNP MODE

IO2 S/U

MAST

DWB

MASTER AM 2 MASTER AM 1

IO2

IO1ENIO1

P/D

MST FAIR

DMA

INC

VME

LOCAL BUS ADDRESS COUNTER

SLAVE STARTING ADDRESS 1

SLAVE STARTING ADDRESS 2

SLAVE ADDRESS TRANSLATION SELECT 1

SLAVE ADDRESS TRANSLATION SELECT 2

SNP

WP1SUP1USR1A321A24

MASTER STARTING ADDRESS 1

MASTER STARTING ADDRESS 2

MASTER STARTING ADDRESS 3

MASTER STARTING ADDRESS 4

MASTER ADDRESS TRANSLATION SELECT 4

MAST

D16

MST RWD

DMA

INC

IO1 WP EN

MASTER VMEBUS

DMA WRT

IO1 S/U

DMA

D16

DMA

HALT

DMA

D64 BLK

ROM SIZE

DMAENDMA

DMA

BLK

ROM BANK B

TBL

DMA

SPEED

DMA FAIR

DMA

BLK

BLK1PRGM1DATA

D64

RELM

DMA

ROM BANK A

Memory Maps

0123456789101112131415

SPEED

0123456789101112131415

DMA

VMEBUS

DMA

VMEBUS ADDRESS COUNTER

BYTE COUNTER

TABLE ADDRESS COUNTER

MPU

DMA

DMA TABLE

INTERRUPT COUNT

CLR

STAT

LBE ERR

LPE

ERR

LOB ERR

LTO

ERR

LBE

ERR

LPE ERR

LOB ERR

LTO

ERR

TBL

ERR

VME ERR

DMA

DONE

1360 9403

This sheet begins on facing page.

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Board Level Hardware Descript ion

Table 1-6. VMEchip2 Memory Map - LCSR Summary (Sheet 2 of 2)

VMEchip2 LCSR Base Address = $FFF40000 OFFSET:

ARB

BGTO

DMA

TIME OFF

DMA

TIME ON

TICK TIME R 1

VME

GLOBAL

TIMER

16171819202122232425262728293031

SCON BRD

FAIL

IRQ

CLR

IRQ

VECTOR BASE

SYS FAIL

IRQ EN

IRQ

CLR

IRQ

AC FAIL

IRQ LEVEL

VME IACK

IRQ LEVEL

SW7

IRQ LEVEL

SPARE

IRQ LEVEL

FAIL

STAT

MWP BERR

IRQ

CLR IRQ

PURS STAT

IRQ

CLR IRQ

CLR

BRD

PURS

FAIL

STAT

OUT

IRQ1E

TIC2

IRQ

CLR

IRQ

ABORT

IRQ LEVEL

DMA

IRQ LEVEL

SW6

IRQ LEVEL

VME IRQ 7 IRQ LEVEL

VECTOR BASE

RST

TIC1

IRQ

EN IRQ

CLR IRQ

SYS RSTWDCLR

VME

DMA

IACK

IRQ

CLR

IRQ

MST

SYS

IRQ

FAIL

LEVEL

WD CLR CNT

SIG3

IRQ

EN IRQ

CLR

IRQ

SYS FAIL

IRQ LEVEL

SIG 3

IRQ LEVEL

SW5

IRQ LEVEL

VME IRQ 6 IRQ LEVEL

FAIL

LEVEL

WD TO

STAT

SIG2

IRQ

CLR IRQ

ABORT

LEVEL

SIG1

IRQ

CLR IRQ

TICK TIME R 1

TICK TIME R 2

SRST

RST

LRST

SIG0

IRQ

CLR

IRQ

MST WP ERROR

IRQ LEVEL

SIG 2

IRQ LEVEL

SW4

IRQ LEVEL

VME IRQ 5 IRQ LEVEL

GPIOEN

LM1 IRQ

IRQ

CLR IRQ

PRE

16171819202122232425262728293031

LM0

IRQ

EN IRQ

CLR IRQ

This sheet continues on facing page.

1-34 Computer Group Literature Center Web Site

Memory Maps

VME

ACCESS

TIMER

LOCAL

BUS

TIMER

COMPARE REGISTER

COUNTER

COMPARE REGISTER

COUNTER

OVERFLOW

COUNTER 2

SCALER

SW7

SW6

IRQ

SET IRQ

CLR

IRQ

P ERROR

IRQ LEVEL

VME IRQ 4 IRQ LEVEL

GPIOO

SW5

IRQ

SET IRQ

CLR

IRQ

SIG 1

SW3

IRQ

SET IRQ

CLR IRQ

SW4 IRQ

IRQ

SET IRQ

CLR IRQ

0123456789101112131415

TIME OUT

SELECT

CLR OVF

COC

TIC

OVERFLOW

COUNTER 1

PRESCALER

CLOCK ADJUST

CLR OVF

TIC

COC

0123456789101112131415

SW3

SW2

SW1

SW0

IRQ

SET

IRQ

CLR

IRQ

SET

IRQ

CLR

IRQ

IRQ1E

IRQ LEVEL

SIG 0

IRQ LEVEL

SW2

IRQ LEVEL

VMEB IRQ 3

IRQ LEVEL

GPIOI GPI

IRQ

SET IRQ

CLR

IRQ

SPARE VME

IRQ

IRQ7

IRQ

REV

EROM

TIC TIMER 2

IRQ LEVEL

VME IRQ 2 IRQ LEVEL

VME IRQ6

IRQ

LM 1

SW1

DIS

SRAM

VME IRQ5

IRQ

DIS

MST

VME

IRQ4

IRQ3

IRQ

BBSY

IRQ

TIC TIMER 1

DIS

BSYTENINT

IRQ2

IRQ

IRQ LEVEL

LM 0

IRQ LEVEL

SW0

IRQ LEVEL

VME IRQ 1 IRQ LEVEL

VME IRQ1

IRQ

DIS

BGN

1361 9403

This sheet begins on facing page.

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Board Level Hardware Descript ion

Table 1-7. MCchip Register Map

MCchip Base Address = $FF F4 2000

Offset D31-D24 D23-D16 D15-D8 D7-D0

$00 MCchip ID MCchip Revision Ge neral Control Interrupt Vector

Base Regis ter $04 Tick Timer 1 Compare Register $08 Tick Timer 1 Counter Register $0C Tick Timer 2 Compar e Register $10 Tick Timer 2 Counter Register $14 LSB Prescaler

Count Register

$18 Tick Timer 4

Interrupt Control

$1C DRAM Parity

Error Interrupt Control

$20 DRAM Space Base Address

$24 DRAM Space

Size

$28 LANC Error

Status

$2C SCSI Error

Status $30 Tick Timer 3 Compare Register $34 Tick Timer 3 Counter Register $38 Tick Timer 4 Compare Register $3C Tick Timer 4 Counter Register $40 Bus Clock PROM Access

$44 RESET Switch

Control

$48 DRAM Control (Reserved)MPU Status(Reserved) $4C 32-bit Prescaler Count Register

Prescaler Cloc k Adjust

Tick Timer 3 Interrupt Control

SCC Interrupt Control

DRAM/SRAM Options

(Reserved) LANC Interrupt

General Purpose Inputs

Time Control Watchdog Tim er

Control

Tick Timer 2 Control

Tick Timer 2 Interrupt Control

Tick Timer 4 Control

SRAM Spac e Base Address Register

SRAM Space Size

Control MVME162LX

Version

Flash Access Tim e Contro l

Access & Watchdog Tim e Base Sele ct

Tick Timer 1 Control

Tick Timer 1 Interrupt Control

Tick Timer 3 Control

(Reserved)

LANC Bus Error Interrupt Control

SCSI Interrupt Control

ABORT Swit ch Interrupt Control

(Reserved)

1-36 Computer Group Literature Center Web Site

Table 1-8. MCECC Internal Register Memory Map

MCECC Base Address = $FFF43000 (1st); $FFF43100 (2nd)

Memory Maps

Offset

Name

D31 D30 D29 D28 D27 D26 D25 D24

$00 CHIP ID CID7 CID6 CID5 CID4 CID3 CID2 CID1 CID0 $04 CHIP RE VISION REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 $08 MEM CONFIG FSTRD 1 0 MSIZ2 MSIZ1 MSIZ0 $0CDUMMY 000000000 $10DUMMY 100000000 $14 BASE ADDRESS BAD31 BAD30 BAD29 BAD28 BAD27 BAD26 BAD25 BAD24 $18 DRAM CON TR L BAD23 BAD22 RWB5 SW AIT RWB3 NCEIEN NCE BENRAMEN

$1C BCLK FREQ BC K7 BCK6 BCK5 BCK4 BCK3 BCK2 BC K1 BCK0 $20DATA CONTRL00DERCZFILLRWCKB000 $24 SCRUB CN TR L RACODERADATAHITDIS SCRB SCRBEN0SBEIENIDIS

$28 SCRUB PERIOD SBPD15 SBPD14 SBPD 13 SBPD 12 SB PD 1 1 SBPD 10 SBPD9 SBPD8 $2C SCRUB PERIOD SBPD7 SBPD6 SBPD5 SBPD4 SBPD3 SBPD2 SBPD1 SBPD0 $30 CHIP PRESCALE CPS7 CPS6 CPS5 CPS4 CPS3 CPS2 CPS1 CPS0 $34 SCRUB TIME

ON/OFF

$38 SCRUB

PRESCALE

$3C SCRUB

PRESCALE

$40 SCRUB

PRESCALE

$44 SCRUB TIMER ST15 ST14 ST13 ST12 ST11 ST10 ST9 ST8

SRDIS 0 STON2 STON1 STON0 STOFF2 STOFF1 STOFF0

0 0 SPS21 SPS20 SPS19 SPS18 SPS17 SPS16

SPS15 SPS14 SPS13 SPS12 SPS11 SPS10 SPS9 SPS8

SPS7 SPS6 SPS5 SPS4 SPS3 SPS2 SPS1 SPS0

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Board Level Hardware Descript ion

Table 1-8. MCECC Internal Register Memory Map (Continued)

MCECC Base Address = $FFF43000 (1st); $FFF43100 (2nd)

Offset

$48 SCRUB TIMER ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0 $4C SCRUB ADDR

$50 SCRUB ADDR

$54 SCRUB ADDR

$58 SCRUB ADDR

$5C ERROR LOGGER ERRLOGERD ESCRB ERA EALT 0 MBE SBE

$60 ERROR

$64 ERROR

$68 ERROR

Name

CNTRL

ADDRESS

D31 D30 D29 D28 D27 D26 D25 D24

00000SAC26SAC25SAC24

SAC23 SAC22 SAC21 SAC20 SAC19 SAC18 SAC17 SAC16

SAC15 SAC14 SAC13 SAC12 SAC11 SAC10 SAC9 SAC8

SAC7SAC6SAC5SAC40000

EA31 EA30 EA29 EA28 EA27 EA 26 EA25 EA24

EA23 EA22 EA21 EA20 EA19 EA 18 EA17 EA16

EA15 EA14 EA13 EA12 EA1 1 EA10 EA9 EA 8

$6C ERROR

ADDRESS

$70 ERROR

SYNDROME

$74 DEFAUL TS1 WRHDISST ATCOLFSTRD SELI1 SEL I0 RSIZ2 RSIZ1 RSIZ0

$78 DEFAULTS2 FRC_OPNXY_FLIPREFDIS TVECT NOCA CHERESST2 RESST1 RESST0

EA7EA6EA5EA40000

S7 S6 S5 S4 S3 S2 S1 S0

1-38 Computer Group Literature Center Web Site

Table 1-9. Z85230 SCC Register Addresses

SCC SCC Register Address

SCC #1 Port B Control $FFF45001

Port B Data $FFF45003 Port A Control $FFF45005 Port A Data $FFF45007

SCC #2 Port B Control $FFF45801

Port B Data $FFF45803 Port A Control $FFF45805 Port A Data $FFF45807

Table 1-10. 82596CA Ethernet LAN Memory Map

Data Bits

Address D31 D16 D15 D0

$FFF46000 Upper Command Word Lower Command Word $FFF46004 MPU Channel Attention (CA)

Memory Maps

Notes 1. Refer to the MPU Port and MPU Channel Attention

registers in the MVME162 Embedded Controller Programmer’s Reference Guide.

2. After resetting, you must write the System Configuration Pointer to the command registers before writing to the MPU Channel Attention register . Wr ites to the System Configuration Pointer must be upper word first, lower word second.

http://www.mcg.mot.com/literature 1-39

Board Level Hardware Descript ion

Table 1-11. 53C710 SCSI Memory Map

53C710 Register Addres s Map Bas e Address is $FFF47000

Big Endian

Mode

00 SIEN SDID SC NTL1 SCNTL0 00 04 SOCL SODL SXFE R SCID 04 08 SBCL SBDL SIDL SFBR 08 0C SSTAT2 SSTAT1 SSTAT0 DSTAT 0C 10 DSA 10 14 CTEST3 CTEST2 CTEST1 CTEST0 14 18 CTEST7 CTEST6 CTEST5 CTEST4 18 1C TEMP 1C 20 LCRC C TEST8 ISTAT DFIFO 20 24 DCMD DBC 24 28 DNAD 28 2C DSP 2C 30 DSPS 30 34 SCRATCH 34 38 DCNTL DWT DIEN DMODE 38 3C ADDER 3C

SCRIPTs

and Little

Endian

Mode

Note Accesses may be 8-bit or 32-bit, but not 16-bit.

1-40 Computer Group Literature Center Web Site

Memory Maps

IPIC Overall Memory Map

The following memory map tabl e includes all devices selecte d by the IPIC map decoder.

Note The IPIC chip on the MVME162LX supports up to four

IndustryPack (IP) interfaces, designated IP_a through I P_d. The controller itself accommodates two IPs: IP_a and I P _b. In the maps t hat follow, the segments applicable to IP_c and IP_d are not used in the controller.

Table 1-12. IPIC Overall Memory Map

Address Ran g e Select ed D ev i ce Port Widt h Size

Programmable IP_a/IP_ab Memory Space D32-D8 64 KB-16 MB Programmable IP_b Memory Space D16-D8 64 KB-8 MB Programmable IP_c/IP_cd Memory Space D32-D8 64 KB-16 MB Programmable IP_d Memory Space D16-D8 64 KB-8 MB $FFF58000-$FFF5807F IP_a I/O Space D16 128 B $FFF58080-$FFF580BF IP_a ID Space D16 64 B $FFF580C0-$FFF580FF IP_a ID Space Repeated D16 64 B $FFF58100-$FFF5817F IP_b I/O Space D16 128 B $FFF58180-$FFF581BF IP_b ID Space D16 64 B $FFF581C0-$FFF581FF IP_b ID Space Repeated D16 64 B $FFF58200-$FFF5827F IP_c I/O Space D16 128 B $FFF58280-$FFF582BF IP_c ID Space D16 64 B $FFF582C0-$FFF582FF IP_c ID Space Repeated D16 64 B $FFF58300-$FFF5837F IP_d I/O Space D16 128 B $FFF58380-$FFF583BF IP_d ID Space D16 64 B $FFF583C0-$FFF583FF IP_d ID Space Repeated D16 64 B $FFF58400-$FFF584FF IP_ab I/O Space D32-D16 256 B $FFF58500-$FFF585FF IP_cd I/O Space D32-D16 256 B $FFF58600-$FFF586FF IP_ab I/O Space Repeated D32-D16 256 B $FFF58700-$FFF587FF IP_cd I/O Space Repeated D32-D16 256 B $FFFBC000-

$FFFBC01F

Control/Status Registers D32-D8 32 B

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Board Level Hardware Descript ion

Table 1-13 contains a summary of the IPIC CSR registers. The CSR registers can be accessed a s bytes, words, or l ongwords; the y should not be accessed as lines. They are shown in the table as bytes.

Table 1-13. IPIC Memory Map—Control and Status Registers

IPIC Base Address = $FFFBC000

Offset

$00CHIP ID 00100011 $01CHIP REVISION 00000000 $02RESERVED 00000000 $03RESERVED 00000000 $04 IP_a MEM BASE

$05 IP_a MEM BASE

$06 IP_b MEM BASE

$07 IP_b MEM BASE

$08 IP_c MEM BASE

$09 IP_c MEM BASE

$0A IP_d MEM BASE

$0B IP_d MEM BASE

$0C IP_a MEM SIZE a_SIZE23 a_SIZE22 a_SIZE21 a_SIZE20 a_SIZE19 a_SIZE18 a_SIZE17 a_SIZE16 $0D IP_b MEM SIZE b_SIZE23 b_SIZE22 b_SIZE21 b_SIZE20 b_SIZE19 b_SIZE18 b_SIZE17 b_SIZE16 $0E IP_c MEM SIZE c_SIZE23 c_SIZE22 c_SIZE21 c_SIZE20 c_SIZE19 c_SIZE18 c_SIZE17 c_SIZE16 $0F IP_d MEM SIZE d_SIZE23 d_SIZE22 d_SIZE21 d_SIZE20 d_SIZE19 d_SIZE18 d_SIZE17 d_SIZE16 $10 IP_a INT0 CONTROL a0_PLTY a0_E/L* a0_INT a0_IEN a0_ICLR a0_IL2 a0_IL1 a0_IL0 $11 IP_a INT1 CONTROL a1_PLTY a1_E/L* a1_INT a1_IEN a1_ICLR a1_IL2 a1_IL1 a1_IL0 $12 IP_b INT0 CONTROL b0_PLTY b0_E/L* b0_INT b0_IEN b0_ICLR b0_IL2 b0_IL1 b0_IL0 $13 IP_b INT1 CONTROL b1_PLTY b1_E/L* b1_INT b1_IEN b1_ICLR b1_IL2 b1_IL1 b1_IL0

UPPER

LOWER

UPPER

LOWER

UPPER

LOWER

UPPER

LOWER

Name

D7 D6 D5 D4 D3 D2 D1 D0

a_BAS E31 a_BASE30 a_ BASE29 a_BASE28 a_BASE27 a_ BASE26 a_BASE25 a_BASE24

a_BAS E23 a_BASE22 a_ BASE21 a_BASE20 a_BASE19 a_ BASE18 a_BASE17 a_BASE16

b_BAS E31 b_BASE30 b_ BASE29 b_BASE28 b_BASE27 b_ BASE26 b_BASE25 b_BASE24

b_BAS E23 b_BASE22 b_ BASE21 b_BASE20 b_BASE19 b_ BASE18 b_BASE17 b_BASE16

c_BASE31 c_BASE30 c_BASE29 c_BASE28 c_BASE27 c_BASE26 c_BASE25 c_BASE24

c_BASE23 c_BASE22 c_BASE21 c_BASE20 c_BASE19 c_BASE18 c_BASE17 c_BASE16

d_BASE31 d_BASE30 d_BASE29 d_BASE28 d_BASE27 d_BASE26 d_BASE25 d_BASE24

d_BASE23 d_BASE22 d_BASE21 d_BASE20 d_BASE19 d_BASE18 d_BASE17 d_BASE16

1-42 Computer Group Literature Center Web Site

Memory Maps

Table 1-13. IPIC Memory Map—Control and Status Registers (Continued)

IPIC Base Address = $FFFBC000

Offset

$14 IP_c INT0 CONTROL c0_PLTY c0_E/L* c0_INT c0_IEN c0_ICLR c0_IL2 c0_IL1 c0_IL0 $15 IP_c INT1 CONTROL c1_PLTY c1_E/L* c1_INT c1_IEN c1_ICLR c1_IL2 c1_IL1 c1_IL0 $16 IP_d INT0 CONTROL d0_PLTY d0_E/L* d0_INT d0_IEN d0_ICLR d0_IL2 d0_IL1 d0_IL0 $17 IP_d INT1 CONTROL d1_PLTY d1_E/L* d1_INT d1_IEN d1_ICLR d1_IL2 d1_IL1 d1_IL0 $18 IP_a GENERAL

$19 IP_a GENERAL

$1A IP_b GENERAL

$1B IP_b GENERAL

$1CRESERVED 00000000 $1DRESERVED 00000000 $1ERESERVED 00000000 $1FIP RESET 0000000RES

Name

CONTROL

D7 D6 D5 D4 D3 D2 D1 D0

a_ERR 0 a_RT1 a_RT0 a_WIDTH1 a_WIDTH0 0 a_MEN

b_ERR 0 b_RT1 b_RT0 b_WIDTH1 b_WIDTH0 0 b_MEN

c_ERR 0 c_RT1 c_RT0 c_WIDTH1 c_WIDTH0 0 c_MEN

d_ERR 0 d_RT1 d_RT0 d_WIDTH1 d_WIDTH0 0 d_MEN

Table 1-14. MK48T08 BBRAM/TOD Clock Memory Map

Address Range Descript ion Size (Bytes)

$FFFC0000 - $FFFC0FFF User Area 4096 $FFFC1000 - $FFFC10FF Networking Area 256 $FFFC1100 - $FFFC16F7 Operating System Area 1528 $FFFC16F8 - $FFFC1EF7 Debugger Area 2048 $FFFC1EF8 - $FFFC1FF7 Configuration Area 256 $FFFC1FF8 - $FFFC1FFF TOD Clock 8

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Board Level Hardware Descript ion

Table 1-15. BBRAM Configuration Area Memory Map

Address Range Description Size (Bytes)

$FFFC1EF8 - $FFFC1EFB Ve rsion 4 $FFFC1EFC - $FFFC1F07 Serial Number 12 $FFFC1F08 - $FFFC1F17 Board ID 16 $FFFC1F18 - $FFFC1F27 PWA 16 $FFFC1F28 - $FFFC1F2B Speed 4 $FFFC1F2C - $FFFC1F31 Ethernet Address 6 $FFFC1F32 - $FFFC1F33 Reserved 2 $FFFC1F34 - $FFFC1F35 Local SCSI ID 2 $FFFC1F36 - $FFFC1F3D Memory Mezzanine PWB 8 $FFFC1F3E - $FFFC1F45 Memory Mezzanine Serial Number 8 $FFFC1F46 - $FFFC1F4D Serial Port 2 Personality PWB 8 $FFFC1F4E - $FFFC1F55 Serial Port 2 Personality Serial No. 8 $FFFC1F56 - $FFFC1F5D IP_a Board ID 8 $FFFC1F5E - $FFFC1F65 IP_a Board Serial Number 8 $FFFC1F66 - $FFFC1F6D IP_a Board PWB 8 $FFFC1F6E - $FFFC1F75 IP_b Board ID 8 $FFFC1F76 - $FFFC1F7D IP_b Board Serial Number 8 $FFFC1F7E - $FFFC1F85 IP_b Board PWB 8 $FFFC1F86 - $FFFC1F8D IP_c Board ID 8 $FFFC1F8E - $FFFC1F95 IP_c Board Serial Number 8 $FFFC1F96 - $FFFC1F9D IP_c Board PWB 8 $FFFC1F9E - $FFFC1FA5 IP_d Board ID 8 $FFFC1FA6 - $FFFC1FAD IP_d Board Serial Number 8 $FFFC1FAE - $FFFC1FB5 IP_d Board PWB 8 $FFFC1FB6 - $FFFC1FF6 Reserved 65 $FFFC1FF7 Checksum 1

1-44 Computer Group Literature Center Web Site

Memory Maps

Table 1-16. TOD Clock Memory Map

Data Bits

Address D7D6D5D4D3D2D1D0 Function

$FFFC1FF8 W R S -- -- -- -- -- CONTROL $FFFC1FF9 ST -- -- -- -- -- -- -- SECONDS 00 $FFFC1FFA x -- -- -- -- -- -- -- MINUTES 00 $FFFC1FFB x x -- -- -- -- -- -- HOUR 00 $FFFC1FFC x F T x x x -- -- -- DAY 01 $FFFC1FFD x x -- -- -- -- -- -- DATE 0 1 $FFFC1FFE x x x -- -- -- -- -- MON TH 01 $FFFC1FFF -- -- -- -- -- -- -- -- YEAR 00

Note W = Write BitR = Read BitS = Signbit

ST = Stop BitFT = Frequency Testx = Unuse

http://www.mcg.mot.com/literature 1-45

Board Level Hardware Descript ion

BBRAM, TOD Clock Memory Map

The MK48T08 BBRAM (also called Non-Volatile RAM or NVRAM) is divided into six areas as shown in Table 1-14. The first five areas are defined by software, while the sixth area , the time-of -day (TOD) clock, is defined by the chip hardware. The first area is reserved for user data. The second area is used by Motorola networking software. The third area is used by the operating syst em. The fourth area is used by the MVME162LX board debugger (162Bug). The fifth area , de tailed in Table 1-15, is the configuration area. The sixth area, the TOD clock, detailed in Tabl e 1-16, is defined by the chip hardware.

The data structure of the configuration bytes starts at $FFFC1EF8 and is as follows.

struct brdi_cnfg {

char version[4]; char serial[12]; char id[16]; char pwa[16]; char speed[4]; char ethernet[6]; char fill[2]; char lscsiid[2]; char mem_pwb[8]; char mem_serial[8]; char port2_pwb[8]; char port2_serial[8]; char ipa_brdid[8]; char ipa_serial[8]; char ipa_pwb[8]; char ipb_brdid[8]; char ipb_serial[8]; char ipb_pwb[8]; char ipc_brdid[8]; char ipc_serial[8]; char ipc_pwb[8]; char ipd_brdid[8]; char ipd_serial[8]; char ipd_pwb[8]; char reserved[65]; char cksum[1]; }

1-46 Computer Group Literature Center Web Site

Memory Maps

The fields are defi ned as follows:

1. Four bytes are reserved for the revis ion or ver sion of thi s struc ture. This revision is stored in ASCII format, with the first two bytes being the major version numbers and the last two bytes being the minor version numbers. For example, if the vers ion of this structure is 1.0, this field contains:

0100

2. Twelve bytes are reserved for the serial number of the board in ASCII format. For example, this field could contain:

000000470476

3. Sixteen bytes are reserved for the board ID in ASCII format. For example, for an MVME162LX board with MC68040, SCSI, Ethernet, 4MB DRAM, and 128 KB SRAM, this field contains:

MVME162-223 (The 11 characters are followed byfive blanks).

4. Sixteen bytes are reserved for the printed wiring assembly (PWA) number assigned to this board in ASCII format. This includes the

01-W prefix. This is for the main logic board if more than one board

is required for a set. Additional boards in a set are defined by a structure for that se t. For example, for an MVME162LX board with MC68040, SCSI, Ethernet, 4MB DRAM, and 128 KB SRAM at revision A, the PWA field contains:

01-W3866B01A (The 12 characters are followed by four blanks.)

5. Four bytes contain the speed of the board in MHz. The first two bytes are the whole number of MHz and the second two bytes are fractions of MHz. For example, for a 25.00 MHz board, this field contains:

2500

6. Six bytes are reserved for the Ethernet address. The address is stored in hexadecimal format. (Refer to the detailed description in Chapter 4.) If the board does not support Ethernet, this field is filled with zeros.

7. These two bytes are reserved.

http://www.mcg.mot.com/literature 1-47

Board Level Hardware Descript ion

8. Two bytes are reserved for the local SCSI ID. The SCSI ID is stored in ASCII format.

9. Eight bytes are reserved for the printed wiring board (PWB) number assigned to the memory mezzanine board in ASCII format. This does not include the

10. Eight bytes are reserved for the serial number assigned to the memory mezzanine board in ASCII format.

11. Eight bytes are reserved for the printed wiring board (PWB) number assigned to the serial port 2 personality board in ASCII format.

12. Eight bytes are reserved for the serial number assigned to the serial port 2 personality board in ASCII format.

13. Eight bytes are reserved for the board identifier, in ASCII format, assigned to the optional firs t Indu stryPack a.

14. Eight bytes are reserved for the serial number, in ASCII format, assigned to the optional firs t Indu stryPack a.

15. Eight bytes are reserved for the printed wiring board (PWB) number assigned to the optional firs t Indu stryPack a.

01-W prefix.

16. Eight bytes are reserved for the board identifier, in ASCII format, assigned to the optional second Indust ryPack b.

17. Eight bytes are reserved for the serial number, in ASCII format, assigned to the optional second Indust ryPack b.

18. Eight bytes are reserved for the printed wiring board (PWB) number assigned to the optional second Indust ryPack b.

19. Eight bytes are reserved for the board identifier, in ASCII format, assigned to the optional third I ndustryPack c.

20. Eight bytes are reserved for the serial number, in ASCII format, assigned to the optional third I ndustryPack c.

21. Eight bytes are reserved for the printed wiring board (PWB) number assigned to the optional third I ndustryPack c.

22. Eight bytes are reserved for the board identifier, in ASCII format, assigned to the optional fourt h Indus tryPack d.

1-48 Computer Group Literature Center Web Site

23. Eight bytes are rese rved for the seri al num ber, i n ASC II fo rm at , assigned to the optional fourth IndustryPack d.

24. Eight bytes are reserved for the printe d wiring board (PWB) number assigned to the optional fourth IndustryPack d.

25. Growth space (65 bytes) is reserved. This pads the structure to an even 256 bytes.

26. The final one byte of the area is reserved for a checksum (as defined in the MVME162Bug Debugging Packag e User’s Manual) for security and d ata integrity of th e configuration area of the NVRAM. This data is stored in hexadecimal format.

Interrupt Acknowledge Map

The local bus distinguishe s interrupt acknowledge cycles from other cycles by pla cing the binary value %11 on TT1-TT0. It also specifies the level that is be ing acknowledged using TM2-TM0. The interrupt handler selects which device within tha t le vel is being acknowledged.

VMEbus Memory M ap

Memory Maps

This section describes the mapping of local resources as viewed by VMEbus masters. Default addres ses for the slave, master, and GCSR address decoders a re provided by the ENV command. Refer to Appendix A for additional information.

VMEbus A ccesses to the Local Bus

The VMEchip2 includes a user-prog rammabl e map decoder for the VMEbus to local bus interface. The map decoder allows you to program the starting and ending addre ss an d the modifiers that the controller responds to.

VMEbus Short I/O Memory Map

The VMEchip2 includes a user-pr ogrammable map decoder for the GCSR. The GCSR map decoder allows you to pr ogram the sta rting addr ess of t he GCSR in the VMEbus short I/O space.

http://www.mcg.mot.com/literature 1-49

Board Level Hardware Descript ion

Software Initialization

Most functions that have been done with switches or jumpers on other modules are done by setting control registers on the MVME162LX Embedded Controller. At power-up or reset, the PROMs that conta in the 162Bug debugging package set up the default values of many of these registers.

Specific programming deta ils may be dete rmined by st udy of the M68040 Microprocessor User’s Manual. Then check the details of all the

controller’s onboard r egi sters as given in the MVME162LX Embedded Controller Programmer’s Reference Guide.

Multi-MPU Programming Considerations

Good programming practice dicta te s that only one MPU at a time have control of the MVME162LX control register s. Of particular note are:

❏ Registers that modify the address map ❏ Registers that require two cycles to access ❏ VMEbus interrupt request registers

Local Reset Operation

Local reset (LRST) is a subset of system reset (SRST). Local reset can be

generated five ways:

❏ Expiration of the watchdog timer ❏ Pressing the front panel RESET switch (if the system controller

function is disabled)

❏ By asserting a bit in the board control register in the GCSR ❏ By SYSRESET* ❏ By powerup reset.

1-50 Computer Group Literature Center Web Site

Note The GCSR allows a VMEbus master to reset the local bus.

Any VMEbus access to the MVME162LX Embedded Controller while it is in the r eset state is igno red. If a global bus timer is enabled, a bus error is generated.

EMC Compliance

Software Initialization

This feature is very dangerous and should be used with caution. The local reset fea ture is a partial system reset, not a complete system reset such as powerup reset or SYSRESET*. When the local bus reset signal is asserted, a local bus cycle m ay be aborted . The VMEchip2 is connected to both the local bus and the VMEbus and if the aborted cycle is bound for the VMEbus, erratic operation may result. Communications betwee n the local processor and a VMEbus master should use interrupts or mailbox locations; reset should not be used in normal communications. Reset should be used only when the local processor is halted or the local bus is hung and reset is the last resort.

The MVME162LX Embedded Controller was tested in an EMCcompliant chassis a nd meets the requirements for Class B equipment. CE compliance mark was achieved under the following conditions:

1. Shielded cables on all external I/O ports.

2. Cable shields connected to earth gr ound via metal shell connectors bonded to a conductive module front panel.

3. Conductive chassis rails connected to earth ground. This provides the path for connecting shields to earth ground.

4. Front panel screws properly tightened.

For minimum RF emissions, it is essential that the conditions above be implemented. Failure to do so c ould compromise the EMC c ompliance of the equipment containing the module.

http://www.mcg.mot.com/literature 1-51

Board Level Hardware Descript ion

1-52 Computer Group Literature Center Web Site

2Hardware Preparation and

Introduction

This chapter provides unpacking instructions, hardware preparation guidelines, and installation instructions for the MVME162LX Embedded Controller.

Unpacking Instructions

If the shipping carton is damaged upon receipt, insist that

Caution

the carrier’s agent be present during the unpacking and inspectio n of the equipment.

Avoid touching areas of integrat ed circ uitry; static discharge can damage circuits.

Unpack the equ ipment f rom th e shippi ng cart on. Pl ace the equi pment on a clean and adequately protected working surface. Refer to the packing list and verify th at all items are present. Save the packing material for storing and reshipping of equipment.

Installation

Hardware Preparation

To select the desired configur a tion and ensure proper operation of the controller, certain option modifications may be necessary before installati on. The controller provides software control for many of these options. Some options cannot be modified in software, and consequently are set by installing or removing jumpers on PCB headers. Most other modifications are perf ormed by setting bits in control registers afte r the controller has been insta lled in a system.

The controller’s registers are described in the MVME162LX Embedded Controller Programmer’s Reference Guide.

2-1

Hardware Preparation and Installation

Figure 2-1 shows the placement of the switches, PCB jumper headers, connectors, and LED indicators on the controller. The controller has be en factory tested and is shippe d with the factory jumper settings listed in the following sections. It operates wi th its require d and factory-insta lled debug monitor, MVME162Bug (162Bug), with these fact ory jumper settings. Settings can be made for:

❏ System controller selection (J1) ❏ General-purpose readable register configura tion (J11) ❏ EPROM/Flash configuration (J12) ❏ SRAM backup power source selection (for onboard SRAM: J1 3 on

the MVME162LX PCB; for the SRAM mezzanine: J1 on the SRAM mezzanine)

❏ SCSI bus termination (J14)

System Controller Select Header (J1)

The MVME162LX Embedded Controller is factory-configured as a VMEbus system controller (a jumper is installed across pins 1 and 2 of PCB header J1). Remove the J1 ju mper if t he control ler i s not to ac t as the system controller. Note that when the MVME162LX is functioning as a system controller, the SCON LED is turned on.

Note For controllers without th e optional VM Ebus in terface ( with

no VMEchip2), the jumper may be installed or removed without affecting normal operation.

System Controller (factory configuration) Not System Controller

2-2 Computer Group Literature Center Web Site

ETHERNET PORT SCSI INTERFACE

MVME

162-2XX

ABORT

RESET

Hardware Preparation

RUNFAIL

SCONFUS ES

DS1

DS2

S1 S2

15 9

J1 1 2

245049

22627

245049

22627

F2 F3

245049

22627

245049

22627

A32

B32

C32

PRIMARY SIDE

CSL 1 2 3 4

33 1

J10

J13 J14

J17

ABCD

J15

100

XU21 SKT

15 16

XU21 SKT

XU22 SKT

J11 J12

XU23 SKT

XU24 SKT

1 2

XU24 SKT

A1B1C1

J16

100

C32

A32

B32

Figure 2-1. MVME162LX Switch, Header, Connector, Fuse, and LED Locations

http://www.mcg.mot.com/literature 2-3

Hardware Preparation and Installation

General-Purpose Readable Jumpers Header (J11)

PCB header J11 provides eight readable jumpers. These jumpers can be read as a register (at $F FF4202D) in the MCchip LCSR. The bit va lues are read as a zero when the jumper is installed, and as a one when the jumper is removed.

If the MVME162BUG firmware is installed, four jumper s are userdefinable (pins 9-10, 11-12, 13-1 4, 15- 16). If the MVME162BUG firmware is not ins talled, seven jumpers are use r-definable (pins 1-2 , 3-4, 5-6, 9-10, 11-12, 13-14, 15-16) .

Note Pins 7-8 (GPI 3) are reserved to select either the Flash

memory map (jumper installed) or the EPROM memory map (jumper removed). They are not user-definable. The address ranges for the various EPROM/Flash configurations appear in the next section of this chapter.

The controller is shipped from the factory with J11 set to all zeros (jumper s on all pins) exce pt fo r G PI 3.

J11

162BUG INSTALLED

USER CODE INSTALLED

GPI 0

GPI 1

GPI 2

GPI 3

GPI 4

GPI 5

GPI 6

EPROMs Selected (factory configuration)

REFER TO 162BUG MANUAL

IN=FLASH; OUT=EPROM

USER-DEFINABLE

16GPI 7

USER-DEFINABLE

IN=FLASH; OUT=EPROM

USER-DEFINABLE

2-4 Computer Group Literature Center Web Site

Hardware Preparation

EPROM/Flash Configuration Header (J12)

The MVME162LX Embedded Controller comes with 1 MB of flash memory and four EPROM sockets ready f or the installation of EPROMs, which may be ordered separately. The EPROM locations are standard JEDEC 32-pin DIP sockets that accommodate four jumper-selectable densities (128 Kbit x 8; 256 Kbi t x 8; 5 12 Kbit x 8; 1 Mbi t x 8) a nd permit disabling of the flash memory.

Header J12 provides eight jumpers to configure the EPROM sockets.

J12

CONFIGURATION 1: 128K x 8 EPROMs CONFIGURATION 2: 256K x 8 EPROMs

J12

CONFIGURATION 5: 1M x 8 EPROMs

WITH ONBOARD FLASH DISABLED

CONFIGURATION 4: 1M x 8 EPROMsCONFIGURATION 3: 512K x 8 EPROMs

J12

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Hardware Preparation and Installation

The next five table s show the addr ess ra nge f or each EP ROM socket in a ll five configurations . GPI 3 (J11 pins 7-8) is a contr ol bit in the MCchip ASIC that allows reset code to be fetched either from flash memory or from EPROMs.

Table 2-1. EPROM/Flash Mapping - 128K x 8 EPROMs

GPI 3 Address Range Device Accessed

Removed 1 $FF800000 - $FF81FFFF EPROM A (XU24)

$FF820000 - $FF83FFFF EPROM B (XU23) $FF840000 - $FF85FFFF EPROM C (XU22) $FF860000 - $FF87FFFF EPROM D (XU21) $FFA00000 - $FFBFFFFF On-Board Flash

Installed 0 $FF800000 - $FF9FFFFF On-Board Flash

$FFA00000 - $FFA1FFFF EPROM A (XU24) $FFA20000 - $FFA3FFFF EPROM B (XU23) $FFA40000 - $FFA5FFFF EPROM C (XU22) $FFA60000 - $FBA7FFFF EPROM D (XU21)

Table 2-2. EPROM/Flash Mapping - 256K x 8 EPROMs

GPI 3 Address Range Device Accessed

Removed 1 $FF800000 - $FF83FFFF EPROM A (XU24)

$FF840000 - $FF87FFFF EPROM B (XU23) $FF880000 - $FF8BFFFF EPROM C (XU22) $FF8C0000 - $FF8FFFFF EPROM D (XU21) $FFA00000 - $FFBFFFFF On-Board Flash

Installed 0 $FF800000 - $FF9FFFFF On-Board Flash

$FFA00000 - $FFA3FFFF EPROM A (XU24) $FFA40000 - $FFA7FFFF EPROM B (XU23) $FFA80000 - $FFABFFFF EPROM C (XU22) $FFAC0000 - $FBAFFFFF

2-6 Computer Group Literature Center Web Site

EPROM D (XU21)

Hardware Preparation

Table 2-3. EPROM/Flash Mapping - 512K x 8 EPROMs

GPI 3 Address Rang e Device Accesse d

Removed 1 $FF800000 - $FF87FFFF EPROM A (XU24)

$FF880000 - $FF8FFFFF EPROM B (XU23) $FF900000 - $FF97FFFF EPROM C (XU22) $FF980000 - $FF9FFFFF EPROM D (XU21) $FFA00000 - $FFBFFFFF On-Board Flash

Installed 0 $FF800000 - $FF9FFFFF On-Board Flash

$FFA00000 - $FFA7FFFF EPROM A (XU24) $FFA80000 - $FFAFFFFF EPROM B (XU23) $FFB00000 - $FFB7FFFF EPROM C (XU22) $FFB80000 - $FBF7FFFF EPROM D (XU21)

Table 2-4. EPROM/Flash Mapping - 1M x 8 EPROMs

GPI 3 Address Rang e Device Accesse d

Removed 1 $FF800000 - $FF8FFFFF EPROM A (XU24)

$FF900000 - $FF9FFFFF EPROM B (XU23) Not used EPROM C (XU22) Not used EPROM D (XU21) $FFA00000 - $FFBFFFFF On-Board Flash

Installed 0 $FF800000 - $FF9FFFFF On-Board Flash

$FFA00000 - $FFAFFFFF EPROM A (XU24) $FFB00000 - $FFBFFFFF EPROM B (XU23) Not used EPROM C (XU22) Not used EPROM D (XU21)

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Hardware Preparation and Installation

Table 2-5. EPROM/Flash Mapping - 1M x 8 EPROMs, On-Board Flash Disabled

GPI 3 Address Range Device Accessed

Removed 1 $FF800000 - $FF8FFFFF EPROM A (XU24)

$FF900000 - $FF9FFFFF EPROM B (XU23) $FFA00000 - $FFAFFF FF EPROM C (XU22) $FFB00000 - $FFBFFFFF EPROM D (XU21) Not used On-Board Flash

Installed 0 Not used On-Board Flash

$FF800000 - $FF8FFFFF EPROM A (XU24) $FF900000 - $FF9FFFFF EPROM B (XU23) $FFA00000 - $FFAFFF FF EPROM C (XU22) $FFB00000 - $FFBFFFFF EPROM D (XU21)

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Hardware Preparation

SRAM Backup Power Source Select Headers (J13, J1)

Jumper header J13 determines the sour ce for onboard st atic RAM backup

power on the cont rol l er’s PCB. Header J1 determines the sourc e for backup power on the 2MB SRAM mezzanine board (if installed).

The following backup power configurations are available for onboard SRAM through header J13. In t he factory conf iguration , the VMEbus +5V standby voltage serve s as primar y and secondary power source (the onboard battery is disconnected).

Notes For controllers without the optional VMEbus interface

(without the VMEchip2 ASIC), you must select the onboard battery as the backup power source.

Caution

Removing all jumpers may temporarily disable the SRAM. Do not remove all jumpers from J13, except for storage.

J13

Secondary Source Onboard Battery

Primary Source VMEbus +5V STBY

Secondary Source Onboard Battery

J13

Backup Power DisabledPrimary Source Onboard Battery

(For storage only)

Primary Source VMEbus +5V STBY

Secondary Source VMEbus +5V STBY

J13

Primary Source Onboard Battery

Secondary Source VMEbus +5V STBY

(Factory configuration)

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Hardware Preparation and Installation

The following backup power configurations are available for the 2MB mezzanine SR AM through header J1 ( located on the m ezzanine). In the f actory configuration, the onboard battery serves a s secondary power source.

Caution

Removing the jumper may temporarily disab le the SRAM mezzanine. Do not remove the jumper from J1, ex cept for storage.

1 2

Onboard Battery

(Factory configuration)

Backup Power Disabled

1 2

(For storage only)

1 2

VMEbus +5V STBY

SCSI Terminator Enable Header (J14)

The controller provides te rminators for the SCSI bus. The SCSI terminators are enabled/disabled by a jumper on header J14. The SCSI terminators may be configured as follows.

J14

On-Board SCSI Bus Terminator Enabled

(factory configuration)

On-Board SCSI Bus Terminator Disabled

J14

If the control ler i s to be us ed at one en d of the SC S I bus ,

the SCSI bus terminators must be enabled.

Caution

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Hardware Preparation

Memory Mezzanine Options

Two 100-pin connectors (J15 and J16) are provide d on the controller’s main module to accommodate optional memory mezzanine boards. The following memory mezzanine options are available:

❏ 4 MB or 8 MB ECC DRAM (stackable on top) ❏ 16 MB or 32 MB ECC DRAM

The mezzanine boards m ay either be used individually or be combined in a stack (no t more t han two deep). The f ollowing conn ector op tions govern stacking arrangements:

❏ The 4 MB and 8 MB boards has connectors on the top and bottom

(primary and secondary) side s of the board. It can be used as follows:

– Individually as the onl y mezzanine board (with nothing stacked

on top) – Sta ck ed with another 4 MB or 8 MB board on top – Stacked with either an 8 MB or 32 MB board on top

❏ The 8 MB or 32 MB board has conne ctors on the bottom only. It can

be used as follows: – Sta ck ed on top of a 4 MB or 8 MB board

– Individually as the only mezzanine board

Note When the mezzanines a re sta cked, the st arting a ddres s of the

larger board must be less than the starting address of the smaller board.

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Hardware Preparation and Installation

Installation Instructions

The following sect ions describe the insta lla tion of IndustryPacks (I Ps) on the MVME162LX Embedded Controller and the installation of the controller in a VME chassi s, and discuss syst em considerati ons relevant to the installation. Ensure that EPROM devices are installed as need ed. Ensure that all header jumpers are configured as desired.

IP Installation on the MVME162LX

Up to two IP modules may be insta lled on the c ontroll er. Ins tall the IPs on the controller as follows:

❏ Each IP has two 50-pin connector s that plug i nto two correspondin g

50-pin connectors on t he con trolle r: J5/ J6, J7/J8 . See F igure 2- 1 for the connector locations.

– Orient the IP(s) so that the tapered connector shells mate

properly. Plug IP_a into connectors J5 and J6; p lug IP_b into J7 and J8. If a double-sized IP is used, plug IP_ab into J5, J6, J7, and J8.

❏ Two additional 50-pin connectors (J3 and J4) are provided behind

the controller’s front panel for external cabling connections to the IP modules. There is a one-to-one correspo ndence between the signa ls on the cabling connectors and the signals on the associated IP connectors (J4 ha s the same IP_a s ignals as J5; J3 has the sa me IP_b signals as J7).

– Connect use r-supplied 50-pin cables to J3 and J4 as needed.

Because of the varying requirements for each different kind of IP, Motorola does not supply these cables.

– Bring the IP cables out the narrow slot in the controller’s front

panel and attach them to the appropriate external equipment, depending on the nature of the particular IP(s).

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Installation Instructions

MVME162LX Module Installation

With EPROMs and IndustryPacks installed and the controller’s headers properly configur ed, proce ed as follows to install the controller in the VME chassis:

1. Turn all equipment power OFF and disconnect the power cable from the AC power source.

Dangerous voltages, capable of causing death, are present

Warning

Caution

in this equipment. Use extreme caution when handling, testing, and ad ju st in g.

To prevent damage t o t he contr oller’ s compo nents, d o not install or remove the controller with the power applied.

2. Remove the chassis cover as instructe d in the user’s manual for the equipment.

3. Remove the filler panel from the card slot where you are going to install the controller.

– If you intend to use the MVME162LX as system controller, it

must occupy the leftmost c ard slot (slot 1). The system cont roller must be in slot 1 to correctly initia te the bus-grant daisy-chain and to ensure proper operati on of the IACK daisy-c hain driver.

– If you do not intend to use the MVME162LX as system

controller, it can occupy any unused double-height card slot.

4. Slide the controller into the selected card slot. Ensure it is seated properly in the P1 and P2 connectors on the backplane. Do not damage or bend connector pins.

5. Secure the controller in the chassis with the screws pro vide d, making good contact wit h the t ransverse m ounting rails to m inimize RF emissions.

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Hardware Preparation and Installation

6. On the chassis ba ckplane, remove the INTERRUPT ACKNOWLEDGE (IACK) and slot occupied by the controller.

7. Connect the appropriate cable(s) to the controller’s panel

connectors for the EIA-232-D serial ports, SCSI port, and LAN Ethernet port.

– Note that some cables are not provided with the MVME162LX

module and must be made or purchased by the user (Motorola recommends shielded cable for all peripheral connections to minimize radiation).

8. Connect the peripheral(s) to the cable(s).

9. Install any other required VMEmodules in the system.

10. Replace the chassis cover.

11. Connect the power cable to the AC power source and turn the equipment power ON.

BUS GRANT (BG) jumpers from the header for the card

System C o nsidera tions

The MVME162LX Embedded Contr oller draws power from both the P1 and the P2 connectors on the VMEbus backplane. P2 is also used for the upper 16 bits of data in 32-bit transfers, and for the upper 8 address lines in extended addressing mode. T he controller may n ot operate prop erly without its main board connected to VMEbus backplane connectors P1 & P2.

Whether the controller oper ates a s a VMEbus master or as a VMEbus slave, it is c onfigur ed for 32 bits of addr ess and 32 bi ts of data (A32/D32) . However, it h andles A16 or A24 dev ices in t he a ddress r ange s indic ate d in Chapter 3. D8 and/or D16 devices in the system must be handled by the MC68040/ MC68LC040 software. Refer to the memory maps in the MVME162LX Embedded Controller Programmer’s Reference Guide.

The controller contains shared onboard DRAM whose base address is software-select able. Both the onboard processor and offboard VMEbus devices see this local DRAM at base physical address $00000000, as programmed by the MVME162Bug firmware. This may be changed via software to any other base address. Ref er to the MVME162LX Embedded Controller Programmer’s Reference Guide for additional information.

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Installation Instructions

If the MVME162LX tries to access offboard resources in a nonexistent location and is not system controller, and if the system does not have a global bus timeout, the MVME162LX waits foreve r for the VMEbus cycle to complete. This will cause the syste m to lock up. The re is only one situation in whi ch the sys tem might lack this globa l bus ti meout: when the MVME162LX is not the system controller and ther e is no global bus timeout elsewhere in the system.

Multiple controll ers may be installed in a single VME chassis. In general, hardware multiprocessor features are supported.

Note

If you are installing multiple controllers in an MVME945 chassis, do not install the controller in slot 12. The height of the IP modules may cause clearance difficulties in that slot position.

Other MPUs on the VMEbus can interrupt, disable , communicate with, and determine the ope rational status of the pr ocessor(s). One registe r of the GCSR (global cont rol/status r egister) se t includes four bits tha t functi on as location monitor s to allow one c ontroller pr ocessor to b roadcast a sign al to any other c ontroller proc essors. All eight regi sters a re accessible fr om any local processor as well as from the VMEbus.

The controller provides +5 Vdc power to the remote LED/switch connector (J2) as well as to IP_b through a 2A fuse (F3) located near J7. Connector J2 is the interfac e for a remote control and indicator panel. If none of the LEDs light and the ABORT and RESET switches do not operate, check fuse F3.

The controller provides +12 Vdc power to the Ethernet transceiver interface through a 1A fuse (F1) located near J3. The

FUSES LED lights to

indicate that +12 Vdc is availa ble . I f the Ethernet transceiver fails to operate, check fuse F1.

The controlle r provides +5 Vdc to the SCSI bus fuse F4, locat ed near J7. One function of the the front panel is to monitor the SCSI bus controller connecte d to a SCSI bus, the

FUSES LED lights when there is

TERMPWR signal through

FUSES LED (part of DS2) on

TERMPWR signal; with the

SCSI terminator power. Because any device on the SCSI bus can provide

TERMPWR, the LED do es not directly indicate the condition of the fuse. If

the LED flickers during SCSI bus operation, check the fuse. This display also indicate s the status of the +5 Vdc (F2 , F3), +12 Vdc (F5) , and -12 Vdc (F6) fuses for the IP modules.

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Hardware Preparation and Installation

The controller uses two Zilog Z85230 serial port controllers to implement the four serial communications interfaces. Each interface supports CTS, DCD, RTS, and DTR control signals as well as the TXD and RXD transmit/receive

data signals. Because the serial clocks are omitted in the controller’s implementation, serial communications are str ictly asynchron ous. The Z 85230 is interfaced as D TE (data te rm inal e quipm ent) w ith EIA -232- D sign al levels. The serial ports are routed to four RJ45 connectors on the front panel.

This chapter provides connection diagrams for the four serial ports on the controller. These ports are connected to external devices through cables connected to the front panel. The figures showing th is are as follows:

❏ Figure 2-2 shows th e pin assignments required in a cable to adapt a

DB25 DTE device to the RJ45 connectors.

DB25 DTE DEVICE RJ45 JACK

DTR

CTS

RXD

TXD

RTS

DCD

3 2 7 4 8

1 2 3 4 5 6 7 8

Figure 2-2. DB25-DTE-to-RJ45 Adapter

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Installation Instructions

❏ Figure 2-3 shows the pin assignments requ ired in a cable to adapt a

DB25 DCE device to the RJ45 connectors.

DB25 DCE DEVICE RJ45 JACK

DSR

DCD 1

RTS

TXD

RXD

CTS

DTR

2 3 7 5

2 3 4 5 6 7 8

Figure 2-3. DB25-DCE-to-RJ45 Adapter

❏ Figure 2-4 diagrams the pin as signments requir ed in a typi cal eight-

conductor serial cable having RJ45 connectors at both ends. Note that all wires are crossed.

RJ45 CONNECTOR RJ45 CONNECTOR

DCD

RTS

TXD

RXD

SG CTS DTR

2 3SG 4 5 6 7 8

1 2 3 4 5 6 7 8

Figure 2-4. Typical RJ45 Serial Cable

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Hardware Preparation and Installation

2-18 Computer Group Literature Center Web Site

3Debugger General Information

Overview

This chapter describes the basic features of the debugger used on the MVME162LX Embedded Controller. The firmware is known as the

"MVME162Bug" or simply the "162Bug". It include s diagnostics for testing

and configuring Industr y Pack (IP) modules.

Description of 162Bug

The162Bug is a powerful evaluati on and debuggin g tool for syst ems built around the MVME162LX CISC-based microcompute rs . Fac ilities are available for loading a nd executing user programs under complete operator control for system evaluation. The 162Bug includes commands for display and modification of memory, breakpoint and tracing capabilitie s, a power fu l assembler/disassembler useful for patching programs, and a power-up self test which verifies the integrity of the system. Various 162Bug routines that handle I/O, data conversion, and string functions are availa ble to user programs through the TRAP #15 system calls.

The 162Bug consists of three parts:

1. A command-driven user-interac tive software debugger (referred to as the "debugger"). Its usage is described in Chapter 4.

2. A command-driven diagnostic package for the MVME162LX controller (referred to as the "diagnostics"). This is described in the MVME162Bug Diagnostics Manual.

3. A user interface which accepts com mands from the system console terminal.

When using the 162Bug, you can operate out of the debugger directory or the diagnosti c directory. If you are oper ating in the de bugger director y, the debugger prompt commands at your disposal.

162-Bug> is disp layed and you have all of the debugger

3-1

Debugger General Information

If you are in the diagnostic directory, the diagnostic prompt

162-Diag> is displayed and you have all of the diagnostic commands at

your disposal as well as all of the debugger commands.

You may switch bet ween direc tories by usin g the S witch Di rector ies ( SD) command, or you may examine the commands in the particular direc tory that you are currently in by using the Help (HE) command.

Because 162Bug is command-driven, it perfor ms its vario us operatio ns in direct response to user commands entered at the keyboard. When you enter a command, the162Bug executes it and then returns you to the prompt. However, if you enter a command that causes execution of the user ta rget code (e.g., "GO"), then control may or may not return to the162Bug,

depending on the outcome of the user’s program. If you have used one or more of Motorol a's other de bugging packages, you

will find the CISC 162Bug very similar. Some effort has also been made to make the interactive commands more consistent. For example, delimiters between commands and arguments may now be commas or spaces interchangeably.

162Bug Implementation

The 162Bug is written mostly in the "C" programming language, providing the benefits of porta bility and maintainabilit y. Where necessary, assembler language is used in the form of separate ly compiled modules containing only assembler cod e (no mixed lang uage modul es are used).

Physically, the 162Bug is contained in a single 27C040 DIP EPROM installed in socket XU24, providing 512KB (128K longwor ds) of stor age. Optionally, the 162Bug can be loaded and execute d in a single fl ash memory chip. The executable code is checksummed at every powe r-on or reset firmware entry, and the result (which includes a pre-calculated checksum contained in the memory devices), is te sted for an expected zero. Thus, users are cautioned against modification of the memory devices unless re-check sum preca utions are taken.

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Installation and Start-up

Even though the 162Bug is installed on the MVME162LX Embedded Controller, you m ust foll ow the st eps listed below in o rder f or the 162B ug to operate properly with the controller.

Installation an d St art-up

Caution

To prevent damage t o t he contr oller’ s compo nents, d o not insert or remove the controller while power is applied.

1. Turn all equipment power OFF. Refer to th e Hardware Preparation section in Chapter 2 and install/remove jumpers on headers as required for your particular application.

Jumpers on heade r J11 af fect t he 162Bug operati on as l isted be low. The default condition for the controller (MVME162-2xx) is with seven jumpers inst alled. Th is is between p ins 1-2, 3-4, 5-6, 9-10, 1112, 13-14, and 15-16. No jumper is installe d on pins 7-8.

These readabl e jumpers can be read a s a register (at $FFF4202 D) on the Memory Controller ASIC (MCchip) . The bit values are read as a one when the jumper is removed (off), and as a zero when the jumper is installed (on). This jumper block (header J11) contains eight bits. Refer also to the MVME162LX Embedded Controller Programmer’s Reference Guide for additional information on the MCchip.

The MVME162Bug reserves/define s the four lower order bits (GPI3 to GPI0). The table on the following page provides a description for the bits reserved/defined by the debugger.

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Debugger General Information

Bit J11 Pins D escription

Bit #0 (GPI0) 1-2 When this bit is a one (high), it instructs the debugger to use

local Static RAM for its work page (i.e., variables, stack,

Bit #1 (GPI1) 3-4 When this bit is a one (high), it instructs the debugger to use

Bit #2 (GPI2) 5-6 Reserved for future use. Bit #3 (GPI3) 7-8 When this bit is a zero (low), it informs the de bugger tha t it is

vector tables, etc.).

the default setup/operation parameters in fla sh memory or ROM versus the user setup/operation parameters in NonVolatile RAM (NVRAM). This is the same as depressing the RESET and AB O RT switches at the same time. This feature can be used in th e ev en t th e us er se t up is co r ru p ted or does not mee t a san i ty ch ec k . Refer to the EN V comman d (described in Appendix A) for the flash memory/ ROM defaults.

executing out of the fla s h me mori es. When this bit is a one (high), it in forms the debugger that it is executing out of the

PROM. Bit #4 (GPI4) 9-10 Open to your application. Bit #5 (GPI5) 11-12 Open to your application. Bit #6 (GPI6) 13-14 Open to your application. Bit #7 (GPI7) 15-16 Open to your application.

Note that when the contr oller sta rts in a cold re set, the 162Bug runs in Board Mode. Using the Environment (ENV) or MENU commands can make the162Bug run in System mode. Refer to Appendix A for additional information.

2. Configure header J1 by installing/removing a jumper between pins 1 and 2. A jumper installed/removed enables /disables the system controller function of the MVME162LX.

3. Refer to the setup procedure for y our particular chassis or system for details concern ing the installation of the MVME162LX Embedded Controller.

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Installation an d St art-up

4. Connect the terminal that is to be used as the 162Bug system console to the defaul t debu g EIA-232-D port at serial port 1 on the front panel of the controll er. Refer t o Chapter 2 for other connection options. Set up the terminal as follows:

– eight bits per character – one stop bit per character – par ity disabled (no parity) – baud r ate 9600 ba ud (default baud rate of controller’s ports at

power-up)

After power- up, the bau d ra te of the debug port can be re conf igured by using the Port Format (PF) command of the 162Bug debugger.

Note In order for high speed se rial communication between the

162Bug and the te rminal to work, th e termina l must do s ome form of handshaking. If the ter minal being used does not do hardware handshaking via the CTS line, then it must do XON/XOFF handshaking. If you get garbled messages and missing characters, check the terminal to ensure XON/XOFF handshaking is enabled.

5. If you want to connect devices such as a host computer system and/or serial print er to the other EIA-232-D port connectors, you must connect the appropriate cable s and configure the port(s) as shown in step 4 (above). After power-up, this(these) port( s) can be reconfigured by progr amming the MVME162LX Z85230 Serial Communications Controlle rs (SCCs), or by using the 162Bug PF command.

6. The EPROM/flash header J12 must be set to configuration 3, with jumpers between J12 pins 5 and 6, 8 and 10, and 9 and 11. This configures it for 512K x 8 EPROMs.

7. Power up the system. The 162Bug executes vario us self-checks and displays the debugger pro mpt "

162-Bug>" (if it is operating in

Board Mode). However, if the ENV command has put the 162Bug in System Mode, the system performs a self-test and tries to autoboot. Refer to the ENV and MENU commands (Table 4-3).

If the confidence test f ails, the test is aborted when the first fault is encountered. If possible, an appropriate message is displayed, and control then returns to the menu.

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Debugger General Information

Note This product contains a Real Time Clock (RTC) device on

board. The devi ce i s b acked up wit h a s elf-c ontained bat tery. Before shipment of the controlle r , the RTC device was

stopped to preserve battery life.

The board’s “Self-Tes ts” (ST)and operating syste ms require that the RTC be operating. Before using the controlle r after the initial installation, start the clock by using the set SET command of the debugger. Set the date and time using the following syntax:

162-Bug> SET [mmddyyhhmm] I [<+/-CAL>;C]

Example: Nov. 7, 1998, 10:37 a.m. = SET 1107981037 The C option allows you to calibrate the real-time clock. R efer to the

MVME162Bug Debugging Package User’s Manual for details. When storing the controller, ensure that the RTC is put into the

power save mode. This will extend the life of the battery. To put the RTC into the power save mode, use the PS command of the debugger. For example:

162-Bug> PS <Return>

Autoboot

Autoboot is a software routine that is contained in the 162Bug Flash/PROM to provide an independent mechanism for booting an operating syste m. This autoboot rou tine automatically sc ans for control lers and devices in a specified sequence until a valid bootable device containing the boot media is found or the list is exhausted. If a valid bootable device is found, a system boot from that device is started. The controller scanning sequence goes from the lowest controll er Logical Unit Number (LUN) detected to the highest LUN detected. Controllers, devices, and their LUNs are listed in Appendi x B.

At power-up, Autoboot is enabled, and providing the drive and controller numbers encountered are valid, the following message is displayed upon the system console:

"Autoboot in progress... To abort hit <BREAK>"

Following this message there is a delay to allow you an opportunity to abort the Autoboot process if you wish. Then the actual I/O is begun: the program pointed to within the volume ID of the media specified is loaded into RAM and control passed to it. If, however, duri ng this time you want to gain control without Autobo ot, you can press the <BREAK> key or the software ABORT or RESET switches.

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ROMboot

Autoboot is controlled by para meters contained in the ENV co m man d. These parameters al low the selection of speci fic boot devices and files, and allow programming of the Boot delay. Refer to the ENV comma nd in Appendix A for more details.

Caution

Although streaming tape can be used to autoboot, the same power supply must be connected to the streaming tape drive, controller, and the MVME162LX. At powerup, the tape controller will position the streaming tape to the load point where the volume ID can correctly be read and used.

If, however, the MVME162LX loses power but the controller does not, and the tape happens to be at the load point, the sequ en ces o f com m ands req ui re d (a tta ch and rewind) cannot be give n to the controller and aut oboot will not be successful.

ROMboot

As shipped from t he factor y, the 162Bug oc cupies a n EPROM insta lled in socket XU24. This leaves three sockets (XU21 - XU23) and the flash available for your use. Contact your Motorola sales office for assistan ce. This function is confi gured/enabled by the Envir onment (ENV) command (refer to Appendix A) and executed at power-up (opt ionally also at reset) or by the RB command assuming there is valid code in the memo ry devices (or optionally elsewhere on the controller or VMEbus) to support it. If ROMboot code is installed, a user-written routine is given control (if the routine meets the format req uirements). One use of ROMboot might be resetting SYSFAIL* on an unintelligent controller module. The NORB command disables the function.

For a user’s ROMboot module to gain control through the ROMboot linkage, four requirements must be met:

1. Power must have just been applied (but the ENV command can change this to also respond to any reset).

2. Your routine must be located within the controller’ s Flash/PROM

memory map (but the ENV command can change this to any other portion of the onboard memory, or even offboa rd VMEbus memory).

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Debugger General Information

3. The ASCII string "BOOT" must be located within the specified memory range.

4. Your routine must pass a checksum test, which ensures that this

routine was really intended to receive control at power-up.

For complete details on how to use ROMboot, refer to the Debugging Package for Motorola 68K CISC CPUs User’s Manual.

Network Boot

Network Auto Boot is a software routine contained in the 162Bug Flash/PROM that provides a mechanism for booting an operating system using a network (loca l Ethernet interface) as the boot device. The Network Auto Boot routine automatical ly scans f or controllers and devices in a specified sequence unti l a valid b ootable devic e containing a boot media is found or the list is exhausted. If a valid bootable device is found, a boot from that device is started. The controller scanning sequence goe s from the lowest controlle r Logical Unit Number (L UN) detected to the highe st LUN detected . Re fer to Appendix C for default LUNs).

At power-up, Network Boot is enabled, and providing the drive and controller numbers encountered are valid, the following message is displayed upon the system console:

"Network Boot in progress... To abort hit <BREAK>"

Following this m essage ther e is a delay to a llow you to abort the Auto B oot process if you wish. Then the actual I/O is begun: the program pointed to within the volume ID of the media specified is loaded into RAM and control passed to it. If, however, dur ing this time you want to gain control without Network Boot, you can press the <BREAK> key or the software ABORT or RESET switches.

Network Auto Boot is controlled by parameters contained in the NIOT and ENV commands. These parameters allow the selection of specific boot devices, systems , and files, and all ow programming of the Boot delay. Refer to the ENV command in Appendix A for additional information.

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Restarting the System

You can initialize the system to a known state in three different ways: reset, abort, and brea k. Ea ch has char acteristics which make it more appropriate than the others in certain situations.

The debugger has a special feature upon a reset condition. This feature is activated by depressing the RESET and ABORT switches at the same time. This f eature instr ucts t he de bugger to use the default setup/ ope ration parameters in ROM versus your setup/operation parameters in NVRAM. This feature can be used in the event your setup/operation parameters are corrupted or do not meet a sanity check. Refer to the ENV comman d (Appendix A) for the ROM defaults.

Reset

Resta r ting the Sys t em

Caution

When the RESET button on the controller is depressed for an extended length of time (varies from board to board), DRAM refresh may be inhibited and memory contents may be lost . To ensure th at the contents of DRAM will not be altered, press and release the RESET button as quickly as possible.

Pressing and releasi ng the controll er’s front panel RESET switch initi ates a system reset. COLD and WARM reset modes are availa ble. By default, the 162Bug is in COLD mode. During COLD reset, a total system initializati on take s place, as i f the c ontroll er had jus t bee n powered up. All static variables (including disk device and controller parameters) are restored to their default states. The breakpoint t able and of fset registe rs are cleared. The target registers are invalidated. Input and output character queues are cleared. Onboard devices (timer, serial ports, etc.) are reset, and the two serial ports are reconfigured to their default state.

During WARM reset, the 162Bug variables and tables are preserved, as well as the target state registers and breakpoints.

Reset must be used if the processor ever halts, or if the 162Bug environment is ever lost (vector table is destroyed, stack corrupted, etc.).

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Debugger General Information

Abort

Abort is invoked by pressing and releasing the ABORT switch on the

controller’s front pa nel. Whenever Abort is invoked when executing a user

program (running target code), a "snapshot" of the processor state is captured and stored in the target registers. For this reason, abort is most appropriate when terminating a user program that is being debugged. Abort should be u sed to regain c ontrol if t he program gets caught in a loop, etc. The target PC, regi ster content s, etc., help to pi npoint the malf unction.

Pressing and releasing the ABORT switch gene rate s a local board condition which may interrupt the proce ssor if enabled. The target registers, reflecting the machine state at the time the ABORT switch was pressed, are displayed on the scree n. Any brea kpoints installed in your code are removed and the breakpoint table remains intact. Control is returned to the debugger.

Break

A "Break" is generated by pressing and releasing the BREAK key on the terminal keyboard. Break does not generate an interrupt. The only time break is reco gnized is when characters are sent or received by the c onsole port. Break removes any breakpoints in your code and keeps the breakpoint table inta ct. Break also takes a snapshot of the machine state if the function was entered using SYSCALL. This machine state is then accessible to you for diagnost ic purposes. Many times it may be d esirable t o terminate a de bugger c ommand prior to its completion; for ex ample, during the display of a lar ge block of memory. Break allows you to terminate the command.

SYSFAIL* Assertion/Negation

Upon a reset/powerup condition the debugger asserts the VMEbus SYSFAIL* line (refer to the VME b us spe ci fication). SYSFAIL* stays asserted if any of the following has occurred:

❏ confidence test failure ❏ NVRAM checksum error ❏ NVRAM low battery condition ❏ local memory configuration status ❏ self test (if system mode) has completed with error ❏ MPU clock speed calculation failure

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After debugger init ialization is done an d none of the above situations ha ve occurred, the SYSFAIL* line is negated. This indicates to the user or VMEbus masters the state of the debugger. In a multi-computer configuration , other VMEbus ma sters could v iew the pertine nt contro l and status registers to de termine which CPU is asserting SYSFAIL*. SYSFAIL* assertion/ne gation is also affected by the ENV command. Refer to Appendix A for additional information.

MPU Clock Speed Calculation

The clock speed o f the micropr ocessor is calc ulate d and che cked against a user definab le param et er h oused in NVRAM (re fer to th e CNFG command in Appendix A). If the check fails, a warning messa ge is displayed. The calculated cl ock speed is also checked against known clock speeds and tolerances.

Memory Requirements

The program portion of the 162Bug is approximately 512KB of code, consisting of downlo ad, debugger, and diagnostic pa ckages. It is contained entirely in Flash or PROM.

Memory Requirements

The 162Bug execute s from $FF800 000 whether in Flash or PROM. If you remove the jumper at J11 pin s 7 and 8, the a ddress spa ces of th e Flash a nd PROM are swapped. For the MVME162-2XX (MVME162LX), factory ship configurat ion is with jum per J11 pins 7- 8 removed (162B ug operates out of EPROM).

The 162Bug initial stack comple tely changes 8KB of SRAM memory at addresses off set $C000 from t he SRAM base addr ess, at power up or reset.

ECC DRAM mezzanines are mapped contiguously starting at zero ($00000000), largest first. With two mezzanines of the same size, the bottom mezzanine is first.

Default on-board

Type of Memory Present Default DRAM

Base Address

Single ECC DRAM mezzanine $00000000 FFE00000 Two ECC DRAM mezzanines

stacked

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$00000000 $FFE00000

SRAM Base Address

Debugger General Information

The 162Bug require s 2KB of NVRAM for stora ge of boa rd c onfigura tio n, communication, and booting parameters. This storage area begins at $FFFC16F8 and ends at $FFFC1EF7.

The 162Bug also requires a minimum of 64KB of contiguous read/write memory to operate. The ENV command controls where this block of memory is located. Regardless of where the onboard RAM is located, the first 64KB is used for 162Bug stack and static variable space. The rest is reserved as user space. Whenever the controller is reset, the target PC is initialized to the a ddress correspondi ng to the be ginning of t he user space; the target stack pointer s are initialized to addresses within the user space, with the target Int errupt Stac k Pointer (IS P) set to the top of the user space.

Terminal Input/Output Control

When entering a command at the prompt, the following contr ol codes may be entered for limited command line editing:

Note The presence of the caret ( ^ ) symbol before a character

indicates that the Contr ol (CTRL) key must be held down while striki ng the character key.

^X (cancel

line)

^H (backs pac e) The cursor is moved back one position. The character

<DEL> (delet e or

rubout)

^D (redisplay) The entire command line as entered so far is

^A (repeat) Repeats the previous line. This ha ppens only at the

The cursor is backspac ed to the begi nnin g of the l ine. If the terminal port is configured with the hardcopy or TTY option (refer to PF command), then a c arriage return and line fe ed is is sued along with another prompt.

at the new cursor position is erased. If the hardcop y option is s e lected, a "/" ch ar acter is typ ed along wit h the deleted character.

Performs the same function as ^H.

redisplayed on the following line.

command lin e. The last line entered is redisp layed but not execute d. T he cursor is positione d at the end of the line. You may enter the line as is or you can add more characters to it. You can edit the li ne by backspacing and typing over old characters.

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When observing output from any 162Bug command, the XON and XOFF characters which are in effect for the terminal port may be entered to control the output, if the XON/XOFF prot ocol is enabled (default). These character s are initial ized to ^S and ^Q respectively by 162Bug, but you may change them with the PF command. In the i nitia lized ( def ault) mo de, operation is as follows:

^S (wait) Console output is halted. ^Q (resume) Console output is resumed.

Disk I/O Support

The 162Bug can initiate disk input /output by communicating with intelligent disk controller modules over the VMEbus. Disk support facilities built into 162 Bug consist of command-leve l disk operat ions, disk I/O system calls (only via one of the TRAP #15 instructions) for use by user programs, and defined data structures for disk parameters.

Parameters suc h as the address where the module is mapped and the type and number of devices atta ched to the controlle r module a re kept in table s by the 162Bug. Default value s for these parameters are assigned at powe rup and cold-start reset, but may be alte red as described in the section on default param et ers , later in th is ch apt er.

Disk I/O Support

Appendix B contains a list of the controllers presently supported, as well as a list of the default configurations for each controller.

Blocks Versus Sectors

The logical block defines the unit of information for disk devices. A disk is viewed by the 162Bug as a st orage area divided into logical blocks. By default, the logical block size is se t to 256 bytes for every block device in the system. The block size can be changed on a per device basis with the IOT comman d.

The sector def ines the unit of inf ormat ion for the media, as viewed by the controller. The sector siz e varies for different controllers, and the value for a specific device can be displayed and changed with the IOT command.

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Debugger General Information

When a disk tr an sfer i s reques t ed, the start and size of the transfer is specified in blocks. The 162Bug trans lates this into an equivalent sector specification, which is then passed on to the controller to initiate the

transfer. If the conversio n from blocks to sectors yields a fractional sector count, an error is returned and no data is tra n sferred.

Device Probe Function

A device probe with entry into the device descriptor table is done whenever a specified device is accessed (i.e., when system calls such as .DSKRD , .DS K W R, .DSK C FI G , .DS K FM T , and .DSK C T RL, and debugger commands BH, BO, IOC, IOP, IOT, MAR, and MAW are used).

The device probe mechanism utilizes the SCSI commands "Inquiry" and "Mode Sense". If the specified controller is non-SCSI, the probe simply returns a status of "devic e present and unknown". The device probe makes an entry into the device descriptor table with the pertinent data. After an entry has been made, the next time a probe is done it simply returns with "device present" status (pointer to the device descriptor).

Disk I/O via 162Bug Comm and s

These following 162Bug commands are provided for disk I/O. Detailed instructions for their use are found in th e Debugging Package fo r Motorola 68K CISC CPUs User’ s Manual . When a command is issued to a particular controller LUN and device LUN, these LUNs are remembered by the 162Bug so that the next disk c ommand defaults to use the same controll er and device.

IOI (Input/Output Inquiry)

This command is used to probe the system for all possible CLUN/DLUN combinations and display inquir y dat a for devices which support it. The device descriptor tabl e only has spa ce for 16 device descriptors; with the IOI command, you can view the table and clear it if necessary.

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IOP (Physical I/O to Disk)

IOP allows you to read or write blocks of data, or to format the specified device in a certain way . IOP crea tes a com ma nd p acket from the arguments you have specified, and then invokes the proper system call function to carry out the operation.

IOT (I/O Te ach)

IOT allows you to change any configurable parame ters and attributes of the device. In addition, it al lows you to see the controller s availabl e in the system.

IOC (I/O Control)

IOC allows you to send command packets as defined by the particular controller dire ctly. IOC can also be used to look at the resultant device packet after using the IOP command.

BO (Bootstrap Operating System)

Disk I/O Support

BO reads an operating system or control program from the specified device into memory, and then transfers control to it.

BH (Bootstrap and Halt)

BH reads an operating system or contro l program from a spec ified device into memory, and then returns control to the 162Bug. It is used as a debugging tool.

Disk I/O via 162Bug System Calls

All operations that actually access the disk are done directly or indirectly by the 162Bug TRAP #15 system calls (the command-level disk operations provid e a convenient way of using these system calls without writing and executing a progr am).

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Debugger General Information

The following syst em calls a re provided to allow us er pr ograms to do disk I/O:

.DSKRD Disk read. System call to read blocks from a disk into

memory.

.DSKWR Disk write. System call to write blocks from memory onto a

disk.

.DSKCFIG Disk configure. This function allows you to change the

configuration of the specified device.

.DSKFMT Disk format. This function allows you to send a format

command to the specified device.

.DSKCTRL Disk control. This function is used to implement any special

device control functions that can not be accommodated easily with any of the other disk functions.

Refer to the Debugging Package for Motorola 68K CISC CPUs User’s Manual for information on using the above and other system calls.

To perform a disk operation, the 162Bug must eventua lly present a particular disk co ntroller module wit h a controller command pac ket which has been especially prepared for that type of controller module (this is accomplished in the respective contr oller dri ver module). It i s importa nt to note that a command pa cket for one type of contr oller modul e usually does not have the same format as a command packet for a different type of module. The system call facilities which do disk I/O accept a generalized (controller-i ndependent) packet format as an argument, and translate it into a controller-speci fi c packet, which is then sent to the specified device. Refer to the system call descriptions in the Debugging Package for Motorola 68K CISC CPUs User’s Manual for additional information on the format and construction of these standardized "user" packets.

The packets which a controller module expects to be given vary from controller to cont roller. The disk driver module for the par ticular ha rdware module (board) must take the standardi zed packet give n to a trap funct ion and create a new packet which is specificall y tailored for the disk drive controller it i s sent to. Refer to documen tation on the particula r controller module for the format of its packets, and for using the IOC comman d.

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Motorola MVME162LX-202, MVME162LX 200 Series, MVME162LX-200, MVME162LX-201, MVME162LX-210 Installation And Use Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Preface

Contents

FIGURES

TABLES

Introduction

Overview

Related Documentation

Models Available

Document Requirements

Available Software

Required Equipment

Features

Specifications

Cooling Requirements

Special Considerations for Elevated-Temperature Operation

Manual Terminology

Block Diagram

Functional Description

Switches and LEDs

ABORT Switch

RESET Switch

Front Panel Indicators

Data Bus Structure

MC68040 or MC68LC040 CPU

No VMEbus Interface Option

Memory Options

DRAM Options

SRAM Options

SRAM Batteries

EPROM and Flash Memory

Battery Backed Up RAM and Clock

VMEbus Interface and VMEchip2

I/O Interfaces

Serial Communications Interface

IndustryPack (IP) Interfaces

Ethernet Interface

SCSI Interface

SCSI T e rminat ion

Local Resources

Programmable Tick Timers

Watchdog Timer

Software-Programmable Hardware Interrupts

Local Bus Timeout

Local Bus Arbiter

Connectors

Memory Maps

Local Bus Memory Map

Normal Address Range

Detailed I/O Memory Maps

IPIC Overall Memory Map

BBRAM, TOD Clock Memory Map

Interrupt Acknowledge Map

VMEbus Memory M ap

VMEbus A ccesses to the Local Bus

VMEbus Short I/O Memory Map

Software Initialization

Multi-MPU Programming Considerations

Local Reset Operation

EMC Compliance

Introduction

Unpacking Instructions

Hardware Preparation

System Controller Select Header (J1)

General-Purpose Readable Jumpers Header (J11)

EPROM/Flash Configuration Header (J12)

SRAM Backup Power Source Select Headers (J13, J1)

SCSI Terminator Enable Header (J14)

Memory Mezzanine Options

Installation Instructions

IP Installation on the MVME162LX

MVME162LX Module Installation

System C o nsidera tions

3Debugger General Information

Overview

Description of 162Bug

162Bug Implementation