Motorola MVME135, MVME135A, MVME135-1, MVME136, MVMEl36A User Manual

MVMEI35 /

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MVME135, MVME135-1

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MVME135A, MVME136,

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MVMEl36A

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32-Bit

Microcomputers

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User's

Manual

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(f!yMOTOROLA

HVHE135/135-1fKV"E136

CUSTOMER

lmER

HVHEl3l/l)

SEPTEMBER

1987

This

letter

;s

directed to customers

using

MVMEl35Bug,

Revision 1.0,

and

to

software designers writing

code

for the

MC6B681

OUART

on

the

MVME135.

The

purpose

is

to

clarify

an

error

in the data sheet

on

the

H(68681

which

defines

the reset condition of the Interrupt Status Register

(lSR)

as

$00.

Two

potential situations

exist that

can

cause

this

register

to not

be

read

as

SOO

after a power-up

or

reset

condition.

The

first

case involves

bits

two

and

six of the

lSR.

the Delta

Break

bits

for

each

seria l port.

Due

to

an

anomaly

in the chip

circuitry,

either

of these

bits

may

be

set

after a power-up

condition.

This

anomaly

has

been

verified

by

both

vendors

of the chip (Motorola

and

Signetlcs)

and

should

not

be

considered

fatal faults in the

part.

as

their

power-up

conditions will not affect

normal

operation of these

bits.

The proper

initialization

sequence for these

bits

is

to

write all port control

registers

to desired values, then issue a "

Reset

Channel

x

Break

Change

Interrupt"

command

for

each

channel.

At

this point,

the

state

of these

bits

will

be

valid

and

further operations of these

bits

will

be

accurate.

The

second

case involves

bit

three of the

ISR,

the Counter/

Timer

Ready

bit.

This

bit

may

be

set

after a power-up

or reset condition

and

prior to

being

read

by

software

In

the

lSR.

The

reason for

this

is that the

HC68681

powers

up

in

the free running timer

mode.

and

the timer

may

reach the

end

of a count-

down

sequence,

setting

the

Counter/Tim~r

Ready

bit

at

any

time

after

release

of the reset line. This

status

condition is

normal

to the device

and

will

not

affect

normal

operation of the part.

The

proper

Initialization

sequence

for

the

HC68681

timer Is to

initialize

the desired timer

modes,

then

perform

a

read

of

the

Stop

Counter

command

address to

clear

ISR

bit

three.

At

this

pOint. further

setting

of the

bit

will

be

due

to

normal

counter/timer

operation

and

may

be

considered valid.

Due

to

operation of the

ISR

In

the

MC68681

as

described

above.

intermittent

failures of the

MVMEI358ug.

Revision 1.0, confidence

test

at

test

SAO

may

be

observed.

These

failures are related to the

ISR

not containing

SOO

after

reset.

As

described, this is

not

a fatal

error,

and

the

MVHE135Bug

will

operate normally

after

exiting the confidence

test.

Future releases of the

MVMEI35Bug

will correct for the operation of the

HC68681

and

will

not

demonstrate

this

error.

We

apologize for

any

inconvenience this

may

cause.

:m,.

...

'''UO''._

..

__

lY

-

--

-----

----------------------------

BUSINESS REPLY MAIL

FIRST CLASS MAIL PERMIT NO . 2565 PHOENIX, ARIZONA

POSTAGE WILL

BE

PAID

BY

ADDRESSEE

®

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ut

~~~~

.

DW164

2900 South

Diablo

Way

Tempe.

AZ

85282-974 1

11" I, ,1,1"

,I, II" I,,, 1,11,1"

/,

"1.

1,,1

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II, I"

II

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NO

POSTAGE

NECESSARY

IF MAILED

IN

THE

UNITED

STATES

m

Z

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C/l

Presentation

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If

you have found technical or typographical errors, please list them here.

PaRe Number DescriPtion of Error

SAFETY

SUMMARY

SAFETY DEPENDS ON YOU

The

following

general

safety

precautions

must

be

observed

during

all

phases

of

operation. service,

and

repair

of

this

equipment.

Failure

to

comply

with

these

precautions

or

with

specific

warnings elsewhere

In this

manual

violates

safety

standards

of

design,

manufacture,

and

Intended

use

of

the equipment.

Motorola

Inc. assumes

no

/lability

for

the

customer's

failure

to

comply

with

these requirements. The

safety

precautions

listed

below

represent

warnings

of

certain

dangers

of

which

we

are

aware. You,

as

the user

of

the

product.

should

follow

these

warnings

and

all

other

safety

precautions

necessary

for

the safe

operation

of

the

eq~lpment

In

your

operating

environment.

GROUND THE

INSTRUMENT.

To

minimize

shock

hazard,

the

equipment

chassis

and

enclosure

must

be

connected

to

an

electrical

ground. The

equipment

is

supplied

with a three-conductor

ac

power

cable.

The

power

cable must

either

be

plugged

into

an

approved

three-contact

electrical

outlet

or

used

with a three-contact

to

two-contact

adapter. with the

grounding

wire

(green)

firmly

connected

to

an

electrical

ground

(safety ground) at the

power

outlet.

The

power

jack

and

mating

plug

of

the

power

cable

meet

International

Electrotechnical

Commission

(IEC) safety standards.

DO NOT OPERATE IN AN EXPLOSIVE ATMOSPHERE.

Do

not

operate the

equipment

in the presence

of

flammable

gases

or

fumes.

Operation

of

any electrical

equipment

in

such

an

environment

constitutes a definite

safety

hazard.

KEEP AWAY FROM LIVE

CIRCUITS.

Operating

personnel

must

not

remove

equipment

covers.

Only

Factory

Authorized

Service Personnel

or

other

qualified

maintenance

personnel

may

remove

equipment

covers

for

internal

subassembly

or

component

replacement

or

any

internal adjustment. Do

not

replace

components

with

power

cable

connected.

Under

certain

conditions,

dangerous

voltages

may

exist

even

with

the

power

cable removed.

To

avoid injuries. always

disconnect

power

and

di~charge

circuits

before

touching

them.

DO NOT SERVICE

OR

ADJUST

ALONE.

Do

not

attempt

internal

service

or

adjustment

unless

another

person,

capable

of

rendering

first aid and

resuscitation. is present.

USE

CAUTION

WHEN EXPOSING

OR

HANDLING

THE

CRT.

Breakage

of

the

Cathode-Ray

Tube

(CRT)

causes a

high-velocity

scattering

of

glass fragments

(implo-

sion).

To

prevent

CRT

implosion,

avoid

rough

handling

or

jarring

of

the

equipment.

Handling

of the

CRT

should

be

done

only

by

qualified

maintenance

personnel

USing

approved

safety

mask and gloves.

DO

NOT

SUBSTITUTE PARTS OR

MODIFY

EQUIPMENT.

Because

of

the

danger

of

introducing

additional

hazards,

do

not

install

substitute

parts

or

perform

any

unauthorized

modification

of

the

equipment.

Contact

Motorola

Field

Service

Division

for

service and

repair to ensure that

safety

features are maintained.

DANGEROUS PROCEDURE

WARNINGS.

Warnings,

such

as

the

example

below,

precede

potentially

dangerous

procedures

throughout

this

manual.

Instructions

contained

in

the

warnings

must be

followed.

You

should

also

employ

all

other

safety

precautions

which

you

deem

necessary

for

the

operation

of

the

equipment

in

your

operating

environment.

WARNING

Dangerous

voltages,

capable

01

causing

death,

are

present

In

this

equipment.

Use

extreme

caution

when

handling,

testing,

and

adjusting.

SP015163

R.l

(1/88)

PREFACE

This

manual

provides

general

information,

hardware

preparation,

installation

instructions,

functional

description,

and

support

information

for

the

MVME135/MVME136

Monoboard

Series

of

32-Bit

Microcomputers. This

manual

is

intended

for

anyone

who

wants

to

design

OEM

systems,

supply

additional

capabil

ity

to

an

existing

compatible

system

or

in

a 1

ab

environment

for

experimental

purposes.

A bas i c

knowl

edge

of

computers

and d i

gita

1 1 ogi

cis

assumed.

To

use

this

manual, you

should

be

faimilar

with

the

publications

listed

in

the

Re7ated Documentation

paragraph

in

Chapter 1 of

this

manual.

The

computer

programs

stored

in

the

read

only

memories

of

this

device contain

material copyrighted

by

r10torola Inc.,

first

published

1988.

and

may

be

used

only

under

a license

such

as

the License for

Computer

Programs

(Article

14)

contained

in

Motorola's

Terms

and

Conditions of Sale.

Rev.

1/79.

WARNING

THIS

EQUIPMENT

GENERATES,

USES,

AND

CAN

RADIATE

RADIO

FREQUENCY

ENERGY

AND

IF

NOT

INSTALLED

AND

USED

IN

ACCORDANCE

WITH

THE

INSTRUCTIONS

MANUAL,

MAY

CAUSE

INTERFERENCE

TO

RADIO

COMMUNICATIONS.

IT

HAS

BEEN

TESTED

AND

FOUND

TO

COMPLY

WITH

THE

LIMITS

FOR A CLASS

A

COMPUTING

DEVICE

PURSUANT

TO

SUBPART J OF

PART

15

OF

FCC

RULES,

WHICH

ARE

DESIGNED

TO

PROVIDE

REASONABLE

PROTECTION

AGAINST

SUCH

INTERFERENCE

WHEN

OPERATED

IN A COMMERCIAL

ENVIRONMENT.

OPERATION

OF

THIS

EQUIPMENT

IN A RESIDENTIAL

AREA

IS

LIKELY

TO

CAUSE

INTERFERENCE

IN

WHICH

CASE

THE

USER,

AT

HIS

OWN

EXPENSE,

WILL

BE

REQUIRED

TO

TAKE

WHATEVER

MEASURES

NECESSARY

TO

CORRECT

THE

INTERFERENCE.

VMEmodule,

VSBbus.

and

135bug

are trademarks of

Motorola

Inc.

Second

Ed

it

ion

Copyright

1989

by r10torola Inc.

First

Edition April

1987

MYMEI35,

MYMEI35-1,

MVMEI35A,

MVME136,

AND

MVMEl36A

32-BIT

MICROCOMPUTERS

USER'S

MANUAL

(MVMEI35jD2)

The

information

in

this

document

has

been

carefully

checked

and

is

believed

to

be

entirely

reliable.

However,

no

responsibility

is

assumed

for

inaccuracies.

Furthermore, Motorola

reserves

the

right

to

make

changes

to

any

products

herei n to

improve

rel

i abi 1 i

ty,

function,

or

design.

Motorola does not assume

any

liability

arising

out

of

the

application

or use

of

any

product

or

circuit

described

herein;

neither

does

it

convey

any

license

under

its

patent

rights

or

the

rights

of

others.

TABLE

OF

CONTENTS

CHAPTER

1 -

GENERAL

INFORMATION

1.1

1.2

1.3

1.3.1

1.3.2

1.4

1.5

1.6

1.7

I

NTRODUCT

ION

...•••.••.•..•.......•...........••.•

FEATURES

.....•..••.•.•••..•.•....••..............

SPECIFICATIONS

.................................

..

Cooling

Requirements

•.....•.•••••••.•..•....•.

FCC

Comp

1 i

ance

•.•.•.......•••.••..••.•.•......

GENERAL

DESCRIPTION

.............................

.

MVME135/136

CONFIGURATIONS

..•.•.............••.•.

REFERENCE

DOCUMENTATION

...............•.....••...

MANUAL

TERMINOLOGY

..............................

.

CHAPTER

2 -

HARDWARE

PREPARATION

AND

INSTALLATION

Page

1-1 1-1

1-2 1-4 1-4 1-5 1-5 1-6

1-7

2.1

INTRODUCTION.. .

.. • .. . ..

..

. .

..

. .

.. ..

..

. .

..

. .

..

2-1

2.2

UNPACKING

INSTRUCTIONS

....

...•.••••••...

.........

2-1

2.3

HARDWARE

PREPARATION.............................

2-1

2.3.1

VMEbus

Lock For

VSBbus

(Jl)

....

.....

......•...

2-4

2.3.2

Bus

Grant/Request Level

Select

(J2)

...........

2-4

2.3.3

Factory

Test Jumper

(J5)

..

........

.•.•..••....

2-6

2.3.4

RAM

Acknowledge

Mode

(J6)

..

...........

.....•••

2-6

2.3.5

ROM

Size

Select

(J7)

•.•.................

...•••

2-7

2.3.6

DRAM

Address

Multiplex

Select

(J8)

•.........••

2-8

2.3.7

Local/VMEbus Timeout

Disable

(Jll)

............

2-8

2.3.8

DRAM

Cycle

Start

Mode

Select

(J12)

.......••.•.

2-9

2.3.9

External

Timer

Select

(JI3,J14)

••.......•.•...

2-10

2.4

SERIAL

PORT

CABLING..............................

2-11

2.4.1

DB-9

To

DB-25

Cable Connection

.•..............

2-11

2.5

VME

CHASSIS

INSTALLATION

•...•....................

2-12

CHAPTER

3 -

OPERATING

INSTRUCTIONS

3.1

INTRODUCTION..............

........

......

.........

3-1

3.2

FRONT

PANEL......................................

3-1

3.2.1

LED

Indicators................................

3-1

3.2.2

ABORT

Switch

(Sl)

.............................

3-1

3.2.3

RESET

Switch (S2)

.............................

3-1

3.2.4

Mapping Switch (S3)

...........................

3-3

3.2.5

System

Configuration

Switch (S4)

...........•..

3-10

3.3

MEMORY

MAP

AND

MAP

DECODER

.•.•.•..•...••...••...•

3-11

3.3.1

MVME135/135-1/135A Main

Memory

Map

•.•.........

3-12

3.3.2

MVME136/135A

Main

Memory

Map

.....•............

3-13

vii

TABLE

OF

CONTENTS

(cant.)

Page

CHAPTER

4 -

FUNCTIONAL

DESCRIPTION

4.1

INTRODUCTION

.....................................

4-1

4.2

GENERAL

DESCR 1 PTION

..............................

4-1

4.2.1

Data

Bus

Structure

...

....................

.....

4-1

4.2.2

M~m?ry

Map.......

.............................

4-1

4.2.3

Tlmlng...........

.............................

4-1

4.2.4

MVMEI35/135-1/136

DRAM

Cycle

Times

....

........

4-1

4.2.5

MVMEI35A/136A

DRAM

Cycle

Times

........

.....

...

4-4

4.2.6

ROM/PROM/EPROM/EEPROM

Cycle

Times

...

..........

4-4

4.2.7

VMEbus

Cycle

Times

...........

......

4-5

4.2.8

VMEbus

Arbitration

Time

...

............

........

4-5

4.3

t4C68020

MPU

......................................

4-6

4.4

t4C68881

FPCP

.....................................

4-6

4.5

MC68851

PMMU

.....................................

4-6

4.6

DEBUG

MONITOR

FIRMWARE

..

......

..........

.........

4-7

4.7

VME

SUBSYSTEM

BUS

(VSBbus)

......

............

.....

4-7

4.8

DYNAMIC

RAM......................................

4-7

4.9

FUNCTION

CODE

ASSIGNMENTS.

...

.......... ..........

4-8

4.10

t4VME135/136

USE

OF

CPU

SPACE.....................

4-8

4.10.1

MC68851

Breakpoint Support

..........

4-9

4.10.2

MC68851

Breakpoint Operation

..................

4-10

4.10.3

MC68851

Breakpoint Architecture

...............

4-11

4.10.4

MC68851

Acknowledge

Cycle

Operation

...........

4-12

4.10.5

Access

Level

Control

..........................

4-12

4.10.6 Coprocessor

Communications

....................

4-13

4.11

INTERRUPT

HANDLER

................................

4-14

4.12

ON

BOARD

ROM/PROM/EPROM

...........................

4-17

4.13

DUAL

SERIAL

PORTS

................................

4-17

4.14

MVME135/136

TIMER

................................

4-17

4.15

LOCAL

CONTROL/STATUS

REGISTERS

...................

4-18

4.15.1 Status Register

Format

And

Functions

..........

4-19

4.15.2 Control Register

Format

And

Functions

.........

4-21

4

.16

~1UL

TIPROCESSOR

CONTROL/STATUS

REGISTERS

(MPCSR)

..

4-27

4.16.1

Base

Address

Selection

........................

4-32

4.17

VSBbus

CONTROL/STATUS

REGISTER...................

4-33

4.17.1

VSBbus

Control/Status

Format

and

Functions

....

4-33

4.18

CONFIGURING A VME

SUBSYSTEM

BUS

..................

4-37

CHAPTER

5 -

SUPPORT

INFORMATION

vii

i

5.1

5.2

5.2.1

INTRODUCTION

....................................

.

INTERCONNECTION

SIGNALS

.........................

.

Connector

PI

Interconnect Signals

............

.

5-1 5-1

5-1

5.2.2

5.2.3

5.2.4

5.2.5

5.2.6

5.3

5.4

TABLE

OF

CONTENTS

(cont.)

Connector

P2

Interconnect Signals

............

.

Connector

J3

Interconnect Signal s

............

.

Connector

J4

Interconnect Signals

............

.

Connector

J9

Interconnect Signals

............

.

Connector

J10

Interconnect Signals

...........

.

PARTS

LIST

......................................

.

SCHEMATIC

DIAGRAMS

..............................

.

Page

5-6 5-13 5-15 5-19 5-20 5-21 5-43

APPENDIX

A -

MVME135/135-1/136

PAL2

SOURCE

LISTING

.............

A-I

APPENDIX

B -

MVME135A/136A

PAL2

SOURCE

LISTING.................

B-1

APPENDIX

C -

MVME135/136

LOCAL

MEMORY

MAP

......................

C-1

FIGURE

2-1.

FIGURE

3-1.

FIGURE

3-2.

FIGURE

3-3.

FIGURE

4-1.

FIGURE

4-2.

FIGURE

4-3.

FIGURE

4-4.

FIGURE

4-5.

FIGURE

4-6.

FIGURE

4-7.

FIGURE

4-8.

FIGURE

4-9.

FIGURE

4-10.

FIGURE

4-11.

FIGURE

4-12.

FIGURE

5-1.

FIGURE

5-2.

FIGURE

5-3.

FIGURE

5-4.

FIGURE

5-5.

LIST

OF

ILLUSTRATIONS

Jumper, Connector,

And

Switch Location

Diagram

...

.

MVME135/136

Front

Panel

..........................

.

MVME135/135-1/136

Slave Access Addressing

........

.

MVMEI35A/136A

Slave

Access

Addressing

............

.

MVME135/135-1/136

Block

Diagram

..................

.

MVME135A/136A

Block

Diagram

......................

.

CPU

Space

Type

Field

Encoding

....................

.

Breakpoint

Acknowledge

Cycle Address

Encoding

....

.

Breakpoi nt

Regi

sters

.............................

.

Breakpoint

Acknowledge

Data

Register

Format

......

.

Breakpoint

Acknowledge

Control Register

Format

...

.

ALC

Interface

Logical

Address

Bus

Encoding

.......

.

Coprocessor

Interface

Address

Bus

Encoding

.......

.

Serial

Port Interconnections

.....................

.

016/032

Default

Data

Segmentation

................

.

MPCSR

And

DRAM

Address

Mapping

...................

.

MVME135/136

Parts Location

Diagram

...............

.

1Mb

DRAM

Mezzanine

Board

Parts Location

Diagram

..

.

4Mb

DRAM

Mezzanine

Board

Parts Location

Diagram

..

.

MVME135/136

By-Pass

Board

Parts Location

Diagram

..

MVME135/136

Schematic

Oiagram

....................

.

2-2

3-2 3-4 3-7 4-2 4-3 4-9

4-10

4-11 4-11

4-12 4-13 4-14

4-17

4-27 4-35

5-33 5-38 5-40 5-42 5-45

ix

FIGURE

5-6.

FIGURE

5-7.

FIGURE

5-8.

TABLE

I-I.

TABLE

1-2.

TABLE

2-1.

TABLE

3-1.

TABLE

3-2.

TABLE

3-3.

TABLE

3-4.

TABLE

4-1.

TABLE

4-2.

TABLE

4-3.

TABLE

4-4.

TABLE

4-5.

TABLE

4-6.

TABLE

4-7.

TABLE

4-8.

TABLE

5-1.

TABLE

5-2.

TABLE

5-3.

TABLE

5-4.

TABLE

5-5.

TABLE

5-6.

TABLE

5-7.

TABLE

5-8.

TABLE

5-9.

TABLE

5-HL

x

TABLE

OF

CONTENTS

(cant.)

1Mb

DRAM

Mezzanine

Schematic

Diagram

4Mb

DRAM

Mezzanine

Schematic

Diagram

PMMU

By-Pass

Board

Schematic

Diagram

LIST

OF

TABLES

MVME135/136

Specifications

........................

.

MVME135/136

Configurations

........................

.

Jumper

Block

Placements

...........................

.

MVME135/136

Front

Panel

LED

Status

................

.

Function

Code

Assignments

.........................

.

MVMEI35/135-1/136

Main

Memory

Map

.................

.

MVt~E135A/136A

Main

Memory

Map

.....................

.

MVMEl35/136

Timing

................................

.

Function

Code

Assignments

.........................

.

ALC

Interface Registers

Map

.......................

.

MC68851

Coprocessor Interface Register

Map

........

.

MC68881

Coprocessor Interface Register

Map

........

.

Interrupt

Handler Priority Assignments

............

.

Multiprocessor

Control/Status Registers

...........

.

Mapping

On

The

VMEbus

.............................

.

Connector

PI

Interconnect Signals

.................

.

Connector

P2

Interconnect Signal s

.................

.

Connector

J3

Interconnect Signals

.................

.

Connector

J4

Interconnect Signals

.................

.

Connector

J9

Interconnect Signals

.................

.

Connector J

10

Interconnect

Si

gna

1 s

................

.

MVME135/136

Parts List

............................

.

1Mb

DRAM

Mezzanine

Board

Parts List

...............

.

4Mb

DRAM

Mezzanine

Board

Parts List

...............

.

PMMU

By-Pass

Board

Parts List

.....................

.

Page

5-97

5

-113

5-131

1-2

1-6 2-3 3-3

3-11

3-12 3-13

4-3 4-9

4-13 4-14 4-15 4-15 4-28 4-30

5-1 5-6

5-13 5-15 5-19 5-20 5-21 5-37 5-39 5-41

GENERAL

INFORMATION

CHAPTER

1 -

GENERAL

INFORMATION

1. 1 I

NTRODUCTI

ON

This

user's

manual

provides

general

information,

preparation

and

installation

instructions,

operating

instructions,

functional

description,

and

support

information

for

the

MVME135/MVME136

series

of

32-bit

microcomputers

(refer

to

section

1.5

for

the

different

module

configurations).

Unless

otherwise

specified,

these

microcomputers

are

referred

to

as

the

MVME135/136

throughout

the

contents

of

thi s user's

manua

1.

2

FEATURES

The

features

of

the

MVMEl35/136

i ncl ude:

.MC68~2~

Virtual

Memory

Microprocessor

with

32-bit

address

and

data

at

16.67

MHz

or

2~.~~

MHz

.

•

1Mb

of

shared

local

DRAM

with

no

wait

cycles,

32-bit

wide;

accessible

from

the

VMEbus

with

optional

parity

(MVME135,

MVME135-1,

and

MVME136

versions

only)

.

•

4Mb

of

shared

local

DRAM

with

one

wait

cycle,

32-bit

wide;

accessible

from

the

VMEbus

with

optional

parity

(MVME135A

version

only)

.

•

4Mb

of

shared

local

DRAM

with

two

wait

cycles,

32-bit

wide;

accessible

from

the

VMEbus

with

optional

parity

(MVME136A

version

only).

Parity

does

not

add any

additional

wait

cycles

for

this

version

.

• On-board

socket

for

MC68881

Floating

Point

Coprocessor

(FPCP)

at

16.67

MHz

or

2~.0~

MHz

.

• On-board

socket

for

MC68851

Demand

Paged

Memory

Management

Unit

(PMMU)

at

16.67

MHz

(MVMEl36

and

MVME136A

versions

only)

.

•

Multi-master

VME

Subsystem

Bus

(VSBbus)

interface;

32-bit

secondary

bus

support.

•

VMEbus

interface;

32-bi t address

and

data

.

•

VMEbus

Interrupt

Handler.

•

Z8036A

Programmabl e

Ti

mer

Modul

e.

•

Periodic

tick

interrupt

(level

6).

• Watchdog

reset

(momentary

local

reset,

local

reset

and hol

d,

or

a

system

level

reset

may

be

software

selected)

.

•

VSBbus

can

eliminate

"software

holes"

in

VMEbus

memory

map

caused

by

except

ion

tabl

es

and

stacks.

1 -1

I

GENERAL

INFORMATION

eSingle

level

system

controller

capability

(level

is

jumper

selectable).

eHigh

level

multiprocessor

control

and

status

registers

used

for

inter-processor

signaling

and

communication.

e

Round

Robin

requesting

provides

fairness

of

VMEbus

mastership

for

systems

with

multi

pl e

MVME135/136s

(software

sel

ectabl

e).

~Two

front

panel

RS-232C

serial

ports

with

level

translators;

eliminating

the

need

for

a

transition

board

between

the

MVME135/136

and a

terminal

or

modem.

eTwo

on-board

ROM

sockets

for a capacity

of

128Kb

(configured

for

Industry

Standard

JEDEC

28-pin

ROM/PROM/EPROM

devices;

user

provided).

1.3

SPECIFICATIONS

General

specifications

for

the

~'VMEI35/136

are

provided

in

the

following

table.

Sections

1.2.2

and

1.2.3

detail

cooling

requ i rements

and

FCC

compl i

ance,

respect i vely.

TABLE

1-1.

MVME135/136

SPECIFICATIONS

Characteristic

Specification

Microprocessor

MC68£120

32-bit

microprocessor

Clock

signal:

MVME135/135A/136/136A

16.67

MHz

CPU

clock frequency

MVME135-1

20.0£1

MHz

CPU

clock frequency

Power

requirements:

MVMEI35/135-1/135A

MVME136/136A

1-2

+5

Vdc,

6.75 A

maximum

(5.6 A typical)

+12

Vdc,

5£1

rnA

maximum

(1£1

rnA

typical)

-12

Vdc,

9£1

mA

maximum

(30

mA

typical)

+5

Vdc,

7.00 A

maximum

(5.8 A typical)

+12

Vdc,

5£1

mA

maximum

(HI

rnA

typical)

-12

Vdc,

9£1

mA

maximum

(3£1

rnA

typical)

NOTE:

Backplane Connectors

--

The

P2

backplane

is

not only necessary

for

32-bit

operation

but

is

also

used

to

connect

+5 V to

the

~1VME135/136

module

for

current

distribution.

The

module

draws

5.6

A under

typical

operation

and

should

not

be

operated without a

P2

backpl ane.

GENERAL

INFORMATION

TABLE

1-1.

MVME135/136

SPECIFICATIONS

(cont.)

Characteristic

Addressing:

System

Size

(Total

on-/off-board)

ROM/EPROM

Serial

I/O

ports

Timer

Interrupts

On-board

memory

MVME135/135-1

MVME136

MV~lEl35A

MVME136A

Temperatures:

Operating

Storage

Rel

ative

humidity

Physical

size

(PCB):

Hei

ght x

wi

dth

Thickness

Specification

32-bits

= 4 gigabytes 1

inear

address space

Two

EPROM/ROM

sockets

for

16Kb

or

32Kb

devices

using

+5

Vdc

only

(JEDEC

standard

28-pin

devices;

user

supplied).

Two

multi-protocol

serial

communications

channels with

RS-232C

interface

(connection

made

vi a

two

DB

-9 connectors

from

the

front

panel).

A

Z8036A

programmable

timer

module with

three

independent

16-bit

timers.

Any

seven

possible

VMEbus

interrupts

can

be

recei

ved

by

the

MVMEl35/136.

VSBbus

has

interrupt

capability.

as

do

most on-board

devices.

1Mb, 0 wa

it

state

wi

thout

parity

and 1 wa

it

state

wi

th pari

ty.

1Mb,

1 wait

state

without

parity

and

2 wait

states

with

parity.

The

MC68851

Paged

Memory

Management

Unit

(PMMU)

adds 1 wait

state

to

local

memory

accesses.

4Mb,

1 wait

state

with

or

without

parity.

4Mb,

2 wait

states

with

or

without

parity.

The

r~C68851

Paged

Memory

Management

Unit

(PMMU)

adds 1 wait

state

to

local

memory

accesses.

o to

50

degrees C

(inlet

air

temperature with

forced

air

cool ing)

-

40

to

85

degrees C

5%

to

95%

(non-condensing)

(not incl uding the

front

panel)

6.30 inches (16.00

cm)

x 9.19 inches (23.34

cm)

0.062 inch (0.157

em)

1-3

I

GENERAL

INFORMATION

TABLE

1-1.

HVHE135/136

SPECIFICATIONS

(cont.)

Characteristic

Part

projections:

Component

side

Solder

side

Connectors:

VMEbus/VSBbus RS-232C

1.3.1

Cool

ing Requirements

Specification

0.50 inch (1.27

cm)

maximum

0.067 inch (0.17

cm)

maximum

DIN

triple

row,

96-pin male

(PI,

P2)

DB-9,

9-pin female (J9, J10)

Motorola

VMEmodules

are

specified,

designed,

and

tested

to

operate

reliably

with

an

incoming

air

temperature

range

from 0

degrees C to

50

degrees

C (32

degrees F to

122

degrees

F)

with

forced

air

coo 1 i ng.

Temperature

qualification

is

performed

in

a

standard

Motorola

VMEsystem

1000

chassis.

Twenty-five

watt

load

boards

are

inserted

in

the

two

card

slots,

one

on

each

side,

adjacent

to

the

board

under

test

to

simulate

a high power

density

system

configuration.

An

assembly

of

three

axial

fans,

rated

at

100

CFM

per

fan,

is

placed

directly

under

the

MVME

card

cage.

The

incoming

air

temperature

is

measured between

the

fan

assembly and

the

card

cage

where

the

incoming

airstream

first

encounters

the

board

under

test.

Test

software

is

executed

as

the

module

is

subjected

to

ambient

temperature

variations.

Case

temperatures

of

critical,

high power

density

integrated

circuits

are

monitored

to

ensure

component

vendors

speci

fi

cat

ions

are

not

exceeded.

While

the

exact

amount

of

airflow

required

for

cooling

depends

on

the

ambient

air

temperature

and

the

type,

number, and

location

of

boards

and

other

heat

sources,

adequate

cooling

can

usually

be

achieved

with

10

CFM

flowing

over

the

module. Less

air

flow

is

required

to

cool

the

module

in

environments

having

lower

maximum

ambients.

Under more

favorable

thermal

conditions

it

may

be

possible

to

operate

the

module

reliably

at

higher

than

50

degrees

C

with

increased

air

flow.

It

is

important

to

note

that

there

are

several

factors,

in

addition

to

the

rated

CFM

of

the

air

mover, which

determine

the

actual

volume

of

air

flowing

over

a module.

1.3.2

FCC

Compl

iance

The

MVME135/136

module

is

tested

in

an

FCC-compliant

chassis,

and

meets

the

requirements

for

Class A equipment.

FCC

compliance

was

achi eved

under

the

foll

owi

ng

condi t ions:

1-4

GENERAL

INFORMATION

1.

Shielded

cables

on

all

external

I/O

ports.

2. Cable

shields

connected

to

earth

ground

via

metal

shell

connectors

bonded

to a conductive

module

front

panel.

3.

Conductive

chassis

rails

connected

to

earth

ground.

This

provides

the

path

for

connecting

shields

to

earth

ground.

4.

Front

panel

screws

properly

tightened.

For

minimum

RF

emissions,

it

is

essential

that

the

conditions

above

be

implemented;

failure

to

do

so

could

compromise

the

FCC

compliance

of

the

equipment

containing

the

modules.

1.4

GENERAL

DESCRIPTION

The

MVME135/136

is

a high

performance

MC68020

microprocessor-based

module implemented

on a VME

double-high,

single-wide

form-factor.

The

MVME135/136

incorporates

an

MC68020, a 32-bit

address

and

data

microprocessor,

a

high

level

multiprocessor

CSR,

and

1Mb

or

4Mb

of

fast

DRAM.

Other

main

features

provided

include

a

Demand

Paged

Memory

Management

Unit

(PMMU), a Floating

Point

Coprocessor

(FPCP),

and

interfaces

to

the

VMEbus

and

the

VSBbus.

The

MVME135/136

is

designed

for

those

applications

which

require

fast

on-board

RAM

and a

secondary

bus (VSBbus). The

features

of

the

MVME135/136

include

high

performance

and

an

elegant

architecture.

The

MVME135/136

is

especially

suited

to

applications

requiring

multiple

processors

where

the

efficiency

of

inter-processor

communication

is

important.

The

135bug

resident

debug package

(refer

to

Motorola

publication

MVME135BUG)

is

the

firmware

package

designed

for

use

with

the

MVME135/136

modul

e.

135bug

provides

a

powerful

system

debuggi

ng

tool

for

VMEmodule

systems.

This

firmware

features

a one

line

assembler/disassembler,

provisions

for

upload/download,

and

disk

bootstrap

commands. 135bug

is

available

as

an

EPROM-based

resident

package

whi

ch

is

plugged

into

IC

sockets

U54

and

U56

on

the

MVME135/136.

1.5

MVME135j136

CONFIGURATIONS

There

are

five

module

configurations

available

in

the

MVME135/136

series

of

32-bit

microcomputers.

These

configurations

are

listed

in

the

following

table.

1-5

I

GENERAL

INFORMATION

TABLE

1-2.

MVME135/136

CONFIGURATIONS

Module

CPU

Clock On-Board

MC68881 MC68851

Designation Cycle

(MHz)

Memory

(FPCP)

(PMMU)

MVME135

16.67

1Mb

Yes

No

MVMEl35-1

20.00

1Mb

Yes

No

MVME135A

16.67

4Mb

Yes

No

MVME136

16.67

1Mb

Yes

MVME136A

16.67

4Mb

Yes

1.

6

REFERENCE

DOCUMENTATION

The

following

publications

may

provide

additional

helpful

information.

If

not

shipped

with

this

product,

they

may

be

purchased

from

Motorola's

Literature

Distribution

Center,

616 West

24th

Street,

Tempe,

Arizona

85282;

telephone

(602)

994-6561.

DOCUM

ENT

T I

TL

E

MC68020

32-Bit

Microprocessor

U.M.

MC68851

Paged Memory Management

Unit

U.M.

MC68881

Floating-Point

Coprocessor

U.M.

MVME204-1/-2 Dual

Ported

Dynamic

Memory

U.M.

MVME204-2F

Dual

Ported

Dynamic

Memory

U.M. MVME224-1/ -2 4/8Mb Dynami c Memory U.M. MVSB2400

VSBchip U.M.

VME

System

Architecture

Guide

VME

Subsystem

Bus

(VSBbus)

Specification

(RevA.1)

135bug

Diagnostic/Debug

Package U.M.

MOTOROLA

PUBLICATION

NUMBER

MC68020UM/AD MC68851UrVAD

MC68881UM/AD MVME204 MVME204F MVME224 MVSB2400 MVMESYSAM/D MVMESB

MVME135BUG

NOTE:

Although

not

shown

in

the

above

list,

each

Motorola

MCD

manual

publication

number

is

suffixed

with

characters

which

represent

the

revision

level

of

the

document,

such

as

"D2"

(the

second

revision

of a manual); a supplement

bears

the

same

number

as

the

manual

but

has a

suffix

such

as

"AI"

(the

first

suppl

ement

to

the

manual).

U.M.

denotes

User's

Manual.

1-

6

GENERAL

INFORMATION

Additional

publications

that

may

provide

helpful

information

are

listed

below.

ANSI/IEEE

Standard 1014-1987

Versatile

Backplane

Bus:

VMEbus

Zilog

Z-CIO

(Z8036)

Counter/Timer

and

Parallel

I/O

Unit Technical

Manual

1.

7

MANUAL

TERMINOLOGY

Institute

of

Electrical

and

Electronics

Engineers, Inc.

345

East 47th

Street

New

York,

New

York

10017

Zilog Incorporation 1315

Del

Avenue

Campbell,

California

95008

(408) 370-8000

Throughout

this

manual, a convention has been

maintained

whereby

data

and

address

parameters

are

preceded

by

a

character

which

specifies

the

numeric format as

follows:

S

%

&

doll ar percent

ampersand

specifies

a hexadecimal

number

specifies

a binary

number

specifies

a decimal

number

Unless

otherwise

specified,

all

address

references

are

in

hexadecimal

throughout

this

manual.

An

asterisk

(*)

following

the

signal

name

for

signals

which

are

level

significant

denotes

that

the

signal

is

true

or

valid

when

the

signal

is

low.

An

asterisk

(*)

following

the

signal

name

for

signals

which

are

edge

significant

denotes

that

the

actions

initiated

by

that

signal

occur

on

high

to

low

transition.

In

this

manual,

assertion

and

negation

are

used

to

specify

forcing

a

signal

to a particular

state.

In

particular,

assertion

and

assert

refer

to

a

signal

that

is

active

or

true;

negation

and

negate

indicate a signal

that

is

inactive

or

false.

These terms

are

used

independently

of

the

voltage

level

(high

or

low)

that

they

represent.

1-7

I

a

GENERAL

INFORMATION

.....

,

1-8

HARDWARE

PREPARATION

CHAPTER

2 -

HARDWARE

PREPARATION

AND

INSTALLATION

2.1

INTRODUCTION

This

chapter

provides

the

unpacking, hardware

preparation,

and

installation

instructions

for

the

MVME135/136.

2.2

UNPACKING

INSTRUCTIONS

NOTE

If

shipping

carton

is

damaged

upon

receipt,

request

that

the

carrier's

agent

be

present

during

unpacking/inspection

of

equipment.

Carefully

unpack

the

equipment

from

the

shipping

carton.

Refer

to

the packing

list

and

verify

that

all

items

are

present.

Save

the

shipping

carton

and

packing

materials

for

storing

or

reshipping

of

the

equipment.

CAUTION

AVOID

TOUCHING

AREAS

OF

INTEGRATED

CIRCUITS;

STATIC

DISCHARGE

CAN

DAMAGE

THESE

CIRCUITS.

Inspect

for

any

shipping

damage.

If

no

damage

exists,

then

the

module can

be

prepared

for

operation

according

to

the

following

sect

ions

of

thi s chapter.

2.3

HARDWARE

PREPARATION

This

section

describes

the

hardware

preparation

for

the

MVME135/136

prior

to

installation.

Observance

of

this

description

will

ensure

the

user

that

all

components

are

properly

configured

for

operation.

Jumper blocks

are

used

to

select

the

various

functions

and

options

of

the

module. Before

the

module

is

installed,

the

user

should

verify

the

jumper

block

configurations

and

alter

the

jumpers, as

required,

for

the

user's

particular

system

operation.

The

MVME135/136

has been

factory

tested

and

is

shipped

with

factory-

installed

jumper

configurations

that

are

illustrated

in

Figure

2-1.

2-1

I

N

.

N

00

o

J2

1

0

o 0

J1

VMEbus

P1

J4

EPROM/ROM

(135bug)

1 Mb

/4Mb

DRAM

MEZZANINE· MODULE

(SHOWN

REMOVED

FOR.

CLARITY )

J5

DS2

DS3

I

LED INDICATORS

(EVEN)

U56

o

MC68851

EXTENDED

VMEbus I VSBbus

P2

VSB DEVICE

U75

1

OR

BY-PASS BOARD

MC6B020

~~

____

-AI~--~~

ODD)

J11

~J8

\

1\

I

, I

SERIAL PORT 2 SERIAL PORT 1

FIGURE

2-1.

JUMPER,

CONNECTOR,

AND

SWITCH

LOCATION

DIAGRAM

)

•

)

:r:

~

;:0

o

:IE:

~

;:0

,...,

-0

;:0

,...,

-0

~

;:0

~

-I

-o

:z

HARDWARE

PREPARATION

Table

2-1

lists

the

jumper

blocks

by

designation,

function,

and

factory-installed

configuration.

A more

detailed

description

of

these

jumper

blocks

is

provided

in

the

following

sections.

Four

switches

(S1,

52,

S3, and S4)

are

located

on

the

MVME135/136's

front

panel.

Switches

S1

and

S2

are

push-buttons

and

switches

S3

and

S4

are

eight-

and

ten-positions

DIP-type

devices,

respectively.

Three

LED

indicators

(FAIL,

HALT,

and

RUN)

are

located

on

the

front

panel.

Refer

to

Chapter 3 for

more

detailed

information

regarding

the

front

panel

and

the

use

of

these

switches

and i

ndi

cators.

The

following

table

lists

and

describes

the

MVME135/136

jumper

blocks.

TABLE

2-1.

JUMPER

BLOCK

PLACEMENTS

Jumper

Function

Factory

Con

fi

gurat

ion

J1

VMEbus

Lock

for

VSBbus

No

jumper

installed.

(Disabled)

J2

Bus

Grant/Reques t Level

Select

J2

(l-2}(5-6}(7-8}(9-11)

( 10-12}(16-18)

J3

Mezzan i ne

Memory

Connect

27-pin

connector

J4

Mezzan i ne

Memory

Connect

56-pin

connector

J5

Factory

Test

Jumper

No

jumper

installed.

J6

RAM

Acknowl

edge

Mode

J6

(l-2)

J7

ROM

Size

Select

J7 (2-3)

J8

DRAM

Address

MUX

Timing

Select

J8

(1-

2)

J9

Seri

a 1

Port 2 (B)

Connect

Front Panel Host Connector

J10

Seri

a 1

Port 1 (A)

Connect

Front Panel Terminal Connector

Jll

Timeout Disable

No

jumper

installed.

(Local

and

VMEbus)

J12

DRAM

Cycle

Start

Mode

Select

J12 (1-2)

J13/J14

External Timer

Sel

ect

J13 (4-6)

(Optional)

2-3

I

HARDWARE

PREPARATION

2.3.1

VMEbus

Lock

For

VSBbus

(J

1)

Jumper block

JI

allows

the

RMC*

(Read

Modify Cycle)

signal

from

the

MC68020

processor

to

be

asserted

on

the

reserved

bus pin P2-B3. This

option

is

provided

for

users

that

require

access

locking

of

the

slave

ports

that

may

have a dual

bus

interface.

Normal

bus

locking

occurs

on

VMEbus

without

this

jumper

for

single

ported

VMEbus

slave

modules. Since

this

lock

feature

is

not

part

of

the

VMEbus

specification

and

since

it

utilizes

a

reserved

bus

pin,

use

of

this

feature

is

recommended

only

when

no

other

method

will

suffice.

Therefore,

JI

is

normally not

installed.

VMEmodules

MVME204-x

and

MVME214

have a

similar

jumper

option

to

allow

their

use with

the

lock

feature

described

above. This jumper

does not need to

be

installed

if

the system

software

executes

only

TAS

(Test

And

Set)

RMC

instruction

cycles.

Jumper

Block

JI

VMEbus

Lock

(Disabled)

No

Jumper

Installed

(Factory Setting)

==========================

:

Fl

2.3.2

Bus

Grant/Request

Level

Select (J2)

Jumper

Block

JI

VMEbus

Lock

(Enabled)

Jumper

Installed

The

VMEbus

has four

prioritized

bus

request

levels

(BR0*

through

BR3*),

each having

an

associated

bus

grant

daisy-chain.

Level 3 has

the

highest

priority

while

level

0 has

the

lowest.

Jumper block

J2

allows

the

user

to

select

the

desired

priority

level

for

VMEbus

accesses. The

following

configurations

illustrate

the

proper jumpering

for

each

bus

arbitration

1 evel .

If

the

MVMEl35/136

is

the

system

controller,

then

the

level 3 configuration

is

recommended.

NOTE:

No

other

configurations

will

work

properly.

2-4

HARDWARE

PREPARATION

Jumper

Block

J2

Jumper

Block

J2

I

Bus

Grant/Request

Level

0

Bus

Grant/Request

Level

1

===========================

+-----

I I

2

1-

-I

2

3 4

3

I I

4

5

1-

-I

6

5 6

7

1--1

8 7

1--1

8

9 0

0

10

9 0 0

10

11

1-

-I

12

11

1-

-I

12

13

I

0

14

13

0

I

14

15

0

16 15

0

16

17

0 0

18

17

0

18

Jumper

Block

J2

Jumper

Block

J2

Bus

Grant/Request

Level

3

Bus

Grant/Request

Level

2 (Factory Setting)

===========================

============================

+-----

1-

-I

2

1

1--1

2

3

0

4 3 0

0

4

5

1-

-I

6 5

1-

-I

6

7

I

8

7

1-

-I

8

9

10

9

I I

10

11

1-

-I

12

11

12

13

0

14

13

0 0

14

15

I

0

16

15

0

I

16

17

0

18

17

0

18

2-5

I

HARDWARE

PREPARATION

2.3.3

Factory Test Jumper (J5)

This

jumper

block

is

provided

for

factory

testing

purposes

only.

No

jumper cap

is

installed

across

jumper

J5

pins

1 and

2.

Jumper

Block

J5

Factory Test

Jumper

No

Jumper

Installed

(Factory Setting)

:

f:]

2.3.4

RAM

Acknowledge

Mode

(J6)

The MVME135/136's

on-board

memory

is

designed

to

operate

with

no

wait

states

when

memory

speeds

are

adequate

or

if

parity

operation

is

not

required.

Jumper

block

J6

allows

for

the

insertion

of

one

wait

state.

Parity

operation

requires

that

a

jumper

cap

be

installed

between jumper

J6

pins

2 and

3.

For optimum

performance,

care

should

be

taken

to

ensure

that

a jumper cap

is

installed

at

jumper J6

pins

1 and 2

when

parity

is

not

required.

The

other

case

where a jumper cap must

be

installed

at

pins

2 and 3

is

to

accommodate

slower

DRAM

devices.

Note

that

the

MVME135A

and

MVME136A

versions

utilize

slower

1M-bit

DRAMs,

therefore,

jumper J6

is

confi

gured

for

1

wait

state

operat

i on. For

no

wa

it

state

operation

at

16.67

MHz,

a 70-nanosecond

memory

mezzanine

module

is

requi

red.

No

wait

state

ope

rat

ion

at

20

MHz

requ i res

a 60-

nanosecond

memory

mezzanine module. Upgrading a

16.67

MHz

MVME135/136

multiprocessor

to

a

20

t4Hz

unit

requires

a

20

MHz

oscillator

(Y2) and

an

80-nanosecond

ten tap

delay

line

(DL4).

The

MVMEI35-1

multiprocessor

is

pre-configured

for

20

MHz

from

the

factory.

User

upgrading

of a MVME135

multiprocessor

to a MVME135-1

configuration

is

not

recommended.

2-6

~,

Jumper

Block

J6

No

Wait

State Operation

MVME135/135-1/136

Versions

(Factory Setting)

Parity

Mode -NOT

Allowed

1 2

3

+- -

I

o

2.3.5

ROM

Size Select

(J7)

HARDWARE

PREPARATION

Jumper

Block

J6

One

Wait

State Operation

MVME135A/136A

Versions

(Factory Setting)

Parity

Mode -All

Versions

2

3

+-

-

o

I

The

MVME135/136

accepts

two

EPROM/ROM

devices

(28-pin

compatible

JEDEC

units).

Jumper block J7

configures

sockets

U54

(odd

byte)

and

U56

(even byte)

for

either

32K

x 8 (27256)

or

64K

x 8 (27512)

size

EPROMs/ROMs.

These

two

device

sizes

are

the

only ones

supported.

These

ROM

sockets

are

usually

occupied

by

135bug, a powerful debug

package

resident

in

two

275]2

EPROM

devices

(optional),

therefore,

a

jumper cap

is

normally

installed

at

jumper J7

pins 2 and

3.

The

MVME135/135A/136/136A

versions

(16.67

MHz)

require

that

the

EPROM/ROM

device

access

times

be

no

greater

than

300 nanoseconds.

The

MVMEl35-1

version

(20

MHz)

requires

device

times

to

be

250

nanoseconds

or

faster.

Jumper

Block

J7

ROM

Size Select

27256

Devices

(64Kb)

==========================

2

3

+--

I

o

Jumper

Block

J7

ROM

Size Select

27512

Devices

(128Kb)

(Factory Setting)

2

3

+--

o

I

2-7

•

HARDWARE

PREPARATION

2.3.6

DRAM

Address Multiplex

Select

(J8)

The

MVME135/136

design

requires

high

performance

memory

devices.

These

devices

have

timing

requirements

that

differ

from

typical

performance

DRAMs.

Jumper

block

J8

allows

the

flexibility

to

accept

t i

mi

ng

from a

wider

vari

ety

of

DRAM

devi

ces

and

is

factory

configured.

Jumper

Block

J8

Normal

High

Performance

DRAM

Multiplex

Timing

(Factory

Setting)

2

3

+--

1

o

2.3.7

Loca1/VMEbus

Timeout Disable

(Jll)

Jumper

block

Jll

performs

a hardware

enable/disable

of

the

local

and

VMEbus

timeout.

This

jumper

is

typically

used

when

debugging a new

design

or

isolating

a problem where bus

errors

occur

due

to

accesses

to

non-existent

memory

space.

Install

ing a jumper cap

across

jumper

Jll

pins

1 and 2

will

prevent

the

cycle

from

being

terminated

by

a bus

error

when a slave

does

not

respond.

This

allows

ease

in

debug

since

the

hung

access

will

remain as long as

the

cyc1 e

is

not

termi

nated

by

a normal acknowl

edge.

When

135bug

is

installed,

the

MVME135/136

will

not

come

up

if

a

jumper cap

is

installed

at

Jll

pins

1 and

2.

This

is

due

to

the

fact

that

as a

course

of

normal

operation,

135bug

initiates

bus

cycles

that

may

be

terminated

by a timeout.

These

cycles

include

searching

for

on-board

coprocessors

(FPCP

or

PMMU)

or

sizing

of

system

memory.

If

the

MVME135/136

is

set

as

the

system

controller,

then

VMEbus

timeout

is

not

affected

by

jumper

Jll,

and

Jll

only

controls

the

local

bus

timeout.

The

MVME135/136

will

not

cause a VMEbus

timeout

if

not

set

as

the

system

controller,

that

function

is

provided

to

the

module

that

has been

configured

as

VMEbus

system

controller.

2-8

Jumper

Block

Jll

Timeout

(Enabled)

No

Jumper

Installed

(Factory Setting)

:

[[

2.3.8

DRAM

Cycle

Start

Mode

Select (J12)

HARDWARE

PREPARATION

Jumper

Block

Jll

Timeout

(Disabled)

Jumper

Install

ed

The

MVME135/136

memory

circuit

has been designed with the

flexibility

to

operate

in synchronous

or

asynchronous modes. This

approach allows

for

performance gains

to

local

memory

when

timing

strobes

are synchronous to

the

CPU

clock.

This

is

the

case

when

operating

with a

MC68020

alone

or

with

the

combination

of a MC68020

and a MC68851

PMMU.

The

asynchronous

mode

allows

for t imi

ng

strobes

that

do

not have

any

relationship

to

the

MC68020

clock.

The

case where

this

jumper

is

installed

would

be

when

a

Memory

Management

Board

is

used

(M68KVMMB851)

.

NOTE:

Use

of

the

Memory

Management

Board

is

not planned

for

the

MVME135/136.

Therefore,

jumper block J12

is

normally

installed

in

the

synchronous

mode.

Jumper

Block

J12

Synchronous

Mode

Select

(Factory Setting)

1 2

3

+--

I

o

Jumper

Block

J12

Asynchronous

Mode

Select

2

3

+--

o

I

2-9

I

HARDWARE

PREPARATION

2.3.9

External Timer

Select

(J13.J14)

Jumper

blocks

J13 and J14

provide

the

means

to

access

timers

2 and 3

of

the

Z8036

timer.

These jumper

blocks

are

designed

to

allow

an

alternate

clock

source

and

to

allow

cascading

of

the

counters.

The

alternate

clock

is

125

KHz,

derived

from

the 4 MHz

clock

that

drives

the

clock

input

of

the

Z8036

(divide

by

32).

The

factory

setting

for

J13 and J14

links

timers

2 and 3

for

diagnostics

purposes.

Also,

the

timer 3 output

;s

used as

the

watch dog

timer

signal

when

the

system

software

configures

the

Z8036

to

perform

the

watch dog

timer

function.

Location

monitor 2 is

also

accessible

as

an

input

clock

source

to

the

Z8036. Thi s coul d

be

set

up

to

count

events

or

perform

synchronizing

functions.

Some

of

the

jumper

pins

are

not

intended

to

be

jumper

configured.

These

provide

external

access

to

timer

2's

trigger

and

timer

3's

output,

trigger,

and

gate

signals.

These

signals

can

be

connected

to

other

circuitry

via

wire-wrap

or

jumper

clip

connections.

Refer

to

the

Zilog

Z-CIO (Z8036)

Counter/Timer

And

Parallel

I/O

Unit

Technical

Manual

for

details

regarding

timer

functionality.

2-10

Jumper

Blocks

J13

and

J14

External

Timer

1/0

Select

(Optional)

T2

Input

Altclock

Location Monitor

(Factory Setting)

3

5

J13

+-----

0 0 0

0

I

J14

+-

-

2

T2

Trigger

4

T2

Output

6

13 Input

o

13

Gate

2

0

13

Trigger

3

0 13 Output

HARDWARE

PREPARATION

2.4

SERIAL

PORT

CABLING

2.4.1

OB-9

To

OB-25

Cable Connection

The

following

diagrams

indicate

the

recommended

cable

connections

for

connecting

the

MVME135/136

serial

ports

to a terminal

or

modem

interface. 135Bug

expects

the

terminal

to

be

attached

to

serial

port

one.

Serial

port 2 may

be

used as

another

terminal

interface,

or

as a

connection

to

a

host

system

for

upload/download

using

S-Record

format.

Connect;

on

To

A Term; na 1

OB-9

08-25

Connector Connector

2 to 2

~'

3 to

3

-

(.)

-

8 to 4

7 to 5

4 to

8

5 to 7

to

20

6

to 6

Connection

To A Modem

08-9 08-25

Connector

3

to

2

2 to

3

7

to 4

8 to

5

6 to

6

5

to

7

to 8

4 to

20

2-11

I

HARDWARE

PREPARATION

2.5

VHE

CHASSIS

INSTALLATION

When

the

MVME135/136

has been prepared

(configured

by

the

user)

as

desired,

it

is

ready

for

system use

and

can then

be

installed

in a

VMEmodule

chassis.

The

following general procedure

is

recommended

for

installation

of the

MVME135/136.

a.

Turn

all

equipment

OFF.

CAUTION

INSERTING

OR

REMOVING

THE

MODULE

WHILE

POWER

IS

APPLIED

COULD

RESULT

IN

DAMAGE

TO

MODULE

PARTS.

AVOID

TOUCHING

AREAS

OF

INTEGRATED

CIRCUITS;

STATIC

DISCHARGE

CAN

DAMAGE

THESE

CIRCUITS.

b.

The

MVME135/136

may

be

installed

into

any

double-high

slot

on

a

VMEmodule

chassis.

Make

certain

that

the intended

slot

does not

have

I/O

cabling

on

P2,

since

that

could

potentially

damage

the

MVME135/136

VSBbus

interface.

c. Using a firm

grip

on

the

module,

slide

the

unit

into

the card

slide

until

the

PI

and

P2

connectors

of

the

unit

align

and

seat

into

the

backplane

sockets.

Use

a firm,

steady

pushing motion to

install

the

unit

snuggly

into

the backplane.

d.

Turn

chass

is

power

ON.

2-12

OPERATING

INSTRUCTIONS

CHAPTER

3 -

OPERATING

INSTRUCTIONS

3.1

INTRODUCTION

This

chapter

provides

necessary

information

to

use

the

MVME135/136

in

a

system

configuration.

This

includes

switches,

operating

controls,

indicators,

and

memory

map

details

found

on

the

MVME135/136

microcomputer.

3.2

FRONT

PANEL

The

MVME135/136's

front

panel

is

illustrated

in

Figure

3-1.

As

shown,

the

red

and

green

LED

indicators

(FAIL,

HALT,

and

RUN)

are

located

on

the

front

panel.

Located below

the

LED

indicators

are

the

two

pushbutton

switches

ABORT

(51) and

RESET

(52).

The

slots

are

cutouts

for

accessing

the

eight-position

DIP

switch

53

and

the

ten-position

DIP

switch

S4.

This

is

followed

by

the

slots

for

the

two

OB-9

connectors

for

Serial

Ports

1 and

2.

3.2.1

LED

Indicators

The

MVME135/136

has

three

LED

indicators:

FAIL,

HALT,

and

RUN.

They

are

described

below.

Table

3-1

provides

the

MVME135/136

module

status

for

all

possible

combinatior.s

of

these

LEOs.

The

FAIL

indicator

(051)

is a discrete

red

LED

that

indicates

the

status

of

the

BOFAIL

software

bit.

The

HALT

indicator

(052)

is a discrete

red

LED

that

indicates

when

the

halt

line

of

the

MPU

is

asserted.

The

HALT

indicator

may

flicker

as a

result

of

normal

CPU

operation.

The

RUN

indicator

(053)

is a discrete

green

LED

that

indicates

when

the

MC68020

address

strobe

is

active.

3.2.2

ABORT

Switch (51)

The

ABORT

switch

is

a momentary

type

switch

that

when

pressed,

causes

a Group 3 Level 7

interrupt

to

the

MC68020

processor.

The

135bug

MVME135/136

Debug

Monitor,

treats

ABORT

as a low

level

reset.

The

resul t bei

ng a di

spl

ay

of

the

MC68020

regi

sters

and/or

return

of

the

program

control

to

135bug.

3.2.3

RESET

Switch (52)

The

RESET

switch

is

a momentary

type

switch

that

when

pressed,

causes a reset

to

occur

locally.

If

the

MVME135/136

is

the

system

controller

(see

54-1), a VMEbus

system

reset

will

also

occur.

3-1

•

OPERATING

INSTRUCTIONS

LED

INDICATORS

ABORT

I RESET {

PUSHBOTTONS

MAPPING

SWITCH 53

SYSTEM

CONFIGURATION

SELECT SWITCH

54

DB·9

SERIAL PORT

CONNECTORS

e

BORT

0

ESET

0

I

J6

U

e

FIGURE

3-1.

MVMEl35/136

FRONT

PANEL

3-2

FAIL

HALT

OSl

DS2

Red

OFF

OFF OFF OFF

ON

OFF

OFF ON ON

OFF

ON

OPERATING

INSTRUCTIONS

TABLE

3-1.

HVHEl35/136

FRONT

PANEL

LED

STATUS

RUN DS3 Green

OFF

ON OFF ON

OFF

ON

OFF

ON

MVMEl35/136

Status

No

power

is

applied to the

module,

or the

MPU

is

not

the current local

bus

master.

Normal

operation.

MPU

is

halted.

MPU

is

runn i ng

and

encounteri

ng

VMEbus

deadlocks

and/or

PMMU

relinquish-and-retry.

The

frequency of

VMEbus

deadlocks and/or

PMMU

relinquish-and-retry

determines the

intensity

of the

HALT

LED.

MPU

is

not the current local

bus

master. Also.

[BRDFAILJ

has

not

been

cleared since

reset

or

has

been

set

by

software.

The

FAIL

indicator

is

also

ON

if

the

MVME135j136

is

the system controll er

and

SYSFA

I L *

is

detected

low

on

VMEbus.

[BRDFAILJ

has

not

been

cleared since

reset

or

has

been

set

by

soft'liare.

The

FAIL

indicator

is

also

ON

if

the

MVMEl35j136

is

the system

controller

and

SYSFAI

L *

is

detected

low

on

VMEbus.

MPU

is

halted

and

[BRDFAIL]

has

not

been

cleared

since

reset

or

has

been

set

by

software.

The

FAIL

indicator

is

also

ON

if

the

MVME135/136

is

the system

controller

and

SYSFAIL*

is

detected

low

on

VMEbus.

MPU

is

runn i n9

and

encounteri

n9

VMEbus

deadlocks

and/or

PMMU

relinquish-and-retry.

The

frequency of

VMebus

deadlocks and/or

PMMU

relinquish-and-entry

determines the

intensity

of the

HALT

LED.

Also,

[BRDFAILJ

has

not

been

cleared since

reset

or

has

been

set

by

software.

3.2.4

Happing

Switch (53)

Switch

S3

is

the

slave

resource

mapping

switch.

It

is

an

eight-

position

piano

type

DIP

switch

that

maps

the

memory

and

MPCSR

on

the

VMEbus.

Mapping

options

for

the

MVME135/l35-1/136

occurs

on

1Mb

boundaries.

Mapping

is

possible

from

0Mb

to

32Mb.

Mapping

options

for

the

MVME135A/136A

occur

on

4Mb

boundaries.

Mapping

is

therefore.

possibl

e from

0Mb

to

128Mb

for

the

MVME135A/136A.

However, each

switch

setting

defines

4Mb

rather

than

1Mb.

3-3

I

W

I

~

o

A15

X

)

h

-

A14

A09

AOO

A07

X

~X:~

x

tX·~

GROUP SELECT

BASE OFFSET

(MPCSR BASE ADDRESS)

SWITCH S3

01010101010101010

~

DRAM

BASE«AODAESS1tf

FIGURE

3-2.

MVME135/135-1/136

SLAVE

ACCESS

ADDRESSING

)

•

~

AOO

0

)

o

-0

,.,.,

;;0

»

--i

.....

:z

Cl

-

:z

V'l

--i

;;0

c:::

("")

--i

-

o

:z

V'l

OPERATING

INSTRUCTIONS

The

following

illustrations

provide various examples

of

MPCSR

and

DRAM

base

addressing

(MVME135/135-1/136

versions

only).

Example

1:

(MVME135/135-1/136

versions

only).

Switch

S3

Mappi

ng

Switch

(Factory Configuration)

(NOTE:

ON

is

0,

OFF

is

1)

11111010101010101

MPCSR

(Located

In

VMEbus

Short

I/O

Space

SFFFF

XXXX)

Base

Addr

= 1 1 0 0 0 0 0 0 0 0 0 0

0000

=

SC000

DRAM Base

Addr = 0000

0 0 0 0 0 0 0 0

0000

0000 = S0000

0000

Example

2:

(MVME135/135-1/136

versions

only).

Switch

S3

Mapping

Switch

(NOTE:

ON

is

0,

OFF

is

1)

MPCSR Base

Addr

= 1 1 0 0 0 0 0 0 0 1 0 0

0000

=

SC040

DRAM Base

Addr = 0000

0 0 0 0 0 0 1 0

0000

0000 = 50020

0000

3-5

I

OPERATING

INSTRUCT

IONS

Example

3: (MVMEl35/135-1/136 versions

only).

I 1 I 1 I 0 I 0 I 0 I 0 I 1

111

MPCSR

Switch

S3

Mapp i ng

Switch

(NOTE:

ON

is

0,

OFF

is

1)

Base

Addr

= 1 1 0 0 0 0 0 0 0 1 1 0

0000

=

SC060

DRAM

Base

Addr = 0000

0 0 0 0 0 0 1 1

0a00

0000

0000 0000 0000 = $0030

0000

Example

4:

(MVME135/135-1/136

versions

only).

101 0 I 0 I 1 I 0 I 0 101 1 I

MPCSR

Switch

S3

Mapping

Switch

(NOTE:

ON

;s

0,

OFF

is

1)

Base

Addr

= 0 0 0 0 0 0 1 0 0 0 1 0

0000

=

S0220

DRAM

Base

Addr = 0000

0 0 0 1 0 0 0 1

0000

0000 = S0110

0000

3-6

l

)

MPCS~

BASE ADDRESS

lNSHORT

1/0

ADDRESS SPACE

A15

AOO

X 0

GROUP

SELECT

BASE OFFSET

(MPCSR BASE ADDRESS)

SWITCH

S3

-----.----.-.

FIGURE

3-3.

MVME135A/136A

SLAVE

ACCESS

ADDRESSING

w

......

)

a

"

,."

;0

l>

--i

Z

G">

z

Vl

--i

;0

C

n

--i

a z

Vl

I

OPERATING

INSTRUCTIONS

The

following

illustrations

provide various examples

of

MPCSR

and

DRAM

base addressing

(MVMEl35A/136A

versions

only).

Example

1:

(MVME135A/136A

versions

only).

I 1 I 1 I 0 I 0 I 0 I 0 I 0 101

Switch

S3

Mappi

ng

Switch

(Factory Configuration)

(NOTE:

ON

is

0,

OFF

is

1)

MPCSR

(Located

In

VMEbus

Short

I/O

Space

SFFFF

XXXX)

Base

Addr

= 1 1 0

~ ~ ~

0 0 0 ~ 0 0

0000

=

$C000

DRAM

Base

Addr = 0000

0 0 0 0 0 0 0 0

0e00

0000

0000 0000

0000 = $0000

0000

Example

2:

(MVME135A/136A

versions

only).

MPCSR

Switch

S3

Mappi

ng

Switch

(NOTE:

ON

is

0,

OFF

is

1)

Base

Addr

= 1 1 0 0 0 0 0 0 0 1 0 0

0000

=

$C040

DRAM Base

Addr = 0000 ~ 0 0 0 1 0 0 0

0~00

0~0~ 00~0 ~000

0000 = $0080

~~00

3-8

Example

3:

(MVME135A/136A

versions

only).

O:FUU~~~~UU

012345678

11111010101011111

MPCSR

OPERATING

INSTRUCTIONS

Switch

S3

Mapp;

ng

Switch

(NOTE:

ON

is

0,

OFF

;s

1)

Base

Addr

= 1 1 0 0 0 0 0 0 0 1 1 0

0000

=

$C060

DRAM

Base

Addr = 0000

0 0 0 0 1 1 0 0

0000

0000 0000

0000

0000 = S00C0

0000

Example

4:

(MVME135A/136A

versions

only).

O:F~~~U~~~U

012345678

10101011101010111

MPCSR

Switch

S3

Mappi

ng

Switch

(NOTE:

ON;s

0,

OFF;s

1)

Base

Addr

= 0 0 0 0 0 0 1 0 0 0 1 0

0000

=

$0220

DRAM Base

Addr = 0000

0 1 0 0 0 1 0 0

0000

0000 0000

0000 = $0440

0000

3-9

I

OPERA

TI

NG I NSTRUCTI

ONS

3.2.5

System

Confi

gurat

ion

Swi

tch

(S4)

Switch

S4

is a ten-position

piano type

DIP

switch

that

provides

the

following

functions

as defined

by

135bug

(refer

to

the

135bug

manual

for

a

more

detailed

description).

Note

that

S4-1

and

S4-2 are

implemented in hardware

and

that

the

other

eight

positions

are

implemented in

the

135bug

monitor.

Switch

S4

00FNFnnnnnnnnnn

System

Configuration Select

..................

~

(Factory Configuration)

1 2 3 4 5 6 7 8 9 10

(NOTE:

ON

is e,

OFF

is

1)

3-1e

L

Ss4-10:

OFF=

Autoboot enabled.

ON

= Autoboot disabled.

4-9

OFF=

MP

bits

enabled.

ON = MP

bits

disabled.

S 4-8

S

4-7

S

4-6

S

4-5

S

4-4

S

4-3

S

4-4

S

4-3

S

4-4

S

4-3

S

4-4

S

4-3

S

4-2

S

4-1

OFF=

VSBbus

disabled.

ON = VSBbus

enabled.

OFF=

VSB

not system

controller.

ON = VSB

is

system

controller.

OFF=

24-bit

VMEbus

addr width.

ON = 32-bit

VMEbus

addr width.

OFF=

16-bit

VMEbus

data width.

ON

32-bit

VMEbus

data width.

ON

{135bug executes 1

oca

11

y,

ON

DRAM

mapped

at

$0.

OFF= { 135bug

executes

locally.

ON

DRAM

mapped

at

SFFXe00ee.

ON

{135bug executes over the

OFF

VMEbus

BASE.

OFF= { 135bug

executes in

first

OFF

off-board

VMEbus

memory.

OFF=

RESET/ABORT

disabled.

ON = RESET/ABORT

enabled.

OFF=

VME

not system

controller.

ON = VME

is

system

controller.

OPERATING

INSTRUCTIONS

3.3

MEMORY

MAP

AND

MAP

DECODER

At

the beginning

of

each

MPU

cycle,

the

map

decoder

determines

what

kind

of

cycle

takes

place

and

which

device

or

function

is

selected

within

that

cycle

type.

Cycle types

are

determined

by

the

function

code 1

ines

FC2

through

FC0,

which are

driven

by

the

MC68020

MPU.

The

cycle

types

and

the

devices

that

respond

are

listed

in Table

3-2.

FC2

FCI

FC0

1

o

TABLE

3-2.

FUNCTION

CODE

ASSIGNMENTS

Cycle

Type

Reserved User

Data

User

Program

Reserved Reserved Supervisory

Data

Responding

Board

Devices/Functions

None

(causes 1

oca

1 timeout).

All

except the

interrupt

handler,

MC68851.

and

MC68881.

All

except the

interrupt

handler,

MC68851,

and

MC68881.

None

(causes local timeout).

None

(causes local timeout).

All

except the

interrupt

handler,

MC68851,

and

MC68881

.

o Supervisory

Program

All

except the

interrupt

handler,

CPU

(lACK)

CPU

Coprocessor

MC68851,

and

MC68881.

VMEbus

interrupt

and

the local

interrupt

handl

er.

MC68851

and

MC68881.

3-11

I

OPERATING

INSTRUCTIONS

3.3.1

HVHEl35/135-1/136

Ha

in

Memory

Hap

The

memory

map

of

devices

that

respond

in

User

Data,

User Program,

Supervisory

Data,

and

Supervisory

Program spaces

is

shown

in

the

following

table.

TABLE

3-3.

MVMEI35/135-1/136

HAIN

MEMORY

MAP

Physical Address

Range

(Hexadecimal) Devices

AccEssed

00000000 -000FFFFF

VMEbus

A32/A24/VSB

or

Optionally

On-board

DRAM

00100000 -00FFFFFF

VMEbus

A32/A24/VSB

01000000 -FFDFFFFF

VMEbus/A32/VSB FFE00000 -FFEFFFFF FFF00000 -FFFIFFFF FFF20000 -FFF9FFFF FFFA0000 -FFFAFFFF FFFB0000 -FFFB002F FFFB0030 -FFFB0031 FFFB0032 FFFB0033 -FFFB0037 FFFB0038 FFFB0039

FFFB003A FFFB003B FFFB003C -FFFB003F FFFB0040 -FFFB004F

On-board

DRAM

On-board

ROM/PROM/EPROM

Not

Used

MVSB2400

(VSB)

Gate

Array

Z8036

Ti

mer

(STAll,

CNll)

Not

Used

STAT2

Not

Used CNT2 CNT3 CNT4 CNT5 Not

Used

MC68681

Serial

Controller

Port Size Size

(Bytes)

032/016

1Mb

032/016

15Mb

032

4Gb 032 016 N/A 016 008 N/A 008 N/A 008 008

008

N/A 038

1Mb

128Kb

512Kb 64Kb 64Kb 2b Ib 4b Ib

Ib Ib 1b

4b

16b

FFFB0050 -FFFB005F

Not

Used

N/A

16b

FFFB0060 -FFFB007F

MPCSR

Regi

sters

008

32b

FFFB0080 -FFFBFFFF

Not

Used

N/A

64Kb

FFFC0000 -FFFEFFFF

Reserved

N/A

128Kb

FFFF0000 -FFFFFFFF

VMEbus

A16

Short

I/O

Space

016

64Kb

Notes

NOTES:

When

the

option 0 bit

(OPT0)

in

Control

Register

5 (CNT5)

is

set,

then

local

ORAr~

appears

in

this

address

space.

When

OPT0

is

cleared,

this

address space

is

decoded

as

VMEbus

A32/A24

or

VSB

(refer

to

section

4.15.2).

3-12

,....

OPERATING

INSTRUCTIONS

3.3.2

MVMEl35A/136A

Main

Memory

Map

The

memory

map

of

devices

that

respond

in

User

Data,

User

Program,

Supervisory

Data,

and

Supervisory

Program spaces

is

shown

in

the

following

table.

TABLE

3-4.

MVME135A/136A

MAIN

MEMORY

MAP

Physical Address

Port

Size

Range

(Hexadecimal) Devices Accessed Size

(Bytes)

Notes

00000000 -003FFFFF

VMEbus

A32/A24/VSB

or

032/016

4Mb

Optionally

On-board

DRAM

004001300 -013FFFFFF

VMEbus

A32/A24/VSB

032/016

12Mb

0101301300 -FFDFFFFF

VMEbus/A32/VSB

032/016

4Gb

FF80e1300 -FFBFFFFF

On-board

DRAM

032

4Mb

FFCe00130 -FFEFFFFF

Not

Used

N/A

3Mb

FFF00130e -FFFIFFFF

On

-board

ROM/PROM/EPROI~

016

128Kb

FFF2e0130 -FFF9FFFF

Not

Used

N/A

1Mb

FFFA00130 -FFFAFFFF

MVSB24ee

(VSB)

Gate

Array

016

64Kb

FFFB0000 -FFFB002F

Z8036

Timer (STATl, CNTl)

008

64Kb

FFFBe030 -FFFBee31

Not

Used

N/A

2b

FFFB0032

STAT2

008

Ib

FFFBe1333 -FFFB0037

Not

Used

N/A

4b

FFFB131338

CNT2

0138

Ib

FFFB13039

CNB

0138

Ib

FFFB1303A

CNT4

0138

Ib

FFFB1303B

CNT5

008

Ib

FFFB1303C -FFFB1303F

Not

Used

N/A

4b

FFFB1313413 -FFFB1304F

MC6868i

Serial

Controller

008

16b

FFFB130513 -FFFB1305F

Not

Used

N/A

16b

FFFB01360 -FFFB13137F

MPCSR

Reg i sters

008

32b

FFFB0080 -FFFBFFFF

Not

Used

N/A

64Kb

FFFC001313 -FFFEFFFF

Reserved

N/A

128Kb

FFFF13I3I313 -FFFFFFFF

VMEbus

A16

Short

I/O

Space

016

64Kb

NOTES:

When

the

option

13

bit

(OPT~)

in

Control

Register

5 (CNT5)

is

set,

then

local

DRAM

appears

in

this

address

space.

When

OPT13

is

cleared,

this

address

space

is

decoded

as

VMEbus

A32/A24

or

VSB

(refer

to

section

4.15.2).

3

-13

I

OPERATING

INSTRUCTIONS

I

3-14

FUNCTIONAL

DESCRIPTION

CHAPTER

4 -

FUNCTIONAL

DESCRI

PTION

4.1

INTRODUCTION

This

chapter

provides

the

overall

block

diagram

level

description

for

the

MVf1E135/136

module. The

general

description

provides

an

overview

of

the

module,

followed

by a detailed

description

of

each

section

of

the

module. The

simplified

block

diagram

for

the

MVMEI35/135-1/136

is

illustrated

in

Figure

4-1

and

for

the

MVMEl35A/136A

in

Figure

4-2.

4.2

GENERAL

DESCR I PTI

ON

The

MVME135/136

is

a

MC68020

microprocessor-based

module. The

module

incorporates

an

MC68020,

a

32-bit

address

and

data

microprocessor,

a

high

level

multiprocessor

CSR.

and

1Mb

(MVME13

5/13 5 -1/136

vers i on

s)

or

4Mb

(MVME

13

5A/

136A

vers i on

s)

of

fast

DRAM.

Other

features

include

a Paged

Memory

Management

Unit

(PMMU).

a

Floating

Point

Coprocessor

(FPCP),

an

A32/D32

VMEbus

interface,

a

secondary

bus

interface

(VSBbus), two RS-232C

serial

ports.

two

16-bit

timers,

two

28-pin

ROM/PROM/EPROM

sockets,

VMEbus

system

controller

functions,

a

seven-level

VMEbus

interrupt

handler,

and a

dual

ported,

high-level

communication

interface

call

ed

the

Mul

t i

processor

Control

and

Status

Regi

sters

(MPCSR).

4.2.1

Data

Bus

Structure

The

data

bus

structure

on

the

MVME135/136

modul e

is

arranged

to

accommodate

the

8-bit,

16-bit,

32-bit.

and

16/32-bit

ports

that

reside

on

the

module.

The

8-bit

ports

are

connected

to

data

lines

D24

through

D31

of

the

local

bus,

the

16-bit

ports

are

connected

to

data

lines

016

through

D31

of

the

local

bus,

and

the

32-bit

ports

are

connected

to

data

1 i nes

D00

through

031

of

the

local

bus.

4.2.2

Memory

Map

The

operation

of

the

map

decoder

and

tables

providing

the

main

memory

maps

of

the

MVME135/136

modules

are

provided

in

Chapter

3.

4.2.3

Timing

General

characteristics

of

the

MVME135j136

module

timing

are

given

in

the

following

sections

and

Table

4-1.

4.2.4

MVME135/135-1j136

DRAM

Cycl e Times

MPU

accesses

to

the

on-board

DRAM

require

a mlnlmum

of

three

MPU

clock

cycles.

A

clock

cycle

at

16.67

MHz

is

60

nanoseconds

and

at

20.00

MHz

is

50

nanoseconds.

4-1

I

.,.

I

N

•

VMEbus EXTENDED VMEbus I VSBbus

FIGURE

4-1.

MVMEI35/135-1/136

BLOCK

DIAGRAM

) )

.."

C

Z

n

-l

o z

):>

r-

o

,...,

VI

n

;:0

"'t:J

-l

o

Z

-l'>o

,

w

VMEbus

.,

EXTENDED

VMEbus/VSBbus

FIGURE

4-2.

MVME135A/136A

BLOCK

DIAGRAM

II

..,.,

c

:z

n

-l

.....

o

:z

»

r-

o

rr1

V>

n

;x:J

"

-l

o :z

I

FUNCTIONAL

DESCRIPTION

The

addition

of

the

PMMU

adds one

wait

cycle

(three

minimum + one

wait

cycle).

Parity

adds one

wait

cycle

to

the

total

number

of

MPU

clock

cycles,

(four

total

for

the

MVME135/135-1 and

five

total

for

the

MVME136).

4.2.5

MVMEl35A/136A

DRAM

Cycle

Times

MPU

accesses

to

the

on-board

DRAM

require

four

MPU

clock

cycles

(three

minimum + one

wait

cycle)

for

slower

memories. A clock

cycle

at

16.67

MHz

is

60

nanoseconds.

The

addition

of a PMMU

adds one

wait

cycle

(three

minimum + one

wait

cycle).

Parity

does

not

add

additional

wait

cycles

on

the

MVME135A/136A.

TABLE

4-1.

MVME135/136

TIMING

MVME135

MVME135'1

MVME135A

MVMEl36

MVME136A

ACCESS SEQUENCE

(15.67

MHz)

(20.00

101Hz)

(16.57

101Hz)

(16.57

MHz)

(16.67

101Hz)

WRITE

READ

WRITE

READ WRITE READ WRITE READ

WRITE READ

MPU

TO LOCAL DRAM 3

3 3

3 4 4

4

4 5 5

(NO

PARITY)

MPU TO

LOCAL

DRAM

4 4

4

5 5

(PARITY

ENABLED)

MPU TO

LOCAL

ROM /

..

B

..

B

..

9

..

9

..

9

PROM/EPROM

VMEbua TO

LOCAL

11

10

11

10 12

11

12

11

DRAM

MPU TO

GLOBAL

DRAM

OVER VSB B

B 9 9 B B 9 9 9

9

(MVME204 •

2F )

MPU

TO

GLOBAL

DRAM

OVER VMEbua 9

10 12

14

9 10

10

11

10

11

(MVME204 • 2F )

WRITE

READ

WRITE READ

WRITE

READ WRITE READ WRITE

READ

ACCESS

SEOUENCE

MVME135 MVMEI3S·1 MVMEI3SA

MVME135

MVME136A

(16.67

101Hz)

(20.00

101Hz)

(16.67

101Hz)

(16.67

101Hz)

(16.67

101Hz)

ALL

T1MES

ARE TOTAL NUMBER OF MC6B020 CLOCK CYCLES.

4.2.6

ROM/PROM/EPROM/EEPROM

Cycle Tines

All

ROM/PROM/EPROM/EEPROM

accesses

require

eight

MPU

clock

cycles

when

NO

PMMU

is

installed,

and

nine

MPU

clock

cycles

to

complete

when

the

PMMU

is

installed.

4-4

FUNCTIONAL

OESCR!

PTION

4.2.7

VMEbus

Cycle

Times

The

following formula assumes

that

the

MVME135/136

module

is

the

current

VMEbus

master

and

that

all

slaves

have

released

OTACK*

and

BERR*.

The

time from

the

activation

of

OS0*/OSI*

to

the

activation

of

OTACK*

is

Tac

in nanoseconds, T

is

the

MPU

clock

period in

nanoseconds,

and N is

the

total

number

of

MPU

clock

periods

required

to

complete a

VMEbus

cycle.

N

must

always

be

rounded

up

to

the

For

read accesses

For

write accesses

N 5

+

[Tac / T]

N 6 +

[Tac / T]

typical typical

The

following formula assumes

that

the

MVMEI35/136

module

is

NOT

the

current

VMEbus

master,

but

that

it

is

the system

controller.

Also,

it

assumes

that

all

have

released

OTACK*

and/or

BERR*

when

the

MVME135/136

module

receives

VMEbus

mastership.

The

delay

from

BR3*

low

(driven

by

MVME135/136)

to

BBSY*

high

and

AS*

high

is

Tr.

The

time

from

the

activation

of

OS0*/OSI*

to

the

activation

of

OTACK*

is

Tac

in nanoseconds, T

is

the

MPU

clock

period

in nanoseconds.

and

N

is

the

total

number

of

MPU

clock

periods

required

to

complete a

VMEbus

cycle.

N must always

be

rounded

to

the next

integer.

For

read accesses

For

write accesses

N 6

+

[Tac

+ Tr)

T]

N 7 +

[Tac

+ Tr)

T]

typical typical

The

following formula assumes

that

the

MVME135/136

module

is

NOT

the

current

VMEbus

master,

and

it

is

NOT

the

system

controller.

Also.

it

assumes

that

all

have

released

OTACK*

and/or

BERR*

when

the

MVME135/136

receives

VMEbus

mastership.

The

delay

from

BRX*

low

(driven

by

MVME135/136)

to

BGXIN*

low

and

AS*

high

is

Tg.

The

time

from

the

activation

of

OS0*/OSI*

to

the

activation

of

OTACK*

is

Tac

in nanoseconds, T

is

the

MPU

clock

period

in

nanoseconds,

and N is

the

total

number

of

MPU

clock

periods

required

to

complete a

VMEbus

cycle.

N

must

always

be

rounded

to to

the

For

read accesses

For

write accesses

4.2.8

VMEbus

Arbitration

Time

N 6 +

[Tac + Tg)

T]

N 7 +

[Tac + Tg)

T]

typical typical

When

the

MVME135/136

module

is

configured as

the

system

controller

and

is

not

requesting

VMEbus

mastership,

the

delay

from

BBSY*

high

and

BR3*

low

to

BG30UT*

low

is

35

nanoseconds

typi

cal

and

50

nanoseconds

maximum.

4-5

I

FUNCTIONAL

DESCRIPTION

When

the

MVMEl35/136

modul e is

not confi gured as

the

system

controller

and

is

not

requesting

VMEbus

mastership,

the

delay

from

BGXIN*

low

to

BGXOUT*

low

is

45

nanoseconds

typical

and

6~

nanoseconds

maximum.

4.3

MC68020

MPU

The

MC68020

is

the

main

microprocessor

of

the

MVMEI35/136.

The

MVMEI35/135A/136/136A

versions

utilize

the

MC68020

operating

at

a

fixed

operating

speed

of

16.67

MHz.

On

the

MVMEI35-1

version,

the

fixed

operating

frequency

is

20.00

MHz.

The

MC68020

is a full

32-bit

microprocessor with

32-bit

registers,

32-bit

data,

and

32-bit

addresses.

Its

advanced

architecture,

enhanced

addressing

modes,

and

on-chip cache

are

advancements over

its

predecessors

in

the

MC68000

family

of

chips.

The

32-bit

data

and

address

architecture

of

the

MC68020

fully

supports

applications

in

environments based

on

an

asynchronous, non-multiplexed

bus

such as

the

VMEbus.

The

microprocessor

includes

control

inputs

and

an

internal

multiplexer

that

enable

it

to

perform

automatic

port

sizing

during each bus

cycle.

Use

of

this

mechanism

facilitates

the

transfer

of

one, two,

or

four byte operands

to

and

from

external

devices

of

any

data

port

width

effectively

eliminating

all

alignment

restrictions.

Refer

to

the

MC68020UM/AD

User's

Manual

for

a

detailed

description

of

its

operation.

4.4

MC68881

FPCP

The

MVMEI35/135A/136/136A

versions

are

equipped with a 16.67

MHz

MC68881

Floating-Point

Coprocessor.

On

the

MVME135-1

version,

the

MC68881

operates

at

20.00

MHz.

The

MC68881

extends

the

main

MPU

integer

data

processing

capabilities.

It

does

this

by

providing a

very high performance

binary

floating-point

arithmetic

unit

and

a

set

of

floating-point

data

registers

that

are

utilized

in a manner

analogous

to

the

use

of

the

integer

data

registers.

The

MC68881

instruction

set

is

a

natural

extension

to

that

of

all

earlier

members

of

the

M68000

family,

and

supports

all

of

the

addressing

modes

of

the

host

MPU.

Refer

to

the

MC68881UM/AD

User's

Manual

for

a

detailed

description

of

its

operation.

4. S MC688S1

PMMU

Memory

management

for

the

MVME136

and

MVME136A

is

provided

by

a

16.67

MHz

MC68851.

The

MC68851

is

a high performance Paged

Memory

Management

Unit

(PMMU)

designed

to

efficiently

support

a

demand

paged

virtual

memory

environment with

the

MC68020

32-bit

microprocessor.

The

PMMU

is

optimized

for

very

fast

logical-to-

physical

address

translations,

to provide a comprehensive access

control

and

protection

mechanism,

and

to

provide

extensive

support

for

paged

virtual

systems. Operating as a

coprocessor

to

the

4-6

FUNCTIONAL

DESCRIPTION

MC68020,

the

PMMU

provides

a

logical

extension

to

the

program

control

and

processing

abilities

of

the

main

processor.

It

does

this

by

providing a set

of

translation,

protection,

and

breakpoint

registers

that

control

operation

of

the

memory

management

mechanism. These

registers

are

utilized

in a manner

similar

to

the

use

of

any

internal

processor

register.

4.6

DEBUG

MONITOR

FIRMWARE

The

MVME135bug

Debug

Monitor firmware package

is

optionally

available

for

use with

any

of

the

MVME135/136

modules. This

firmware

offers

32

debug

capability,

upload/download,

disk

bootstrap

commands, a one

line

assembler/disassembler

with

full

MC68881

support,

as well as a

full

set

of

on-board

diagnostics.

Refer

to

the

135bug Diagnostic/Debug Package

User's

Manual

for

a

detailed

description

of

its

operation.

4.7

VME

SUBSYSTEM

BUS

(VSBbus)

The

VME

Subsystem

Bus

(VSBbus

is a subset

of

the

VMEbus)

is a local

extension

bus.

It

allows a

processor

board

to

access

additional

memory

and

I/O

over a local

bus, removing

traffic

from

the

global

bus

and

improvi

ng

the

total

throughput

of

the

system.

The

VSBbus

interface

occupies

64

I/O

pins

on

connector

P2

and

utilizes

the

multiplexing

of

address

and

data

in

order

to

accommodate

full

32-bit

functionality,

along

with

appropriate

control

signals,

within

the

64-pin

allotment.

On

the

MVME135/136

modules,

VSBbus

is

implemented through

the

use

of

the

MVSB2400.

The

MVSB2400

is

a 132-pin

gate

array

subset

of

the

VSBbus

specification

in a

PGA

package.

The

MVSB2400

provides

most

of

the

functionality

required

to

support a master

VSBbus

interface

using one

VLSI

device

and a few

external

gates,

and

contains

most

of

the

bus

drivers

for

the

VSBbus

and

all

of

the

address

and

data

multiplexing

circuits.

Refer

to

the

MVSB2400

VSBchip

User's

Manual

for a deta

i 1

ed

descri

pt i on

of

its

operat

ion.

Although

the

MVSB2400

VSBchip

has a

slave

mode,

the

MVME135/136

does not

support

VSBbus

sl

ave

accesses.

4.8

DYNAMIC

RAM

The

MVME135/136's

dynamic

random

access

memory

uses

256K

x 1

or

1M

x

1 dynamic

RAMs

surface

mounted

on

a mezzanine

board,

providing

a

total

of

1Mb

to

4Mb

of

local

DRAM

with

optional

parity.

It

is

accessible

from

the

MC68020,

the

refresh

circuitry,

and

the

VMEbus,

each

of

which

requests

and

is

granted

use

of

the

DRAM

by

an

on-board

arbiter.

The

on-board

DRAM

is

designed to

operate

at

zero

wait

cycles

at

both

16.67

MHz

and

20.00

MHz

without

parity

and

a bypass board

installed

4-7

I

FUNCTIONAL

DESCRIPTION

in

the

PMMU

socket.

Memory

management,

pari

ty

and

the

processor

clock

frequency

all

affect

the

speed

of

the

local

DRAM

and

VMEbus

accesses.

Because

the

local

address

and

data

buses

are

used

to

access

the

on-

board

DRAM,

any

device

that

uses

the

DRAM

must become

the

local

bus

master.

An

on-board

arbiter

handles

this

using

the

MC68~2~

arbitration

logic

to

transfer

local

bus

mastership

from

the

current

master

to

the

next.

During normal

operation,

the

MC68~2~

is

the

local

master.

When

the

VMEbus

requires

use

of

the

DRAM,

the

arbiter

requests,

and

is

granted

the

local

bus

by

the

MC68~2~.

At

this

time,

memory

timing

circuitry

executes

one

DRAM

cycle

(read

or

write)

and

rel

inquishes

the

local

bus

mastership,

after

which,

the

MC68~20

resumes

local

bus

mastership.

If

a

refresh

cycle

is

required,

the

current

bus

cycle

is

stretched,

eliminating

the

need

for

the

refresh

circuitry

to

obtain

local

bus

mastership.

The

user

can

select

the

address

at

which

the

on-board

DRAM

appears

from

the

VMEbus

by

setting

S3

(an

8-position

DIP

switch).

This

switch

is

used

not

only

to

determine

the

address

of

the

DRAM,

but

is

also

used

to

determine

the

location

at

which

the

Multiprocessing

Control/Status

Register

(MPCSR)

is

located.

This

mapping

is

explained

in

detail

in

section

4.16

and mapping examples

are

provided

in

section

3.2.4.

On-board

DRAM

responds

to a VMEbus

access

only

when

address

modifier

lines

AM~

through

AMS

indicate

extended

or

standard,

privileged

or

non -pri

vil

eged

data

or

program

space.

4.9

FUNCTION

CODE

ASSIGNMENTS

Decoding

logic

on

the

MVME13S/136

module

determines

the

supervisor

or

user

processor

state

and

type

of

address

space

ass

i gnments

controlled,

for

each

cycle,

by

the

collective

state

of

the

MC68~2~

Function

Code

pins

(FC2,

FC1,

and

FC~).

In

addition

to

the

standard

supervisor

or

user

processor

state

and

type

of

address

space,

the

MVME13S/136

modules use

the

CPU

space

assignment

to

implement

coprocessor,

interrupt

handl i ng, and

other

functions.

Refer

to

Table

4-2

for

the

function

code

assignments.

4.10

MVHEl35/136

USE

OF

CPU

SPACE

The

MVME13S/136

devices

and

functional

blocks

respond

to

four

types

of

CPU

space

accesses

(FC2-FC~

=

Ill):

breakpoint

(MC688Sl),

access

level

(MC688S}),

coprocessor

(Me688S}

and MC6888!), and

interrupt

acknowledge. The

type

of

access

determined

by

A19

through

A}6

is

illustrated

in

Figure

4-3.

4-8

FUNCTIONAL

DESCRIPTION

TABLE

4-2.

FUNCTION

CODE

ASSIGNMENTS

FC2

FCI

FCO

CYCLE

TYPE

RESPONDING MVME135 I 136 MODULE

DEVICES

I FUNCTIONS

0

RESERVED

NONE

(CAUSES

LOCAL TIMEOUT).

0 0 1

USER DATA

ALL

EXCEPT ThE INTERRUPT HANDLER, ThE

MC6S851

,

AND

ThE

MC68881.

0

1

0 USER PROGRAM

ALL EXCEPT

ThE

INTERRUPT HANDLER,

ThE

MC66651,

AND

ThE

MC681181.

0 1

1 RESERVED

NONE

(CAUSES LOCAL TIMEOUT).

1

0

RESERVED

NONE

(CAUSES LOCAL TIMEOUT).

1

0

1 SUPERVISORY DATA

All

EXCEPT ThE INTERRUPT HANDLER,

ThE

MC6SaS1,

AND

ThE

UC6aB81.

1 1

0 SUPERVISORY PROGRAM ALL EXCEPT

ThE

INTERRUPT HANDLER, ThE

MC68&51,

AND

ThE

MC681181

,

1 1

1 CPU

(lACK)

ThE

LOCAL HANDLER AND

ThE

VMEbua INTERRUPT.

1

CPU

COPROCESSOR

ThE

MC6SaS

1 AND

1oIC66681.

FUNCTION CODE

FC3

F~

rA~31~

__________________

-fA~19~

__

~Al~6rA~15~

________________________

~A~OO

I 0 1 1 1 I I x x x x x x x x x x x x I

TYPE

FIELD

I I

CPU SPACE

TYPE

FIELD

CPU SPACE TRANSACTION

(AID.

A16)

o 0 0 0 BREAKPOINT ACKNOWlEOGE

000

1

ACCESS LEVEL

CONTROL

o 0 1 0

COPROCESSOR COMlolUNICA TlONS

1 1 1 1

INTERRUPT ACKNOWLEDGE

FIGURE

4-3.

CPU

SPACE

TYPE

FIELD

ENCODING

4.10.1

MC68851

Breakpoi

nt

Support

In

order

to

simplify

debugging

and

emulation

for

system

developers,

the

designers

of

the

MC68851

took

full

advantage

of

an

MC68020

extension

to

the

M68000

family

instruction

set,

the

BreaKPoinT

instruction

BKPT,

and

the

supporting

breakpoint

acknowledge bus

cycl

e.

The

three

low

order

bi

ts

of

the

instruct i on

are

used as

immediate

data

that

can

be

transmitted

by

the

breakpoint

acknowledge

bus

cycle

to

an

external

device

to

signal

that

the

processor

has

encountered a breakpoint

and

requires

further

direction.

Since

the

three

low

order

bits

represent

data,

the

processor

can

respond

to

4-9

I

FUNCTIONAL

DESCRIPTION

eight

opcodes

($4848

to

$484F)

thus

providing

a means

of

initiating

eight

different

types

of

breakpoint

processing.

4.10.2

MC68851

Breakpoint Operation

During

MVME135/136

operation

after

the

processor

fetches

a

breakpoint

opcode,

it

performs a breakpoint

acknowledge

cycle

in

which,

it

sets

the

function

code 1 ines

to

indicate

CPU

space

and

sets

address

lines

A16

through

A19

to

indicate

the

breakpoint

acknowledge

type

of

CPU

space.

It

also

decodes

the

three

low

order

bits

of

the

opcode

and

places

the

obtained

breakpoint

number

on

address

lines

A2

through

A4.

On

decoding

the

address

lines

when

it

begins

its

acknowledge

cycle,

the

MC68851

has two

options.

It

can

force

the

processor

to

initiate

illegal

instruction

exception

processing

by

asserting

the

BERR

signal

or

it

can

obtain

from one

of

its

eight

breakpoint

register

pairs a replacement

opcode

corresponding

to

the

breakpoint

number,

place

this

opcode

on

the

processor

data

bus and

assert

the

DSACK

signal. The

processor

then

replaces

the

breakpoint

opcode

in

its

instruction

pipeline

with

the

new

opcode

supplied

by

the

MC68851

and

continues

execution.

The

systems

programmer has

full

discretion

to

design

the

actions

initiated

by

execution

of

the

replacement

opcode.

The

breakpoint

acknowledge

cycle

address

bus

decoding

by

the

MC68851

is

illustrated

in

Figure

4-4.

The

bits

marked

"x"

are

zero

filled

by

the

CPU

and

ignored

by

the

MC68851.

FUNCTION CODe

A19 A15 A04

AOO

x x x x x x x x x x x

-\

o 0 0 0 j

o 0 0 0 0 0 0 0 0 0 0 j

BKPTI

jx

x

BREAKPOINT ACKNOWLEDGe

J

CPU SPACE CYCLE

1

BKPT.

BREAKPOINT SELECTED

0

0 BREAKPOINT REGISTER 10

0 0

1

BREAKPOINT REGISTER

'1

0 1 0

BREAKPOINT REGISTER

'2

0 1 1

BREAKPOINT

REGISTER

.3

1

0

BREAKPOINT REGISTER

'4

1 0 1

BREAKPOINT REGISTER

15

1

0 BREAKPOINT REGISTER

.6

1 1

1

BREAKPOINT REGISTER

'7

FIGURE

4-4.

BREAKPOINT

ACKNOWLEDGE

CYCLE

ADDRESS

ENCODING

4-10

FUNCTIONAL

DESCRI

PTION

4.10.3

MC68851

Breakpoi

nt

Archi

tecture

For each

of

the

eight

breakpoint

opcodes

recognized

by

the

MC68020,

the

MC68851

has

a

pair

of

registers:

a

breakpoint

acknowledge

control

register

and a

breakpoint

acknowledge

data

register.

Figure

4-5

illustrates

these

and

the

breakpoint

opcode

to

which

each

pair

corresponds.

15 o

15

o

CORRESPONDING

OPCODE

BAOO

BACO

S4848

BADI

BAC1

$4849

BAD2 BAC2

S464A

BAD3

BACl

$484B

BAD4 BAC4

$484C

BADS

BACS

$4SCO

BAD6 BACS

S4ME

BAD7

BAC7

S484f

FIGURE

4-5.

BREAKPOINT

REGISTERS

Each

of

the

breakpoint

acknowledge

data

registers,

BAD0

through

BAD7,

can be

loaded

with a replacement

opcode

for

transfer

to

the

MC68020

during

the

MC68851

acknowledge

cycle.

Using

the

PMOVE

instruction,

the

16-bit

value

for

a

legal

MC68020

opcode

may

be

written

to

(or

read

from) any

BADx

register

in

the

format

illustrated

in

Figure

4-6.

15

BAD.

REPLACEMENT

OPCOOE

FIGURE

4-6.

BREAKPOINT

ACKNOWLEDGE

DATA

REGISTER

FORMAT

The

manner

in

which

the

data

in

controlled

by

data

written

acknowledge

control

register

-

Figure

4-7.

a

BAD x register

is

actually

used

is

in

the

corresponding

breakpoint

BACx-

in

the

format

illustrated

in

15

7

o

BAC. I BPE

I 0 I 0 I 0 I 0 I 0 0 I 0 I

FIGURE

4-7.

BREAKPOINT

ACKNOWLEDGE

CONTROL

REGISTER

FORMAT

4-11

I

FUNCTIONAL

DESCR!

PTION

4.10.4

MC68851

Acknowledge

Cycle Operation

Bit

IS

of a BACx

register

acts

as a BreakPoint Enable

(BPE)

control

field.

During

the

MC688S1

acknowledge

cycle,

when

the

breakpoint

register

pair

corresponding

to

the

transmitted

breakpoint

number

has been

selected,

the

BPE

bit,

if

clear,

disables

transmission

of

the

replacement opcode

currently

in

BADx

by

causing

the

MC688S1

to

assert

the

BERR

signal

and

thereby

forcing

the

processor

to

initiate

exception

processing.

The

BPE

bit

in

all

eight

registers

is

cleared

by a reset

cycl

e.

Bits

0 through 7

of a BACx

register

are

used as a

breakpoint

skip

count

field

whose value

specifies

the

number

of

times

that,

in

response

to

repeated

processor

breakpoint

acknowledge

cycles

causing

selection

of

that

particular

BACx

register

(and

the

corresponding

BADx

register),

the

MC688S1

will

transmit

the

current

replacement opcode

before

forcing

the

processor

to

initiate

exception

processing

by

asserting

the

BERR

signal.

A

reset

cycle

does not

clear

the

skip

count

field

in

any

of

the

eight

acknowledge

control

registers.

Refer

to

the

NC68851

User's

Manual

for a more

detailed

description

of

the

MC68851

breakpoint

registers

and

functions.

4.10.5

Access

Level

Control

For communications between

the

MC68020

and

the

MC68851

during

the

Access

level

Control

(ACL)

type

of

CPU

space

operations,

the

PMMU

has

an

interface

that

includes

a

register

set

and

support

for

a

communications

protocol.

The

protocol

includes

electrical

and

command

level

mechanisms

that

enable

the

MC688S1

to

extend

the

means

of

protect i on

offered

by

the

rna; n processor.

Although

not

part

of

the

MC68851

programming model,

the

Access

level

Control

Registers

(AlCR)

operate

as communication

ports,

each

register

handling a specific

control

function.

To

use

the

function

associated

with a

register,

the

processor

accesses

the

register

by

encoding

the

address

bus

fields

illustrated

in

Figure

4-8.

Bits

positions

marked with

an

"x"

are

zero

filled

by

the

MC68020

and

ignored

by

the

PMMU.

FUNCTION CODE

FC3

FCO

A",,3C!...1

_---"!"'r-

_____

~F---r"'-------____rAO:.::.6-------=:A=OO

L

'11

xxxx

xxxxxxxx

4-12

ACCESS LEVEL CONTROL

BUS CYCLE PRIVILEGE LEVEL

000000000

MMU

REGISTER

ACCESS LEVEL

CONTROL INTERFACE REGISTER SELECT

CPU

SPACE CYCLE

FIGURE

4-8.

ALC

INTERFACE

LOGICAL

ADDRESS

BUS

ENCODING

FUNCTIONAL

OESCRI

PTION

The

MMU

register

(ALCR

select)

field,

A0

through

A15,

is

decoded

by

the

MC68851

to

select

the

appropriate

ALCR.

Although

the

MC68851

decodes the

full

address

range

specified

on

M through

A15,

the

ALCRs

occupy only

the

lower

128

bytes

of

this

range.

Table 4-3

provides a

map

of

the

MC68851

access

control

interface

registers

as

they appear in

the

CPU

address space. Refer

to

the

MC68851

User's

Manual

for a more

detailed

description

of

the

MC6885l

access

level

control

registers

and

functions.

TABLE

4-3.

ALC

INTERFACE

REGISTERS

MAP

REGISTER

MC68851

ACCESS

LEVEl

INTERFACE REGISTER

SELECT BUS

31

23

0

0000000

CL READ

(UNUSED, RESERVED)

0000100

ACCESS STATUS

READ

(UNUSED, RESERVED)

0001000

IAL

WRITE (UNUSED,

RESERVED)

0001100

DAL WRITE

(UNUSED,

RESERVED)

,

10000xx

FUNCTION

CODE

0 DESCRIPTOR ADDRESS

WRlTE

I

10001xx

FUNCTION CODE I DESCRIPTOR ADDRESS

(USER

DATA)

WRITE

I

10010x.

FUNCTION CODE 2 DESCRIPTOR ADDRESS

(USER

PROGRAM)

WRITE

I 0 0 I I • x

FUNCTION CODE 3 DESCRIPTOR ADDRESS

(USER

RESERVED)

WRITE

10100.·x

FUNCTION CODE 4 DESCRIPTOR ADDRESS (SUPERVISOR

DATA)

WRITE I

I

I 0 I 0 I • x FUNCTION CODE 5 DESCRIPTOR ADDRESS (SUPERVISOR PROGRAM)

WRITE

I

I 0 I I 0

••

FUNCTION

CODE

6 DESCRIPTOR ADDRESS

WRITE

1 0 1 1 1 x x I FUNCTION CODE 7 DESCRIPTOR ADDRESS

(CPU

SPACE)

WRITE

4.1e.6 Coprocessor

Communications

Both

the

MC68851

and

the

MC6888}

contain

a

set

Interface

Registers

(CIRs)

by

which

the

main

coprocessor

communicate. These

registers

are

not

programming

model

implemented

by

these

coprocessors,

of

Coprocessor

processor

and

the

FUNCTION

CODE

FC3

FCO

A31

A19

A15 A13 A12

A04

AOO

I 0 I I I

I x

x x x x

• x •

x x

x

• I 0 0 I o I CP

·10

I 0 0 0 0 0 0 0 0 I

CIR

SELECT

I

COPROCESSOR

COMMUNICATIONS--1

COPROCESSOR

INTERF~

REGISTER SELECT

CPU SPACE CYCLE

CP·IO

COPROCESSOR SELECTED

(A15·

A13)

0 0 0

MC68851

0 0 I

MC688S1

FIGURE

4-9.

COPROCESSOR

INTERFACE

ADDRESS

BUS

ENCODING

4-13

I

FUNCTIONAL

DESCRIPTION

Part

of

the

CPU

space

accessed

vi a

the

MC68020

address

bus

is

dedicated

to

coprocessor

functions.

Figure

4-9

illustrates

the

required

address

bus

encoding

for

coprocessor

accesses

in

the

CPU

space.

The

bit

pos

it

ions

marked

with

an

"x"

are

ignored

by

the

MC68851

and

MC68881

and

are

zero

filled

by

the

MC68020.

Table

4-4

identifies

locations

and

characteristics

of

the

MC68851

coprocessor

interface

registers

in

the

CUP

space,

that

are

used

for

communications between

the

MC68020

and

the

MC68851.

Table

4-5

identifies

the

locations

and

characteristics

of

the

MC68881

coprocessor

interface

registers

in

the

CPU

space

that

are

used

for

communications between

the

MC68020

and

the

MC68881.

For a more

detailed

description

of

the

MC68851

and

MC68881

coprocessor

registers

and

functions,

refer

to

the

MC68851

User's

Manual and

the

MC68881

User's

Manual.

TABLE

4-4.

MC68851

COPROCESSOR

INTERFACE

REGISTER

MAP

A04 ·AOO

MC68851

ACCESS LEVEL INTERFACE REGISTER

(IN

BINARY)

31

15

0

o 0 0 0 •

RESPONSE

(READ)

00

0 1 •

CONTROL

(WRITE)

001

O.

SAVE

(READ)

o 0 1 1 •

RESTORE (

READ

I WRITE )

01

00.

OPERATION

WORD

(WRITE)

o 1 0 1 •

COMMAND

(WRITE)

01

1 0 x

(RESERVED)

o 1 1 1 •

CONDITION

(WRITE)

1

00

x x

OPERAND

( READ

I WRITE )

1

0 1 x x

REGISTER SELECT

(READ)

(RESERVED J

1 1 0 • x

INSTRUCTION ADDRESS ( READ I WRITE )

1 1 1

I •

OPERAND ADDRESS

(WRITE)

4.11

INTERRUPT

HANDLER

The

MVME135/136

module

allows

interrupts

to

the

on-board

CPU

from

up

to

16

sources.

The

interrupt

handl

er

preprocesses

interrupt

sources

into

three

groups

of

seven

interrupts

corresponding

to

the

seven

MC68020

interrupt

levels.

The

groups

are

labeled

Group 1, Group 2,

and Group

3.

Interrupt

service

priority

is

determined

by

the

interrupt

level

and

the

group number.

Interrupts

of

different

levels

are

processed

according

to

the

standard

interrupt

processing

discipline.

Interrupts

of

the

same

level

are

processed

according

to

the

group number.

4

-14

FUNCTIONAL

OESCRI

PTION

TABLE

4-5,

MC68881

COPROCESSOR

INTERFACE

REGISTER

MAP

A04,

AOO

MC68881

ACCESS LEVEL INTERFACE REGISTER

liN

BINARY)

31

15

0

00

0 0 x RESPONSE

(READ)

o 0 0 1 x CONTROL

(WRITE )

o

0

lOx

SAVE

(READ)

00

1 1 x

RESTORE

(

READ

I WRITE)

o 1

0 0 x

OPERATION

WORD

(WRITE)

o 1 0 1 x COMMAND (ViRITE )

o 1

lOx

( RESERVED)

o 1 1 1

x

CONDITION

(WRITE)

1

00

x x OPERAND

( READ

I WRITE )

1

0 1 x x

REGISTER SELECT

(READ)

(RESERVED)

1

lOx

x

INSTRUCTION

ADDRESS

(WRITE)

1 1 1

••

OPERAND ADDRESS

( READ

I

WRITE

)

The

interrupt

handl

er

processes

Group 2 and Group 3

interrupts

differently

from Group 1

interrupts

which

are

reserved

for

VMEbus

interrupts.

If

the

interrupt

being

acknowledged

is

a Group 2

or

3

interrupt,

the

interrupt

handler

fetches

the

appropriate

exception

vector

number from

PROM

and

sends

it

to

the

CPU

via

the

local

bus,

If

the

interrupt

being

acknowledged

is

a Group 1

interrupt,

the

exception

vector

number

is

fetched

from

the

VMEbus

where

it

will

be

placed

by

the

interrupting

device,

Table

4-6

describes

the

interrupt

assignments,

TABLE

4-6,

INTERRUPT

HANDLER

PRIORITY

ASSIGNMENTS

PRIORITY WITHIN A PARTICULAR INTERRUPT LEVEL

DETERJ.UNES

THE SERVICE

ORDER

INTERRUPT

(HIGHEST)

( MIDOLE)

(LOWEST)

LEVEL

GROUP J

(VECTOR')

GROUP 2 (VECTOR')

GROUP 1

7

ABORT"

($40)

ACFIRQ' ($41 )

VUEbu.IRar

6 TURlRQ'

($42)

SFIRO'

($013)

VUEbu.

IR06'

5

SlotRQ'

($44)

SlGHP-

(S45)

VMEbu. IROS'

4 UNASSIGNED

VSBIRQ'

($47)

I

VMEb

...

IRQ.'

~.

3 UNASSIGNED UNASSIGNED

VMEbu.

IRaJ'

2

LMIRO'

($4A)

SlGLP-

($4B)

I

VMEbu.

IR02'

1

UNASSIGNED

I

VMEbus

!R01'

l

WITHIN A GROUP

" INTERRUPT PRIORITY DECREASES

WITH

DECREASING

LEVEL

WITHIN

A PARTICULAR INTERRUPT LEVEL, INTERRUPT

PRIORITY

DECREASES

FROM

LEFT

TO

RIGHT.

4-15

I

FUNCTIONAL

DESCRIPTION

ABORT*

<

Abort

Pushbutton

IRQ>

ABORT*

is

the

interrupt

caused

by

the

ABORT

pushbutton.

ACFIRQ*

<

VHEbus

AC

Power

Fail

IRQ>

ACFIRQ*

is

the

interrupt

caused

by

the

ACFAIL*

line

being

asserted

on

the

VMEbus.

TMRIRQ*

< Timer

IRQ>

TMRIRQ*

is

the

local

timer

chip's

interrupt.

This

will

also

be

the

broadcast

IRQ

caused

by

a

transition

on

the

IRQl* 1

ine

of

the

VMEbus

similar

to

the

MVME130,

provided

that

the

Z8036

timer

chip

is

preconfigured

to

assert

TMRIRQ*

upon

receipt

of a broadcast

IRQ

input.

SFIRQ*

<

VMEbus

System

Fail

IRQ>

SFIRQ*

is

the

interrupt

caused

by

the

SYSFAIL* 1 ine

of

the

VMEbus

being

asserted.

This

interrupt

is

maskab1e

using

the

SYSFIEN

bit

of < CNT3>

.

SIOIRQ*

< Dual Channel

Serial

Port

IRQ>

SIOIRQ*

is

the

interrupt

from

the

local

serial

port

chip,

the

MC68681.

The SIOIRQ*

interrupt

is

handled

the

same

as

all

other

local

interrupts,

where

the

vector

is

suppl

ied

by a PROM.

SIGHP*

<

MPCSR

High

Priority

IRQ>

SIGHP*

is

the

signal

high

priority

interrupt

from

the

MPCSR.

This

interrupt

is

maskable

using

the

SHPIEN

bit

of

< CNT3>.

VSBIRQ*

<

VSBbus

IRQ>

VSBIRQ*

is

an

interrupt

from

the

secondary

bus,

VSBbus.

This

interrupt

is

maskab1e

using

the

VSBIEN

bit

of

< CNT!>.

LMIRQ*

<

Location

Monitor

IRQ>

LMIRQ*

is

the

interrupt

caused

from

the

location

monitor

indicating

there

was a VME

access

to

the

Short

I/O

broadcast

area.

This

interrupt

is

maskable

using

the

LMIEN

bit

of < CNT3>

.

SIGLP*

<

MPCSR

Low

Pri

ori

ty

IRQ>

SIGLP*

is

the

signal

low

priority

interrupt

from

the

MPCSR.

This

interrupt

is

maskabl e us i

ng

the

SLPI

EN

bit

of < CNT3>

.

IRQl*-IRQ7* <

VMEbus

IRQ7*-IRQl*>

Interrupts

IRQl*

through

IRQ7*

are

the

VMEbus

interrupts.

These

interrupts

are

individually

maskable

using

the

VBIMSKI

through

VMIMSK7

bi

ts

of < CNT2>

.

4-16

FUNCTIONAL

OESCR!

PTION

4.12

ONBOARD

ROM/PROM/EPROM

The

MVME135/136

module has

two

28-pin

JEOEC

sockets

that

are

organized as a

single

bank. This

bank

appears

as a

16-bit

word

port

to

the

MC68020

and can

be

configured

for

32K

x 8

or

64K

x 8

ROM/PROM/EPROMs

with

an

access

time

of

250

nanoseconds

or

faster,

providing a total

of

128Kb

of

non-volatile

storage.

If

32K

x 8

devices

are

used,

they

will

appear twice in

the

128Kb

ROM/PROM/EPROM

address

space.

4.13

DUAL

SERIAL

PORTS

For

its

two

asynchronous

serial

ports,

the

MVME135/136

module uses

the

MC68681

to

provide

the

timing

and

control

necessary

to

support

two

independent communications

channels.

Both

serial

ports

utilize

standard

RS-232C

drivers

and

receivers.

Signals

are

available

through

DB-9

connectors

located

on

the

MVME135/136

module's

front

panel.

Both

ports

are

configured

as a

9-wire

DTE

interface

as

illustrated

in

Figure

4-10.

SERIAL PORT 1

SERIAL PORT 2

1

OCO

DeO

2

RXO

J

TXO

4

OTA

5

SG

6

OSR

DSR

6

7

RTS

7

8

CTS

g

FG

CTS

I :

FG

FIGURE

4-10.

SERIAL

PORT

INTERCONNECTIONS

4.14

MVME135/136

TIMER

Timer

functions

for

the

MVME135/136

modules

are

provided

by a Z8036

Counter/Timer

and

Parallel

I/O

Unit.

This

device

offers

two

independent

a-bit.

double-buffered,

bidirectional

I/O

ports,

three

independent

16-bit

counter/timers,

and a 4-bit

special

purpose

I/O

port.

The

latter

is

used in

conjunction

with one

counter/timer

to

implement a watchdog

timer

and

also

provide a means

for

software

selection

of a reset

type.

The

function

of

each

of

the

timers

is

described

below.

4-17

I

FUNCTIONAL

DESCRIPTION

Timer # 1 - User Programmabl e Timer

This programmable

timer

is

not

utilized

by

the

MVME135/136

hardware

or on-board firmware

and

is

therefore,

available

to

the

user.

Timer

#2 -Periodic

Tick Timer

When

enabled,

this

timer

causes a

local

Group 3 interrupt

on

Level 6

when

it

times

out.

Group

3, Level 6

;s

the

highest

local

interrupt

except

for

ABORT.

Timer

periods

range

from 1 to

l~

mill iseconds

and

are

software

sel

ectabl

e.

Timer

#3 -Watchdog

Timer

This time

is

capable of

generating

three

types

of

reset

(two

local

and

one

global).

The

watchdog timer must

be

periodically

serviced

by

software

to

prevent timeout so

that

the

module

is

not

reset.

When a reset

does

occur, a bit

indicating

this

condition

is

set

in

the

local

Control/Status

Register

(CSR)

to

provide

for

software

recovery,

if

needed. A corresponding

bit

is

also

set

in the

Multiprocessing

Control/Status

Register

(MPCSR)

to

provide

other

bus

masters with

the

reset

indication.

Because system

controller

functions

are independent

of

local

reset,

the

MVME135/136

modules

will

not

assert

the

SYSRESET

signal

on

the

VMEbus

when

either

of

the

local

reset

options

is

chosen.

Two

types

of

local

reset

are

available

from

the watchdog

reset

timer

and

are

enabled

via

bits 6 and

7

(WD~,

WDl)

of

Local Control

Register

#5.

They

are a

r'10mentary

Reset

of

sufficient

duration

to

reset

all

hardware

on

the

module,

and

a Reset

And

Hold.

The

momentary

reset

option allows

the

MC6802~

microprocessor

and

other

devices

to

come

back

up

and

operate.

The

reset

and

hold

option

keeps

the

module in

local

reset

until

a

SYSRESET

is

asserted

on

the

VMEbus,

or

until

another

VMEbus

master

clears

the

R&H

bit

in

the

MPCSR.

Both

options

are

software

selectable.

The

global

reset

option

for

the

watchdog

timer

will

cause a

2~0

millisecond

minimum

reset

pulse to appear

on

the

VMEbus

SYSRESET

line.

This

option

is

also

software

selectable.

4.15

LOCAL

CONTROL/STATUS

REGISTERS

The

MVME135/136

Control/Status

Registers

(CSR)

use

the

two

Z8~36

8-

bit

parallel

ports

to

provide local

and

system

side

information

to

the

on-board

MPU

and

control

of

various

local

and

system

level

functions.

4-18

FUNCTIONAL

DESCRIPTION

Switch

54

is a 10-position

switch,

settable

from

the

front

panel.

Switch

positions

1

and

2

are

control

functions

(refer

to

section

3.2.5

for a brief

description

of

these

switch

functions).

Switch

positions

3 through

10

are

readable

and

constitute

STAT1

(Status

Register

1)

as

defined

below.

In

the following

text.

PA

is

physical

address,

RC

is

reset

condition,

(res)

is

reserved,

and

NA

is

not

available

for

use.

4.15.1 Status Register

Format

And

Functions

The

following

text

describes

the

format

and

functions

of

the

Status

Registers.

<STAT1>

Physical Address:

SFFFB000D

(Read

Only)

RC = None

007

006

DOS

004

003

002

001

000

GP7 GP6

GP5 GP4 GP3

GP2

GP1

GPO

84·3

84·4

84·5

84·6

84-7 S4-8

84·9

84·10

GP7-GP0

< General Purpose User

Status

Bits>

GP0

through

GP7

are

front

panel

selectable

user

status

bits

(54-3

through

54-10) used

for

software

steering.

Access

to

this

register

will

read Port A

of

the

timer.

135bug

configures

Port A of

the

timer as

an

input

port

and

uses

these

general

purpose

bits

to

perform

various

optional

switching

functions.

For a complete

description

of

135bug' s use of

these

switches,

refer

to

the

135bug

Diagnostic/Debug Package

User's

Manual.

If

firmware

other

than

135bug

is

used,

the

resident

firmware

must

configure

Port A

of

the

timer

before reading

STAT!,

otherwise,

the

data

will

not

be a valid

representation

of

the

switch

settings.

Refer

to

the Zilog

Z-CIO

(Z8036) Counter/Timer

and

Parallel

I/O

Unit

Technical

Manual

for

information

on

programming

the

timer

registers.

<STAT2>

Physical Address:

SFFFB0032

(Read

Only)

RC = Not

Valid

007

006

005

004 003

002

001

000

I RAMERR"IRMCERR"I ABORT" 18Y8FAIL'1 VBER" I VSBERR" IMMUBEWI LCLERR·I

Data

bits

00, 01, 02, 03, 06,

and

07

will

clear

automatically

when

read. These

six

data

bits

will

indicate

the

bus

error

that

is

the

most

recent

only.

The

contents

of

this

register

is

invalid

after

4·19

I

FUNCTIONAL

DESCRIPTION

power-up

reset,

and

should

be

read once

by

the

system software

to

initial

ize

the

bus

error

status

bits

to

their

inactive

state.

RAMERR*

< Local

DRAM

Parity

Error>

RAMERR*,

when

low,

indicates

that

the

bus

error

was

caused

by

a

local

DRAM

memory

read where a

single-bit

error

had

been

detected.

The

board must

be

properly

configured

for

parity

operation.

Refer

to

the

descri

pt

ions

of

jumper J6

and

parity

enabl

e,

sect

ions

2.3.4

and

4.15.2,

respectively.

RMCERR*

<

Read-Modi

fy-Write

Cycl

e Error>

The

shared

memory

architecture

of

the

MVME135/136

module

requires

that

during a

slave

access

to

the on-board

DRAM,

the

MC68020

must

give

up

the

local

bus. A lockup

condition

occurs

when

another

bus

master has

possession

of the

VMEbus

and

is

trying

to

access

the

MVME135/136

DRAM

and

the

MVME135/136

has

just

begun

an

access

to a

memory

location

that

resides

in

VMEbus

mapped

memory

space.

Normally,

this

situation

is

handled

by

circuitry

on

the

MVME135/136

that

detects

the

lockup

and

asserts

BERR*

and

HALT*

to

the

local

MC68020

causing a

retry.

The

MC68020

terminates

the

cycle,

and

then

arbitrates

the

local

bus

away

allowing

the

slave

access

to

complete.

After

the slave

access

has completed

and

the

MC68020

becomes

the

local

bus

master,

the

retry

cycl e then

compl

etes,

all

transparent

to

the system

software.

RMCERR*

indicates

that

the

lockup

condition

described

above has

occurred while

the

local

MC68020

was

executing a TAS

(Test

And

Set)

cycle.

The

MC68020

will

not

do a retry,

while

it

is

performing a

locked

cycle

(RMC*

asserted).

When

this

situation

is

detected,

a

bus

error

is

asserted

to

the

MC68020,

and

the

RMCERR*

status

bit

is

asserted. During

the

bus

error

handling

routine,

the

system

software

must

examine

STAT2.

If

RMCERR*

is

asserted,

the

processor

retry

flag

should

be

set

before

returning

from

exception

processing.

This in

effect

causes a

software

retry

for

the

lockup

condition

when

RMC*

type

cycles

are

involved.

ABORT*

<

ABORT

Pushbutton

Status>

The

system

software

can monitor the

status

of

the

MVME135/136

ABORT

pushbutton

via

the

ABORT

status

flag.

Pressing

the

ABORT

pushbutton

will

cause a

level

seven

interrupt.

During

abort

interrupt

handling,

135bug

monitors

this

status

flag

before

returning

from

exception

to

ensure

that

the

abort

interrupt

is

seen

only once.

4-20

FUNCTIONAL

DESCRIPTION

SYSFAIL*

<

VMEbus

System

Fa

i 1

ure

Status>

A system

fail

ure,

communi

cated

to

thi s modu1

e vi a

the

VMEbus

SYSFAIL*

signal,

will

set

the

SYSFAIL*

flag = e.

If

the

SYSFIEN*

bit

is

set

when a system

failure

occurs,

the

MVME135/136

interrupt

hand1

er

wi

11

assert

SF I RQ*

to

the

processor.

VBER*

<

VMEbus

Bus

Error>

VBER*

= 0,

if a VMEbus

reference

made

by

this

MVME135/136

caused

a

bus

error

(i

.e.,

only

VMEbus

bus

errors

made

by

this

MVME135/136

when

it

is

VMEbus

master

wi

11

be

logged)

.

VSBERR*

<

VSBbus

Bus

Error>

VSBERR* = e,

if a VSBbus

reference

made

by

this

MVME135/136

caused

a bus

error.

VSBERR*

will

be

asserted.

HMUBER*

<

HMU

Bus

Error>

MMUBER* = 0,

when

the

bus

error

signal

from

the

MMU

device

has been

asserted.

The

MMU

wi

11

assert

BERR*

and

HAL

T*

to

the

MC68e2e

during

Relinquish

and

Retry

operations,

in

which

it

forces

the

current

logical

bus

master

to

terminate

the

current

bus

cycle.

release

the

logical

bus,

and

retry

the

bus

cycle

when

it

is

once

again

logical

bus

master.

The

concurrent

assertion

of

HALT*

and

BERR*

by

the

MMU

constitutes

the

Retry

phase

of

the

Re1

inquish

and

Retry

cycle.

The

MMUBER*

status

bit

will

only

indicate

true

MMU

cycle

faults,

not

Relinquish

and

Retry

cycle

types.

LCLERR*

< Local Timeout

Error>

LCLERR*,

when

low.

indicates

that a reference

to a locally

mapped

device

caused a timeout

bus

error.

This

signal

is

also

asserted

if

an

access

attempt

is

made

to

local

coprocessors

such

as

the

MC68881

or

MC68851

that

is

not

installed

in

the

module.

4.15.2

Control

Register

Format

And

Functions

The

following

text

describes

the

format

and

functions

of

the

Control

Registers.

<CNT!>

Physical Address:

$FFFBe00E

(Read/Write)

RC = None

007 006 005

004

003

002

001

000

,

BRIROI',

WWP I PAREN' I VSBIEN I NA NA NA

NA

Access

to

this

register

will

read

the B port

of

the

timer.

Data

bit

e7

should

always

be

programmed as

an

input.

Data

bits

e5 and e6

are

4-21

I

FUNCTIONAL

DESCRIPTION

used

for

testing

and use

of

parity

on

the

local

DRAM.

They must

be

programmed

as

outputs

to

be

used.

Data

bit

e4

is

a mask

for

the

VSBbus

interrupt

and must

be

programmed as

an

output

to

be

used.

BRIRQI*

<

Broadcast

Interrupt

Input>

BRIRQI*

is

actually

an

input

to

the

Z8036

timer

from

the

VMEbus

IRQl*.

This

is

provided

to

allow

the

user

that

has

several

MVME135/136's

to

interrupt

all

of

these

processors

with a single

VMEbus

interrupt.

IRQl*

cannot

be

used as a

VMEbus

interrupt

if

BRIRQI*

is

used

to

interrupt

the

MVME135/136

through

the

Timer and

therefore

must

be

masked

at

CNT2.

The

VMEbus

interrupter

that

causes

BRIRQI* by

asserting

VMEbus

IRQl* must

also

negate

this

level.

This

interrupt

must

not

be

acknowledged

on

the

VMEbus

in

this

mode.

If

normal

VMEbus

IRQl*

operation

is

desired,

then

the

Timer

input

must be programmed

to

not

recognize

the

BRIRQI*

interrupt.

The Timer I/O

connected

to

VMEbus

IRQl* must

never

be

programmed as

an

output

(Timer

port

B,

bit

7).

WWP

<

Write

Wrong

Parity>

WWP*,

when

high,

forces

parity

to

be

written

incorrectly

to

local

DRAM.

This

facil

itates

testing

of

on-board

parity

circuitry.

PAREN*

<

Pari

ty

Enabl

e>

PAREN*,

when

low,

enables

parity

error

reporting

by

allowing

bus

errors

to

the

local

processor

on

read

cycles

where

parity

faults

are

detected.

Parity

should

not

be

enabled,

unless a jumper

cap

is

installed

across

jumper

J6

pins

2 and

3.

VSBIEN

<

VSBbus

Interrupt

Enable>

VSBIEN,

when

high,

enables

the

MVMEl35/136

to

be

interrupted

by

the

VSBIRQ*

interrupt

signal.

VSBIRQ*

is

the

interrupt

signal

from

the

VSBbus.

<CNT2>

Physical Address:

$FFFBee38

(Read/Write)

RC = 11111111

007

006

DOS

004

003

002

001

000

! VBIMSK7! VBIMSK6! VBIMSKSI VBIMSK41 VBIMSK3! VBIMSK2!

VBIMSK1 ! VMSKO

!

CNT2

indicates

which

VMEbus

interrupt

this

module's

interrupt

handler

will

respond

to.

If

VBIMSKx

= 1,

then

the

module

will

not

respond

to

the

VMEbus

IRQx.

VMSK

is a DRAM

mask

bit.

When

active

it

will

not

allow

slave

access

to

the

local

DRAM.

4-22

FUNCTIONAL

DESCRIPTION

VBIMSK7-1

<

VMEbus

Interrupt

Mask

Bits>

The

MVMEI35/136

Interrupt

Handl

er

wi

11

respond

to

the

VMEbus

interrupts

that

have

thei r correspond i ng

bit

pos

it

ions

set

in

CNT2

as

follows:

1.

VBIMSKx = 0,

acknowledge

VMEbus

VBIRQx*.

2.

VBIMSKx = 1,

mask

VMEbus

VBIRQx*.

After

reset,

all

CNT2

bits

pOo'ler

up

=

1,

masking

all

VMEbus

interrupts

and

allowing

slave

access

to

local

DRAM

from

VMEbus.

VMSK*

<

VMEbus

Access

Mask>

VMSK*,

when

low,

disallows

any

local

DRAM

access

from

VMEbus.

This

feature

allows

the

MVME135/136

local

memory

to

become

completely

private

to

the

MC68020

CPU.

<CNT3>

007

Physical Address:

$FFFB0039

(Read/Write)

005

003 002

BUSY

<

MVME135/136

Modul e Busy>

RC = 11111111

DOD

Software

steering

bit

that

shows

the

module's

system

readiness.

BUSY

is

used

by

135bug as a

status

flag

during

diagnostic

operation.

BUSY

is

imaged

in a read

only

register

in

the

MPCSR

(refer

to

section

4.16).

ALLIEN*

< All

Interrupt

Enable>

When

ALLIEN* = 0,

all

MVME135/136

interrupts

are

enabled

to

the

Interrupt

Handler.

When

ALLIEN

= 1,

all

interrupts

are

disabled

allowing

vector

table

initialization.

SYSFI

EN*

<

SYSFAI L Interrupt

Enabl

e>

SYSFIEN

is

used

to

enable

SYSFIRQ

to

the

local

interrupt

handler

when a system

failure

occurs.

Refer

to

the

SYSFAIL

status

register

bit

for

more

details

regarding

SYSFAIL*.

When

SYSFIEN

= 1 (power

up

case),

the

SYSFIRQ*

is

disabled.

When

SYSFIEN

= 0 and

VMEbus

SYSFAIL*

is

asserted,

SYSFIRQ

will

be

asserted

to

the

MVME135/136

Interrupt

Handler.

SHPIEN*

< Si gna 1

Hi

gh

Pri

ority

Interrupt

Enabl

e>

SHPIEN*,

when

low,

enables

an

interrupt

to

occur

when

SIGHP

is

set

4-23

I

FUNCTIONAL

DESCRIPTION

in

the

MPCSR

(refer

to

section

4.16).

SHPIEN*,

when

high,

prevents

SIGHP

from

being

set

in

the

MPCSR.

This

restriction

applys

only

to

Artwork

Revisions

A-C. Artwork

Revision E allows

SIGHP

to

be

set

independent

of

the

state

of

SHPIEN*.

SLPIEN*

<

Signal

Low

Priority

Interrupt

Enable>

SLPIEN*,

when

low,

enables

an

interrupt

to

occur

when

SIGLP

is

set

in

the

MPCSR

(refer

to

section

4.16).

SLPIEN*,

when

high,

prevents

SIGLP

from

being

set

in

the

t~PCSR.

This

restriction

applys

only

to

Artwork

Revisions A through

C.

Artwork

Revision E allows

SIGLP

to

be

set

independent

of

the

state

of

SLPIEN*.

LMIEN*

<

Location

Monitor

Interrupt

Enable>

LMIEN*,

when

low,

enables

an

interrupt

to

occur

from

location

monitor

zero,

in

the

MPCSR

(refer

to

section

4.16).

BRIRQO*

<

Broadcast

Interrupt

Output>

BRIRQO*,

when

low,

asserts

VMEbus

IRQ1*.

This

is

not

intended

to

cause

a

VMEbus

interrupt.

This

bit

is

intended

for

use as a

broadcast

mechanism

that

is

compatible

with

the

MVME13~,

where

VMEbus

IRQ1*

is

connected

to

bit 7 of

Timer

Port

B and

causes

a

timer

interrupt.

The

MVME135/136

is

also

capable

of

being

interrupted

in

this

way.

Refer

to

the

BRIRQI*

description

under

CNTl.

VSBIRQO*

<

VSBbus

Interrupt

Output>

VSBIRQO*,

when

low,

asserts

VSBIRQ*

low

on

VSBbus,

allowing

the

MVME135/136

to

generate

VSBbus

interrupts

for

diagnostics

applications.

<CNT4>

Physical Address:

$FFFB003A

(Read/Write)

RC

=

1-------

007 006

005

004

003

002

001

000

IGLBRES-I

NA

NA NA

NA

GLBRES*

<Global

Reset>

GLBRES*,

when

low,

will

cause

a

2~~

millisecond

system

reset.

This

will

happen

whether

the

MVME135/136

is

the

system

controller

or

not.

The

data

in

this

register

is

undefined

when

read.

4-24

FUNCTIONAL

DESCRI

PTION

<CNT5>

Physical

Address:

$FFFB003B

(Read/Write)

RC = 11111111

007

006 005

004

003

002

001

000

woo

W01

LTMO

VTMO

OPTO

32124'

32116"

BOFAIL

I

WD0,WDl

< Watch

Dog

Timer

Control

Bits>

When

the

watch dog

timer

times

out,

the

following

function

occurs.

WD1

WD0

Function

0 0

Momentary

System

Reset.

0

1

Momentary

Local Reset.

1 0

Local Reset

and

Hold.

1

Watchdog

Timer Disabled.

LTMO

< Local

Timeout

Enabled>

When

set,

the 1 oca 1 timeout

generator

is

enabl

ed.

VTMO

<

VMEbus

Timeout Enabled>

When

set,

the

VMEbus

timeout

generator

is

enabled.

OPT0

< Local

DRAM

Address

0>

When

set,

local

DRAM

is

mapped

at

00000000

(hex).

The

local

DRAM

always

appears

at

FFE00000

(hex)

for

the

MVME135/135-1/l36

versions

and

at

FF800000

(hex)

for

the

MVf1E135A/136A

versions.

32/24*

<

VMEbus

Address

Si

ze

Sel

ect>

This

bit

provides

a

software

selectable

32-

and

24-bit

address

option

for

VMEbus

references.

The

appropriate

address

modifiers

are

generated

for

32-

or

24-bit

address

VMEbus

accesses.

32/24*

=

1

indicates

32-bit

address

option;

32/24*

= 0

indicates

a

24-bit

address

space.

Refer

to

the

following

memory

map

chart

for

the

affect

of

the

32/24*

bit

on

the

MVME135/136

VMEbus

memory map.

If

32/24* = 0:

00000000-00FFFFFF A

24-bit

address

modifier

is

generated.

01000000-FFDFFFFF

A

32-bit

address

modifier

is

generated.

(MVME135/135A/135-1/136

versions)

01000000-FF7FFFFF A

32-bit

address

modifier

is

generated.

(MVME136A

version)

4-25

I

FUNCTIONAL

DESCRIPTION

If

32/24* = 1:

00000000-FFDFFFFF A 32-bit

address modifier

is

generated.

(MVME135/135A/135-1/136

versions)

00000000-FF7FFFFF A 32-bit

address modifier

is

generated.

(MVME136A

version)

Either

with 32/24*

set

or

cleared:

FFE00000-FFFEFFFF

Local

address space.

(MVMEI35/135A/135-1/136

versions)

FF800000-FFFEFFFF

Local

address space.

(MVME136A

version)

FFFF0000-FFFFFFFF

A 16-bit address modifier

is

generated

(VMEbus

short I/O).

32/16*

<

VMEbus

Data

Si

ze Sel ect>

This

bit

provides

a software

selectable

32-

or

16-bit

VMEbus

data

width. This

bit

should

be

used with

care

because

when

32/16* = 0,

all

memory

references

to

VMEbus

are

forced to

be

16

bits.

When

32/16* = 1,

all

memory

references

to

the

VMEbus

can

be

32

bits.

The

memory

map

can

be

customi

zed

in hardware

by

the

user

to

segment

016

and

D32

address space. This

is

performed

by

programming

PAL2

(U60)

for

the

particular

application.

The

default

memory

map

for

032

and

016

data

space

is

illustrated

in Figure 4-11. Refer

to

Appendix A

for

the

description

and

equations

for

PAL2

(for

the

MVMEI35/135-1/136

versions

only).

Refer

to

Appendix B

for

the

description

and

equations

for

PAL2

(for

the

MVME135A/136A

versions

only) .

BDFAIL

< Board

or

System Failure>

If

this

bit

is

= 1 (and

the

ISF

bit

in

the

MPCSR

is

clear),

then

the

SYSFAIL*

line

on

VMEbus

will

be

asserted.

The

"FAIL"

LED

will

be

ill

umi

nated,

whenever

BDFAI

Lis

set.

4-26

FUNCTIONAL

DESCRIPTION

SHORT

1/0

SPACE

A16/016

LOCAL RESOURCES

A32/018

A32/032

A24/032

ANOIOR

A32 I 032

$FFFFFFFF

$FFFFOOOO

$FF800000

nus ADDRESS SPACE IS

016

SUPPORTS

018

DUAL PORT

1/0

CARDS SUCH

loS

TliE

UVME332XT

MULTI·

CHANNEL SERIAL COMMUNICATlONS CONTROLLER

AND

TliE

UVME393

IoIUL

Tl·

CHANNEL

GRAPHICS CONTROLLER.

$FOOOOOOO

$01000000

FIGURE

4-11.

D16/D32

DEFAULT

DATA

SEGMENTATION

4.16

MULTIPROCESSOR

CONTROL/STATUS

REGISTERS

(MPCSR)

The

MVME135/136

modules are designed

for

multiprocessor

applications

providing a number

of hardware

features

for

this

type

of

environment. These include global access to

and

control

of

the

status

of

several

modul

e funct ions,

as

well as

the

abil

ity

to

generate

virtual

interrupts

to

selected

boards,

and/or

simultaneous

interrupts

to

multiple

boards.

Their

design does not

define

or

limit

in

any

way

the

architecture

of a multiprocessor

application,

but,

rather,

eases

its

development,

particularly

from

the

point

of

view

of

software.

The

registers

provided

to

facilitate

use

of

a

MVME135/136

module in

any

multiprocessor

environment

(the

MPCSR),

is

illustrated

in Table

4-7.

The

MPCSR

is

dual

ported

between the

local

MC68020

microprocessor

and

VMEbus.

The

MPCSR

may

be

accessed

by

the

local

processor

at

$FFFB0060

to

7F,

or

from

the

MPCSR

VMEbus

mapped

location.

4-27

I

FUNCTIONAL

DESCRIPTION

TABLE

4-7,

MULTIPROCESSOR

CONTROL/STATUS

REGISTERS

ADDRESS OFFSET

007

006

I

005

I

004

D03

I

CO2

I

001

I

DOD

1

10

BYTE

3 BSY

seON

I

FAIL

I

WDT UNDEFINED

5

KING' @

LM2'

I

LM1'

I

LMO'

ISF

I LKTR

HI

UNDEFINED

7

R&H

UNDEFINED

RONR

I

UNDEFINED

9 H&H UNDEFINED

B

StGLP

UNDEANED

D

SIGHP

UNDEFINED

F

UNDEFINED

11

MPO

UNDEFINED

13

MP1

UNDEFINED

15

MP2

UNDEFINED

17 MP3

UNDEFINED

19

MP

COrAM

BYTE

lB

10

IF

@ ALSO DESIGNATED LM3',

@@ LKTR

IS

READ ONLY FROM VMEbu8

AND

IS READ/WRITE FROM

THE

LOCAL BUS,

10

<

10

Byte>

This byte

is

the

image

of

the

mapping

switch used to

map

the

MPCSR

and

DRAM

on

the

VMEbus.

This byte allows the

local

processor

to

i dent i fy where

other

bus

masters

wi

11

be

access i

ng

its

memory.

The

MPCSR

will

be

at

xxxyyyyy

on

the

VMEbus,

where "xxx"

is

the group

base address

and

"yyyyy"

is

the base

offset

within

the

group.

The

module

10

can

be

read

visually

from

the

board

by

looking

at

the

8-

bit

mapping switch S3. Refer to

the

Local

DRAM

and

MPCSR

Mapping

examples in

section

3.2.4.

BSY

<

Busy

Bi

t>

This

bit

will

come

up

asserted

and

is

typically

used

to

indicate

that

the

MVME135/136

is

not ready to

operate

at

the

system

level.

This

will

be

the

case while

the

MVME135/136

is

executing

confidence

tests

and

during

initialization

of

local

resources.

This

bit

is

read only

and

is

an

image

of the

local

busy

bit

located

in

CNT3.

The

function

of

this

bit

is

determined only

by

the

resident

firmware/system

software.

4-28

FUNCTIONAL

DESCRIPTION

SCON

< System

Controll

er

Bit>

This

bit

is

the

image

of

the

local

control

bit

that

establishes

the

module as

the

VME

system

controller.

This

bit

is

active

high,

read

only.

FAIL

<

Fail

Bit>

This

bit

enables

another

VMEbus

master

to

determine

if

the

MVME135/136

has

indicated

a

local

failure.

This

bit

is

the

image

of

the

local

BDFAIL

bit.

It

will

also

be

able

to

determine

if

the

module

is

asserting

the

SYSFAIL* 1 ine

on

the

VMEbus

by

setting

or

clearing

the

ISF

bit,

and

monitoring

for

the

SYSFAIL

interrupt.

This

bit

is

read

only.

wor

< Watchdog Timer

Bit>

Thi s

status

bi

t i ndi

cates

whether

a watchdog

reset

has

occurred

on

the

module.

This

bit

is

read

only,

and

is

cleared

when

read.

KING(LH3*)

<

KING

Bit>

This

bit

will

come

up

asserted

and

will

indicate

that

the

module

has

not

been

disqualified

as

the

system

initializer.

The

location

monitor

can

clear

this

bit

on

all

modules

in

the

group

at

the

same

time.

LH0*-LH2*

<

Location

Monitor

Bits>

The

local

processor

can

be

interrupted

by a broadcast

cycle.

This

cycle

can

be

recognized

by

all

MVME135/136s

in

the

system.

This

is

accomplished

with

a

location

monitor

that

will

detect

a

VMEbus

cycle

to

the

Al6

(Short

I/O)

addresses

determined

by

the

VMEbus

mapping

switch.

There

is

an

enable

bit

in

the

local

CSR

(CNB)

that

will

allow

the

MVME135/136

to

mask

the

location

monitor

interrupt.

LM~*

is

the

only

location

monitor

bit

that

can

cause

an

interrupt.

The

MPCSR

resides

on

odd

addresses

in

the

VMEbus

Short

I/O

space.

The

VMEbus

base

address

in

this

space

will

be mappable as shown in

Table

4-8.

Locally

the

address

of

the

MPCSR

is

FFFB~~6~-FFFB~~7F.

Location

monitor

examples:

For

MPCSR

mapped

at

~~~~

in

VMEbus

Short

I/O.

(Group

~)

VME

word

access

to

~3E0

-

will

clear

LM0*

and

cause a

location

monitor

interrupt,

if

the

system software

has setup

the

proper

enables

and

lowered

the

processor

mask.

VME

word

access

to

03E2 -will

clear

LMl*.

VME

word

access

to

03E4 -will

clear

LM2*.

VME

word

access

to

03E6 -will

clear

LM3*

(KING

bit).

4-29

I

L

UNCTIONAL

DESCRIPTION

TABLE

4-8.

MAPPING

ON

THE

VMEbus

SWITCH

53

SEnlNGS

I

10

BYTE

(IN

MPCSR)

123

4 5 6 7 B

000

0 0 0 0 0 00000001 00000010

MPCSR

BASE

ADDRESS

I

(VME SHORT

110

SPACE)

o 0 0 0

$ 0

020

$ 0 0 4 0

DRAM

BASE ADDRESS

(

MVME135 I 135-1

1136 )

$ 0

000

0 0 0 0

S 0 0

1 0 0 0 0 0

00200000

I

DRAM BASE

ADDRESS

( MVME136A)

$ 0 0 0 0 0

000 00400000 008

0 0

000

UP

TO

31

DIFFERENT

MPCSR

START

ADDRESSES

FOR

EACH

GROUP

000 000 000

o 0 0

o 0 o 0

001

1 1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1 1 00000

o 0 0 0 1

00010

o 0 1 0 0

00101

00111110

o 0 1 1 1 1 1 1

010

0 0 0 0 0 01000001 010

000

1 0

01011100

o 1 0 1 1 1 0 1 o 1 0 1 1 1 1 0

o 1 0 1 1 1 1 1

01100000 01

00001 01

00010

01111100

o 1 1 1 0 1

o 1 0 o 1 1 1 1

$ 0 3 8 0

$ 0 3 A 0

$ 0 3 C 0

SOl

C 0

SOlDO

$

OlE

0

RESERVED

FOR

BROADCAST,

GROUP

0

$ 2 0 0 0 $ 0 0 0 0

$ 2 0 2 0 $

001

0

5

2

040

5 0 0 2 0

o 0 0 0

5

2 8 0

5 2 A 0

$ 2 3 C 0

$ 0 1

COO

0 0 0

$01000000 $ 0 1 E 0 0

000

RESERVED

FOR

BROADCAST,

GROUP

1

$4000

$0000

o 0 0 0

$ 4

020

$ 0 0 1 0

o 0 0 0

404

0 s 0 0 2 0 o 0 0 0

$ 4 8 0

$ 4 A 0

4 3 C 0

$01CO

0000

$01000000 S01EO

0000

RESERVED

FOR

BROADCAST,

GROUP

2

$6000

$00000000 $ 6 0 2 0 $ 0 0 1 0 0 0 0 0 $ 6 0 4 0 $ 0 0 2 0

000

0

5

6 3 8 0 5 0 1

COO

0 0 0

Sl!3AO

$01000000 $ 6 3

COOlE

0

000

0

RESERVED

FO~

BROADCAST,

GROUP

3

NOTE:

SErnNG

S3-4

THROUGH

S3·8

TO 1 (ALL

OFF)

IS

NOT

ALLOWED.

$ 0 7 0 0 0 0 0 0 $ 0 7 4 0 0 0 0 0

$ 0 7

BOO

0 0 0

$ 0 0 0 0 0

000

$ 0

040

0 0 0 0

$ 0

080

0

000

07000000

$07400000

$ 0 7 8 0 0 0 0 0

o 0 0 0

$

004

0

$ 0 0 8 0

o 0 0 0

o 0 0 0 o 0 0 0

070

0 0 0 0 0

5 0

7 4 0 0 0 0 0

$07800000

o 0 0 0 0 0 0 0

5 0

040

0 0 0 0

500800000

5

070

0 0

000

50740

000

0

S 0

7 8 0 0 0 0 0

THIS

ADDRESS SPACE

FOR

EACH

GROUP

IS

USED

AS

BROADCAST

ADDRESSES

FOR

LOCATlON

MONITORS.

ISF

< Inhi

bit

SYSFAIL

Bi

t>

If

the

module has a

BDFAIL

asserted

locally

and

ISF

is

not

active,

then

the

module

is

asserting

SYSFAIL*

on

the

VMEbus.

Another

bus

master can

force

the

MVME135/136

to negate

the

SYSFAIL*

line

by

setting

the

ISF

bit

in the

MPCSR.

This

is

helpful

to prevent

interrupts

after

a module has

been

diagnosed as

failed.

4-30

FUNCTIONAL

OESCRI

PTION

LKTR

<

VHEbus

Locked

Trans

fer>

LKTR

when

asserted

wi

11

cause

the

access

to

lock

possession

of

VMEbus

to

this

MVME135/136

module. The normal

release

on

request

functioning

of

the

MVME135/136

requester

is

disabled

and

release

of

VMEbus

mastership

will

not

occur

until

LKTR

is

negated.

LKTR

is

intended

to

allow

the

system

software

to

execute

rout

i nes

over

VMEbus

ina

determi

ni

st

i c amount

of

time.

If

LKTR

is

asserted,

the

MVME135/136

module

is

not

contending

for

VMEbus

ownership

with

other

VMEbus

masters.

LKTR,

when

set,

does

not

immediately

lock

the

VMEbus,

unless

VMEbus

mastership

has

already

occurred

from

cycles

and

was

not

requested

away

by

another

VMEbus

master.

LKTR

should

be used

with

extreme

care

since

other

bus

masters

will

not

be

able

to

obtain

VMEbus

ownership

until

the

local

CPU

has

cleared

the

LKTR

bit.

LKTR

is

Read/Write

from

the

local

processor

over

the

locally

mapped

address

location,

and

is

read

only

from

the

VMEbus

mapped

location.

When

LKTR

is

cleared,

the

MVMEl35/136

VMEbus

requester

operates

in

Re1ease-On-Request

mode,

holding

VMEbus

mastership

only

until

another

VMEbus

master

requests

the

VMEbus.

Re1ease-On-Request

operation

is

more

efficient

because

the

total

number

of

VMEbus

arbitration

cycles

is

reduced.

R&H

<

Reset

and

Hol d Bi

t>

Another

VMEbus

master

will

be

able

to

place

the

module

in

reset

by

asserting

this

bit

location.

The

module

will

remain

in

reset

until

the

location

is

cleared

or

a system

reset

occurs.

When

R&H

is

set,

a

minimum

of 5 microseconds

may

elapse

before

the

module

is

placed

in

reset.

When

R&H

is

cleared,

.5

seconds

minimum

will

elapse

before

the

module

completes

reset.

To

prevent

memory

corruption,

it

is

recommended

that

HALT

and

HOLD

be

asserted

before

R&H

is

asserted.

RONR

<

Request

On

No

Request>

RONR,

when

set,

forces

fhe

MVME135/136

requester

to

wait

to

request

the

VMEbus

until

the

request

level

that

it

is

using

has been

negated.

Thi s

causes

all

MVME135/136

modu1

es

that

are

on

the

same

VMEbus

request

level,

and have

RONR

asserted

to

share

the

available

VMEbus

bandwidth

equally.

The

effect

of

RONR

operation

is

like

round

robi n arbi

trat

ion.

However,

RONR

allows

round

robi

n

operation

with a single

level

VMEbus

arbiter,

and

does

not

limit

the

number

of

masters

equally

sharing

the

bus

to

the

number

of

arbitration

levels

of

the

system bus (VMEbus).

When

RONR

is

negated,

strict

priority

determined

by

the

MVMEI35/136's

position

in

the

VMEbus

daisy-chain

will

determine

the

bus bandwidth

obtained.

MVME135/136's

or

other

VMEbus

masters

that

are

nearer

to

the

VMEbus

arbi

ter

wi

11

obtain

most

of

the

4-31

I

FUNCTIONAL

DESCRIPTION

available

bus

bandwidth.

RONR

may

be used

when

it

is

important

for

all

of

the

MVME135/136

modules

to

have

fair

access

to

VMEbus.

Other

bus

masters

that

are

not

equipped

with

the

RONR

feature

may

starve

the

VME135

from

access

to

the

VMEbus,

since

the

MVME135/136

is

attempt i ng

to

be

fa i r and

the

other

bus

masters

are

not.

It

may

be

necessary

to

experiment

with

different

configurations

of

VMEbus

arbitration

levels

and

implementations

of

RONR

operation

with

other

VMEbus

masters.

Also,

experimentation

with

the

system

configuration

with

respect

to

position

within

the

VMEbus

arbi

trat

ion

da i

sy-cha

i n

is

recommended.

H&H

<

Halt

and

Hol d Bi

t>

This

bit

enables

another

VMEbus

master

to

place

the

module

in

halt

by

setting

this

bit.

This

ability

is

provided

to

allow

upload

and

download

of

the

DRAM

with

the

local

processor

operation

suspended.

SIGLP

<

Signal

low

Priority>

The

local

processor

may

be

interrupted

by

asserting

this

bit

location.

There

is a control

bit

in

the

local

control

registers

that

will

allow

this

interrupt

to

occur

(SLPIEN

in < eNT3».

This

is a level 2 interrupt

to

the

local

processor.

SIGHP

<

Signal

High

Priority>

The

local

processor

may

be

interrupted

by

asserting

this

bit

location.

There

is a control

bit

in

the

local

CSR

that

will

allow

this

interrupt

to

occur

(SHPIEN

in < CNT3».

This

signal

is

a

higher

priority

locally

(level

5)

than

SIGLP.

MP0-MP3

<

Mul t i-Processor

Bi

ts>

These

are

read/write

bits

in

the

most

significant

bit

of

each

byte

they

occupy.

They

may

be

used as semaphores

or

as handshake

bits

for

passing

information

through

the

MP

COMMunication

(MP

COMM)

channel

described

below.

MP

COMM

<

Multi-Processor

Communication Byte>

This

is a byte

wide communications

path

that

allows

interaction

to

be accompl i shed between bus

masters

independently

of

DRAM.

4.16.1

Base

Address

Selection

The

MVME135/136

modules have

an

a-position

switch

(S3)

for

locating

the

MPCSRs,

as

well

as

the

local

DRAM,

in

the

VMEbus

address

space.

A

total

of

eight

groups

is

accommodated and

within

each group a

unique

base

address

for

up

to

31

processor

modules can be

selected.

The

32nd

address

range

for

each group

is

reserved

for

location

monitor

accesses

capable

of

broadcasting

an

interrupt

to

all

processor

4-32

FUNCTIONAL

DESCRIPTION

boards

within

that

group.

Figure

4-12

illustrates

the

MPCSR

and

DRAM

mapping

capability

provided

by

switch

S3

and

gives

an

example

of

the

addresses

selected

by a specific

setting

of

the

switch.

Refer

to

Table

4-8

for

a 1

isting

of

the

MPCSR

and

DRAM

base

addresses

that

can

be

selected

by

switch

S3. Note

that

using

a

S3

base

offset

sett i ng

to

obta

ina

un

i que

address

for a processor

modu1 e results

in

the

same

DRAM

address

regardless

of

the

S3

group

setting.

Therefore,

for

a

system,

the

maximum

number

of

processor

modules

each having

DRAM

with a unique

VMEbus

address

is

31.

4.17

VSBbus

CONTROL/STATUS

REGISTER

There

are

three

registers

in

the

VSBchip. They

are

the

control

and

status

register,

the

decode

address

register.

and

the

block

transfer

count/extended

address

register.

This

register

is

referred

to

as

the

VSBCSR.

VSBbus

Regi

ster

o

* 1

* 2

Function

Control

and

Status Block Transfer/Extended Address Decode

Address

*

Not

used

and

should not

be

accessed

on

the

MVME135/136.

4.17.1

VSBbus

Control/Status

Reg;

ster

Format

And

Funct; ons

This

register

controls

those

functions

which

if

asserted

could

drastically

affect

the

functioning

of

the

MVME135/136.

Altering

any

of

these

bits

should

be done with

care.

These

bits

select

the

VSBchip,

enable

the

VSBbus

System

Controller

function,

enable

block

transfer,

set

the

MC68020

mode,

enable

external

decoding,

make

the

bus

read

only,

enable

the

bus

timeout

timer,

and

enable

the

bus

fairness

mode.

The

status

register

reflects

only

the

latest

BERR

condition.

When

a

new

BERR

condition

occurs,

any

previously

set

bits

may

change.

This

register

is

cleared

upon

reading

or

when a reset

condition

occurs.

The

following

text

describes

this

register.

4-33

I

01'>

W

01'>

•

MPCSR

BASE ADDRESS

IN

SHORT

I/O

ADDRESS

SPACE

A15

x

GROUP

SELECT

(MPCSR BASE ADDRESS)

SWITCH

S3

DRAM

BASE

ADDRESS

MAPPING

SWITCH

EXAMPLE:

SWITCH

53

~:F~~~~~~~~

(NOTE:

OH;O,

OFF:1)

1 2 3 4 5

678

GROUP

, • 1 1 0 • 6

11

1 0 1 0 1 0 1 0

11

1 0 1

Y

yt

t

rrl

MPCSR

BASE

ADDRESS

= 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0

~

DRAM

BASE

ADDRESS.

0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FIGURE

4-12.

MPCSR

AND

DRAM

ADDRESS

MAPPING

)

AOO

o

~

."

C

:z

n

~

o

:z

»

r-

C1

rTl

Vl

n

;0

"

~

o

:z

FUNCTIONAL

DESCRIPTION

Physical Address:

$FFFA00~0

(Read/Write)

RC

FFFF

031

025

015

011

000

NA

I

STATUS

I

CONTROL

Bi t 00

SCON* < VSBbus

System

Contro

11

er>

SCON*

selects

the

VSBchip as

the

System

Controller.

VSBbus

SCON*

does

not

affect

VMEbus

system

controller

selection.

Bit

01

Not Used

Bi t 02

BLOCKEN* < Block

Transfer

Enabl

e>

BLOCKEN*

is

used

to

enable

a

master

block

transfer.

This

bit

should

never

be

written

to

zero

on

the

MVMEl35/136.

Bit

03

10* < 010

Processor

Select>

10*,

when

asserted,

selects

the

MC68010

mode

and

when

negated

selects

the

MC68020

mode.

This

bit

should

never

be

written

to

zero

on

the

MVME

135/136.

Bi t 04

VSBDEN < VSBbus

Decode Enabl

e>

VSBDEN,

when

asserted

allows

the

AS*

signal

to

generate

the

PAS*

signal

without

waiting

for

QAS*,

thus

allowing

decode

on

VSBbus

slaves

to

determine

which bus

(VSBbus

or

VMEbus)

will

be

used.

If

a

VSBbus

slave

is

not

found,

the

cycle

is

automatically

directed

to

VMEbus.

Bi t 05

READONLY* < VSBbus

Read

Only>

READONLY*

prevents

writes

from

occurring

on

the

VSBbus

from

this

master.

Write

cycles

are

automatically

directed

to

VMEbus

for

cache

monitoring,

when

READONLY*

is

asserted.

Bi t 06

VSBEN* < VSBbus

Enabl

e>

VSBEN*

enables

the

master

mode

if

the

VSBbus

device

SLAVE*

is

negated.

On

the

MVMEl35/136,

the

SLAVE*

is

pulled

high.

Therefore,

slave

accesses

to

the

MVME135/136

over

VSBbus

cannot

occur. Bi t 07 Bit

08

Bi

t

09

Not Used

ENT00* < Enab1

e Timeout Opti

on

0>

ENT01* < Enable

Timeout

Option

1>

The

VSBchip

implements

the

bus

timer

function

with

various

timeout

periods.

The

timeout

period

may

be

chosen

to

be

64

microseconds,

4-35

I

FUNCTIONAL

DESCRIPTION

128

microseconds,

256

microseconds,

or

infinite

by

setting

bits

08

and

09

in

the

control

register.

The

timeout

counter

is

started

when

PAS*

is

asserted

and

is

disabled

when

PAS*

is

negated.

If

the

counter

times

out

before

the

PAS*

signa 1 is

nega

ted the

ERR*

signa

1

is

asserted

and

the

BUSTIMEOUT*

bit

is

set

in

the

status

register.

The

times

given

are

for

ClK

equal

to

16.67

MHz.

ENTOl * ENT00*

Timeout Period

1 1

Infinite

1 0

256

microseconds

0

1

128

microseconds

0

64

microseconds

Bit

10

ROBIN* < Round

Robin

Fairness

Requester>

ROBIN*

enables

the

fairness

mode

in

the

bus

requester

when

asserted.

Bus

bandwidth

is

shared

equally

among

VSBbus

masters

that

all

have

fairness

mode.

When

ROBIN*

is

negated,

the

bus

bandwidth

is

prioritized

by a daisy-chain

scheme where

the

modules

closest

to

the

system

controller

will

receive

most

of

the

available

bus

bandwidth.

Bit

11

WRERROR* < Wr;

te

Error

status

Bit>

WRERROR*

reports

the

fact

that

a

write

to

a

read

only

bus

was

attempted.

Bit

12

BUSTIMEOUT* < VSBbus

Timeout>

BUSTIMEOUT*

reports

the

fact

that a VSBbus

timeout

has

occurred.

Bit

13

ASACKI:l*

< Address

And

Si ze

Status

0>

ASACK0*

reports

the

status

of

the

bus

ASACK0*

line

the 1 ast

bus

error.

Together

wi

th

ASACKI

*,

it

response

and

size

of

the

sl

ave

modul e accessed.

foll

owi

ng

chart.

ASACKl*

ASACK0*

Status

1 1

No

Sl

ave

Response

1 0

8-Bit

Slave Response

0

1

16-Bit

Sl

ave

Response

0 0

32-Bit Slave Response

4-36

at

the

time

of

i

nd i cates

the

Refer

to

the

FUNCTIONAL

DESCRIPTION

Bi t 14

ASACKI

* <

Address

And

5i ze

Status

1>

ASACKl*

reports

the

status

of

the

bus

ASACKl*

line

at

the

time

of

the

last

bus

error.

Together

with

ASACKI3*,

it

indicates

the

response

and

size

of

the

sl

ave

modul e accessed.

Refer

to

the

chart

above.

Bi t 15

ERR* < VSBbus

Error

Status>

ERR*,

when

asserted,

reports

that

a bus

error

has

occurred.

Thi s bi t

indicates

status

only

for

VSBbus

cycles

that

are

terminated

with

a

VSBbus

error.

4.18

CONFIGURING A VME

SUBSYSTEM

BUS

The

MVME135/136

module

gains

much

of

its

power and

flexibility

by

use

of

the

VME

Subsystem

Bus

(VSBbus).

VSBbus

is

implemented

in

a

gate

array

device

and

performs

almost

all

VSBbus

requirements.

VSBbus

on

the

MVME135/136

is

a

master

only,

multiple

master

interface,

meaning

that

the

MVME135/136

cannot

be

accessed

over

VSBbus. However,

multiple

MVME135/136s

can be

used

on

a

single

subsystem

and

share

VSBbus

slave

resources.

VSBbus

can

be

implemented

with a 64-pin

ribbon

cable.

In

this

configuration,

only

two

MVME135/136s

may

share

VSBbus

with

up

to

four

VSBbus

sl

ave

devices.

It

is

important

to

note

that

when a ribbon

cable

is

used,

at

least

one

of

the

slave

devices

must

connect

VSB

BGIN*

to

VSB

BG*

(P2

A31

to

P2

C32).

VSBbus

backplanes

are

available

in

varied

configurations,

typically

up

to

six

slots.

These

backplanes

plug

into

P2

connectors

on

the

VME

P2

backplane.

VSBbus

backplanes

are

needed

for

applications

requiring

more

than

two

VSBbus

masters.

The

backplane

will

require

jumpering

for

configuring

VSB

BGIN*

to

BG*

for

each

slot

where a

VSBbus

master

such as

the

MVME135/136

is

installed.

Socketed

signal

terminators

(R2e and

R21)

are

provided

on

the

MVME135/136

module.

If a ribbon

cable

is

used,

these

terminators

do

not

require

reconfiguration

and

should

remain

installed

in

the

module.

If a VSBbus

backplane

is

used

that

provides

proper

VSBbus

signal

termination,

R20

and

R21

must

be

removed.

Also,

if

more

than

two

MVME135/136s

are

installed

in

single

subsystem,

then

the

terminators

should

only

be

installed

in

the

modules

that

reside

at

each end

of

the

subsystem

bus.

Proper

VSBbus

signal

termination

is

essential

for

rel

iable

VSBbus

operation.

Refer

to

the

VME

Subsystem

Bus

(VSBbus)

Specification

for

more

detailed

information

on

VSBbus

configuration

and

signal

terminators.

4-37

I

FUNCTIONAL

DESCRIPTION

I

4-38

SUPPORT

INFORMATION

CHAPTER

5 -

SUPPORT

INFORMATION

5.1

INTRODUCTION

This

chapter

provides

the

connector

signal

descriptions,

parts

list

with

associated

parts

location

diagram,

and

the

schematic

diagram

for

the

different

versions

of

the

MVMEI35/136

module,

the

1Mb

and

4Mb

DRAM

mezzanine

board,

and

the

PMMU

by-pass

board.

5.2

INTERCONNECTION

SIGNALS

The

MVMEI35/136

module

interconnects

with

VMEbus

through

connector

Pl.

Connector

P2

interconnects

the

MVMEI35/136

modul e

wi

th

the

extended

VMEbus

and

the

secondary

extens i on

bus,

VSBbus.

5.2.1

Connector P 1

Interconnect

Signals

Connector

PI

is a standard

DIN

triple

row,

96-pin

male

connector.

All

Motorola

VMEbus

specifications

are

met

by

the

MVME135/136

module.

The

connections,

VMEbus

signal

mnemonics, and

signal

descriptions

for

the

PI

connector

are

provided

in

Table

5-1.

Refer

to

the

ANSI/IEEE

Standard

HH4-1987

(Versatile

Backplane

Bus:

VMEbus)

for a complete

description

of

the

VMEbus

signals.

Number

AI-A8

A9 AHI

All AI2

TABLE

5-1.

CONNECTOR

PI

INTERCONNECT

SIGNALS

Si

gna 1

Mnemonic

000-007

GND SYSCLK

GND DSI*

Signal

Name

and

Description

DATA

BUS

(bits

0-7) - Eight

of

16

three -state

bidirectional

data

lines

that

provide the data

path between

the

data

transfer

bus master

and

slave. GROUND SYSTEM

CLOCK

- A

constant

16

MHz

clock

signal

that

is

independent

of

processor

speed

or

timing

and

is

used as a timing

reference. GROUND DATA

STROBE

I - A

three-state

driven

signal

that

indicates

during byte

and

word

transfers

that

a

data

transfer

will

occur

on

data

bus

lines

008

through

015

and

data

lines

024

through

031

for

32-bit

data

transfers.

5-1

I

SUPPORT

INFORMATION

TABLE

5-1.

CONNECTOR

PI

INTERCONNECT

SIGNALS

(cont.)

Number Al3

Al4

AIS Al6

Al7 AI8

Al9 A2"

A21

A22

5-2

Signal

Mnemonic

DS"*

WRITE*

GND DTACK*

GND AS*

GND

IACK*

IACKIN*

IACKOUT*

Signal

Name

and

Description

DATA

STROBE"

- A

three-state

driven

signal

that

indicates

during byte

and

word

transfers

that

a

data

transfer

will

occur

on

data

bus 1 ines 0""

through 0"7

and

data

lines

016

through

023

for

32-bit

data

transfers.

WRITE

A

three-state

driven

signal

that

specifies

that

the

data

transfer

cycle

in

progress

is

either

a read

or a write.

A high

level

indicates

a read

operation; a low

level

indicates

a

write

operat i on. GROUND DATA

TRANSFER

ACKNOWLEDGE -An

open-collector

driven signal generated

by a data

transfer

bus

slave.

The

falling

edge

of

this

signal

indicates

that

valid

data

is

available

on

the

data

bus

duri

ng

a read

cycle,

or

that

data

has

been

accepted

from

the

data

bus

duri

ng a write

cycle. GROUND ADDRESS

STROBE -The

falling

edge

of

this

signal

is

used

to

indicate

that a valid

address

is

on

the

address bus.

AS*

is

an

active

low,

TTL

three-

state

signal.

GROUND

INTERRUPT

ACKNOWLEDGE -An

open-collector

driven

input

signal

that

indicates

a

VME

interrupt

acknowl

edge

eyc 1 e.

The

VME

system contro

11

er

has

been

interrupted

on

one

of

seven 1 eve 1

sand

is

now

acknowl

edg i ng

the

interrupt.

INTERRUPT

ACKNOWLEDGE

IN

-

The

IACKIN*

and

IACKOUT*

lines

form a daisy-chained

acknowledge

signal.

The

IACKIN*

input

signal

is

connected

directly

to

IACKOUT*

on

the

MVMEl35/136.

INTERRUPT

ACKNOWLEDGE

OUT

- See

IACKIN*

(pin

A21)

.

SUPPORT

INFORMATION

TABLE

5-1.

CONNECTOR

PI

INTERCONNECT

SIGNALS

(cont.)

Pin Signal

Number

Mnemonic

A23

AM4

A24-A27

A07-A04

A28-A30

A03-A01

A31 A32

Bl

B2 B3

B4

B5

B6

B7

-12V

+15V

BBSY*

NC ACFAIL*

BG0IN*

BG00UT* BGIIN* BGIOUT*

Signal

Name

and

Descri

pt

ion

ADDRESS

MODIFIER

(bit

4) -One

of

four

input 1 ines

that

provide

additional

information

about

the

address bus, such as

size,

cycle

type,

and/or

data

transfer

bus master

identification.

ADDRESS

BUS

(bits

07-04) - Four

of

31

three-state

input

lines

that

specify

an

address in

the

memory

map. ADDRESS

BUS

(bits

03-01) - Three

of

31

three-state

input

lines

that

specify

an

address in

the

memory

map.

During

an

interrupt

acknowledge

cycle,

address

bus

lines

A~l

through

A~3

are used to

indicate

the

interrupt

level

that

is

being

acknowledged.

-12

Vdc

POWER -Used

by

system

logic

circuits.

+5

Vdc

POWER -Used

by

system log

icc

i rcu

its.

VMEbus

BUSY -An

open-collector

driven

signal

generated

by

the

current

Data

Transfer

Bus

(DTB)

master

to

indicate

that

it

is

using

the

bus.

NOT

CONNECTED.

SYSTEM

AC

POWER

FAIL -An

open-collector

driven

signal

which

indicates

that

the

AC

input

to

the

power supply

is

not being provided

or

the

required

input

voltage

level

is

not being met.

BUS

GRANT

IN

(level

0) -The

"bus

grant

in"

and

"bus

grant

out"

form

a da i sy-cha i

ned

bus

grant.

A

grant

received

at

the

jumpered

level

indicates

the

module

may

become

the

bus master.

The

remaining

three

"bus

grant

in" 1 ines are

connected

directly

to

their

respective

"bus

grant

out"

lines.

BUS

GRANT

OUT

(level

0) - see

BG0IN*

(pin B4).

BUS

GRANT 1 IN -Same

as

BG0IN

on

B4.

BUS

GRANT

lOUT -Same

as

BG~OUT

on

B5.

5-3

I

SUPPORT

INFORMATION

TABLE

5-1.

CONNECTOR

PI

INTERCONNECT

SIGNALS

(cant.)

Number B8

B9

Bl~

B11 B12

B13

Signal

Mnemonic

BG2IN* BG20UT* BG3IN* BG30UT*

BR"*

BRl*

B14

BR2*

B15

BR3*

B16-B19

AM~-AM3

B2~

GND

B21,B22

NC

B23

GND

Signal

Name

and

Description

BUS

GRANT

2

IN

-

Same

as

BG"IN

on

B4.

BUS

GRANT 2 OUT -Same

as

BG~OUT

on

B5.

BUS

GRANT

3

IN

-

Same

as

BG"IN

on

B4.

BUS

GRANT 3 OUT -Same

as

BG"OUT

on

B5.

BUS

REQUEST

(1

eve

1

")

-

One

of four

open -co

11

ector

driven signals

that

are generated

by

requesters.

These

signals indicate that a data

transfer

bus

master

in

the daisy-chain requires access to the

bus. BUS

REQUEST

(level

1) -Same

as

BR"*

on

B12.

BUS

REQUEST

(level

2) -Same

as

BR"*

on

B12.

BUS

REQUEST

(1

eve 1 3) -Same

as

BR"*

on

B12.

ADDRESS

MODIFIER

(bits

~-3)

-

Same

as

AM4

on

A23.

GROUND

NOT

CONNECTED

GROUND

824-83"

IRQ7*-IRQl*

INTERRUPT

REQUEST

(bits

7-1)-

These

signals are

generated

by

an

interrupter

and

carry the

prioritized

interrupt requests.

Level 7 is

the

highest

priority

and

level 1 the lowest.

B31

B32 CI-C8

5-4

+5VSTDBY

+5V

D~8-D15

+5Vdc

STANDB~

-

This

1 ine

suppl

ies

+5

Vdc

to

devices requiring battery

backup.

+5

Vdc

POWER -Used

by

system

logic

circuits.

DATA

BUS

(bits 8-15) - Eight of

16

three-state

bidirectional data lines

that

provide the data

path

between

the data

transfer

bus

master

and

slave.

SUPPORT

INFORMATION

TAB

LE

5-1.

CONNECTOR

Pl

INTERCONNECT

SIGNALS

(cant.)

Number

c'

m

Cll

Cl'

Signal

Mnemonic

GND

SYSFAIl*

BERR*

SYSRESET*

Cl3

LWORO*

C14

A.M5

C15-C30

A23-A08

C31

+12V

C32

+5V

Signal

Name

and

Description

GROUND

SYSTEM

FAILURE -An

open-collector

driven

signal

that

indicates

a

failure

has

occurred

in

the

system.

SYSFAIL*

may

be

generated

by

any module

on

the

VMEbus.

BUS

ERROR -An

open-collector

driven

signal

generated

by a slave.

BERR*

indicates

that

an

unrecoverable

error

has

occurred

and

the bus

cycle

must

be

aborted.

SYSTEM

RESET -An

open-collector

driven

signal

which,

when

low,

will

cause

the

system

to

be

reset. l

ONGWORD

- A

three-stilte

driven

signal

specifying

that

the

cycle

is

a byte/word

transfer

(when

high)

or

a 10ngword

transfer

(when

low).

ADDRESS

MODIFIER

(bit

5)

-

Same

as

AM4

on

A23.

ADDRESS

BUS

(bits

23-08) -

16

of

31

three-state

input

lines

that

specify

an

address

in

the

memory

map. +12

Vdc

POWER -Used

by

system

logic

circuits.

+5

Vdc

POWER -Used

by

system

logic

circuits.

5-

5

I

SUPPORT

INFORMATION

5.2.2

Connector

P2

Interconnect

Si

gna

1 s

Connector

P2

is

a standard

DIN

triple

row,

96-pin male

connector.

Table 5-2

lists

the

extended

VMEbus

and

the

VSBbus

signals.

Number

Al

A2

A3

A4

A5

A6

A7

A8

A9

AI0

All

Al2

5-6

TABLE

5-2.

CONNECTOR

P2

INTERCONNECT

SIGNALS

Signal

Mnemonic

MAD00

MAD02

MAD04

MAD06

MAD08

MADl0

MADI2

MAD14

MADl6

MADI8

MAD20

MAD22

Signal

Name

and

Description

VSBbus

MULTIPLEXED

ADDRESS/DATA

(bit

00) -One

of

32

multiplexed address/data lines

that

are

contra

11

ed

by

the three-

state

dri vers

on

the

master

and

slave devices

and

are

use

to broadcast

or receive addresses

and

data over the

VSBbus.

All

lines are active high,

TTL

three-state

signals. VSBbus

MULTIPLEXED

ADDRESS/DATA

(bit

02) -Same

as

MAD00

on

pi n AI.

VSBbus

MULTIPLEXED

ADDRESS/DATA

(bit

04) -Same

as

MAD00

on

AI.

VSBbus

MULTIPLEXED

ADDRESS/DATA

(bit

06) -Same

as

MAD00

on

AI.

VSBbus

MULTIPLEXED

ADDRESS/DATA

(bit

08) -Same

as

MAD00

on

AI.

VSBbus

MULTIPLEXED

ADDRESS/DATA

(bit

10) -Same

as

MAD00

on

AI.

VSBbus

MULTIPLEXED

ADDRESS/DATA

(bit

12) -Same

as

MAD00

on

AI.

VSBbus

MULTIPLEXED

ADDRESS/DATA

(bit

14) -Same

as

MAD00

on

pi n AI.

VSBbus

MULTIPLEXED

ADDRESS/DATA

(bit

16) -Same

as

MAD00

on

pi n AI.

VSBbus

MULTIPLEXED

ADDRESS/DATA

(bit

18) -Same

as

MAD00

on

AI.

VSBbus

MULTIPLEXED

ADDRESS/DATA

(bit

20) -Same

as

MAD00

on

AI.

VSBbus

MULTIPLEXED

ADDRESS/DATA

(bit

22) -Same

as

MAD00

on

AI.

Number Al3

Al4

A15

A16

Al7

AlB

Al9

A20

A21

A22

SUPPORT

INFORMATION

TABLE 5-2.

CONNECTOR

P2

INTERCONNECT

SIGNALS

(cont.)

Signal

Mnemonic

MAD24

MAD26

MAD2B

MAD30

GND

MIRQ*

MDS*

MWRITE*

SPACE0

SPACEl

Signal

Name

and

Description

VSBbus

MULTIPLEXED

ADDRESS/DATA

(bit

24) -Same

as

MAD00

on

AI.

VSBbus

MULTIPLEXED

ADDRESS/DATA

(bit

26) -Same

as

MAD00

on

AI.

VSBbus

MULTIPLEXED

ADDRESS/DATA

(bit

2B)

-

Same

as

MAD00

on

AI.

VSBbus

MULTIPLEXED

ADDRESS/DATA

(bit

30) -Same

as

MAD00

on

pi n AI. GROUND VSBbus

INTERRUPT

REQUEST

- This signal.

when

low,

indicates that a secondary master or sl

ave

device

is attempting to interrupt the primary master.

This

line is

an

active

low,

TTL

open-collector

signal. VSBbus

DATA

STROBE -The

fa

11

i

ng

edge

of

MDS*

indicates that a valid data

transfer

will occur

on

the

bus

(MAD00

to

MAD31)

at

this

time.

During

write cycles, write data

is

valid at the falling

edge

of

MDS*.

This

line

is

an

active

low,

TTL

three-state

signal.

VSBbus

WRITE -This

signal,

when

low,

indicates

that

a write operation

is

to

be

performed

and

when

high, indicates

that

a read operation will occur.

~1WRITE

is

valid

when

MAS*

is

asserted

on

the

bus.

This

line

is

an

active

low,

TTL

three-state

signal.

VSBbus

SPACE

SELECT 0 (bit

0) -One

of

two

signals

that

are driven

by

the active master

and

used

to

select

either

one

of three address spaces

(i.e

..

the

System

Address

Space,

the

I/O

Address

Space,

or the Alternate

Address

Space), or to

initiate

an

interrupt

acknowledge,

or

an

arbitration

cycle.

VSBbus

SPACE

SELECT I (bit

1) -

Same

as

SPACE0

on

A2I.

5-7

•

II

SUPPORT

INFORMATION

TABLE

5-2.

CONNECTOR

P2

INTERCONNECT

SIGNALS

(cont.)

Number

A23

A24

A25-30 A31

A32

B1 B2 B3

B4-B11

B12

5-8

Signal

Mnemonic

MBLOK*

MERR*

GND MBGIN*

MBR*

+5V GND

P2B3

A24-A31

GND

Signal

Name

and

Description

VSBbus

LOCK

- This

signal,

when

low,

indicates

the

bus

is

locked

and

that

no

other

master can

obtain

possession

of

the

bus.

MBLOK*

is

also

used in

certain

modes

to

indicate

that

a block

transfer

cycle

is

in

progress.

This

line

is

an

active

low,

TTL

three-state

signal.

VSBbus

ERROR

- This

signal,

when

low,

is

issued

by

the

selected

slave

module

to

indicate

a

fault

condition

while attempting a

data

transfer

operation.

This

would

typically

be

the

result

of

a

parity

error

detected

on a slave

device.

This

1 ine

is

an

active

low,

TTL

open-collector

signal. GROUND VSBbus

GRANT

IN

- This input

signal

is

generated

by

the

arbiter

or a requester.

The"

bus

grant

in"

and

"bus grant out"

signals

form

a

bus

grant

daisy-chain.

MBGIN*

indicates

to

the

module

receiving

it,

that

it

may

use

the

VSBbus.

VSBbus

REQUEST

- This

signal

is

an

output

from

the

requester

and

an

input

to

the

arbiter

when

system

controller

and

to

the

requester

at

all

times.

MBR*

is

used

by

the

arbi

ter

to

determi

ne

when

another master needs

the

bus.

MBR*

is

used

by

the

requester

to

release

the

bus

(ROR).

This

line

is

an

active

low,

TTL

three-state

signal.

+5

Vdc

POWER -Used

by

system 1 ogi c c i rcu i

ts.

GROUND VMEbus

RESERVED

PIN -Optionally

used

by

the

MVME135/136

and

MVME204-x

system

combi

nat i on

as

a

lock

signal

for

VMEbus

via

jumper

Jl.

ADDRESS

BUS

(bits

24-31) - These

are

the

eight

optional

three-state

driven

address

lines

which

speci fy the extended

VME

memory

address.

GROUND

SUPPORT

INFORMATION

TABLE

5-2.

CONNECTOR

P2

INTERCONNECT

SIGNALS

(cont.)

Signal

Number

Mnemonic

Signal

Name

and

Description

B13

+5V

+5

Vdc

POWER -Used

by

system

logic

circuits.

B14-B21

D16-D23

DATA

BUS

(bits

16-23)

- Eight of the

16

bidirectional

three-state

driven data lines

which

provide the

expanded

data path

between

the

DTB

master

and

slave for the optional

expanded

data

bus

configuration.

B22

GND

GROUND

B23-B30

D24-D31

B3I B32

C1

C2

C3

C4

C5

C6

C7

C8

GND +5V MAD01

MAD03

MAD05

MAD07

MAD09

MAD

11

MAD13

MADI5

DATA

BUS

(bits

24-31)

- Eight of the

16

bidirectional

three-state

driven data lines

which

provide the

expanded

data path

between

the

DTB

master

and

slave for the optional

expanded

data

bus

configuration.

GROUND

+5

Vdc

POWER -Used

by

system

logic

circuits.

VSBbus

MULTIPLEXED

ADDRESS/DATA

(bit

01) -Same

as

MAD00

on

AI.

VSBbus

MULTIPLEXED

ADDRESS/DATA

(bit

03) -Same

as

MAD00

on

AI.

VSBbus

MULTIPLEXED

ADDRESS/DATA

(bit

05) -Same

as

MAD00

on

AI.

VSBbus

MULTIPLEXED

ADDRESS/DATA

(bit

07) -Same

as

MAD00

on

AI.

VSBbus

MULTIPLEXED

ADDRESS/DATA

(bit

09) -Same

as

MAD00

on

AI.

VSBbus

MULTIPLEXED

ADDRESS/DATA

(bit

II) -

Same

as

MAD00

on

AI.

VSBbus

MULTIPLEXED

ADDRESS/DATA

(bit

13) -Same

as

MAD00

on

AI.

VSBbus

MULTIPLEXED

ADDRESS/DATA

(bit

15)

Same

as

MAD00

on

AI.

5-9

•

I

SUPPORT

INFORMATION

TABLE

5-2.

CONNECTOR

P2

INTERCONNECT

SIGNALS

(cant.)

Signal

Number

Mnemonic

Signal

Name

and

Description

C9

MAD17

VSBbus

MULTIPLEXED

ADDRESS/DATA

(bit

17) -Same

as

MAD00

on

AI.

C10

MAD19

VSBbus

MULTIPLEXED

ADDRESS/DATA

(bit

19) -Same

as

MAD00

on

AI.

Cl1

MAD21

VSBbus

MULTIPLEXED

ADDRESS/DATA

(bit

21) -Same

as

MAD00

on

AI.

C12

MAD23

C13

MAD25

C14

MAD27

CIS

MAD29

C16

MAD31

C17-C20

GND

C21

MSIZ0

C22

MAS*

C23

MSIZl

C24

GND

C25

MACK*

5-Hl

VSBbus

MULTIPLEXED

ADDRESS/DATA

(bit

23) -Same

as

MAD00

on

AI.

VSBbus

MULTIPLEXED

ADDRESS/DATA

(bit

25) -Same

as

MAD00

on

AI.

VSBbus

MULTIPLEXED

ADDRESS/DATA

(bit

27) -Same

as

MAD00

on

AI.

VSBbus

MULTIPLEXED

ADDRESS/DATA

(bit

29) -Same

as

MAD00

on

pi n AI.

VSBbus

MULTIPLEXED

ADDRESS/DATA

(bit

31) -Same

as

MAD00

on

pi n AI. GROUND VSBbus

SIZE

(bit

0) -One

of

two

lines

which

in

conjunction

with

MAD00

and

MAD01,

determine the

active portion of the data bus. This line

is

an

active

low,

TTL

three-state

signal.

VSBbus

ADDRESS

STROBE -The

falling

edge

of

MAS*

indicates that a valid address

is

present

on

the

MAD00

to

MAD31

bus. This line

is

an

active

low,

TTL

three-state signal.

VSBbus

SIZE

(bit

1) -Same

as

MSIZ0

on

C2I.

GROUND

VSBbus

DATA

TRANSFER

ACKNOWLEDGE

- This signal

is

issued

by

a slave

devi

ce

to complete the

handshake

for a data transfer operation. This line

is

an

active

low,

TTL

three-state

signal.

Number

C26

C27

C28

C29

C3~

SUPPORT

INFORMATION

TABLE

5-2.

CONNECTOR

P2

INTERCONNECT

SIGNALS

(cont.)

AC

Signal

Mnemonic

ASACK1*

ASACK~*

MCACHE*

WAIT*

Signal

Name

and

Descri pt i

on

VSBbus

ADDRESS

CYCLE

COMPLETE

- This signal is

issued

by

a slave device to indicate

that

address

decoding

has

been

completed.

All

slave devices

must

allow

AC

to

go

high

after

the

decode

interval

has

elapsed regardless of whether the device

is

se

1 ected

by

the current address

on

the bus.

AC

is

an

active high,

TTL

open-collector signal.

VSBbus

ADDRESS/SIZE

ACKNOWLEDGE

(bit

1) -One

of

two

lines

that are driven

by

VSBbus

slave devices

and

are

used

to perform several functions.

The

slave device

that

is

selected

by

address decoding

must

drive at

least

one

ASACK*

signal to control

switching

and

multiplexed address/data

bus

from

address to data. Secondly,

ASACK~*

and

ASACK1*

are

encoded

to indicate to the master the size of

the data

bus

for the slave

module.

Finally,

ASACK*

can

be

gated with signal

AC

on

the master

device.

The

condition of

AC

active

and

ASACK*

inactive, while

MAS*

is

asserted,

is

defined to

indicate that

no

VSBbus

slave

module

has

decoded

the address being driven

at

that

time or that

there are

no

VSBbus

slave

modules

installed.

This

provides the

VSBbus

master the opportunity to

switch to the

VMEbus

when

VSBbus

slaves are

not

responding.

ASACK~*

and

ASACK1*

are active

low,

TTL

open-collector signal s.

VSBbus

ADDRESS/SIZE

ACKNOWLEDGE

(bit

~)

-

Same

as

ASACK1*

on

C27.

VSBbus

CACHEABLE

- This signal

is

issued

by

a

slave device

at

the

same

time

that

ASACK~*

and

ASACK1*

are issued to indicate

that

the current

transfer

is

cacheable.

MCACHE*

remains inactive

to indicate that the

transfer

is

non-cacheable.

This

line

is

an

active

low,

TTL

open-collector

signal. VSBbus

HOLD

THIS

CYCLE

- This signal

is

an

input

line

used

only

in

the master

mode

to indicate

that

this

VSBbus

cycle should not

be

terminated until

the signal is negated.

The

DSACK1*

and

DSACK~*

lines

are not asserted until

this

line

is

negated.

5-11

I

SUPPORT

INFORMATION

Number

C31

C32

5-12

TABLE 5-2.

CONNECTOR

P2

INTERCONNECT

SIGNALS

(eont.)

Signal

Mnemonic

MBBSY*

MBG*

Signa 1 Name

and

Oeseri pt

ion

VSBbus

BUSY -This

signal

is

driven

by

the current

master to indicate

that

it

is

using the

bus_

When

the master releases

this

line,

the resultant

rising

edge

causes the

arbiter

to

sample

the

bus

request line

and

grant the

bus

to the requester.

This line is

an

active

low,

TTL

open-collector

signal.

VSBbus

GRANT

OUT -This

line

is

the output of the

on

chip requester.

MBG*

is

asserted

whenever

the

module

receives a

bus

request

and

is

the

system

contro

11

er

and

does

not

need

the

bus

or

when

it

is

not

the

system

controller

and

it

receives a

bus

grant

in

and

it

does

not

need

the bus.

This

line

is

an

active

low,

TTL

open-collector signal.

SUPPORT

INFORMATION

5.2.3

Connector

J3

Interconnect

Si

gna

1 s

Connector

J3

is a 27-pin,

single-row

connector

used

for

connecting

the

MVME135j136

to

the

1Mb

or

4Mb

DRAM

mezzanine

module.

Table

5-3

list

the

connection,

signal

mnemonic,

and

signal

description

for

the

connector.

Number

1-

113

12

13

14

15

16

17

18

19

20

TABLE

5-3.

CONNECTOR

J3

INTERCONNECT

SIGNALS

Signal

Mnemonic

LD00-LDI0

GND

+5V

WRl*

WR0*

CAS3*

WR2*

CAS0*

CASl*

CAS2*

Signal

Name

and

Description

LOCAL

DATA

BUS

(bits

00-10) - Eleven

of

32

local

data 1 ines

that

are connected

directly

to

the

MC68020

microprocessor.

GROUND

+5

Vdc

POWER -Used

by

system

logic

circuits.

DRAM

WRITE

ENABLE

BYTE

I - Thi s

signal,

when

asserted,

causes

data

to

be

written

into

local

data

bits

LD08

through LOIS.

DRAM

WRITE

ENABLE

BYTE

0 - This

signal,

when

asserted,

causes

data

to

be

written

into

local

data

bits

LD00

through

LD07.

DRAM

COLUMN

ADDRESS

STROBE

BYTE

3 - This

signal,

when

asserted, strobes column addresses

to

local

DRAMs

connected

to

data

bits

LD24

through

LD31.

DRAM

WRITE

ENABLE

BYTE

2 -

Th

iss i gna

1,

when

asserted,

causes

data

to

be

written

into

local

data

bits

LD16

through

LD23.

DRAt4

COLUMN

ADDRESS

STROBE

BYTE

0 -

Th

iss i gna

1 ,

when

asserted, strobes column addresses

to

local

DRMs

connected

to

data

bits

LD00

through

LD07.

DRAM

COLUMN

ADDRESS

STROBE

BYTE

I - This

signal,

when

asserted, strobes column addresses

to

local

DRAMs

connected

to

data

bits

LD08

through

LOIS.

DRAM

COLU~IN

ADDRESS

STROBE

BYTE

2 - This

signal,

when

asserted, strobes column addresses

to

local

DRAMs

connected

to

data

bits

LD16

through

LD23.

5-13

•

SUPPORT

INFORMATION

TABLE

5-3.

CONNECTOR

J3

CONNECTIONS

(cont.)

Pin Signal

Number

Mnemonic

Signal

Name

and

Description

21

WR3*

DRAM

WRITE

ENABLE

BYTE

3 - This

signal,

when

asserted,

causes

data

to

be

written

into

local

data

bits

LD24

through

LD31.

22

GND

GROUND

23

+5V

+5

Vdc

POWER -Used

by

system

log

i c

ci

rcu

its.

24

25

26

27

5-14

REFRAS

NORMRAS

ROWADDR*

MEZZERR*

DRAM

REFRESH

ROW

ADDRESS

STROBE -REFRAS

is

logically

OR'

ed

with

NORMRAS,

with

timing

to

perform

CAS

before

RAS

refresh.

NORMAL

DRAM

CYCLE

ROW

ADDRESS

STROBE

- This

DRAM

address

multiplexed

control

signal

is

used

as

a

timing

strobe

for

normal

memory

cycles.

ROW

ADDRESS

SELECT

- This

signal

is

used

to

switch

from

row

to

column

addresses

on

the

DRAM

Mezzanine. MEZZANINE

ERROR

- This

signal

is

asserted

when

the

mezzanine

parity

detection

circuitry

has

detected

a

single-bit

error.

,""

SUPPORT

INFORMATION

5.2.4

Connector J4

Interconnect

Signals

Connector

J4

is a 57-pin,

double-row

connector

used

for

connecting

the

MVME135/136

to

the

1Mb

or

4Mb

DRAM

mezzanine

module.

Table

5-4

list

the

connection,

signal

mnemonic, and

signal

description

for

the

connector.

Number

2

3

4

5 6 7 8 9

10

11

12

13

14

15

16

17 18

TABLE

5-4.

CONNECTOR

J4

INTERCONNECT

SIGNALS

Signal

Mnemonic

LD16

LD24 LD17 LD25

LD18 LD26 LD19 LD27 +5V GND

LD2~

LD28 LD21 LD29 LD22 LD30 LD23 LD31

Signal

Name

and

Description

LOCAL

DATA

BUS

(bit

16) -

One

of

32

local

data

lines

that

are connected

directly

to

the

MC68~2~

microprocessor.

LOCAL

DATA

BUS

(bit

24) -

Same

as

LD16

on

l.

LOCAL

DATA

BUS

(bit

17) -

Same

as

LD16

on

l.

LOCAL

DATA

BUS

(bit

25) -

Same

as

LD16

on

1.

LOCAL

DATA

BUS

(bit

IS) -

Same

as

LD16

on

l.

LOCAL

DATA

BUS

(bit

26) -

Same

as

LD16

on

1.

LOCAL

DATA

BUS

(bit

19) -

Same

as

LD16

on

1.

LOCAL

DATA

BUS

(bit

27) -

Same

as

LD16

on

1.

+5

Vdc

POWER -Used

by

system

logic

circuits. GROUND LOCAL

DATA

BUS

(bit

2~)

-

Same

as

LD16

on

1.

LOCAL

DATA

BUS

(bit

2S) -Same

as

LD16

on

l.

LOCAL

DATA

BUS

(bit

21) -

Same

as

LD16

on

l.

LOCAL

DATA

BUS

(bit

29) -

Same

as

LD16

on

1.

LOCAL

DATA

BUS

(bit

22) -

Same

as

LD16

on

l.

LOCAL

DATA

BUS

(bit

3~)

-

Same

as

LD16

on

1.

LOCAL

DATA

BUS

(bit

23) -

Same

as

LD16

on

1.

LOCAL

DATA

BUS

(bit

31) -

Same

as

LD16

on

1.

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Motorola MVME135, MVME135A, MVME135-1, MVME136, MVMEl36A User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual