Motorola MPIC2113DW, MPIC2113P Datasheet

1

Motorola TMOS Power MOSFET Transistor Device Data

Power Products Division

 

    

The MPIC2113 is a high voltage, high speed, power MOSFET and IGBT driver
with independent high and low side referenced output channels. Proprietary HVIC
and latch immune CMOS technologies enable ruggedized monolithic construction.
Logic inputs are compatible with standard CMOS or LSTTL outputs. The output
drivers feature a high pulse current buffer stage designed for minimum driver
cross–conduction. Propagation delays are matched to simplify use in high frequen­cy applications. The floating channel can be used to drive an N–channel power
MOSFET or IGBT in the high side configuration which operates from 10 to 600
volts.

• Floating Channel Designed for Bootstrap Operation

• Fully Operational to +600 V

• Tolerant to Negative Transient Voltage

• dV/dt Immune

• Gate Drive Supply Range from 10 to 20 V

• Undervoltage Lockout for Both Channels

• Separate Logic Supply

• Operating Supply Range from 5 to 20 V

• Logic and Power Ground Operating Offset Range from –5 to +5 V

• CMOS Schmitt–triggered Inputs with Pull–down

• Cycle by Cycle Edge–triggered Shutdown Logic

• Matched Propagation Delay for Both Channels

• Outputs In Phase with Inputs

PRODUCT SUMMARY

V

OFFSET 600 V MAX

I

O+/– 2 A/2 A

V

OUT 10 – 20 V

t

on/off

(typical)

120 & 94 ns

Delay Matching

10 ns

PIN CONNECTIONS

(TOP VIEW)

8

HO

9

V

DD

10

HIN

11

SD

12

LIN

13

V

SS

14

7
6
5
4
3
2
1

V

B

V

S

V

CC

COM

LO

9

HO

V

DD

11

HIN

12

SD

13

LIN

14

V

SS

15

8
7
6
5
4
3
2

V

B

V

S

V

CC

COM

LO

14 LEADS PDIP MPIC2113P

16 1

10

16 LEADS SOIC (WIDE BODY)

MPIC2113DW

This document contains information on a new product. Specifications and information herein are subject
to change without notice.

Order this document

by MPIC2113/D



SEMICONDUCTOR TECHNICAL DATA



Device

Package

HIGH AND LOW

SIDE DRIVER

ORDERING INFORMATION

MPIC2113P PDIP

MPIC2113DW SOIC WIDE

DW SUFFIX

PLASTIC PACKAGE

CASE 751G–02

SOIC – WIDE

16

1

P SUFFIX

PLASTIC PACKAGE

CASE 646–06

14

1

 Motorola, Inc. 1996

MPIC2113

2

Motorola TMOS Power MOSFET Transistor Device Data

SIMPLIFIED BLOCK DIAGRAM

PULSE

GEN

UV

DETECT

PULSE
FILTER

HV

LEVEL

SHIFT

COM

LO

V

CC

V

S

V

B

HO

R
R

S

Q

V

DD

HIN

SD

LIN

V

SS

UV

DETECT

DELAY

VDD/V

CC

LEVEL

SHIFT

VDD/V

CC

LEVEL

SHIFT

R Q

S

R Q

S

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute
voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air
conditions.

Rating

Symbol Min Max Unit

High Side Floating Absolute Voltage

V

–0.3

625

V

High Side Floating Absolute Voltage
High Side Floating Supply Offset Voltage

V

B

V

–0.3

V

–25

625

V

+0.3

V

DC

High Side Floating Supply Offset Voltage
High Side Floating Output Voltage

V

S

V

HO

VB–25

VS–0.3

VB+0.3
VB+0.3

High Side Floating Output Voltage
Low Side Fixed Supply Voltage

V

HO

V

CC

VS–0.3

–0.3

VB+0.3

25

Low Side Fixed Supply Voltage
Low Side Output Voltage

V

CC

V

LO

–0.3
–0.3

25

VCC+0.3

LO

V

DD

CC

+0.3

VSS+25

DD

V

SS

SS

+25

VCC+0.3

Logic Input Voltage (HIN, LIN & SD)

SS

V

IN

CC

–25

VSS–0.3

CC

+0.3

VDD+0.3

Allowable Offset Supply Voltage Transient dVS/dt – 50 V/ns
*Package Power Dissipation @ TA ≤ +25°C (14 Lead DIP)

(16 SOIC–WIDE)

P

D

–

–
–

1.6

1.25

Watt

Thermal Resistance, Junction to Ambient (14 Lead DIP)

(16 SOIC–WIDE)

R

θJA

–
–

75

100

°C/W

Operating and Storage Temperature Tj, T

stg

–55 150 °C

Lead Temperature for Soldering Purposes, 10 seconds T

L

– 260 °C

RECOMMENDED OPERATING CONDITIONS

The Input/Output logic timing Diagram is shown in Figure 1. For proper operation the device should be used within the recommended condi­tions. The VS and VSS offset ratings are tested with all supplies biased at 15 V differential.

High Side Floating Supply Absolute Voltage

V

B

VS+10 VS+20

High Side Floating Supply Offset Voltage V

S

Note 1 600

High Side Floating Output Voltage V

HO

V

S

V

B

Low Side Fixed Supply Voltage V

CC

10 20

Low Side Output Voltage V

LO

0 V

CC

Logic Supply Voltage V

DD

VSS+5 VSS+20

Logic Supply Offset Voltage V

SS

–5 5

Logic Input Voltage (HIN, LIN & SD) V

IN

V

SS

V

DD

Ambient Temperature T

A

–40 125 °C

Note 1: Logic operational for VS of –5 to +600 V. Logic state held for VS of –5 V to –VBS.

Logic Supply Voltage
Logic Supply Offset Voltage

–0.3

VCC–25

V