Motorola MPC970FA Datasheet
SEMICONDUCTOR TECHNICAL DATA
1
REV 2
Motorola, Inc. 1997
1/97
The MPC970 is a 3.3V compatible, PLL based clock driver devices
targeted for high performance RISC or CISC processor based systems.
• Fully Integrated PLL
• Output Frequency Up to 250MHz
• Compatible with PowerPC and Pentium Processors
• Output Frequency Configuration
• On–Board Crystal Oscillator
• 52–Lead TQFP Packaging
• ±50ps Typical Cycle–to–Cycle Jitter
The MPC970 was designed specifically to drive today’s PowerPC 601
and Pentium processors while providing the necessary performance to
address higher frequency PowerPC 601 as well as PowerPC 603 and
PowerPC 604 applications. The 2x_PCLK output can toggle at up to
250MHz while the remaining outputs can be configured to drive the other
system clocks for MPC 601 based systems. As the processor based
clock speeds increase the processor bus will likely run at one third or
even one fourth the processor clock. The MPC970 supports the
necessary waveforms to drive the BCLKEN input signal of the MPC 601
when the processor bus is running at a lower frequency than the
processor. The MPC970 uses an advanced PLL design which minimizes
the jitter generated on the outputs. The jitter specification is well within the
requirements of the Pentium processor and meets the stringent
preliminary specifications of the PowerPC 603 and PowerPC 604
processors. The application section of this data sheet deals in more detail
with driving PowerPC and Pentium processor based systems.
The external feedback option of the MPC970 provides for a near zero delay between the reference clock input and the outputs
of the device. This feature is required in applications where a master clock is being picked up off the backplane and regenerated
and distributed on a daughter card. The advanced PLL of the MPC970 eliminates the dead zone of the phase detector and
minimizes the jitter of the PLL so that the phase error variation is held to a minimum. This phase error uncertainty makes up a
major portion of the part–to–part skew of the device.
For single clock driver applications the MPC970 provides an internal oscillator and internal feedback to simplify board layout
and minimize system cost. By using the on–board crystal oscillator the MPC970 acts as both the clock generator and distribution
chip. The external component is a relatively inexpensive crystal rather than a more expensive oscillator. Since in single board
applications the delay between the input reference and the outputs is inconsequential an internal feedback option is offered. The
internal feedback simplifies board design in that the system designer need not worry about noise being coupled into the feedback
line due to board parasitics and layout. The internal feedback is a fixed divide by 32 of the VCO. This divide ratio ensures that the
input crystals will be ≤20MHz, thus keeping the crystal costs down and ensuring availability from multiple vendors.
PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation.
LOW VOLTAGE
PLL CLOCK DRIVER
FA SUFFIX
52–LEAD TQFP PACKAGE
CASE 848D–03
MPC970
MOTOROLA TIMING SOLUTIONS
BR1333 — Rev 6
2
xtal1
xtal2
Ref_Sel
TClk
PLL_En
VCO_Sel
Ext_FB
IntFB_Sel
MPC601_CLKs
BClk_Div0
BClk_Div1
PCI_Div0
PCI_Div1
Frz_Data
Frz_Clk
Frz_Strobe
Com_Frz
MR/Tristate
PLL
Freeze
Control
Register
Clock,
De–Skew,
Freeze
3–State
Drivers
2x_PCLK
PCLKEN
BCLKEN
BCLK0
BCLK1
BCLK2
BCLK3
BCLK4
PCI_CLK0
PCI_CLK1
PCI_CLK2
PCI_CLK3
PCI_CLK4
PCI_CLK5
PCI_CLK6
Clock
Dividers
Figure 1. Enable/Disable Scheme
The MPC970 offers a very flexible output enable/disable scheme. This enable/disable scheme helps facilitate system debug
as well as provide unique opportunities for system power down schemes to meet the requirements of “green” class machines.
The MPC970 allows for the enabling of each output independently via a serial input port or a common enable/disable of all
outputs simultaneously via a parallel control pin. When disabled or “frozen” the outputs will be locked in the “LOW” state, however
the internal state machines will continue to run. Therefore when “unfrozen” the outputs will activate synchronous and in phase
with those outputs which were not frozen. The freezing and unfreezing of outputs occurs only when they are already in the “LOW”
state, thus the possibility of runt pulse generation is eliminated. A power–on reset will ensure that upon power up all of the outputs
will be active.
For IC and board level testing a MR/Tristate
input is provided. When pulled “LOW” all outputs will tristate and all internal flip
flops will be reset. In addition the internal PLL can be bypassed and the fanout dividers and output buffers can be driven directly
by the TClk input pin. Note that in this mode it will take a number of input clock pulses to cause output transitions as the TClk is
fed through the internal dividers.
The MPC970 is fully 3.3V (3.6V for PowerPC 601 designs) compatible and requires no external loop filter components. All
inputs accept LVCMOS/LVTTL compatible levels while the outputs provide LVCMOS levels with the capability to drive 50Ω
transmission lines. For series terminated lines each MPC970 output can drive two 50Ω lines in parallel thus effectively doubling
the fanout of the device.
MPC970
TIMING SOLUTIONS
BR1333 — Rev 6
3 MOTOROLA
pci_pclk_enb
pci_clk
bclk
>50dc
bclk
50dc
pclk
2x_PCLK
PCLKEN
BCLKEN
BCLK0
BCLK1
BCLK2
BCLK3
BCLK4
PCI_CLK0
PCI_CLK1
PCI_CLK2
PCI_CLK3
PCI_CLK4
PCI_CLK5
PCI_CLK6
Freeze,
De–Skew
Freeze,
De–Skew
Freeze,
De–Skew
Freeze,
De–Skew
Freeze,
De–Skew
Freeze,
De–Skew
Freeze,
De–Skew
Freeze,
De–Skew
Freeze,
De–Skew
Freeze,
De–Skew
Freeze,
De–Skew
Freeze,
De–Skew
Freeze,
De–Skew
Freeze,
De–Skew
Freeze,
De–Skew
Freeze
Register
Mux
pci_clk6_frz
pci_clk5_frz
pci_clk4_frz
pci_clk3_frz
pci_clk2_frz
pci_clk1_frz
pci_clk0_frz
bclk4_frz
bclken_frz
pclken_frz
2x_plck_frz
bclk3_frz
bclk2_frz
bclk1_frz
bclk0_frz
Serial
Input
Register
Serial
Input
Controller
Clock
Dividers
÷
2
BCLK_Div0
BCLK_Div1
PCI_Div0
PCI_Div1
MPC601_Clks
IntFB_Sel
Ext_FB
xtal2
xtal1
Ref_Sel
VCO_Sel
PLL_EN
TClk
PLL
fVCO
fVCO/2
2x_pclk
4x_pclk
Com_frz
Frz_Clk
Frz_Strobe
Frz_Data
MR/Tristate
Figure 2. Simplified Block Diagram
Synchronizer
MPC970
MOTOROLA TIMING SOLUTIONS
BR1333 — Rev 6
4
MPC601_Clks
GNDO
BCLK0
VCCO
BCLK1
GNDO
BCLK2
VCCO
BCLK3
GNDO
BCLK4
VCCO
VCO_Sel
PCI_Div1
PCI_CLK4
VCCO
PCI_CLK3
GNDO
PCI_CLK2
PCI_Div0
VCCO
PCI_CLK1
GNDO
PCI_Clk0
VCCO
Ext_FB
VCCO
2x_PCLK
GNDO
BCLKEN
VCCO
PCLKEN
GNDO
PCI_CLK6
BClk_Div0
VCCO
PCI_CLK5
GNDO
BClk_Div1
GNDI
MR/Tristate
Frz_Clk
Frz_Strobe
Frz_Data
Com_Frz
PLL_EN
Ref_Sel
IntFB_Sel
VCCI
TClk
xtal1
xtal2
40
41
42
43
44
45
46
47
48
49
50
51
52
25
24
23
22
21
20
19
18
17
16
15
14
12345678910111213
39 38 37 36 35 34 33 32 31 30 29 28 27
26
MPC970
Figure 3. 52–Lead Pinout (Top VIew)
FUNCTION TABLE 1
MPC601_Clks 2x_PCLK PCLKEN BCLKEN BCLK PCI_CLK
0 VCO/4 VCO/4 VCO/4 X X
1 VCO/2 VCO/4 BCLK* X X
* Output is purposely delayed vs 2x_PCLK output.
FUNCTION TABLE 2
PCI_Div1 PCI_Div0 PCI_CLK BCLK_Div1 BCLK_Div0 BCLK
0 0 BLCK 0 0 PCLKEN
0 1 BCLK/2 0 1 PCLKEN/2
1 0 BCLK/3 1 0 PCLKEN/3
1 1 PCLKEN 1 1 PCLKEN/4
FUNCTION TABLE 3
Control Pin Logic ‘0’ Logic ‘1’
VCO_Sel fVCO/2 fVCO
Ref_Sel TCLK Crystal Osc
PLL_En Bypass PLL Enable PLL
IntFB_Sel Ext Feedback Int Feedback
MPC970
TIMING SOLUTIONS
BR1333 — Rev 6
5 MOTOROLA
ABSOLUTE MAXIMUM RATINGS*
Symbol Parameter Min Max Unit
V
CC
Supply Voltage –0.3 4.6 V
V
I
Input Voltage –0.3 VDD + 0.3 V
I
IN
Input Current ±20 mA
T
Stor
Storage Temperature Range –40 125 °C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is
not implied.
DC CHARACTERISTICS (TA = 0 to 70°C)
Symbol Characteristic Min Max Unit Condition
V
CC
Power Supply Voltage 3.0 3.8 V
I
CC
Quiescent Power Supply 250 mA
V
IL
Input Voltage LOW LVCMOS Inputs 0.3V
DD
V
V
IH
Input Voltage HIGH LVCMOS Inputs 0.7V
DD
V
I
IH
Input Current HIGH LVCMOS Inputs –100 µA VIN = V
CC
I
IL
Input Current LOW –200 µA VIN = GND
V
OH
Output Voltage HIGH VDD–0.2 V IOH = –20mA (Note 1.)
V
OL
Output Voltage LOW 0.2 V IOL = 20mA (Note 1.)
I
OZ
Tristate Output Leakage Current –10 10 µA VOH = VCC or GND
C
IN
Input Capacitance 4 pF
C
pd
Power Dissipation Capacitance pF
C
OUT
Output Capacitance 8 pF
1. The MPC970 outputs can drive series or parallel terminated 50Ω (or 50Ω to VCC/2) transmission lines on the incident edge (see Applications
Info section).
PLL INPUT REFERENCE CHARACTERISTICS (TA = 0 to 70°C)
Symbol Characteristic Min Max Unit Condition
tr, t
f
TCLK Input Rise/Falls 3.0 ns
f
ref
Reference Input Frequency 10 Note 2. MHz
f
refDC
Reference Input Duty Cycle 25 75 %
2. Maximum input reference is limited by the VCO lock range and the feedback divider .
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