Motorola MPC952FA Datasheet
SEMICONDUCTOR TECHNICAL DATA
1
REV 3
Motorola, Inc. 1998
2/98
The MPC952 is a 3.3V compatible, PLL based clock driver device
targeted for high performance clock tree applications. The device
features a fully integrated PLL with no external components required.
With output frequencies of up to 180MHz and eleven low skew outputs
the MPC952 is well suited for high performance designs. The device
employs a fully differential PLL design to optimize jitter and noise
rejection performance. Jitter is an increasingly important parameter as
more microprocessors and ASiC’s are employing on chip PLL clock
distribution.
• Fully Integrated PLL
• Output Frequency up to 180MHz
• High Impedance Disabled Outputs
• Compatible with PowerPC, Intel and High Performance RISC
Microprocessors
• Output Frequency Configurable
• TQFP Packaging
• ±100ps Cycle–to–Cycle Jitter
The MPC952 features three banks of individually configurable outputs.
The banks contain 5 outputs, 4 outputs and 2 outputs. The internal divide
circuitry allows for output frequency ratios of 1:1, 2:1, 3:1 and 3:2:1. The
output frequency relationship is controlled by the fsel frequency control
pins. The fsel pins as well as the other inputs are LVCMOS/LVTTL
compatible inputs.
The MPC952 uses external feedback to the PLL. This features allows
for the use of the device as a “zero delay” buffer. Any of the eleven
outputs can be used as the feedback to the PLL. The VCO_Sel pin allows for the choice of two VCO ranges to optimize PLL
stability and jitter performance. The MR/OE
pin allows the user to force the outputs into high impedance for board level test.
For system debug the PLL of the MPC952 can be bypassed. When forced to a logic HIGH, the PLLEN input will route the
signal on the RefClk input around the PLL directly to the internal dividers. Because the signal is routed through the dividers, it
may take several transitions of the RefClk to affect a transition on the outputs. This features allows a designer to single step the
design for debug purposes.
The outputs of the MPC952 are LVCMOS outputs. The outputs are optimally designed to drive terminated transmission lines.
For applications using series terminated transmission lines each MPC952 output can drive two lines. This capability provides an
effective fanout of 22, more than enough clocks for most clock tree designs. For more information on driving transmission lines
consult the applications section of this data sheet.
PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation.
LOW VOLTAGE
PLL CLOCK DRIVER
FA SUFFIX
TQFP PACKAGE
CASE 873A-02
MPC952
MOTOROLA ECLinPS and ECLinPS Lite
DL140 — Rev 3
2
Figure 1. MPC952 Logic Diagram
VCO
200–480MHz
PHASE
DETECTOR
LPF
fsela
VCO_Sel
FBin
÷4/÷
6
Qa0
Qa1
Qa2
Qa3
Qa4
REFCLK
PLL_En
÷
2
fselb
÷4/÷
2
Qb0
Qb1
Qb2
Qb3
fselc
÷2/÷
4
Qc0
Qc1
MR/OE
(Int Pull Down)
(Int Pull Down)
(Int Pull Down)
(Int Pull Down)
(Int Pull Down)
FUNCTION TABLES
fsela Qan fselb Qbn fselc Qcn
0
1
÷4
÷6
0
1
÷4
÷2
0
1
÷2
÷4
Control Pin Logic ‘0’ Logic ‘1’
VCO_Sel fVCO fVCO/2
MR/OE Output Enable High Z
PLL_En Enable PLL Disable PLL
Pin Name Description
VCCA PLL Power Supply
VCCO Output Buffer Power Supply
VCCI Internal Core Logic Power Supply
GNDI Internal Ground
GNDO Output Buffer Ground
PLL_En
VCCO
Qb2
Qb3
GNDO
GNDO
Qc0
Qc1
VCCO
VCCO
Qa2
Qa1
GNDO
Qa0
VCCI
VCCA
GNDO
Qb1
Qb0
VCCO
VCCO
Qa4
Qa3
GNDO
VCO_Sel
fselc
fselb
fsela
MR/OE
REFCLK
GNDI
FBin
25
26
27
28
29
30
31
32
15
14
13
12
11
10
9
12345678
24 23 22 21 20 19 18 17
16
MPC952
Figure 2. 32–Lead Pinout (Top View)
MPC952
ECLinPS and ECLinPS Lite
DL140 — Rev 3
3 MOTOROLA
ABSOLUTE MAXIMUM RATINGS*
Symbol Parameter Min Max Unit
V
CC
Supply Voltage –0.3 4.6 V
V
I
Input Voltage –0.3 VDD + 0.3 V
I
IN
Input Current ±20 mA
T
Stor
Storage Temperature Range –40 125 °C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not
implied.
DC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%)
Symbol Characteristic Min Typ Max Unit Condition
V
IH
Input HIGH Voltage 2.0 3.6 V
V
IL
Input LOW Voltage 0.8 V
V
OH
Output HIGH Voltage 2.4 V IOH = –20mA (Note 1.)
V
OL
Output LOW Voltage 0.5 V IOL = 20mA (Note 1.)
I
IN
Input Current ±120 µA Note 2.
C
IN
Input Capacitance 2.7 4 pF
C
pd
Power Dissipation Capacitance 25 pF
I
CC
Maximum Quiescent Supply Current 160 mA Total ICC Static Current
I
CCA
PLL Supply Current 15 20 mA
1. The MPC952 outputs can drive series or parallel terminated 50Ω (or 50Ω to VCC/2) transmission lines on the incident edge (see Applications
Info section).
2. Inputs have pull–up, pull–down resistors which affect input current.
PLL INPUT REFERENCE CHARACTERISTICS (TA = 0 to 70°C)
Symbol Characteristic Min Max Unit Condition
tr, t
f
TCLK Input Rise/Falls 3.0 ns
f
ref
Reference Input Frequency Note 3. Note 3. MHz
f
refDC
Reference Input Duty Cycle 25 75 %
3. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider.
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