Motorola MPC946FA Datasheet
SEMICONDUCTOR TECHNICAL DATA
1
REV 1
Motorola, Inc. 1996
10/96
The MPC946 is a low voltage CMOS, 10 output clock buffer. The 10
outputs can be configured into a standard fanout buffer or into 1X and
1/2X combinations. The ten outputs were designed and optimized to drive
50Ω series or parallel terminated transmission lines. With output to output
skews of 350ps the MPC946 is an ideal clock distribution chip for
synchronous systems which need a tight level of skew from a large
number of outputs. For a similar product with more outputs consult the
MPC949 data sheet.
• Clock Distribution for Pentium Systems with PCI
• 2 Selectable LVCMOS/LVTTL Clock Inputs
• 350ps Output to Output Skew
• Drives up to 20 Independent Clock Lines
• Maximum Input/Output Frequency of 150MHz
• Tristatable Outputs
• 32–Lead TQFP Packaging
• 3.3V VCC Supply
With an output impedance of approximately 7Ω, in both the HIGH and
the LOW logic states, the output buffers of the MPC946 are ideal for
driving series terminated transmission lines. More specifically each of the
10 MPC946 outputs can drive two series terminated transmission lines.
With this capability, the MPC946 has an effective fanout of 1:20 in
applications using point–to–point distribution schemes.
The MPC946 has the capability of generating 1X and 1/2X signals from
a 1X source. The design is fully static, the signals are generated and
retimed inside the chip to ensure minimal skew between the 1X and 1/2X
signals. The device features selectability to allow the user to select the
ratio of 1X outputs to 1/2X outputs.
Two independent LVCMOS/LVTTL compatible clock inputs are available. Designers can take advantage of this feature to
provide redundant clock sources or the addition of a test clock into the system design. With the TCLK_Sel input pulled HIGH the
TCLK1 input is selected.
All of the control inputs are LVCMOS/LVTTL compatible. The Dsel pins choose between 1X and 1/2X outputs. A LOW on the
Dsel pins will select the 1X output. The MR/Tristate input will reset the internal flip flops and tristate the outputs when it is forced
HIGH.
The MPC946 is fully 3.3V compatible. The 32–lead TQFP package was chosen to optimize performance, board space and
cost of the device. The 32–lead TQFP has a 7x7mm body size with a conservative 0.8mm pin spacing.
Pentium is a trademark of Intel Corporation.
FA SUFFIX
TQFP PACKAGE
CASE 873A–02
LOW VOLTAGE
1:10 CMOS CLOCK DRIVER
MPC946
MOTOROLA TIMING SOLUTIONS
BR1333 — Rev 6
2
VCCa
Qa2
GNDa
Qa1
VCCa
Qa0
GNDa
Qc3
GNDc
Qc2
VCCc
Qc1
GNDc
Qc0
VCCc
GNDb
Qb0
VCCb
Qb1
GNDb
Qb2
VCCb
VCCc
TCLK_Sel
VCCI
TCLK0
TCLK1
Dsela
Dselb
Dselc
GNDI
25
26
27
28
29
30
31
32
15
14
13
12
11
10
9
12345678
24 23 22 21 20 19 18 17
16
MPC946
Pinout: 32–Lead TQFP (Top View)
FUNCTION TABLES
TCLK_Sel Input
0
1
TCLK0
TCLK1
Dselx Outputs
0
1
1x
1/2x
MR/OE Outputs
0
1
Enabled
Hi–Z
LOGIC DIAGRAM
TCLK1
Qa0:2
TCLK0
TCLK_Sel
3
R
÷
2
MR/OE
÷
1
Dsela
Qb0:2
3
Dselb
Qc0:3
4
Dselc
MR/OE
0
1
0
1
0
1
0
1
(Int Pull Up)
(Int Pull Up)
(Int Pull Down)
(Int Pull Down)
(Int Pull Down)
(Int Pull Down)
(Int Pull Down)
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