Motorola MPC941FA Datasheet
SEMICONDUCTOR TECHNICAL DATA
1
REV 0.1
Motorola, Inc. 1997
2/97
"
!
The MPC941 is a 1:27 low voltage clock distribution chip. The device
features the capability to select either a differential L VPECL or an LVTTL/
LVCMOS compatible input. The 27 outputs are LVCMOS or LVTTL
compatible and feature the drive strength to drive 50Ω series or parallel
terminated transmission lines. With output–to–output skews of 250ps, the
MPC941 is ideal as a clock distribution chip for the most demanding of
synchronous systems. For a similar product with a smaller number of
outputs, please consult the MPC940 data sheet.
• LVPECL or LVCMOS/LVTTL Clock Input
• 250ps Maximum Targeted Output–to–Output Skew
• Drives Up to 54 Independent Clock Lines
• Maximum Output Frequency of 250MHz
• High Impedance Output Enable
• 52–Lead TQFP Packaging
• 3.3V V
CC
Supply Voltage
With a low output impedance, in both the HIGH and LOW logic states,
the output buffers of the MPC941 are ideal for driving series terminated
transmission lines. More specifically, each of the 27 MPC941 outputs can
drive two series terminated 50Ω transmission lines. With this capability,
the MPC941 has an effective fanout of 1:54 in applications where each
line drives a single load. With this level of fanout, the MPC941 provides
enough copies of low skew clocks for most high performance
synchronous systems.
The differential LVPECL inputs of the MPC941 allow the device to interface directly with a LVPECL fanout buffer like the
MC100EP111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS/LVTTL input
provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In
addition, the two clock sources can be used to provide for a test clock interface as well as the primary system clock. A logic HIGH
on the LVCMOS_CLK_Sel pin will select the TTL level clock input.
The MPC941 is fully 3.3V compatible. The 52–lead TQFP package was chosen to optimize performance, board space and
cost of the device. The 52–lead TQFP has a 10x10mm body size with a conservative 0.65mm pin spacing.
This document contains information on a product under development. Motorola reserves the right to change or
discontinue this product without notice.
LOW VOLTAGE
1:27 CLOCK
DISTRIBUTION CHIP
FA SUFFIX
52–LEAD TQFP PACKAGE
CASE 848D–03
MPC941
MOTOROLA TIMING SOLUTIONS
BR1333 — Rev 6
2
VCCO
VCCO
Q7
Q6
Q5
GNDO
Q4
Q3
VCCO
Q2
Q1
Q0
GNDO
GNDO
GNDO
Q16
Q17
Q18
VCCO
Q19
Q20
GNDO
Q21
Q22
Q23
VCCO
GNDOQ8Q9
Q10
VCCO
Q11
Q12
GNDO
Q13
Q14
Q15
VCCO
VCCO
VCCO
Q26
Q25
Q24
GNDO
40
41
42
43
44
45
46
47
48
49
50
51
52
25
24
23
22
21
20
19
18
17
16
15
14
12345678910111213
39 38 37 36 35 34 33 32 31 30 29 28 27
26
MPC941
GNDO
GNDI
VCCI
LVCMOS_CLK
LVCMOS_CLKSEL
PECL_CLK
PECL_CLK
VCCO
Pinout: 52–Lead TQFP (Top View)
FUNCTION TABLE
LVCMOS_CLK_Sel Input
0
1
PECL_CLK
LVCMOS_CLK
LOGIC DIAGRAM
LVCMOS_CLK
Q0
PECL_CLK
0
1
LVCMOS_CLK_Sel
PECL_CLK
Q1–Q25
25
Q26
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