MPC561/MPC562 / MPC563/MPC564 RISC MCU
Including Peripheral Pin Multiplexing with
Flash and Code Compression Options
Features
The MPC561/MPC562 / MPC563/MPC564 are members of the Motorola MPC500 RISC Microcontroller
family. As shown in the block diagram, they are composed of:
• High performance CPU system
— High performance core
• Single issue integer core
• Compatible with PowerPC instruction set architecture
• Precise exception model
• Floating point
• Extensive system development support
— On-chip watchpoints and breakpoints
— Program flow tracking
— Background debug mode (BDM)
— IEEE-ISTO Nexus 5001-1999 Class 3 Debug Interface
— MPC500 system interface (USIU, BBC, L2U)
— Fully static design
— Four major power saving modes
• On, doze, sleep, deep-sleep and power-down
— 32-Kbyte static RAM (CALRAM)
— 512-Kbyte flash (UC3F) on MPC563/MPC564
— General-purpose I/O support
• On address (24) and data (32) pins
• 16 GPIO in MIOS14
• Many peripheral pins can be used as GPIO when not used as primary functions
• 2.6-V outputs on external bus pins
• PPM (peripheral pin multiplexing with parallel-to-serial driver) module
• Available in package or die
— Plastic ball grid array (PBGA) packaging
Key Feature Details
MPC500 System Interface (USIU)
• System configuration and protection features:
— Periodic-interrupt timer
— Bus monitor
— Software watchdog timer
— Real-time clock (RTC)
This document contains information on a new product. Specifications and
information herein are subject to change without notice.
• All features configurable and controllable via the auxiliary port
• Security features for production environment
• Supports the RCPU debug mode via the auxiliary port
• READI module can be reset independent of system reset
Integrated I/O System
Two Time Processor Units (TPU3)
• True 5-V I/O
• Two time processing units (TPU3) with16 channels each
• Each TPU3 is a micro-coded timer subsystem
• Eight-Kbytes of dual port TPU RAM (DPTRAM) shared by two TPU3 modules for TPU micro-code
22-Channel Modular I/O System (MIOS14)
• Six modulus counter sub-modules (MCSM)
• 10 double-action sub-modules (DASM)
• 12 dedicated PWM sub-modules (PWMSM)
• One MIOS14 16-bit parallel port I/O sub-modules (MPIOSM)
Two Enhanced Queued Analog-to-Digital Converter Modules (QADC64E)
• Two queued analog-to-digital converter modules (QADC64_A, QADC64_B) providing a total of 32
analog channels
• 16 analog input channels on each QADC64E module using internal multiplexing
• Directly supports up to four external multiplexers
• Up to 41 total input channels on the two QADC64E modules with external multiplexing
• Software configurable to operate in Enhanced or Legacy (MPC555 compatible) mode
• Unused analog channels can be used as digital input/output pins
— GPIO on all channels in Enhanced mode
• 10-bit A/D converter with internal sample/hold
• Typical conversion time of less than 5 µs (>200 K samples/second)
• Two conversion command queues of variable length
• Automated queue modes initiated by:
— External edge trigger
— Software command
— Periodic/interval timer within QADC64E module, that can be assigned to both queue 1 and 2
— External Gated trigger (queue 1only)
• 64 result registers
— Output data is right- or left-justified, signed or unsigned
MPC561/MPC563 PRODUCT BRIEFMOTOROLA
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• Alternate reference input (ALTREF), with control in the conversion command word (CCW)
Three CAN 2.0B Controller (TouCAN) Modules
• Three TouCAN modules (TOUCAN_A, TOUCAN_B, TOUCAN_C)
• Each TouCAN provides the following features:
— 16 message buffers each, programmable I/O modes
— Maskable interrupts
— Independent of the transmission medium (external transceiver is assumed)
— Open network architecture, multi-master concept
— High immunity to EMI
— Short latency time for high-priority messages
— Low-power sleep mode, with programmable wake-up on bus activity
— TOUCAN_C pins are shared with MIOS14 GPIO or QSMCM
Queued Serial Multi-Channel Module (QSMCM)
• One queued serial module with one queued SPI and two SCIs (QSMCM)
• QSMCM matches full MPC555 QSMCM functionality
• Queued SPI
— Provides full-duplex communication port for peripheral expansion or inter-processor commu-
nication
— Up to 32 preprogrammed transfers, reducing overhead
— Synchronous serial interface with baud rate of up to system clock / 4
— Four programmable peripheral-selects pins:
— Support up to 16 devices with external decoding
— Support up to eight devices with internal decoding
— Special wrap-around mode allows continuous sampling of a serial peripheral for efficient inter-
facing to serial analog-to-digital (A/D) converters
• SCI
— UART mode provides NRZ format and half- or full-duplex interface
— 16 register receive buffers and 16 register transmit buffers on one SCI
— Advanced error detection and optional parity generation and detection
— Word-length programmable as eight or nine bits
— Separate transmitter and receiver enable bits, and double buffering of data
— Wake-up functions allow the CPU to run uninterrupted until either a true idle line is detected,
or a new address byte is received
Peripheral Pin Multiplexing (PPM) PPM
• Synchronous serial interface between the microprocessor and an external device
• Four internal parallel data sources can be multiplexed through the PPM
— TPU3_A: 16 channels
— TPU3_B: 16 channels
— MIOS14: 12 PWM channels, 4 MDA channels
— Internal GPIO: 16 general-purpose inputs, 16 general-purpose outputs
• Software configurable stream size
• Software configurable clock (TCLK) based on system clock
• Software selectable clock modes (SPI mode and TDM mode)
The following are optional features of the MPC561/MPC562 / MPC563/MPC564:
• 56-MHz operation (40 MHz is default)
• Code compression supported on the MPC562 and the MPC564
— Compression reduces instruction memory requirements by 40-50%
— Compression optimized for automotive (non-cached) applications
• 512 Kbytes flash (available on the MPC563/MPC564 only)
— Single array
— Page mode read
— Block (64 Kbytes) erasable
— External 4.75- to 5.25-V VFLASH program, erase, and read power supply
(As viewed from top, through the package and silicon)
VSS VSS VSSVSSVSS VSS
VSS VSS VSSVSSVSS VSSA_CNTX0
VSS VSS VSSVSSVSS VSS
VSS VSS VSSVSSVSS VSS
VSS VSS VSSVSSVSS VSS
VSS VSS VSSVSSVSS VSS
ADDR_SG
ADDR_SGPI
PIOA18
ADDR_SG
PIOA13
ADDR_SG
PIOA14
ADDR_SG
PIOA15
OA20
ADDR_SGPI
OA16
ADDR_SGPI
OA17
ADDR_SGPI
OA9
ADDR_SG
PIOA23
ADDR_SG
PIOA19
ADDR_SG
PIOA31
ADDR_SG
PIOA8
NVDDL
ADDR_SGP
IOA21
ADDR_SGP
IOA30
ADDR_SGP
IOA22
ADDR_S
GPIOA26
ADDR_S
GPIOA24
ADDR_S
GPIOA28
ADDR_S
GPIOA27
DATA_SG
PIOD1
ADDR_SG
PIOA25
ADDR_SG
PIOA29
DATA_SG
PIOD31
DATA_SG
PIOD5
DATA_SG
PIOD0
DATA_SG
PIOD30
DATA_SG
PIOD3
DATA_SG
PIOD7
DATA_SG
PIOD28
DATA_SG
PIOD29
DATA_SG
PIOD2
NVDDL
DATA_SGP
IOD26
DATA_SGP
IOD27
DATA_SGP
IOD4
DATA_SG
PIOD9
DATA_SG
PIOD24
DATA_SG
PIOD25
DATA_SG
PIOD6
DATA_SGP
IOD11
DATA_SGP
IOD22
DATA_SGP
IOD23
DATA_SGP
IOD8
DATA_SG
PIOD12
DATA_SG
PIOD13
DATA_SG
PIOD21
DATA_SG
PIOD10
VSS
VSS
VDDH
VDDH
NVDDL
DATA_SGPI
OD15
DATA_SGPI
OD19
DATA_SGPI
OD20
ETRIG2_
PCS7 MDA13 MDA28
ETRIG1_
MDA14 MDA29 VSSVDDVSSQVDDL B
PCS6
MDA11 M DA15
MDA12 M DA27
DATA_S
VSSVDDVSSQVDDLVSSEXTAL AC
GPIOD14
IRQ5_B_S
DATA_S
GPIOC5_M
GPIOD16
ODCK1
DATA_S
IRQ6_B_M
GPIOD17
ODCK2
DATA_S
VDDH VSSVSSVSSVDDVSS AF
GPIOD18
VSSVSSVDDVSS A
VDDHVDDVSSQVDDLVSS C
VDDVSSQVDDLVSSVSS D
QVDDLVSSVSSVSS E
MDA30MDA31
MPWM1_MD
MPWM16
O2
MPWM17_M
MPWM18_MDO6MPWM19_M
DO3
MPIO32B6_
MPIO32B7_MP
MPWM4_MD
WM5
O6
MPIO32B12_
MPIO32B11_C
C_CNTX0
_CNRX0
VF0_MPIO32
VF1_MPIO32B
B0_MDO1
1_MCKO
VFLS0_MPIO
VF2_MPIO32B
32B3_MSEO
2_MSEI_B
PCS2_QGPI
O2
SCK_QGPIO
6
RXD1_QGPI1TXD2_QGPO2
EPEEBOEPEE
CLKOUTVSSFVDDFVFLASH U
VDDEXTCLKVSS
NVDDL
VSSVDDVSSQVDDLXTAL AD
VSSVSSVDDVSSQVDDL AE
_B
PCS0_SS_B_
PCS1_QGPIO1
MOSI_QGPIO5
TXD1_QGPO
_C_CNTX0
PORESET_B
IRQ7_B_MODCK3RSTCONF_B
MPWM0_MD
I1
MPWM3_PP
MPWM2_PP
M_RX1
M_TX1
MPIO32B5_
DO7
MDO5
MPIO32B8_
MPIO32B9_
MPWM20
MPWM21
MPIO32B10_
MPIO32B13_
PPM_TSYNC
PPM_TCLK
MPIO32B15_
MPIO32B14_
PPM_TX0
PPM_RX0
VFLS1_MPIO
32B4
A_CNRX0
QGPIO0
MISO_QGPIO4PCS3_QGPI
O3
PULL-SEL
1
RXD2_QGPI
VDDH
2_C_CNRX0
ENGCLK_BU
CLK
KAPWR W
_TRST_B
VDDSYN Y
_TEXP
NOTE: The flash balls are only available on the MPC563 and MPC564. These are no connect balls on
the MPC561 and MPC562. Flash supplies and inputs are located on the following balls: T23, T24, U24,
U25. U26.
1. Add R2 suffix for parts shipped in tape and reel media.
Order Part
Number
1
Package InfoTemperature
Range
Maximum
Frequency
Code
Compression
Table 2 lists the documents that provide a complete description of the MPC561/563 and are required
to design properly with the part. Documentation is available from a local Motorola distributor, a Motorola
semiconductor sales office, a Motorola Literature Distribution Center, or through the Motorola Semiconductor documentation page on the Internet (the source for the latest information).
Table 2 Available Documentation
Document Number Title
MPC561_3RM/ADMPC561/MPC563 Reference Manual
AN1821/DException Table Relocation and Multi-Processor
Address Mapping in the Embedded MPC5XX Family
AN2109/DMPC555 Interrupts.
AN2127/DEMC Guidelines for MPC500-Based Automotive Powertrain Systems
MPC561/MPC563 PRODUCT BRIEFMOTOROLA
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MPC561/MPC563 PRODUCT BRIEFMOTOROLA
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MPC561/MPC563 PRODUCT BRIEFMOTOROLA
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MPC561/MPC563 PRODUCT BRIEFMOTOROLA
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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty,
representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can
and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must
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