MOTOROLA MPC555PB Technical data
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Product Brief
MPC555PB/D
Rev. 3, 2/2003
MPC555 Product Brief
This document provides an overview of the
diagram showing the maj or modula r components and secti ons that l ist the major f eatures.
MPC555 member of the Motorola MPC500 RISC Microcontroller family.
T a ble 1. MPC555 Features
Device Flash Code Compression
MPC555 448 Kbytes Code compression not supported
MPC555
microcontroller, including a block
1 Introduction
The MPC555 device offers the following features:
• PowerPC™ core with floating-point unit
• 26 Kbytes fast RAM and 6 Kbytes TPU microcode RAM
• 448 Kbytes Flash EEPROM with 5-V programming
• 5-V I/O system
• Serial system: queued serial multi-channel module (QSMCM), dual CAN 2.0B
controller
modules (TouCAN
• 50-channel timer system: dual time processor units (TPU3), modular I/O system
(MIOS1)
• 32 analog inputs: dual queued analog-to-digital converters (QADC64)
• Submicron HCMOS (CDR1) technology
• 272-pin plastic ball grid array (PBGA) packaging
• 40-MHz operation, -40
for the suffix A device)
• 32-bit architecture (PowerPC ISA architec ture compliant)
• Core performance measured at 52.7-Kbyte Dhrystones (v2.1) @ 40 MHz
• Fully static, low power operation
• Integrated double-precision floating-point unit
• Precise exception model
TM
)
°C to 125 °C with dual supply (3.3 V, 5 V) (-55 °C to 125 °C
The
Block Diagram
• Extensive system development support
— On-chip watchpoints and breakpoints
— Program flow tracking
— BDM on-chip emulation development interface
1.1 Block Diagram
Figure 1 is a block diagram of the MPC555.
Burst
Interface
RCPU
16 Kbytes
SRAM
QADC QADC QSMCM
L-bus
256 Kbytes
Flash
10 Kbytes
SRAM
TouCAN
192 Kbytes
Flash
U-bus
E-bus
USIU
L2U
UIMB
IMB3
TPU3
DPTRAM
TPU3 TouCAN MIOS1
Figure 1. MPC555 B lock Diagram
1.2 Key Features
The MPC555 key features are explained in the following sections.
1.2.1 Four-Bank Memory Controller
• Works with SRAM, EPROM, Flash EEPROM, and other peripherals
• Byte write enables
• 32-bit address decodes with bit masks
2 MPC555 Product Brief MOTOROLA
1.2.2 U-Bus System Interface Unit (USIU)
• Clock synthesizer
• Power management
• Reset controller
• MPC555 decrementer and time base
• Real-time clock register
• Periodic interrupt timer
• Hardware bus monitor and software watchdog timer
• Interrupt controller that supports up to eight external and eight internal interrupts
• IEEE 1149.1 JTAG test access port
• External bus interface
— 24 address pins, 32 data pins
— Supports multiple master designs
— Four-beat transfer bursts, two-clock minimum bus transactions
— Supports 5V inputs, provides 3.3-V outputs
Key Features
1.2.3 Flexible Memory Protection Unit
• Four instruction regions and four data regions
• 4-Kbyte to 16-Mbyte region size support
• Default attributes available in one global entry
• Attribute support for speculative accesses
1.2.4 448-Kbyte Flash EEPROM Memory
• One 256-Kbyte and one 192-Kbyte module
• Page read mode
• Block (32-Kbyte) erasable
• External 4.75-V to 5.25-V program and erase power supply
1.2.5 26-Kbytes of Static RAM
• One 16-Kbyte and one 10-Kbyte module
• Fast (one-clock) access
• Keep-alive power
• Soft defect detection (SDD)
1.2.6 General-Purpose I/O Support
• Address (24) and data (32) pins can be used for general-purpose I/O in single-chip mode
• Nine general-purpose I/O pins in MIOS1 unit
• Many peripheral pins can be used for general-purpose I/O when not used for primary function
• 5-V tolerant inputs/outputs
MOTOROLA MPC555 Product Brief 3
Key Features
1.2.7 Two Time Processor Units (TPU3)
• Each TPU3 module provides these features:
— A dedicated micro-engine operates independently of the RCPU
— 16 independent programmable channels and pins
— Each channel has an event register consisting of a 16-bit capture register, a 16-bit compare
register and a 16-bit comparator
— Nine pre-programmed timer functions are available
— Any channel can perform any time function
— Each timer function can be assigned to more than one channel
— Two timer count registers with programmable prescalers
— Each channel can be synchronized to one or both counters
— Selectable channel priority levels
— 5-V tolerant inputs/outputs
• 6-Kbyte dual port TPU RAM (DPTRAM) is shared by the two TPU3 modules for TPU microcode
1.2.8 18-Channel Modular I/O System (MIOS1)
• Ten double action submodules (DASM)
• Eight dedicated PWM sub-modules (PWMSM)
• Two 16-bit modulus counter submodules (MCSM)
• Two parallel port I/O submodules (PIOSM)
• 5-V tolerant inputs/outputs
1.2.9 Two Queued Analog-to-Digital Converter Modules
(QADC64)
Each QADC provides:
• Up to 16 analog input channels, using internal multiplexing
• Up to 41 total input channels, using internal and external multiplexing
• 10-bit A/D converter with internal sample/hold
• Typical conversion time of 10 µs (100,000 samples per second)
• Two conversion command queues of variable length
• Automated queue modes initiated by:
— External edge trigger/level gate
— Softwar e command
• 64 result registers
• Output data that is right- or left-justified, signed or unsigned
• 5-V reference and range
4 MPC555 Product Brief MOTOROLA
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