Motorola MMDF2N06V1 Datasheet
DUAL TMOS MOSFET
3.3 AMPERES
60 VOLTS
R
DS(on)
= 0.115 OHM
Source–1
1
2
3
4
8
7
6
5
Top View
Gate–1
Source–2
Gate–2
Drain–1
Drain–1
Drain–2
Drain–2
D
S
G
CASE 751–05, Style 11
SO–8
TM
1
Motorola TMOS Power MOSFET Transistor Device Data
N–Channel Enhancement–Mode Silicon Gate
TMOS V is a new technology designed to achieve an on–resistance area product about one–half that of standard MOSFET s. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS E–FET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.
New Features of TMOS V
• On–resistance Area Product about One–half that of Standard
MOSFETs with New Low Voltage, Low R
DS(on)
Technology
• Faster Switching than E–FET Predecessors
Features Common to TMOS V and TMOS E–FETS
• Avalanche Energy Specified
• I
DSS
and V
DS(on)
Specified at Elevated Temperature
• Static Parameters are the Same for both TMOS V and TMOS E–FET
• Miniature SO–8 Surface Mount Package – Saves Board Space
• Mounting Information for SO–8 Package Provided
MAXIMUM RATINGS
(TJ = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain–to–Source Voltage V
DSS
60 Vdc
Drain–to–Gate Voltage, (RGS = 1 MΩ) V
DGR
60 Vdc
Gate–to–Source Voltage — Continuous V
GS
± 20 Vdc
Drain Current — Continuous @ TA = 25°C
Drain Current — Continuous @ TA = 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
I
D
I
D
I
DM
3.3
0.5
9.9
Adc
Apk
Total Power Dissipation @ TA = 25°C
(1)
P
D
2.0 W
Operating and Storage Temperature Range TJ, T
stg
–55 to 175 °C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 3.3 Apk, L = 10 mH, RG = 25 Ω)
E
AS
54 mJ
Thermal Resistance, Junction to Ambient
(1)
R
θJA
62.5 °C/W
Maximum Lead Temperature for Soldering Purposes, 0.0625″ from case for 10 seconds T
L
260 °C
DEVICE MARKING
2N06V
(1) Mounted on G10/FR4 glass epoxy board using minimum recommended footprint.
ORDERING INFORMATION
Device Reel Size Tape Width Quantity
MMDF2N06V1 7″ 12mm embossed tape 500
MMDF2N06V2 13″ 12mm embossed tape 2500
This document contains information on a new product. Specifications and information herein are subject to change without notice.
E–FET and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Order this document
by MMDF2N06V/D
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1996
MMDF2N06V
2
Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise noted)
Characteristic
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)
V
(BR)DSS
60
—
—
66
—
—
Vdc
mV/°C
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)
I
DSS
—
—
—
—
10
100
µAdc
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc) I
GSS
— — 100 nAdc
ON CHARACTERISTICS
(1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
V
GS(th)
2.0
—
2.8
5.8
4.0
—
Vdc
mV/°C
Static Drain–to–Source On–Resistance
(VGS = 10 Vdc, ID = 3.3 Adc)
R
DS(on)
— 0.106 0.115
Ohm
Drain–to–Source On–Voltage
(VGS = 10 Vdc, ID = 3.3 Adc)
(VGS = 10 Vdc, ID = 1.7 Adc, TJ = 150°C)
V
DS(on)
—
—
—
—
0.5
0.4
Vdc
Forward Transconductance (VDS = 15 Vdc, ID = 1.7 Adc) g
FS
4.0 7.0 — Mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
C
iss
— 370 520 pF
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
C
oss
— 110 150
Transfer Capacitance
f = 1.0 MHz)
C
rss
— 25 50
SWITCHING CHARACTERISTICS
(2)
Turn–On Delay Time
t
d(on)
— 9.0 20
ns
Rise Time
(VDD = 30 Vdc, ID = 3.3 Adc,
t
r
— 7.0 10
Turn–Off Delay Time
VGS = 10 Vdc,
RG = 9.1 Ω)
t
d(off)
— 34 70
Fall Time
G
= 9.1 Ω)
t
f
— 18 40
Gate Charge
Q
T
— 15 20 nC
(V
DS
= 48 Vdc, ID = 3.3 Adc,
Q
1
— 3.0 —
(VDS = 48 Vdc, ID = 3.3 Adc,
VGS = 10 Vdc)
Q
2
— 4.0 —
Q
3
— 5.0 —
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(1)
(IS = 3.3 Adc, VGS = 0 Vdc)
(IS = 3.3 Adc, VGS = 0 Vdc, TJ =
150°C)
V
SD
—
—
0.82
0.64
1.2
—
Vdc
Reverse Recovery Time
t
rr
— 39 —
ns
(I
S
= 3.3 Adc, VGS = 0 Vdc,
t
a
— 33 —
(IS = 3.3 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
t
b
— 6.0 —
Reverse Recovery Storage Charge Q
RR
— 0.075 — µC
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
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