motorola mmdf2n05 Datasets

Page 1

Motorola TMOS Power MOSFET Transistor Device Data

 

Medium Power Surface Mount Products

    !     

EZFETs are an advanced series of power MOSFETs which utilize Motorola’s High Cell Density TMOS p rocess and contain monolithic back–to–back zener diodes. These zener diodes provide protection against ESD and unexpected transients. These miniature surface mount MOSFETs feature ultra low R

DS(on)

and true logic level performance. They are capable of withstanding high energy i n the a valanche and c ommutation m odes a nd t he drain–to–source diode has a very low reverse recovery time. EZFET devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc–dc converters, and power management in portable a nd battery p owered p roducts such as c omputers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives.

• Dual N–Channel MOSFET in SO–8 Package with 1500 V ESD Level

• Ultra Low R

DS(on)

Provides Higher Efficiency and Extends Battery Life

• Logic Level Gate Drive — Can Be Driven by Logic ICs

• Miniature SO–8 Surface Mount Package — Saves Board Space

• Diode Is Characterized for Use In Bridge Circuits

• Diode Exhibits High Speed, With Soft Recovery

• I

DSS

Specified at Elevated Temperature

• Mounting Information for SO–8 Package Provided

MAXIMUM RATINGS

(TJ = 25°C unless otherwise noted)

Rating

Symbol Value Unit

Drain–to–Source Voltage V

DSS

50 Vdc

Drain–to–Gate Voltage (RGS = 1.0 MΩ) V

DGR

50 Vdc

Gate–to–Source Voltage — Continuous V

± 15 Vdc

Drain Current — Continuous @ TA = 25°C

Drain Current — Continuous @ TA = 70°C Drain Current — Single Pulse (tp ≤ 10 µs)

2.0

1.7

8.0

Adc

Apk

Total Power Dissipation @ TA = 25°C (1) P

2.0 Watts

Operating and Storage Temperature Range TJ, T

stg

– 55 to 150 °C

Thermal Resistance — Junction to Ambient R

θJA

62.5 °C/W

Maximum Temperature for Soldering Purposes T

260 °C

DEVICE MARKING

D2N05Z

ORDERING INFORMATION

Device Reel Size Tape Width Quantity

MMDF2N05ZR2 13″ 12 mm embossed tape 2500 units

(1) When mounted on G10/FR–4 glass epoxy board using minimum recommended footprint.

This document contains information on a new product. Specifications and information herein are subject to change without notice.

EZFET, HDTMOS and MiniMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. Thermal Clad is a trademark of the Bergquist Company.



SEMICONDUCTOR TECHNICAL DATA

Order this document

by MMDF2N05ZR2/D

 Motorola, Inc. 1996





DUAL TMOS

POWER MOSFET

2.0 AMPERES 50 VOLTS

DS(on)

= 0.300 OHM

CASE 751–05, Style 11

SO–8

Source–1

1 2 3 4

8 7 6 5

Top View

Gate–1

Source–2

Gate–2

Drain–1 Drain–1 Drain–2 Drain–2

Motorola Preferred Device

Preferred devices are Motorola recommended choices for future use and best overall value.

Page 2

MMDF2N05ZR2

Motorola TMOS Power MOSFET Transistor Device Data

ELECTRICAL CHARACTERISTICS

(TA = 25°C unless otherwise noted)

Characteristic

Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Drain–to–Source Breakdown Voltage (Cpk ≥ 2.0) (3)

(VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive)

(BR)DSS

50 —

56 55

— —

Vdc

mV/°C

Zero Gate Voltage Drain Current

(VDS = 15 Vdc, VGS = 0 Vdc) (VDS = 15 Vdc, VGS = 0 Vdc, TJ = 55°C)

DSS

— —

2.0 25

µAdc

Gate–Body Leakage Current (VGS = ± 15 Vdc, VDS = 0) I

GSS

— 0.14 0.5

ON CHARACTERISTICS

(1)

Gate Threshold Voltage (Cpk ≥ 2.0) (3)

(VDS = VGS, ID = 0.25 mAdc) Threshold Temperature Coefficient (Negative)

GS(th)

2.0 —

3.0

–5.0

4.0 —

Vdc

mV/°C

Static Drain–to–Source On–Resistance (Cpk ≥ 2.0) (3)

(VGS = 10 Vdc, ID = 1.5 Adc) (VGS = 5.0 Vdc, ID = 0.6 Adc)

DS(on)

— —

200 350

300 500

mΩ

Forward Transconductance

(VDS = 15 Vdc, ID = 2.5 Adc)

— 2.0 —

mMhos

DYNAMIC CHARACTERISTICS

Input Capacitance

iss

— 104 — pF

Output Capacitance

(VDS = 15 Vdc, VGS = 0 Vdc,

f = 1.0 MHz)

oss

— 58 —

Transfer Capacitance

f = 1.0 MHz)

rss

— 16 —

SWITCHING CHARACTERISTICS

(2)

Turn–On Delay Time

d(on)

— 24 48 ns

Rise Time

— 46 92

Turn–Off Delay Time

VGS = 10 Vdc,

RG = 25 Ω)

d(off)

— 130 260

Fall Time

= 25 Ω)

— 71 142

— 3.3 4.6 nC

(see figure 8)

= 25 Vdc, ID = 1.3 Adc,

— 0.7 —

(VDS = 25 Vdc, ID = 1.3 Adc,

VGS = 10 Vdc)

— 1.3 —

— 1.4 —

SOURCE–DRAIN DIODE CHARACTERISTICS

Forward On–Voltage

(IS = 2.0 Adc, VGS = 0 Vdc)

— 0.82 1.4

Vdc

— 66 —

(IS = 2.0 Adc, VGS = 0 Vdc,

/dt = 100 A/µs)

— 23 —

dIS/dt = 100 A/µs)

— 43 —

Reverse Recovery Storage Charge Q

— 0.08 — µC

(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%. (2) Switching characteristics are independent of operating junction temperature.

Gate Charge

Reverse Recovery Time

(VDD = 30 Vdc, ID = 0.6 Adc,

Page 3

MMDF2N05ZR2

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

DSS

, LEAKAGE (nA) R

DS(on)

, DRAIN–TO–SOURCE RESISTANCE (OHMS)

DS(on)

, DRAIN–TO–SOURCE RESISTANCE (OHMS)

0 0.4 0.8 1.2 1.6 2

0.5

1.5

VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 1. On–Region Characteristics

, DRAIN CURRENT (AMPS)

VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics

0.8

1.0

1.2

0.05

Figure 3. On–Resistance versus

Gate–to–Source Voltage

ID, DRAIN CURRENT (AMPS)

Figure 4. On–Resistance versus Drain Current

and Gate Voltage

100

Figure 5. On–Resistance Variation

with Temperature

VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 6. Drain–to–Source Leakage Current

versus Voltage

VDS ≥ 10 V

TJ = 25

TJ = –55°C

25°C

100°C

0.6

0.2

TJ = 25°C

2.5

0.5

52.5 3 3.5 4

0.4

0.65

0 0.5 1 2.5 3

0 5 10 15 30

3.9 V

20 25

0.25

0.45

1.5

5.5 6 6.5 87 7.5 9 10 VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)

1.5 2

10 V

VGS = 5.0 V

TJ = 25°C

DS(on)

, DRAIN–TO–SOURCE RESISTANCE (NORMALIZED)

TJ, JUNCTION TEMPERATURE (°C)

–50 0 50 100 150

0.5

1.0

1.5

2.0 VGS = 10 V

ID = 1 A

1257525–25

VGS = 0 V

TJ = 125°C

100°C

0.2 0.6

1.81.41

2.5

4.3 V

5.0 V

5.5 V

6.0 V

6.5 V7 V

VGS = 10 V

ID = 1.5 A TJ = 25

3.5

4.5 5.5 6 6.5

8.5 9.5 3.5 4

0.1

0.01 35 40 45 50

25°C

Page 4

MMDF2N05ZR2

Motorola TMOS Power MOSFET Transistor Device Data

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged by current from the generator.

The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies greatly with applied voltage. Accordingly , gate charge data is used. In most cases, a satisfactory estimate of average input current (I

G(AV)

) can be made from a rudimentary analysis of

the drive circuit so that t = Q/I

G(AV)

During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, V

SGP

. Therefore, rise and fall times may

be approximated by the following: tr = Q2 x RG/(VGG – V

GSP

)

tf = Q2 x RG/V

GSP

where VGG = the gate drive voltage, which varies from zero to V

RG = the gate drive resistance and Q2 and V

GSP

are read from the gate charge curve.

During the turn–on and turn–off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are:

d(on)

= RG C

iss

In [VGG/(VGG – V

GSP

)]

d(off)

= RG C

iss

In (VGG/V

GSP

)

The capacitance (C

iss

) is read from the capacitance curve at a voltage corresponding to the off–state condition when calculating t

d(on)

and is read at a voltage corresponding to the

on–state when calculating t

d(off)

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The M OSFET output capacitance also complicates t he mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified.

The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

Figure 7. Capacitance Variation

C, CAPACITANCE (pF)

VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

10 0 10 15 25

TJ = 25

°C

VDS = 0 V

VGS = 0 V

150

100

iss

oss

rss

5 5

iss

rss

250

200

Page 5

MMDF2N05ZR2

Motorola TMOS Power MOSFET Transistor Device Data

Figure 8. Gate–To–Source and Drain–To–Source

Voltage versus Total Charge

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

, GATE–TO–SOURCE VOLTAGE (VOLTS)

Qg, TOTAL GATE CHARGE (nC)

0 0.5 1 1.5

ID = 1.3 A TJ = 25

2 4

, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

t, TIME (ns)

RG, GATE RESISTANCE (OHMS)

1 10010

VGS = 10 V TJ = 25

d(on)

1000

100

d(off)

2.5 3 3.5

DRAIN–TO–SOURCE DIODE CHARACTERISTICS

The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI.

System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 11. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses.

The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by high

di/dts. The diode’s negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy.

Compared to Motorola standard cell density low voltage MOSFETs, high c ell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.

0.5 0.55 0.6 0.85

1.75

VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

, SOURCE CURRENT (AMPS)

VGS = 0 V TJ = 25

0.65 0.7

1.5

1.25

0.75

0.5

0.25

0.75 0.8

Page 6

MMDF2N05ZR2

Motorola TMOS Power MOSFET Transistor Device Data

, SOURCE CURRENT

t, TIME

Figure 11. Reverse Recovery Time (trr)

di/dt = 300 A/µs

Standard Cell Density

High Cell Density

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define the maximum s imultaneous drain–to–source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance – General Data and Its Use.”

Switching between the off–state and the on–state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (V

DSS

) is exceeded, and that the transition

time (tr, tf) does not exceed 10 µs. In addition the total power

averaged over a complete switching cycle must not exceed (T

J(MAX)

– TC)/(R

θJC

A power MOSFET designated E–FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non–linearly with an increase of peak current in avalanche and peak junction temperature.

Figure 12. Maximum Rated Forward Biased

Safe Operating Area

0.1 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

, DRAIN CURRENT (AMPS)

DS(on)

LIMIT THERMAL LIMIT PACKAGE LIMIT

0.01

VGS = 20 V SINGLE PULSE

TC = 25

0.1

10 ms

100

1 ms

Page 7

MMDF2N05ZR2

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

Figure 13. Thermal Response

Figure 14. Diode Reverse Recovery Waveform

di/dt

0.25 I

TIME

t, TIME (s)

Rthja(t), EFFECTIVE TRANSIENT

THERMAL RESISTANCE

0.1

0.01

D = 0.5

SINGLE PULSE

1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01

0.2

0.1

0.05

0.02

0.01

1.0E+02 1.0E+03

0.001

0.0106 Ω0.0431 Ω0.1643 Ω0.3507 Ω0.4302

Ω

177.14 F2.9468 F0.5064 F0.1406 F0.0253 F

Chip

Ambient

Dual SO–8 Thermal RC Network

Page 8

MMDF2N05ZR2

Motorola TMOS Power MOSFET Transistor Device Data

INFORMATION FOR USING THE SO–8 SURFACE MOUNT PACKAGE

MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface

between the board and the package. With the correct pad geometry, the packages will self–align when subjected to a solder reflow process.

inches

0.060

1.52

0.275

7.0

0.024

0.6

0.050

1.270

0.155

4.0

SO–8 POWER DISSIPATION

The power dissipation of the SO–8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by T

J(max)

, the maximum rated junction

temperature of the die, R

θJA

, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO–8 package, PD can be calculated as follows:

PD =

J(max)

– T

θJA

The values for the equation are found in the maximum

ratings table on the data sheet. Substituting these values into

the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device which in this case is 2.0 Watts.

= 2.0 Watts

The 62.5°C/W for the SO–8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS

The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected.

• Always preheat the device.

• The delta temperature between the preheat and soldering

should be 100°C or less.*

• When preheating and soldering, the temperature of the

leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C.

• The soldering temperature and time shall not exceed

260°C for more than 10 seconds.

• When shifting from preheating to soldering, the maximum

temperature gradient shall be 5°C or less.

• After soldering has been completed, the device should be

allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress.

• Mechanical stress or shock should not be applied during

cooling.

* Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.

150°C – 25°C

PD =

62.5°C/W

Page 9

MMDF2N05ZR2

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL SOLDER HEATING PROFILE

For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. T aken together , these control settings make up a heating “profile” for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 12 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The

line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177–189°C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.

STEP 1

PREHEAT

ZONE 1 “RAMP”

STEP 2

VENT

“SOAK”

STEP 3

HEATING

ZONES 2 & 5

“RAMP”

STEP 4

HEATING

ZONES 3 & 6

“SOAK”

STEP 5

HEATING

ZONES 4 & 7

“SPIKE”

STEP 6

VENT

STEP 7

COOLING

200

150

100

TIME (3 TO 7 MINUTES TOTAL)

MAX

SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)

205

TO 219°C PEAK AT SOLDER JOINT

DESIRED CURVE FOR LOW MASS ASSEMBLIES

100°C

150°C

160

170°C

140

Figure 15. Typical Solder Heating Profile

DESIRED CURVE FOR HIGH MASS ASSEMBLIES

Page 10

MMDF2N05ZR2

Motorola TMOS Power MOSFET Transistor Device Data

PACKAGE DIMENSIONS

CASE 751–05

SO–8

ISSUE M

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

STYLE 11:

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. DRAIN 2

7. DRAIN 1

8. DRAIN 1

SEATING PLANE

1 4

4X P

A0.25 (0.010)MT B

S S

0.25 (0.010)MB

8X D

X 45

–A–

–B–

–T–

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 4.80 5.00 0.189 0.196 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.18 0.25 0.007 0.009 K 0.10 0.25 0.004 0.009 M 0 7 0 7 P 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019

__ __

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters can and do vary in different applications. All operating parameters, including “T ypicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

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MFAX: [email protected] – TOUCHTONE (602) 244–6609 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, INTERNET: http://Design–NET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298

MMDF2N05ZR2/D

*MMDF2N05ZR2/D*

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