Motorola MCP750HA, MCP750HA-1252-F, MCP750HA-1232-F, MCP750HA-233-F, MCP750HA-366-F Installation And Use Manual

...

Download

MCP750HA Hot Swap CompactPCI

Single Board Computer

Installation and Use

MCP750HA/IH3

December 2000

Printed in the United States of America.

Motorola

and the Motorola symbol are registered trademarks of Motorola, Inc.

PowerPC™isatrademarkofIBM Corporation,andisusedby Motorola, Inc. underlicense from IBM Corporation.

CompactPCI is a registered trademark of PCI Industrial Computer Manufacturers Group. All other products mentioned in this document are trademarks or registered trademarks of

their respective holders.

Safety Summary

The following general safety precautions must be observed during all phases of operation, service, and repair of this equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual could result in personal injury or damage to the equipment.

The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You, as the user of the product, should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment.

Ground the Instrument.

To minimize s hock hazard, the equipment chassis and enclosure must be connected to an electrical ground. If the equipment is supplied with a three-conductor AC power cable, the power cable must be plugged into an approved three-contact electrical outlet, with the grounding wire (green/yellow) reliably connected to an electrical ground (safety ground) at the power outlet. The power jack and mating plug of the power cable meet International Electrotechnical Commission (IEC) safety standards and local electrical regulatory codes.

Do Not Operate in an Explosive Atmosphere.

Do not operate the equipment in any explosive atmosphere such as in the presence o f flammable gases or fumes. Operation of any electrical equipment in such an environment could result in an explosion and cause injury or damage.

Keep Away From Live Circuits Inside the Equipment.

Operating personnel must not remove equipment covers. Only Factory Authorized Service Personnel or other qualifiedservice personnel may remove equipment covers for internal subassemblyor component replacementor any internal adjustment. Service personnel should not replace components with power cable connected. Under certain conditions, dangerous voltages may exist even with the power cable removed. To avoid injuries, such personnel should always disconnect power and discharge circuits before touching components.

Use Caution Whe n Exposing or Handling a CRT.

Breakage of a Cathode-Ray Tube (CRT) causes a high-velocity scattering of glass fragments (implosion). To prevent CRT implosion, do not handle the CRT and avoid rough handling or jarring of the equipment. Handling of a CRT should be done only by qualified service personnel using approved safety mask and gloves.

Do Not Substitute Parts or Modify Equipment.

Do not install substitute parts or perform any unauthorized modification of the equipment. Contact your local Motorola representative for service and repair to ensure that all safety features are maintained.

Observe Warnings in Manual.

Warnings, such as the example below, precede potentially dangerous procedures throughout this manual. Instructions contained in the warnings must be followed. You should also employ all other safety precautions which you deem necessary for the operation of the equipment in your operating environment.

To prevent serious injury or death from dangerous voltages, use extreme caution when handling, testing, and adjusting this equipment and its

Warning

components.

Flammability

All Motorola PWBs (printed wiring boards) are manufactured with a flammability rating of 94V-0 by UL-recognized manufacturers.

EMI Caution

This equipment generates, uses and can radiate electromagneticenergy. It

Caution

This product contains a lithium battery to power the clock and calendar circuitry.

Caution

may cause or be susceptible to electromagnetic interference (EMI) if not installed and used with adequate EMI protection.

Lithium Battery Caution

Dangerof explosionif battery is replaced incorrectly.Replace batteryonly with the same or equivalent type recommended by the equipment manufacturer. Dispose of used batteries according to the manufacturer’s instructions.

Attention

Vorsicht

Il y a danger d’explosion s’il y a remplacement incorrect de la batterie. Remplacer uniquement avec une batterie du même type ou d’un type équivalent recommandé par le constructeur. Mettre au rebut les batteries usagées conformément aux instructions du fabricant.

Explosionsgefahr bei unsachgemäßem Austausch der Batterie. Ersatz nur durch denselben oder einen vom Herstellerempfohlenen Typ. Entsorgung gebrauchter Batterien nach Angaben des Herstellers.

CE Notice (European Community)

This is a Class A product. In a domestic environment, this product may

Warning

MotorolaC omputer Group products with the CE marking comply with the EMC Directive (89/336/EEC). Compliance with this directive implies conformity to the following European Norms:

EN55022 “Limits and Methods of Measurement of Radio Interference Characteristics of Information Technology Equipment”; this product tested t o Equipment Class A

EN50082-1:1997 “Electromagnetic Compatibility—GenericImmunity Standard, Part

1. Residential, Commercial and Light Industry”

System products also fulfill EN60950 (product safety) which is essentiallythe requirement for the Low Voltage Directive (73/23/EEC).

Board products are t ested in a representative system to show compliance with the above mentioned requirements. A proper installation in a CE-marked system will maintain the required EMC/safety performance.

cause radio interference, in which case the user may be required to take adequate measures.

In accordance with European Community directives, a “Declaration of Conformity” has been made and is on file within the European Union. The “Declaration of Conformity” is available on request. Please contact your sales representative.

Notice

While reasonable efforts have been made to assure the accuracy of this document, Motorola,Inc. assumes no liability resulting from any omissionsin this document, or from the use of the information obtained therein. Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes.

Electronic versions of this material may be read online, downloaded for personal use, or referenced in another document as a URL to the Motorola Computer Group website. The textitself may not be published commercially in print or electronicform, edited, t ranslated, or otherwise altered without the permission of Motorola, Inc.

It is possible that this publication may contain reference to or information about Motorola products(machines and programs),programming, or services that are not availablein your country. Such references or information must not be construed to mean that Motorola intends to announce such Motorola products, programming, or services in your country.

Limited and Restricted Rights Legend

If the documentation contained herein is supplied, directly or indirectly, to the U.S. Government, the following notice shall apply unless otherwise agreed to in writing by Motorola, Inc.

Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (b)(3) of the Rights in TechnicalData clause at DFARS 252.227-7013 (Nov.

1995) and of the Rights in Noncommercial Computer Software and Documentation clause at DFARS 252.227-7014 (Jun. 1995).

Motorola, Inc. Computer Group 2900 South Diablo Way Tempe, Arizona 85282

Contents

About This Manual

Summary of Changes................................................................................................xvii

Overview of Contents ..............................................................................................xviii

Comments and Suggestions.......................................................................................xix

Conventions Used in This Manual.............................................................................xix

CHAPTER 1 Hardware Preparation and Installation

Introduction ................................................................................................................1-1

Equipment Required ..................................................................................................1-3

Overview of Start-up Procedure ................................................................................1-4

Unpacking Instructions ..............................................................................................1-5

Hardware Configuration ............................................................................................1-6

MCP750HA Base B oard Preparation ........................................................................1-6

Flash Bank Selection (J9) ...................................................................................1-6

Hardware Installation ..........................................................................................1-9

ESD Precautions .................................................................................................1-9

Compact FLASH Memory Card Installation.............................................................1-9

RAM300 Memory Mezzanine Installation ..............................................................1-11

PMC Module Installation.........................................................................................1-13

MCP750HA Module Installation.............................................................................1-15

System Considerations.............................................................................................1-18

MCP750HA Module Power Requirements .............................................................1-18

CHAPTER 2 Operating Instructions

Introduction ................................................................................................................2-1

Applying Power .........................................................................................................2-1

Memory Maps............................................................................................................2-2

Processor Memory Map......................................................................................2-3

Default Processor Memory Map..................................................................2-3

PCI Local Bus Memory Map..............................................................................2-4

CompactPCI Memory Map.................................................................................2-5

PCI Arbitration ...................................................................................................2-5

Interrupt Handling...............................................................................................2-6

vii

DMA Channels...................................................................................................2-7

Sources of Reset.................................................................................................2-7

Endian Issues......................................................................................................2-8

Processor/Memory Domain ........................................................................2-9

Role of the Raven ASIC..............................................................................2-9

PCI Domain.................................................................................................2-9

PCI and Ethernet .........................................................................................2-9

CHAPTER 3 Functional Description

Introduction ...............................................................................................................3-1

Features......................................................................................................................3-1

General Description...................................................................................................3-2

Block Diagram...........................................................................................................3-4

Hot Swap Circuitry.............................................................................................3-5

CompactPCI Interface........................................................................................3-5

PCI Expansion Connector (J4)...........................................................................3-6

Domain Ownership.............................................................................................3-7

Ethernet Interface ...............................................................................................3-8

PCI Mezzanine Interface....................................................................................3-9

PC97307 ISA Super I/O Device.......................................................................3-10

Asynchronous Serial Ports ........................................................................3-10

Parallel Port/Printer Interface....................................................................3-11

Floppy Disk/Tape Drive Controller ..........................................................3-11

Keyboard and Mouse Interface .................................................................3-12

PCI Peripheral Bus Controller (PBC) ..............................................................3-12

EIDE Series Termination..................................................................................3-13

Real-Time Clock/NVRAM/Watchdog Timer Function ...................................3-13

Programmable Timers......................................................................................3-14

Raven General Purpose Timers.................................................................3-14

Raven Watchdog Timers...........................................................................3-15

M48T559 Watchdog Timer.......................................................................3-15

Interval Timers..........................................................................................3-15

16-Bit Timers ............................................................................................3-16

Serial Communications Interface .....................................................................3-16

Z8536 CIO Device ....................................................................................3-17

MCP750HA Board Identifier ...........................................................................3-17

Base Module Feature Register .........................................................................3-18

Serial Port Signal Multiplexing........................................................................ 3-19

Signal Multiplexing (MX).........................................................................3-19

ABORT(ABT) Switch (S2).............................................................................. 3-21

viii

RESET(RST) Switch (S1)................................................................................3-21

Reset and Abort Header (J21)...........................................................................3-22

Front Panel Indicators (DS1 - DS4)..................................................................3-22

Fuses and Polyswitches (Resettable Fuses)......................................................3-23

Speaker Control ................................................................................................3-23

MPC750 Processor ...........................................................................................3-24

Flash Memory............................................................................................3-24

RAM300 Memory Module ...............................................................................3-25

Compact FLASH Memory Card.......................................................................3-25

TMCP700 Transition Module...........................................................................3-25

Serial Interface Modules............................................................................3-26

CHAPTER 4 Connector Pin Assignments

MCP750HA Connectors............................................................................................4-1

Common Connectors .................................................................................................4-1

CompactPCI Connectors (J1/J 2).........................................................................4-2

CompactPCI HSC/User I/O Connector (J3).......................................................4-4

Local Bus Expansion Connector (J4) .................................................................4-5

User I/O Connector (J5)......................................................................................4-6

PCI Mezzanine Card Connectors ( J 11/J12/J13/J14)...........................................4-7

Front USB Connectors (J17/J18)......................................................................4-10

10BaseT/100BaseTX Connector (J8) ...............................................................4-10

COM1 Connector (J15) ....................................................................................4-11

Reset and Abort Header (J21)...........................................................................4-12

Debug Connector (J16).....................................................................................4-12

DRAM Mezzanine Connector (J7)...................................................................4-16

EIDE Compact FLASH Connector (J20) .........................................................4-19

CHAPTER 5 PPCBug

PPCBug Overview.....................................................................................................5-1

PPCBug Basics ..........................................................................................................5-1

Memory Requirements .......................................................................................5-3

PPCBug Implementation ....................................................................................5-3

MPU, Hardware, and Firmware Initialization ...........................................................5-3

Using PPCBug ...........................................................................................................5-6

Debugger Commands .........................................................................................5-7

Standard Commands....................................................................................5-7

High Availability Commands....................................................................5-11

Unsupported Commands ...........................................................................5-11

Debugger System Call Interfaces.....................................................................5-12

High Availability System Call Interfaces .................................................5-12

Unsupported System Call Interfaces.........................................................5-12

Bug Diagnostics .......................................................................................................5-13

Diagnostic Tests................................................................................................5-14

High Availability Diagnostic Commands .................................................5-15

Unsupported PPCBug Diagnostic Commands..........................................5-16

CHAPTER 6 CNFG and ENV Commands

Overview ...................................................................................................................6-1

CNFG - Configure Board Information Block............................................................6-1

ENV - Set Environment.............................................................................................6-2

Configuring the PPCBug Parameters.................................................................6 -3

APPENDIX A Specifications

Specifications............................................................................................................A-1

Cooling Requirements..............................................................................................A-2

EMC Compliance .....................................................................................................A-2

APPENDIX B Hardware Preparation and Installation for TMCP700

Introduction .............................................................................................................. B-1

Unpacking Instructions............................................................................................. B-1

TMCP700 Transition Module Preparation...............................................................B-1

Serial Ports 1 and 2............................................................................................B-4

Configuration of Serial Ports 3 and 4................................................................ B-4

ESD Precautions................................................................................................ B-9

TMCP700 Transition Module Installation................................................................B-9

TMCP700 Transition Module..................................................................................B-11

CompactPCI Connectors (J3/J 4/J5).................................................................B-12

Serial Ports 1 and 2 (J10/J11) (TMCP700 I/O Mode).....................................B-12

Serial Ports 3 and 4 (J6/J24) (TMCP700 I/O Mode)....................................... B-13

Parallel Connector (J7) (TMCP700 I/O Mode) ............................................... B-14

Keyboard/Mouse Connector (J16) (TMCP700 I/O Mode).............................B-15

USB Connectors (J18/J19) (Optional TMCP700 I/O Mode)..........................B-15

EIDE Connector (J15)..................................................................................... B-16

Floppy Port C onnector (J17)...........................................................................B-17

+5VDC Power Connector (J14) ...................................................................... B-17

Speaker Output Connector (J13)..................................................................... B-18

PMC I/O Connectors (J2/J21)..........................................................................B-18

APPENDIX C Related Documentation

Motorola Computer Group Documents ....................................................................C-1

Manufacturers’ Documents.......................................................................................C-2

Related Specifications...............................................................................................C-3

List of Figures

Figure 1-1. MCP750HA Base Board Block Diagram................................................1-2

Figure 1-2. MCP750HA Switches, Headers, Connectors, and LEDs........................1-8

Figure 1-3. Compact FLASH Placement on MCP750HA.......................................1-10

Figure 1-4. RAM300 Placement on MCP750HA....................................................1-12

Figure 1-5. PMC Module Placement on MCP750HA.............................................1-14

Figure 1-6. MCP750HA Board Insertion Sequence ................................................1-17

Figure 2-1. PPCBug System Startup..........................................................................2-2

Figure 3-1. MCP750HA Block Diagram...................................................................3-4

Figure 3-2. Active/Passive System ............................................................................3-7

Figure 3-3. Serial Port Signal Multiplexing.............................................................3-19

Figure 3-4. MX Signal Timings...............................................................................3-21

xiii

List of T ables

Table 1-1. Startup Overview ......................................................................................1-4

Table 2-1. Processor Default View of the Memory Map...........................................2-3

Table 2-2. PBC DMA Channel Assignments.............................................................2-7

Table 2-3. Classes of Reset and Effectiveness...........................................................2-8

Table 3-1. MCP750HA Features ................................................................................3-1

Table 3-2. Series Termination for Ultra DMA EIDE...............................................3-13

Table 3-3. Old CPU Configuration Register............................................................3-17

Table 3-4. Base Module Status Register ..................................................................3-18

Table 3-5. Multiplexing Sequence of the MX Function ..........................................3-20

Table 3-6. Fuse Assignments ...................................................................................3-23

Table 3-7. SIM Type Identification..........................................................................3-26

Table 4-1. CompactPCI Connector J1........................................................................4-2

Table 4-2. CompactPCI Connector J2........................................................................4-3

Table 4-3. J3 User I/O Connector ..............................................................................4-4

Table 4-4. J4 Local PCI Expansion Connector..........................................................4-5

Table 4-5. J5 User I/O Connector ..............................................................................4-6

Table 4-6. PCI Mezzanine Card Connector ...............................................................4-7

Table 4-7. PCI Mezzanine Card Connector ...............................................................4-9

Table 4-8. USB 0 Connector J18 .............................................................................4-10

Table 4-9. USB 1 Connector J17 .............................................................................4-10

Table 4-10. 10BaseT/100BaseTX Connector J8......................................................4-11

Table 4-11. COM1 Connector J15 ...........................................................................4-11

Table 4-12. Reset/Abort Header J21 ........................................................................4-12

Table 4-13. Debug Connector (J16).........................................................................4-12

Table 4-14. DRAM Mezzanine Connector (J7).......................................................4-16

Table 4-15. EIDE Compact FLASH Connector J20 ................................................4-19

Table 5-1. Debugger Commands ...............................................................................5-7

Table 5-2. High Availability Specific Debugger Commands...................................5-11

Table 5-3. Unsupported Debugger Commands........................................................5-11

Table 5-4. High Availability Specific Debugger System Calls................................5-12

Table 5-5. Unsupported Debugger System Calls.....................................................5-13

Table 5-6. Specific Diagnostic Test Groups.............................................................5-14

Table 5-7. PPCBug Diagnostic Commands For High Availability Systems ...........5-15

Table 5-8. Unsupported PPCBug Diagnostic Commands .......................................5-16

Table A-1. MCP750HA Specifications ...................................................................A-1

Table B-1. Serial Connections - Ports 1 and 2 (J10 and J11) (TMCP700) ........... B-12

Table B-2. Serial Connections - Ports 3 and 4 (J6 and J24) (TMCP700) ............. B-13

Table B-3. Parallel Connector J7 (TMCP700) ...................................................... B-14

Table B-4. Keyboard/Mouse Connector J16 (TMCP700) ..................................... B-15

Table B-5. EIDE Connector (J15) ......................................................................... B-16

Table B-6. Floppy Connector (J17) ....................................................................... B-17

Table B-7. +5Vdc Power Connector (J14) ............................................................ B-18

Table B-8. Speaker Output Connector (J13) ......................................................... B-18

Table B-9. PMC I/O Connector (J2) ..................................................................... B-18

Table B-10. PMC I/O Connector (J21) ................................................................. B-20

Table C-1. Motorola Computer Group Documents .................................................C-1

Table C-2. Manufacturer’s Documents ................................................................... C-2

Table C-3. Related Specifications ........................................................................... C-3

xvi

About This Manual

This manual provides general product information; hardware preparation, installation,and operating instructions along with a functional description of the MCP750HA series Single Board Computers (SBCs). These SBCs are used in conjunction with the Motorola CPX8000, CPX2000, and CPX1000 series systems.

Currently, the boards are available in the following configurations:

Model Number Description

MCP750HA-1232-F MPC750-233 MHz CPU, 32MB ECC DRAM, 9MB FLASH, MB L2

Cache

MCP750HA-1242-F MPC750-233 MHz CPU, 64MB ECC DRAM, 9MB FLASH, 1MB L2

Cache

MCP750HA-1252-F MPC750-233 MHz CPU, 128MB ECC DRAM, 9MB FLASH, 1MB L2

Cache

MCP750HA-1262-F MPC750-233 MHz CPU, 256MB ECC DRAM, 9MB FLASH, 1MB L2

Cache MCP750HA-233-F MPC750-366 MHz CPU, NO DRAM, 5MB FLASH, 1MB L2 Cache MCP750HA-366-F MPC750HA-366 MHz CPU MCP750HA-366-K MPC750HA-366 MHz CPU KIT

Summary of Changes

The following table shows changes made to this manual since its last release.

Date Changes

December 2000 Information on the Watchdog timer status added to page 6-8 December 2000 Information on the Network Boot Controller removed from page 6-8. December 2000 I nformation and examples concerning claim domain A and B added to

page 6-11.

December 2000 Information and examples concerning firmware command buffer added

to page 6-13.

xvii

Overview of Contents

This section outlines the contents of each chapter.

Chapter 1, Hardware Preparation and Installation, outlines the hardware

preparation and installation procedures for the MCP750HA series Single Board Computers.

Chapter 2, Operating Instructions, provides information applicable to the

MCP750HA family of Single Board Computers in a system configuration. This includes the power-up procedure along with descriptions of the switches and LEDs, memory maps, and software initialization.

Chapter 3, Functional Description, describes the MCP750HA single-

board computer on a block diagram level.

Chapter 4, Connector Pin Assignments, summarizes the pin assignments

for the following groups of connectors and headers for the MCP750HA.

Chapter 5, PPCBug, provides information on the PPCBug and its

architecture. Additionally, it describes the monitor (interactive command portion of the firmware), and provides instructions on using the PPCBug debugger and the associated special commands. A complete list of PPCBug commands is also included in this chapter.

xviii

Chapter 6, CNFG and ENV Commands, outlines how to use the factory-

installeddebug monitor, PPCBug, to modify certain parameters contained in the PowerPC board's Non-Volatile RAM (NVRAM), also known as Battery Backed-up RAM (BBRAM).

Appendix A, Specifications, lists the general specifications for

MCP750HAbase boards. Subsequentsectionsdetail cooling requirements and FCC compliance.

Appendix B, Hardware Preparation and Installation for TMCP700,

provides hardware preparation and installation instructions, as well as Pin Assignment information for the TMCP700 Transition Module.

Appendix C, Related Documentation, lists related Motorola Computer

Group Documents, Manufacturer’s Documents, related Specifications, and how to obtain Motorola Computer Group literature.

Comments and Suggestions

Motorolawelcomes and appreciates your comments on its documentation. We want to know what you think about our manuals and how we can make them better. Mail comments to:

Motorola Computer Group Reader Comments DW164 2900 S. Diablo Way Tempe, Arizona 85282

You can also submit comments to the following e-mail address:

reader-comments@mcg.mot.com

In all your correspondence, please list your name, position, and company. Be sure to include the title and part number of the manual and tell how you used it. Then tell us your feelings about its strengths and weaknesses and any recommendations for improvements.

Conventions Used in This Manual

The following typographical conventions are used in this document:

bold

is used for user input that you type just as it appears; it is also used for commands, options and arguments to commands, and names of programs, directories and files.

italic

is used for names of variablesto which you assign values. Italic is also used for comments in screen displays and examples, and to introduce new terms.

courier

is used for system output (for example, screen displays, reports), examples, and system prompts.

xix

<CR> represents the carriage return or Enter key.

CTRL

representsthe Control key.Execute control characters by pressing the Ctrl key and the letter simultaneously, for example, Ctrl-d.

1Hardware Preparation and

Introduction

Note The MCP750HA is identified as a CPX750HA in some chassis

The term MCP750HA is used throughout this document to refer to all models of the MCP750HA or CPX750HA CPU based boards that employ hot swap capabilities. Refer to the table on page xvii in the About This

Manual section for a complete list of model numbers.

Installation

and firmware documentation for packaging and ordering purposes, but both numbers apply to the same board.

The MCP750HA is a single-slot Hot Swappable CompactPCI board equipped with a PowerPC™ Series microprocessor. The board can be purchased in a standard (MCP750) or Hot Swap capable (MCP750HA) version with 32MB, 64MB, 128MB, or 256MB of ECC DRAM.

The complete MCP750HA consists of the base (main) board plus an:

❏ ECC DRAM module (RAM300) for memory (shipped with the

board) and an

❏ Optional PCI Mezzanine Card (PMC) for additional versatility

The diagram in Figure 1-1 illustrates the architecture of the MCP750HA base board.

1-1

Hardware Preparation and Installation

L2 Cache

Processor

MPC750

32/64-bit PMC Slot

DEC21140

Ethernet

Serial

USB

Front Panel

PMC SLot

Ethernet

Debug Connector

Falcon Chipset

66 MHz PPC750 Processor Bus

33MHz 32/64-bit PCI Local Bus

SROM

AT24C04

10BT/

100BTx

USB 0

USB 1

Super I/O

PC97307

KEYBOARD

SERIAL

MOUSE

PARALLEL

FLOPPY DISK

User I/O J3 & J5 CompactPCI J1/J2

MK48T559

(8MB Linear Flash, up to 256MB of DRAM)

Memory

Controller

PCI Bridge

&MPIC

Raven ASIC

PBC

VT82C586B

ISA

Registers

NVRAM/

WD/ RTC

ESCC

Z85230

Compact

FLASH

2 SYNC/ASYNC

Flash/DRAM Expansion

IDE

ISA

CIO

z8536

FLASH

System

Registers

Clock

Generator

Reset

Control

Arbitration

Control

PCI-PCI BRIDGE

DEC21154

33 MHz 32/64-bit PCI Bus

32/64-bit Compact PCI Bus

HA Ver. Hot

Swap Control

Figure 1-1. MCP750HA Base Board Block Diagram

1-2 Computer Group Literature Center Web Site

Equipment Required

The following equipment is required to complete an MCP750HA system:

❏ CompactPCI system enclosure ❏ System console terminal ❏ Operating system (and/or application software) ❏ Disk drives (and/or other I/O) and controllers ❏ Transition module (TMCP700) and connecting cables (optional) ❏ HSC/Bridge Module (High Availability Chassis only)

MCP750HA modules are factory configured for I/O handling via a TMCP700 transition module. There are various MCP750HA models available that correspond to different memory configurations and processorspeeds. One transition module supports all configurations of the board.

Equipment Required

Note Contact your local Motorola sales representative and/or your

designated sales/systems engineer or distributor for the latest configuration specifications on the various MCP750HA models available.

Refer also to the appropriate sections on the MCP750HA and transition module installation for additional information.

http://www.motorola.com/computer/literature 1-3

Hardware Preparation and Installation

Overview of Start-up Procedure

The following table lists the tasks that you will need to perform before using this board. It also informs you where to find the information you need to perform each step. Be sure to read this entire chapter (including all caution and warning notes) before you begin.

Table 1-1. Startup Overview

Task Section or Manual Reference

Unpack the hardware. Unpacking Instructions Configure the hardware by

setting jumpers on the boards and transition modules.

Ensure CompactFLASH card is installed (if required).

Ensure memory mezzanines areproperlyinstalledonthe board

Install PMC Module (if required)

Install the MCP750HA in the chassis

Install transition module into chassis

Install HSC/Bridge Modules, Peripherals, and any other devices or equipment used

Power up the system Applying Power

MCP750HA Base Board Preparation and TMCP700 Transition Module Preparation

Compact FLASH Memory Card Installation

RAM300 Memory Mezzanine Installation

PMC Module Installation

MCP750HA Module Installation

TMCP700 Transition Module Installation

(optional) Refer to Appendix C, Related Documentation,

for documentation on the specific chassis in use (for example, CPX2108/2208, or CPX2000, or CPX8216 and 8216T).

1-4 Computer Group Literature Center Web Site

Table 1-1. Startup Overview (Continued)

Task Section or Manual Reference

Note that the debugger initializes the MCP750HA

Initialize the system clock. Using PPCBug

Examine and/or change environmental parameters.

Program the board as needed for your applications.

Using PPCBug

Note:YoumayalsowishtoobtainthePPCBug Firmware Package User’s Manual and the CPX750HA PPCBug Firmware User’s Manual

listed in Appendix C, Related Documentation.

SET command

Chapter 6, CNFG and ENV Commands

MCP750 Single Board Computer Programmer’s Reference Guide, listed in Appendix C, Related

Documentation

Unpacking Instructions

, Debugger Commands,andthe

Note If the shipping carton is damaged upon receipt, request that the

carrier's agent be present during the unpacking and inspection of the equipment.

Unpack the equipment from the shipping carton. Carefully check the packing list and verify that all items are present. Save the packing material for storing and reshipping of equipment.

Avoid touching areas of integrated circuitry; static discharge can damage circuits.

Caution

http://www.motorola.com/computer/literature 1-5

Hardware Preparation and Installation

Hardware Configuration

To produce the desired configuration and ensure proper operation of the MCP750HA, you may need to carry out certain hardware modifications before installing the module.

The MCP750HA provides software control over most options: by setting bits in control registers after installing the module in a system, you can modify its configuration. Note that the MCP750HA control registers are described in Chapter 3, Functional Description, and/or in the MCP750

Series Programmer's Reference Guide, listed in Appendix C, Related

Documentation.

Some optionsare not softwareprogrammable. Such options are controlled through installation or removal of jumpers or interface modules on the base board itself or the associated transition module.

MCP750HA Base Board Preparation

Figure 1-2 shows the location of switches, jumpers, connectors, and LED

indicators on the MCP750HA. Manually configured items on the base board include a flash bank selection (J9).

For additional information on the configured items of the transition module, refer to the section entitled TMCP700 Transition Module

Preparation in Appendix B, Hardware Preparation and Installation for TMCP700 or to the respective user’s manuals for the transition modules

(listed in Appendix C, Related Documentation). The MCP750HA is factory tested and shipped with the configurations

described in the following sections. The board’s factory-installed debug monitor and PPCBug operates properly with these factory settings.

Flash Bank Selection (J9)

The MCP750HA has provisions for 1MB of 16-bit Flash memory. The RAM300 memory mezzanine accommodates 8MB of additional 64-bit Flash memory.

1-6 Computer Group Literature Center Web Site

MCP750HA Base Board Preparation

The flash memory is organized in either one or two banks, with each bank beingeither 16 or 64 bits wide. Bank B contains the onboard debugger and PPCBug.

To enable Flash Bank A (8MB memory on the RAM300 mezzanine), install a jumper on header J9 across pins 1 and 2. To enable Flash Bank B (1MBmemory on thebase board), install ajumper on headerJ9 across pins 2and3.

J9J9

3 2

Flash Bank A Enabled

(8MB on RAM300 mezzanine)

Flash Bank B Enabled (1MB on base board)

3 2

(FactoryConfiguration)

J10 - Factory Use Only

HeaderJ10 is an ISP program download cable connection that isleft on the board for MCG factory use only.

http://www.motorola.com/computer/literature 1-7

Hardware Preparation and Installation

PCI MEZZANINE CARD

10/100 BASE T

J21

J10

J11

J13

J5 J4 J3 J2 J1

J12

J14

COM 1

J15

XU1

XU2

J20

RST

S2S1

ABT

CPU

BFL

CPI

CPCI

USB 1

USB 0

J17

J18

1902

189

DS4

DS2 DS1

DS3

J16

1902 189

2641 9910

Figure 1-2. MCP750HA Switches, Headers, Connectors, and LEDs

1-8 Computer Group Literature Center Web Site

Hardware Installation

The following sections discuss the installation of mezzanine cards on the MCP750HA base board, the installation of the complete MCP750HA assembly into a CompactPCI chassis, and the system considerations relevant to installation. Before installing the MCP750HA, make sure that the serial ports and all jumpers are properly configured.

In most cases, the mezzanine card (RAM300 ECC DRAM module) is already in place on the base board. The user-configured jumpers are accessible with the mezzanines installed.

Should it be necessary to install mezzanines on the base board, refer to the following sections for a description of the installation procedure.

ESD Precautions

Compact FLASH Memory Card Installation

Use ESD

Wrist Strap

Motorola strongly recommends that you use an antistaticwrist strap and a conductive foam pad when installing or upgrading a system. Electronic components such as disk drives, computer boards, and memory modules are extremely sensitive to ESD. After removing a component from the system or its protective wrapper, place the component on a grounded, static-freesurface. In handlinga board, place it component side up. Do not slide the component over any surface.

If an ESD station is not available, you can avoid damage resulting from ESD by wearing an antistatic wrist strap (available locally) attached to an unpainted metal part of the system chassis.

Compact FLASH Memory Card Installation

The Compact FLASH memory card mounts on the MCP750HA base board, under the RAM300 memory mezzanine. To upgrade or install a Compact FLASH memory card, refer to Figure 1-3 andproceed as follows:

1. Attach an ESD strap to your wrist. Attach the other end of the strap to the chassis (for proper grounding). The ESD strap must be

http://www.motorola.com/computer/literature 1-9

Hardware Preparation and Installation

secured to your wrist and to chassis ground throughout the procedure.

2. If you are installing the board in a non-hot swap chassis,perform an operating system shutdown. Turn the AC or D C power off and remove the AC cord or DC power lines from the system. Remove the chassis or system cover(s) as necessary to access the compact PCI module.

2117 9710

Figure 1-3. Compact FLASH Placement on MCP750HA

Insertingor removingmodules thatare not H A capable with power applied

Caution

Warning

1-10 Computer Group Literature Center Web Site

may result in damage to module components.

To prevent injury, use extreme caution when handling, testing, and adjusting this equipment. Dangerous voltages capable of causing death exist.

Caution

RAM300 Memory Mezzanine Installation

3. Carefully remove the MCP750HA from the CompactPCI card slot and place it on a clean and adequately protected working surface with connectors J1 through J5 facing you.

Avoid touching areas of integrated circuitry; static discharge can damage these circuits.

4. If installed, remove the RAM300 mezzanine module by first removing four phillips-head screws at the corners of the mezzanine and then by gently lifting it near the connector end of the module. Refer to the RAM300 Memory Mezzanine Installation procedure below.

5. Slide the Compact FLASH memory card into the J20 connector and ensure that pin 1 of the card aligns w ith pin 1 of J20.

6. Place the RAM 300 mezzanine module on top of the base board.The connector on the underside of the mezzanine should connect smoothly with the corresponding connector (J7) on the MCP750HA.

7. Insert the four short phillips-head screws through the holes at the corners of the RAM300 mezzanine and into the standoffs on the MCP750HA. Tighten the screws.

8. Reinstall the MCP750HA assembly in the proper card slot. Ensure that the module is properly seated in the backplane connectors. Do not damage or bend connector pins.

9. If the board was installed in a non-hot swap chassis, replace the chassis or system cover(s), reconnect the system to the AC or DC power source, and turn the equipment power on.

RAM300 Memory Mezzanine Installation

The RAM300 DRAM mezzanine mounts on top of the MCP750HA base board.To upgrade or install a RAM300 mezzanine, refer to Figure 1-4 and proceed as follows:

http://www.motorola.com/computer/literature 1-11

Hardware Preparation and Installation

1. Attach an ESD strap to your wrist. Attach the other end of the ESD strap to the chassis as a ground. The ESD strap must be secured to your wrist and to ground throughout the procedure.

2. If the DRAM is being installed in a non-hot swap chassis, perform an operating system shutdown. Turn the AC or DC power off and remove the AC cord or DC power lines from the system. Remove chassis or system cover(s) as necessary for access to the compact PCI module.

11661.00 9611 (2-3)

Figure 1-4. RAM300 Placement on MCP750HA

Inserting or removing memory mezzanine modules with power applied

Caution

1-12 Computer Group Literature Center Web Site

may result in damage to module components.

Warning

Caution

PMC Module Installation

To prevent injury, use extreme caution when handling, testing, and adjusting this equipment. Dangerous voltages capable of causing death exist.

3. Carefully remove the MCP750HA from the CompactPCI card slot and place it on a clean and adequately protected working surface with connectors J1 and J5 facing you.

Avoid touching areas of integrated circuitry; static discharge can damage these circuits.

4. Place the RAM 300 mezzanine module on top of the base board.The connector on the underside of the RAM300 should connect smoothly with the corresponding connector (J7) on the MCP750HA.

5. Insert the four short phillips-head screws through the holes at the corners of the RAM300 mezzanine and into the standoffs on the MCP750HA. Tighten the screws

6. Reinstall the MCP750HA assembly in its proper card slot. Be sure the module is well seated in the backplane connectors. Do not damage or bend the connector pins.

7. If the DRAM was installed in a non-hot swap chassis, replace the chassis or system cover(s), reconnect the system to the AC or DC power source, and turn the equipment power on.

PMC Module Installation

PCI mezzanine card (PMC) module mount beside the RAM300 mezzanine on top of the MCP750HA base board. To install a PMC module, refer to

Figure 1-5 and proceed as follows:

http://www.motorola.com/computer/literature 1-13

Hardware Preparation and Installation

1. Attach an ESD strap to your wrist. Attach the other end of the ESD strap to the chassis as a ground. The ESD strap must be secured to your wrist and to ground throughout the procedure.

2. If the PMC module is being installed in a non-hot swap chassis, perform an operating system shutdown. Turn the AC or DC power off and remove the AC cord or DC power lines from the system. Remove chassis or system cover(s) as necessary for access to the CompactPCI.

2088 9708

Figure 1-5. PMC Module Placement on MCP750HA

Inserting or removing PMC modules with power applied may result in

Caution

Warning

1-14 Computer Group Literature Center Web Site

damage to module components.

To prevent injury, use extreme caution when handling, testing, and adjusting this equipment. Dangerous voltages capable of causing death exist.

Caution

MCP750HA Module Installation

3. Carefully remove the MCP750HA from the CompactPCI card slot and place it on a clean and adequately protected working surface with connectors J1 and J5 facing you.

Avoid touching areas of integrated circuitry; static discharge can damage these circuits.

4. Remove the PCI filler from the front panel.

5. Slide the edge connector of the PMC module into the front panel opening from behind and place the PMC module on top of the base board. The four connectors on the underside of the PMC module should then connect smoothly with the corresponding connectors (J11/12/13/14) on the MCP750HA.

6. Insert the four short phillips-head screws (provided with the PMC) through the holes on the bottom side of the MCP750HA and the PMC f ront bezel and into rear standoffs. Tighten the screws.

7. Reinstall the MCP750HA assembly in its proper card slot. Be sure the module is well seated in the backplane connectors. Do not damage or bend connector pins.

8. If the PMC module was installed in a non-hot swap chassis, replace the chassis or system cover(s), reconnect the system to the AC or DC power source, and turn the equipment power on.

MCP750HA Module Installation

With mezzanine board(s) installed and headers properly configured, proceed as follows to install the MCP750HA in the CompactPCI chassis:

1. Attach an ESD strap to your wrist. Attach the other end of the ESD strap to the chassis as a ground. The ESD strap must be secured to your wrist and to ground throughout the procedure.

2. If the board is being installed in a non-hot swap chassis, perform an operating system shutdown. Turn the AC or D C power off and

http://www.motorola.com/computer/literature 1-15

Hardware Preparation and Installation

remove the AC cord or DC power lines from the system. Remove chassis or system cover(s) as necessary for access to the CompactPCI modules.

To prevent injury, use extreme caution when handling, testing, and adjusting this equipment. Dangerous voltages capable of causing death

Warning

Caution

exist.

3. Remove the filler panel from the card slot (system slot).

Avoid touching areas of integrated circuitry; static discharge can damage these circuits

Note The MCP750HA must be installed in the CompactPCI system

slot in order to provide clocks and arbitration to the other slots. The system slot is identified with a triangle symbol, which is markedon the backplane. Some CompactPCIsubracks may have a red guide rail to mark the system slot.

4. Set the VIO on the backplane to either 3.3V or 5V, depending upon your system’s signaling requirements.

Ensure the backplane does not bus J3, J4 or J5 signals to other slots.

Caution

1-16 Computer Group Literature Center Web Site

5. Slide the MCP750HA into the system slot. Grasping the top and bottom injector handles, be sure the module is well seated in the P1 through P5 connectors on the backplane. Do not damage or bend connector pins. Secure the MCP750HA in the chassis with the screwsprovided,making good contact withthe transversemounting rails to minimize RF emissions.

MCP750HA Module Installation

Step 1 Step 2

Step 3

Figure 1-6. MCP750HA Board Insertion Sequence

6. Replace the chassis or system cover(s), making sure that no cables are pinched. Cable the peripherals to the panel connectors.For nonhot swap chassis, reconnect the system to the AC or DC power source, and turn the equipment power on.

http://www.motorola.com/computer/literature 1-17

Hardware Preparation and Installation

System Considerations

The MCP750HA is designed to operate as a CompactPCI system slot board.As a systemslot board,the MCP750HA provides system clocks and arbitration for the other peripheral slots in the subrack. Consequently, the MCP750HA must be installed in a subrack system slot marked with a triangle symbol.

The MCP750HA provides seven peripheral slot clock outputs (CLK0CLK6) per CompactPCI specification 2.0 R2.1. Arbitration for the seven peripheral slot bus masters is provided by the MCP750HA.

On the MCP750HA base board, the standard serial console port (COM1) servesas thePPCBug debuggerconsole port.The firmwareconsole should be set up as follows:

❏ Eight bits per character ❏ One stop bit per character ❏ Parity disabled (no parity) ❏ Baud rate of 9600 baud

9600 is the default baud rate for serial ports on MCP750HA boards. After power-upyou can reconfigurethe baud rateif you wish, using the PPCBug PF (Port Format) command via the command line interface.Whatever the baud rate, some type of hardware handshaking — either XON/OFF or via the RTS/CTS line — is desirable if the system supports it.

MCP750HA Module Power Requirements

The MCP750HA module draws +5VDC, +3.3VDC, VIO, +12VDC, and

-12VDC from the CompactPCI backplane connector J1. TheMCP750HA supplies +5.0VDC, +3.3VDC, +12VDC, and -12VDC to

J3 and J5 for use by the transitionmodule. Separatelyfused +5VDC is also provided for the keyboard/mouse. Separate +5VDC fused power is also provided for each USB channel and the PMC slot +5VDC. See Table 3-4

on page 3-18 for fuse assignments.

1-18 Computer Group Literature Center Web Site

2Operating Instructions

Introduction

This chapterprovides information applicableto the MCP750HA family of Single Board Computers in a system configuration. This includes the power-up procedure along with descriptions of the switches and LEDs, memory maps, and software initialization.

Applying Power

After you have verified that all the necessary hardware preparation has been done (with all connections made correctly) and that the installationis complete, you can power up the system. The MPU, hardware, and firmware initialization process is performed by the PowerPC™ PPCBug power-upor system reset.The firmware initializes the devices on the SBC module in preparation for booting the operating system.

The firmware is shipped from the factory with an appropriate set of defaults. In most cases there is no need to modify the firmware configuration before you boot the operating system.

Figure 2-1 shows the basic initialization process that takes place during

PowerPC system startup. When using the MCP750HA in a hot swap capable chassis, the module

may be inserted and extracted with power applied. For additional information on PPCBug, refer to Chapter 5, PPCBug,and

Chapter 6, CNFG and ENV Commands, to the PPCBug Firmware

Package User’s Manual, andtotheCPX750 High Availability PPCBug FirmwareUser’s Manual. Both manuals arelisted in AppendixC, Related

Documentation.

2-1

Operating Instructions

STARTUP

SYSTEM

INITIALIZATION

CONSOLE

DETECTION

RUN SELF TESTS

(IF ENABLED)

AUTOBOOT

(IF ENABLED)

OPERATING

SYSTEM

11734.00 9702

Figure 2-1. PPCBug System Startup

The MCP750HA front panel has LEDstatus indicators(

BFL,CPU, PCI, CPCI). Foradditional informationon

ABORT and RESET switches and four

front panel operation, refer to Chapter 3, Functional Description.

Memory Maps

There are three points of view for memory maps:

2-2 Computer Group Literature Center Web Site

Memory Maps

❏ The mappingof all resources as viewed by the processor (MPU bus

memory map)

❏ The mapping of onboard resources as viewed by PCI local bus

masters (PCI bus memory map)

❏ The mapping of onboard resources as viewed by the CompactPCI

bus.

The following sections provide a general description of the MC P750HA memory organization from three points of view listed above. Detailed memory maps can be found in the MCP750 Single Board Computer

Programmer's Reference Guide, listed in Appendix C, Related

Documentation.

Processor Memory Map

The processor memory map configuration is under the control of the Raven bridge controller ASIC and the Falcon memory controller chip set. The Raven and Falcon devices adjust system mapping to suit a given application via programmable map decoder registers. At system power-up or reset, a default processor memory map takes over.

Default Processor Memory Map

The default processor memory map that is valid at power-up or reset remains in effect until reprogrammed for specific applications. Table 2-1 defines the entire default memory map ($00000000 to $FFFFFFFF).

Table 2-1. Processor Default View of the Memory Map

Processor Address Size Definition Notes

Start End

00000000 7FFFFFFF 2GB Not Mapped 80000000 8001FFFF 128KB PCI/ISA I/O Space 1 80020000 FEF7FFFF 2GB-16MB-640KB Not Mapped FEF80000 FEF8FFFF 64KB Falcon Registers

http://www.motorola.com/computer/literature 2-3

Operating Instructions

Table 2-1. Processor Default View of the Memory Map (Continued)

Processor Address Size Definition Notes Start End

FEF90000 FEFEFFFF 384KB Not Mapped FEFF0000 FEFFFFFF 64KB Raven Registers FF000000 FFEFFFFF 15MB Not Mapped FFF00000 FFFFFFFF 1MB ROM/Flash Bank A or Bank B 2

Notes 1. Default map for PCI/ISA I/O space. Allows software to

determine whether the system is MPC105-based or Falcon/Raven-based by examining either the PHB Device ID or the CPU Type register.

2. The first 1MB of ROM/Flash bank A (soldered 4MB or 8MB ROM/Flash) appears in this range after a reset if the rom_b_rv control bit in the Falcon’s ROM B Base/Size register is cleared. If the rom_b_rv control bit is set, this address range maps to ROM/Flash bank B (socketed 1MB ROM/Flash).

For detailed processor memory maps, including suggested PREPcompatible memory maps, refer to the MC P750 Single Board Computer

Programmer's Reference Guide (MCP750A/PG), listed in Appendix C,

PCI Local Bus Memory Map

The PCI memory map is controlled by the Raven ASIC and by the 21154 PCI-to-PCI bridges. The Raven and the PCI-to-PCI bridges adjust system mapping to suit a given application via programmable map decoder registers.

No default PCI memory map exists. Resetting the system turns the PCI map decoders off, and they must be reprogrammed in software for the intended application.

2-4 Computer Group Literature Center Web Site

Memory Maps

For detailed PCI memory maps, including suggested PREP-compatible memory maps, refer to the MCP750 Single Board Computer

Programmer's Reference Guide, listed in Appendix C, Related

Documentation.

CompactPCI Memory Map

The processor will a ccess devices on the CompactPCI busses by using transaction forwarding provided by the DEC 21154 PCI-to-PCI bridge. Transaction forwarding within the 21154 is based on address ranges definedin the 21154 base and limit registers.The 21154 provides registers for I/O, memory, and prefetchable memory spaces. These registers define the address range for which PCI transactions are forwarded downstream from the primary PCI bus to the CompactPCI bus (secondary bus). All devices on the CompactPCI bus must be configured for addressing within thisdefined range.Conversely,these registersalso define the addresses for which transactions will be forwarded upstream. Any CompactPCI bus address, generated by a CompactPCI bus master, not in the defined memory range, will be forwarded upstream, to the Primary PCI bus. There isno address translationbetween CompactPCIbusses and the Primary PCI bus.

Recommendations for CompactPCI mapping, including suggested PREPcompatible memory maps, can be found in the MCP750 Single Board Computer Programmer's Reference Guide.

PCI Arbitration

There are 6 potential local PCI bus masters on the MCP750HA singleboard computer:

❏ Raven ASIC (MPU/PCI bus bridge controller) ❏ DEC 21154 PCI-to-PCI bridge ❏ External PCI bus master via J4 connector, used by the hot swap

bridge

❏ VIA 82C586B PBC (Peripheral Bus Controller) PCI/ISA bridge

http://www.motorola.com/computer/literature 2-5

Operating Instructions

❏ DEC 21140 Ethernet Controller ❏ PMC Slot (PCI mezzanine card)

The arbitration for these six bus mastering devices is provided by custom onboard hardware. This arbiter implements a rotating priority scheme in which the last master granted becomes the lowest priority. The order of rotation is shown in the list above.

Interrupt Handling

The Raven ASIC provides an MPIC Interrupt Controller to handle various interrupt sources. It controls PHB (PCI Host Bridge) MPU/local bus interface functions on the MCP750HA, as well as performing interrupt handling. Sources of interrupts may be any of the following:

❏ The Raven ASIC itself (timer interrupts or transfer error interrupts) ❏ The processor (processor self-interrupts) ❏ The Falcon chip set (memory error interrupts) ❏ The PCI bus (interrupts from PCI devices) ❏ The CompactPCI bus (interrupts from CompactPCI devices) ❏ The CompactPCI expansion bus (interrupts from HSC and

expansion bus)

❏ Power monitor interrupts ❏ Watchdog timer interrupt ❏ The ISA bus (interrupts from ISA devices)

For details on interrupt handling, refer to the MPC750 Single Board ComputerProgrammer’s ReferenceGuide. For details on chassis interrupt

routing, refer to the chassis documentation that applies to the specific model you are using. Refer to Appendix C, Related Documentation,fora list of those documents.

2-6 Computer Group Literature Center Web Site

Memory Maps

DMA Channels

The PBC supports seven DMA channels. Channels 0 through 3 support 8bit DMA devices. Channels 5 through 7 are dedicated to 16-bit DMA devices. The channels are allocated as follows:

Table 2-2. PBC DMA Channel Assignments

PBC

Priority

1 Channel 0 DMA1 Serial Port 3 Receiver (Z85230 Port A Rx) 2 Channel 1 Serial Port 3 Transmitter (Z85230 Port A Tx) 3 Channel 2 Floppy Drive Controller 4 Channel3 ParallelPort 5 Channel 4 DMA2 Not available — Cascaded from DMA1 6 Channel 5 Serial Port 4 Receiver (Z85230 Port B Rx) 7 Channel 6 Serial Port 4 Transmitter (Z85230 Port B Tx) 8 Channel7 NotUsed

PBC

Label

Sources of Reset

The MCP750HA SBC has seven potential sources of reset:

Controller DMA Assignment

1. Power-on/Undervoltage Reset.

2. Front Panel

RESET switch (will generate a hard reset when

depressed).

3. Reset and Abort Header J21 Pins 2-3.

4. Watchdog timer Reset function controlled by the SGS-Thomson MK48T559 Watchdog Timer or the Raven Watchdog Timers.

5. Port 92 Register via the PBC

6. CompactPCI Bus via the 21154 Bridge Control Register.

7. Optional external reset from J5 pin A22.

http://www.motorola.com/computer/literature 2-7

Operating Instructions

For details on using resets, refer to the MCP750 Single Board Computer Programmer's Reference Guide, listed in Appendix C, Related

Documentation.

Table 2-3. Classes of Reset and Effectiveness

Table 2-3 shows which devices are affected by the various types of resets.

Device

Affected

Reset Source

PowerOn/undervoltage

Front Panel Reset Switch

J21 Reset Header

W atchdog Timer Reset

S/W Hard Reset (PBC Port 92 Register)

CompactPCI Reset (21154 BCR)

External Reset (J5)

Processor Raven

ASIC

√√√√√√ √

√√√√√√

Falcon

Chip Set

PCI

Devices

ISA

Devices

Compact

PCI

Busses

√

Hot

Swap

Bridge

Endian Issues

The MCP750HA supports both little-endian and big-endian software. The PowerPC is inherently big-endian, while the PCI bus is inherently littleendian. The following sections summarize how the MCP750HA handles software and hardware differences in big- and little-endian operations. For furtherdetailson endian considerations,refer to the MCP750 Single Board

Computer Programmer’s Reference Guide, listed in Appendix C, Related

Documentation.

2-8 Computer Group Literature Center Web Site

Memory Maps

Processor/Memory Domain

The MPC750 processor can operate in both big-endian and little-endian mode.However, it always treatsthe external processor/memorybus as bigendian by performing address rearrangement and reordering when running in little-endian mode. The PPC registers in the Raven PCI bus bridge controller ASIC and the Falcon memory controller chip set, as well as DRAM, ROM/Flash, and system registers, always appear as big-endian.

Role of the Raven ASIC

Because the PCI bus is little-endian, the Raven performs byte swapping in both directions (from PCI to memory and from the processor to PCI) to maintain address invariance while programmed to operate in big-endian mode with the processor and the memory subsystem.

In little-endian mode, the Raven reverse-rearranges the address for PCIbound accesses and rearranges the address for memory-bound accesses (from PCI). In this case, no byte swapping is done.

PCI Domain

The PCI bus is inherently little-endian. All devices connected directly to the PCI bus operate in little-endian mode, regardless of the mode of operation in the processor’s domain.

PCI and Ethernet

Ethernet is also byte-stream-oriented; the byte having the lowest address in memory is the first one to be transferred regardless of the endian mode. Sincethe Raven maintains address invariance in both l ittle-endian and bigendian mode, no endian issues should arise for Ethernet data. However, big-endian software m ust still take the byte-swapping effect into account when accessing the registers of the PCI/Ethernet device.

http://www.motorola.com/computer/literature 2-9

3Functional Description

Introduction

This chapter describes the MCP750HA single-board computer on a block diagramlevel. The General Descriptionon page 3-2 provides an overview of the MCP750HA, followed by a detaileddescription of several blocks of circuitry. Figure 3-1 shows a block diagram of the board’s architecture.

Detailed descriptions of other MCP750HA blocks, including programmableregisters in the ASICs and peripheral chips can be found in the MCP750 Single Board Computer Programmer’s Reference Guide, listed in Appendix C, Related Documentation. You may also refer to this guide for a more detailed functional description of the MCP750HA.

Features

The following table summarizes the features of the MCP750HA singleboard computers.

Table 3-1. MCP750HA Features

Feature Description

Microprocessor MPC750 PowerPC processor ECC DRAM 32MB-256MB on RAM300 module L2 cache memory Populated with 1MB on base board Flash Memory Two 32-pin PLCC sockets (1MB 16-bit Flash) on base board; two banks

(8MB 64-bit Flash) on RAM300 module Real-time clock 8KB NVRAM with RTC and battery backup (ST Microelectronics M48T559) Switches Status LEDs four: BFL, CPU, PCI, and CPCI Tick timers Three programmable 16-bit timers W atchdog timers Provided in SGS-Thomson M48T559 or Raven 3

RESET and ABORT

3-1

Functional Description

Table 3-1. MCP750HA Features (Continued)

Feature Description

Interrupts Software interrupt handling via Raven (PCI-MPU bridge) and Peripheral Bus

Controller

Serial I/O 1 async port (COM1) via front panel. 2 async ports, 2 sync/async ports via the

transition module

Parallel I/O IEEE 1284 bidirectional parallel port (PC87307 SIO) via the transition

module Ethernet I/O 10BaseT/100BaseTX connection via the front panel PCI interface One IEEE P1386.1 PCI Mezzanine Card (PMC) slot; one 110 pin

CompactPCI connector (J4) for PCI expansion/Hot Swap bridge. Keyboard/mouse

interface Floppy disk

controller CompactPCI 33 MHz, 64-bit CompactPCI interface with DEC 21154 PCI-to-PCI bridge. USB I/O USB Host/Hub interface with two ports routed to the front panel or transition

EIDE Primary EIDE port routed to onboard Compact FLASH connector. Secondary

HSC Interface Interface to the Hot Swap Controller (J3)

Support for keyboard and mouse input (PC87307 SIO) via the transition

module

Support for floppy disk drive (PC87307 SIO) via the transition module

module

EIDE port routed to the transition module

General Description

The MCP750HA is a single-slot single-board computer equipped with an MPC750 PowerPC™ 750 Series microprocessor. The processor implements a backside cache controller and the board comes with 1MB of cache memory.

The MCP750HA is a hot swap capable single-slot single board computer. It is designed to be used with an HSC8216 Bridge Module in an N+1 HiAvailability environment. The MCP750HA/HSC complement allow for hot swap capability of processor and CPCI Hot Swap compliant I/O modules.

3-2 Computer Group Literature Center Web Site

General Description

As shown in Features on page 3-1, the MCP750HA offers many standard featuresdesirable in a CompactPCI computersystem—such as PCIBridge and Interrupt Controller, an ECC Memory Controller chipset, 9MB of linear FLASH memory, IDE Compact Flash memory, 16MB to 256MB of ECC-protected DRAM, interface to a CompactPCI bus, Hot Swap logic, and several I/O peripherals.

The I/O peripheral interfaces present on the onboard PCI bus include: a 10/100BaseT Ethernet interface, a USB host controller, an ISA master/slave interface, a Fast EIDE interface and one PMC Slot. Functions provided from the ISA bus are two async and two sync/async serial ports, keyboard, mouse, a floppy disk controller, printer port, a real time clock, and NVRAM.

The MCP750HA interfacesto a CompactPCI bus using a DEC 21154 PCIto-PCI bridge device. This device provides a 64-bit primary and a 64-bit secondary interface allowing full 64-bit data access between CompactPCI bus devices and the host/PCI bridge. This bus is capable of driving seven CompactPCI slots.

Another key feature of the MCP750HA family is the PCI (Peripheral Component Interconnect) bus. In addition to the on-board local bus peripherals, the PCI bus supports an industry-standard mezzanine interface,IEEE P1386.1 PMC (PCI MezzanineCard). PMC modules offer a variety of possibilitiesfor I/O expansion. The base board supports PMC I/O for the front panel or J3/TMCP700.

http://www.motorola.com/computer/literature 3-3

Functional Description

Block Diagram

FDD

RTC

Parallel

L2 Cache

SRAM

MPC750

Keyboard

DRAM

FLASH

Sys CSR

PMC

Slot 1

60X System Bus

Falcon Falcon

Raven

32/64-Bit PCI Local Bus

PCI-to-PCI

Bridge 1

Expansion Connector

(Bridge 2)

IDE Bus

Peripheral Bus

Controller

Ethernet

Compact

FLASH

Hot Swap

Controller

Interface

Mouse

Async Serial

(2 channels)

Sync/Async

ISA SIO

ISA Local Resource Bus

NVRAM

RTC

SROM

USB 1

USB 2

Serial

(2 channels)

ISA CSR

Figure 3-1. MCP750HA Block Diagram

3-4 Computer Group Literature Center Web Site

Hot Swap Circuitry

The MCP750HA may be safely inserted and extracted from the system chassis while power is applied. The hot swap circuitry will protect the board from electrical d amage. The MCP750HA uses an LTC1643 hot swap controller device from Linear Technologies to implement hot swap capability.

Insystems that support high availability,theCPCI bus may beactive while the MCP750HA is inserted and/or removed without disturbing the bus traffic. This is accomplished by pin-staged CPCI bus connections, a switchedpre-charged voltage level applied to bussed pins and three-stated PCI-to-PCI bridge signals during insertion and removal.

The BD_SEL# signal from CPCI bus J1 pin D1 must be driven true (low) for the back end power supplies to switch on. When BD_SEL# is not asserted only a small portion of the MCP750HA circuitry is powered.

The HLTY# signal is driven true (low) to the CPCI bus J1 pin B4 when the +5.0VDC, +3.3VDC, +12VDC, and -12VDC input power supplies are all within tolerance. This can be used as a status indicator.

Block Diagram

CompactPCI Interface

The CompactPCI bus interface will support up to 7 CompactPCI peripheral cards. The CompactPCI bus interface is provided using the DEC 21154 PCI-to-PCI bridge chip. This device implements a 64-bit primary data bus and 64-bit secondary data bus interface and is PCI 2.1 compliant. The 21154 provides read/write data buffering in both directions.

The MCP750HA uses an external arbiter which implements a level rotating algorithm for all CompactPCI masters. The arbiter latency is typically one PCI clock. If the arbiter detects that an initiator has failed to assert FRAME# within 16 clock of the grant, the arbiter will negate the grant. The arbiter parks the CPCI bus at the last bus master by keeping the last grant asserted until a new bus request is asserted. After a reset, the arbitter parks the CPCI bus at DEC21154 until a new request is asserted.

http://www.motorola.com/computer/literature 3-5

Functional Description

The MCP750HA provides the 33 MHz clocks for each of the CompactPCI slots. All clock source outputs are active when the MCP750HA is owner of the CPCI bus.

The21154 supports3.3V or 5Vsignalling at the PCI busseswith aseparate VIO pin for the primary and secondary bus buffers. The primary bus signallingvoltage is tied to +5 volts. The secondary bus signalling voltage is tied to the CPCI bus VIO, so the MCP750HA is a universal board that may operate in a +3.3V or +5V chassis.

PCI Expansion Connector (J4)

The expansion connector can be used to route the local PCI bus to a secondaryPCI-to-PCI bridge. In addition,signals needed by the Hot Swap Controller/Bridge Module are routed through J3. Refer to the chassis specific information found in the MCG chassis manual for your particular product. A list of those manuals is included in Appendix C, Related

Documentation. Figure 3-2 on the following page shows a typical high

availability architecture implementation.

3-6 Computer Group Literature Center Web Site

Block Diagram

Active CPU

I/O Domain A

I/O

L O T

Figure 3-2. Active/Passive System

Domain Ownership

I/O

Active HSC

I/O Domain B

Passive

CPU/HSC

I/O

S L O T

In High Availability systemimplementations, thePCI-to-PCI bridge is not available until the Domain ownership is established. The PCI-to-PCI bridge will not connect to the CPCI bus until directed by software. This default is the result of the architecture, in which the Domains may already be actively under the control of a second CPU board. In this case, live insertion of a MCP750HA must not disrupt the active CPCI bus.

The bus ownership is automatically established by the hot swap control circuitry in non-high availability systems. The backplane must leave the control lines J3-A15, J3-A16, J3-A17, and J3-A18 as no connects in nonhigh availability implementations. Pull-up resistors located on the MCP750HA will then allow for normal PCI-to-PCI Bridge operation.

http://www.motorola.com/computer/literature 3-7

Functional Description

In the high availability systems, a Hot Swap Controller device is present on the local PCI bus. This device can be used by the software to gain or relinquish control of the Domains (CPCI buses). The HSC is also used to

oversee the HA functionality of the other I/O boards inserted into the nonhost system slots. At the debugger diagnostic level, the PPCBug commands that can be used to control the HA features are described in

Chapter 5, PPCBug. Refer to the Hot Swap Controller Driver

documentation of the specific operating system used for further information about HSC functions and system calls invoked by the operating system.

Ethernet Interface

The MCP750HA module uses Digital Equipment’s DECchip 21140 PCI Fast Ethernet LAN controller to implement an Ethernet interface that supports 10BaseT/100BaseTX connections. The balanced differential transceiver lines are coupled via on-board transformers.

The MCP750HA routes its 10BaseT/100BaseTX lines to an RJ45 connector on the front panel.

Every MCP750HA is assigned an Ethernet station address. The address is $08003E2xxxxx,wherexxxxx is the unique 5-nibble number assigned to the board (that is, every board has a different value for xxxxx).

Each MCP750HA displays its Ethernet station address on a label attached to the base board in the PMC connector keepout area just behind the front panel. In addition, the six bytes including the Ethernet station address are stored in an SROM off the DECchip Ethernet controller. That is, the value 08003E2xxxxx is stored in SROM. Where xxxxx is a unique 5-nibble number for the board.

Note The Ethernet station address of boards manufactured after March

2000 is $0001AFxxxxxx

3-8 Computer Group Literature Center Web Site

Caution

Block Diagram

These bytes are stored in bytes 0x4 through 0x19 in the Ethernet SROM. The Ethernet information in the SROM is stored in DEC Version 3 format. For further information on this refer to the Digital Semiconductor 21x4 Serial ROM Format, Version 3.03 document.

Use e xtreme caution when viewing the contentsof the Ethernet SROM via the PPCBUG SROM command. If the contents are modified incorrectly this could cause the PPCBUG Firmware Ethernet Drivers to work incorrectly.

Note: When the board is shipped from the factory, it should contain the

proper SROM data for the MCP750HA, which has 10BaseT/100 BaseTX Ethernet connections. There should not be a need to change the SROM contents.

For the pin assignments of the 10BaseT/100BaseTX connector, refer to

Table4-11onpage4-11.

PCI Mezzanine Interface

A k ey feature of the MCP750HA family is the Peripheral Component Interconnect (PCI) bus. In addition to the on-board local bus devices (Ethernet, graphics, etc.), the PCI bus supports an industry-standard mezzanine interface, I EEE P1386.1 PCI Mezzanine Card (PMC).

PMC modules offer a variety of possibilities for I/O expansion through Fiber Distributed Data Interface (FDDI), Asynchronous Transfer Mode (ATM), graphics, and Ethernet ports. The base board supports PMC front panel and rear transition module I/O.

http://www.motorola.com/computer/literature 3-9

Functional Description

The MCP750HA supports one PMC slot. Four 64-pin connectors on the base board (J11, J12, J13, and J14) interface with 32-bit or 64-bit IEEE P1386.1 PMC-compatible mezzanines to add any desirable function. The

Mezzanine Type PMC (PCI Mezzanine Card)

Mezzanine Size S1B: Single width, standard depth (75mm x 150mm) with front panel PMC Connectors J11 through J14 (32/64-Bit PCI with front and rear I/O) Signaling Voltage V

PCI Mezzanine Card slot has the following characteristics:

= 5.0VDC

Refer to Chapter4, Connector Pin Assignments,for the pin assignmentsof thePMC connectors. For additionalprogramming information,refer to the PCI bus descriptions in the MCP750 Single Board Computer

Programmer's Reference Guide, listed in Appendix C, Related

Documentation, and to the user documentation for the PMC m odules that

youintendtouse.

PC97307 ISA Super I/O Device

The MCP750HA uses the PC97307 ISA Super I/O device from National Semiconductor to provide the following:

❏ Two asynchronous serial ports ❏ Parallel port via transition module ❏ Floppy disk drive support via transition module ❏ A PS/2 keyboard and mouse interface via transition module ❏ A parallel printer port interface

Asynchronous Serial Ports

The Super I/O device provides two UART devices which are compatible withstandard 16450or 16550A UARTs. The default configurationassigns COM1 to IRQ4 and COM2 to IRQ3 of the PBC. The default configuration can be changed by programming the ISA Super I/O device accordingly.

3-10 Computer Group Literature Center Web Site

The COM1 port is wired as an RS-232 interface to a PC compatible DB9 connector on the front panel and it is also routed to the transition module via J3. COM2 is wired as an RS-232 interface and is routed to the J3 I/O connector for transition module I/O.

For additional programming information, refer to the PCI and ISA bus discussions in the MCP750 Single Board Computer Programmer's ReferenceGuide, listed in Appendix C, Related Documentation, andtothe vendor documentation for the ISA Super I/O device.

Parallel Port/Printer Interface

The parallel port is a full IEEE1284 bi-directional parallel port/printer interface that supports standard enhanced and extended port modes. All parallel I/O interface signals are routed to the transition module that includes series damping resistors.

Hardwareinitializesthe parallelport asPPT1 with anISA I/O base address of $3BC. This default configuration also assigns the parallel port to Peripheral Bus Controller (PBC) interrupt request line IRQ7. The default configuration can be changed by reprogramming the ISA Super I/O device. For additional programming information, refer to the PCI and ISA bus discussions in the MCP750 Single Board Computer Programmer's Reference Guide and to the vendor documentation for the ISA Super I/O device.

Block Diagram

Floppy Disk/Tape Drive Controller

The ISA Super I/O device incorporates a PS/2-compatible low- and highdensitydisk drive controllerfor use withan optional externaldisk drive, or a domain specific FLOPPY connector on the backplane. The drive interfaces with the ISA Super I/O controller via the transition module.

The ISA Super I/O disk drive controller is compatible with the DP8473, 765A, and N82077 devices commonly used to implement floppy disk controllers. Software written for those devices may be used without change to operate the ISA Super I/O controller. The ISA Super I/O device may be used to support any of the following devices:

❏ 3

/2-inch 1.44MB floppy disk drive

http://www.motorola.com/computer/literature 3-11

Functional Description

❏ 5

/4-inch 1.2MB floppy disk drive

❏ Standard 250Kbps to 2Mbps tape drive system

Keyboard and Mouse Interface

The National Semiconductor PC97307 ISA Super I/O chip is used to implement certain segments of the ROM-based keyboard and mouse interface control. The keyboard and mouse control signals are routed to a single 6-pin circular DIN connector on the transition module. Keyboard functions can be obtained by plugging the keyboard directly into this connector.To get both keyboard and mouse functions requires a Y adapter cable (Motorola Part Number: 30NW9302B83). Refer to the TMCP700 Transition Module Installation and Use manual for details.

PCI Peripheral Bus Controller (PBC)

The MCP750HA uses the VIA Technologies VT82C586 Peripheral Bus Controller(PBC) to supply the interfacebetween the PCI local bus and the ISA, IDE and USB systems I/O bus (illustrated in Chapter 1, Hardware

Preparation and Installation).

The PBC controller provides the following functions:

❏ ISA (Industry Standard Architecture) bus arbitration for DMA

devices

❏ ISA interrupt mapping ❏ USB v1.0/HCI v1.1 compatible host/hub interface with two ports ❏ Enhanced IDE Controller with ultra DMA-33 support ❏ Interrupt controller functionality to support 14 ISA interrupts ❏ Edge/level control for ISA interrupts ❏ Seven independently programmable DMA channels ❏ Three interval counters/timers (82C54 functionality)

❏ I

C interface via software programmable GPIO port

3-12 Computer Group Literature Center Web Site

Accesses to the configuration space for the PBC are performed by way of the CONADD and Configuration Address and Data (CONDAT) registers in the Raven bridge controller ASIC.The registers are located at offsets $CF8 and $CFC, respectively, from the PCI I/O base address.

EIDE Series Termination

Series termination resistors have been added to the secondary EIDE bus routed to the J5 user I/O connector. The EIDE drive interfaces with the PBC controller via the transition module or a domain specific EIDE connector on the backplane. Refer also to Chapter 4, Connector Pin

Assignments. The resistance values are given in the following table.

Table 3-2. Series Termination for Ultra DMA EIDE

Signal Host Termination

DIOR#:HDMARDY#:HSTROBE 22 ohm DIOW#:STOP 22 ohm CS0#, CS1# 33 ohm DA0, DA1, DA2 33 ohm DMACK# 22 ohm DD15 through DD0 33 ohm DMARQ 82 ohm INTRQ 82 ohm IORDY:DDMARDY#:DSTROBE 82 ohm RESET# 33 ohm

Block Diagram

Real-Time Clock/NVRAM/Watchdog Timer Function

The MCP750HA employs an ST Microelectronics surface-mount M48T559 RAM and clock chip to provide 8KB of non-volatile static RAM, a real-time clock, and a watchdog timer function.This chip supplies

http://www.motorola.com/computer/literature 3-13

Functional Description

a clock, oscillator, crystal, power failure detection, memory write protection, 8KB of NVRAM, and a battery in a package consisting of two parts:

❏ A 28-pin 330mil SO device containing the real-time clock, the

oscillator, power failure detection circuitry, timer logic, 8KB of static RAM, and gold-plated sockets for a battery

❏ A SNAPHAT battery housing a crystal along with the battery

TheSNAPHAT battery package is socket mounted on top of the M48T559 device. The battery housing is keyed to prevent reverse insertion.

The clock furnishesseconds, minutes, hours, day, date, month, and year in BCD 24-hour format. Corrections for 28-, 29- (leap year), and 30-day months are made automatically. The clock generates no interrupts. Althoughthe M48T559is an 8-bit device, 8-, 16-, and32-bit accessesfrom the ISA bus to the M48T559 are supported. Refer to the MCP750 Single Board Computer Programmer's Reference Guide and to the M48T559 data sheet for detailed programming and battery life information.

Programmable Timers

Among the resources available to the local processor are a number of programmable timers. Timers and counters on the MCP750HA are provided by the Raven ASIC, the M48T559, the PBC, and the Z8536 CIO device (diagrammed in Chapter 1, Hardware Preparation and

Installation). They can be programmed to generate periodic interrupts to

the processor.

Raven General Purpose Timers

The Raven ASIC contains four 32-bit general purpose timers. Each timer is driven by a divide-by-eightprescaler which is synchronized to the PPC processor bus clock. For a 66.66 MHz system, the timer frequency would be 8.25 MHz. Each timer may be programmed to generate an MPIC interrupt.

3-14 Computer Group Literature Center Web Site

Raven Watchdog Timers

TheRaven ASICcontains two Watchdog timers,WDT1, and WDT2. Each timer is functionally equivalent but independent. These t imers will continuously decrement until they reach a count of 0 or are reloaded by software. The timeout period is programmable from 1 microsecond up to 4 seconds. If the timer count reaches 0, a timer output signal will be asserted. The output of Watchdog Timer 1 is routed to generate an MPIC interrupt. The output of Watchdog Timer 2 is logically ORed onboard to provide a hard reset.

Following a device reset, WDT1 is enabled with a default timeout of 512 milliseconds and WDT 2 is enabled with a default timeout of 576 milliseconds. Each of these signals is typically delayed an additional 4.8 seconds (2 seconds minimum) using logic external to Raven. Each timer must be disabled or reloaded by software to prevent a timeout. Software may reload a new timer value or force the timer to reload a previously loadedvalue. To disable or load/reloada timer requires a two step process. The first step is to write the pattern $55 to the timer register key field which will arm the timer register to enable an update. The second step is to write the pattern $AA to the key field along with the new timer information. During the power-up configuration of the Raven ASIC, PPCBug disables the two Watchdog timers.

Block Diagram

M48T559 Watchdog Timer

The M48T559 contains one Watchdog timer. This Watchdog timer output is logically ORed with the Raven Watchdog timer 2 output to provide a hard reset. Refer to the device data sheet and the MCP750 Single Board Computer Programmer’s Reference Guide for programming information.

Interval Timers

The PBC has three built-in counters that are equivalent to those found in an 82C54 programmableinterval timer. The counters are grouped into one timer unit, Timer 1, in the PBC. Each counter output has a specific function:

http://www.motorola.com/computer/literature 3-15

Functional Description

❏ Counter 0 is associated with interrupt request line IRQ0. It can be

used for system timing functions, such as a timer interrupt for a time-of-day function.

❏ Counter 1 generates a refresh request signal for ISA memory. This

timer is not used in the MCP750HA.

❏ Counter 2 provides the tone for the speaker output function on the

PBC (the

SPEAKER_OUT signal which can be cabled to an external

speaker via the transition module).

The interval timers use the OSC clock input as their clock source. The MCP750HA drives the OSC pin with a 14.31818 MHz clock source.

16-Bit Timers

Three 16-bit timers, provided by the Z8536 CIO device, are available on the MCP750HA. For information on programming these timers, refer to the data sheet for the Z8536 CIO device.

Serial Communications Interface

The MCP750HA uses a Zilog Z85230 Enhanced Serial Communications Controller(ESCC) to implement the two serialcommunications interfaces, which are routed through the transition module. The Z85230 supports synchronous (SDLC/HDLC) and asynchronous protocols. The MCP750HA hardware supports asynchronous serial baud rates of 110B/s to 38.4 KB/s.

Each interface supports the CTS, DCD, RTS, and DTR control signals as well as the TxD and RxD transmit/receive data signals, and TxC/RxC synchronousclock signals. Since not all modem control lines are available in the Z85230, a Z8536 CIO is used to provide the missing modem lines.

A PAL device performs decodingof register accessesand pseudo interrupt acknowledge cycles for the Z85230 and the Z8536 in ISA I/O space. The PBC controller supplies DMA support for the Z85230.

The Z85230 receives a 10 MHz clock input. The two synchronous ports will support data transfers up to 2.5 Mbits/sec. The Z85230 supplies an interruptvector during pseudo interrupt acknowledgecycles. The vectoris

3-16 Computer Group Literature Center Web Site

modified within the Z85230 according to the interrupt source. Interrupt request levels are programmed via the PBC. All modem control lines from the ESCC are multiplexed/de-multiplexed through J3 by the P2MX function due to I/O pin limitations. Refer to the Z85230 data sheet and to the MCP750 Single Board Computer Programmer's Reference Guide for additional information.

Z8536 CIO Device

The Z8536 CIO device complements the Z85230 ESCC by supplying modem control lines not provided by the Z85230 ESCC. In addition, the Z8536 CIO device has three independent 16-bit counters/ timers. The Z85230 receives a 5 MHz clock input.

MCP750HA Board Identifier

The MCP750HA CPU board is uniquely identified by the following registers:

❏ The CPU Configuration Register is an 8-bit register located at

ISA I/O address x0800. The CPUType field will return Eh for the MCP750HA.

Block Diagram

Table 3-3. Old CPU Configuration Register

REG Old CPU Configuration Register - $FE000800

BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0

FIELD CPUTYPE

OPER RR

RESET $E $F

http://www.motorola.com/computer/literature 3-17

Functional Description

❏ TheBaseModuleStatusRegisteris an 8-bit read-only register

locatedat ISAI/O addressx803. The BASE_TYPE fieldwill return E2h for the MCP750HA.

REG Base Module Status Register - Offset $0803

BIT SD7 SD6 SD5 SD4 SD3 S D2 SD1 SD0

FIELD BASE_TYPE

OPER R

RESET N/A

Table 3-4. Base Module Status Register

For information on user accessible registers, refer to the MCP750 Single Board Computer Programmer’s Reference Guide.

Base Module Feature Register

The Base Module Feature Register contains the details of the MCP750HA single-board computer’s configuration. It is an 8-bit read-only register located on the base board at ISA I/O address $0802.

REG Base Module Feature Register — Offset $0802

BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0

FIELD Not

Used

OPER RRR R R R R R

RESET 1 N/A 1 N/A 1 1 N/A 1

SCCP

∗ Not

Used

PMC1P∗ Not

Used

Not

Used

LANP∗ Not

Used

∗ Z85230 ESCC present. If set, there is no on-board synchronous

SCCP

serial support (the ESCC is not present). If cleared, the Z85230 ESCC is installed and there is on-board support for synchronous serial communication.

PMC1P

∗ PMC slot 1 present. If set, no PCI mezzanine card is installed in

PMC slot 1. If cleared, PMC slot 1 contains a PCI mezzanine card.

∗ Ethernet present. If set, no Ethernet transceiver interface is

LANP

installed. If cleared, there is on-board Ethernet support.

3-18 Computer Group Literature Center Web Site

Serial Port Signal Multiplexing

Due to pin limitations of the J3 connector, the MCP750HA multiplexes and de-multiplexes some signals between the MCP750HA board and the TMCP700 transition module. This hardware function is transparent to the software. The block diagram for the signal multiplexing is shown in Figure

3-3:

Block Diagram

MXDO

MXSYNC#

MXCLK

Serial

Figure 3-3. Serial Port Signal Multiplexing

Signal Multiplexing (MX)

There are four pins that are used for the MX function: MXCLK, MXSYNC#, MXDO,andMXDI.MXCLK is the 10 MHz bitclock for the time-multiplexed

data lines MXDO and MXDI. MXSYNC# is asserted for one bit time at Time Slot 15 by the MCP750HA board. MXSYNC# is used by the transition

Function

Connector

MXDI

http://www.motorola.com/computer/literature 3-19

Functional Description

module to synchronize with the MCP750HA board. MXDO is the timemultiplexed output line from the main board and MXDI is the timemultiplexed line from the transition module. A 16-to-1 multiplexing

scheme is used with 10 MHz bit rate. Sixteen Time Slots are defined and allocated as follows:

Table 3-5. Multiplexing Sequence of the MX Function

MXDO

(From MCP750HA)

TIME SLOT SIGNAL NAME TIME SLOT SIGNAL NAME

0RTS30CTS3 1DTR31DSR3/MID1 2 LLB3/MODSEL 2 DCD3 3 RLB3 3 TM3/MID0 4RTS44 RI3 5DTR45CTS4 6 LLB4 6 DSR4/MID3 7 RLB4 7 DCD4 8IDREQ8TM4/MID2

9Reserved9 RI4 10 Reserved 10 Reserved 11 Reserved 11 Reserved 12 Reserved 12 Reserved 13 Reserved 13 Reserved 14 Reserved 14 Reserved 15 Reserved 15 Reserved

MXDI

(From TMCP700)

The MX f unction is used with PALs and some discrete devices. MXSYNC# is clocked out using the falling edge of MXCLK,andMXDO by using the rising edge of the MXCLK. MXDI is sampled at the rising edge of MXCLK (thetransitionmodule synchronizesMXDI withMXCLK’s risingedge). The timing relationships among MXCLK, MXSYNC#, MXDO,andMXDI are shown in Figure 3-4:

3-20 Computer Group Literature Center Web Site

Block Diagram

Time Slot 15 Time Slot 0

CLK

SYNC#

RTS3 DTR3 LLB3 RLB3Reserved

CTS3 DSR3 DCD3 TM3Reserved

Figure 3-4. MX Signal Timings

ABORT(ABT) Switch (S2)

When activated by software, the ABORT switch can generate an interrupt signal to the processor. The interrupt is normally used to abort program execution and return control to the debugger firmware located in the MCP750HAand Flash memory. The interruptsignal reachesthe processor modulevia ISA bus interrupt line IRQ8 PB7 of the Z8536 CIO device, which handles various status signals, serial I/O lines, and counters.

Time Slot 1 Time Slot 2

∗. The signal is also availableat pin

Time Slot 3

The interrupter connectedto the ABORT switch is an edge-sensitive circuit, filtered to remove switch bounce.

RESET(RST) Switch (S1)

The RESET switch resets all onboard devicesand generates a CompactPCI backplane reset.

http://www.motorola.com/computer/literature 3-21

Functional Description

Reset and Abort Header (J21)

A three pin header is provided to facilitate remote reset and abort

operations. Connection to J21 will allow external stimulation of the Reset and Abort signal lines just as if the front panel switches were depressed. Refer to Chapter 4, Connector Pin Assignments, for the definition of pin assignments for the header.

Front Panel Indicators (DS1 - DS4)

There are four LEDs on the MCP750HA front panel:

❏ BFL (DS2, yellow). Board Failure; lights when the BRDFAIL∗ signal

line is active.

❏ CPU (DS4, green). C PU activity; lights when the DBB∗ (Data Bus

Busy) signal line on the processor bus is active.

❏ PCI (DS3, green). PCI activity; lights when the IRDY∗ (Initiator

Ready) signal line on the PCI bus is active. This indicates that the local PCI bus is active.

❏ CPCI (DS1, green). CPCI activity; lights when the IRDY* (Initiator

Ready) signal line on the CPCI bus is active. This indicates that the CPCI bus is active.

3-22 Computer Group Literature Center Web Site

Block Diagram

Fuses and Polyswitches (Resettable Fuses)

The MCP750HA provides current limit protection for the power rails. The voltages protected are +5VDC, PMC +5VDC, +3.3VDC, +12VDC and

-12VDC. Polyswitches are provided for both USB output voltages and keyboard/mouse Vcc. Table 3-6 lists the fuses with the voltages they protect.

Table 3-6. Fuse Assignments

Fuse# Type Voltage/Purpose/J Number Fuse

Rating

U63* Electronic +3.3VDC for onboard voltage, to J12 PMC connector

and to J3/J4 Transition module connectors.

U63 Electronic +5VDC for onboard voltage and to J3/J4/J5 Transition

module connectors

R391 Polyswitch +5VDC to J5 Transition module connector for

keyboard/mouse voltage (J5 - C21)

U63 Electronic +12VDC to J12 PMC (J12-1) connector and J3

Transition module connector (J3-B19)

U63 Electronic –12VDC to J11 PMC (J11-2) connector and J3

Transition module connector (J3-C19) R95 Polyswitch +5VDC to J18 USB Channel 0 connector (J5-C19) 1.1 Amps R2 Polyswitch +5VDC to J17 USB Channel 1 connector (J5-E18) 1.1 Amps

9.8 Amps

1.1 Amps

1Amp

Note *The main supply voltages are protected by an electronic circuit

breaker. The MCP750HA uses an LTC1643 hot swap controller devicefrom Linear Technologiesto implement fold-backcurrent limiting and overcurrent protection.

Speaker Control

The MCP750HA base board supplies a SPEAKER_OUT signal to the transitionmodule. The transition module containsa two pin jumper header (J13) which allows the speaker to obtain a beep tone.

http://www.motorola.com/computer/literature 3-23

SPEAKER_OUT signal to be cabled to an external

Functional Description

MPC750 Processor

The MCP750HA is designed t o support the enhanced version of the

Flash Memory

MPC750 360-pin BGA processor chip with 32MB to 256MB of ECC DRAM, 1 MB of level 2 cache (L2 cache), and up to 9MB of Flash memory. The L2 cache and 1MB of 16-bit Flash memory reside on the MCP750HA base board. The ECC DRAM and 8MB of additional (64-bit) FlashmemoryarelocatedontheRAM300memorymezzanine.

The MPC750 is a 64-bit processor with 64KB on-chip cache (32KB data cache and 32KB instruction cache). The L2 cache is implemented with an on-chip, two way set associative tag memory and with external synchronous SRAMs for data storage.

The Raven bridge controller ASIC provides the bridge between the MPC750microprocessorbus andthe PCI localbus.Electrically,the Raven chip is a 64-bit PCI connection. Four programmable map decoders in each direction provide flexible addressing between the MPC750 microprocessor bus and the PCI local bus.

The MCP750HA base board has provision for 1MB of 16-bit Flash memory in two 8-bit sockets. The RAM300 memory mezzanine accommodates 8MB of additional 64-bit Flash memory.

The onboard monitor/debugger, PPCBug, resides in the Flash chips. PPCBug provides functionality for:

❏ Booting the operating system ❏ Initializing after a reset ❏ Displaying and modifying configuration variables ❏ Running self-tests and diagnostics ❏ Updating firmware ROM

Under normal operation, the Flash devices are in read-only mode, their contents are pre-defined, and they are protected against inadvertent writes due to loss of power conditions. However, for programming purposes,

3-24 Computer Group Literature Center Web Site

programming voltage is always supplied to the devices and the Flash contents may be modified by executing the proper program command sequence. Refer to the third-party data sheet and/or to the PPCBug

Firmware Package User’s Manual, listed in Appendix C, Related

Documentation, for further device-specific information on modifying

Flash contents.

RAM300 Memory Module

The RAM 300 is the ECC DRAM memory mezzanine module that (together with an optional PCI mezzanine card) plugs into the base board to make a complete MCP750HA single-board computer. See Chapter 1,

Hardware Preparation and Installation, for more information.

RAM300 modules of 32, 64, 128, or 256MB are available for memory expansion. The ECC DRAM is controlled by the Falcon memory controllerchip set. The FalconASICs perform two-way interleaving, with double-bit error detection and single-bit error correction.

In addition to the ECC DRAM, the RAM300 module supplies 8MB of additionalsoldered-in 64-bit Flash memory. A jumperheader (J9) tells the Falcon chip set where in memory to fetch the board reset vector. Depending on the configuration of J9, resets execute either from Flash memory Bank A or from Bank B.

Block Diagram

Compact FLASH Memory Card

The MCP750HA supports a single EIDE compatible Compact FLASH Memory Card off of the PBC Primary EIDE interface. Currently available CompactFLASH memory cards provide from 2MB to 96MB of formatted capacity. Once configured, this memory will appear as a standard ATA (EIDE) disk drive.

TMCP700 Transition Module

The TMCP700 transition module (see Appendix B, Hardware

Preparationand Installation for TMCP700, for more information) is used

in conjunction with all models of the MCP750HA base board.

http://www.motorola.com/computer/literature 3-25

Functional Description

The features of the TMCP700 include:

❏ A parallel printer port (IEEE 1284-I compliant)

❏ Two EIA-232-D asynchronous serial ports (identifiedas COM1 and

COM2 on the front panel)

❏ Two synchronous serial ports (SERIAL 3 and SERIAL 4 on the front

panel), configured for EIA-232-D, EIA-530, V.35, or X.21 protocols

❏ Two Universal Serial Bus (USB) ports ❏ Two 60-pin Serial Interface Module (SIM) connectors ❏ A 40-pin header for the secondary EIDE port ❏ Two 64-pin headers for PMC IO ❏ A 34-pin header for a floppy port ❏ A 2-pin header for speaker output

Serial Interface Modules

The synchronous serial ports on the TMCP700 are configured via Serial Interface Modules (SIMs), used in conjunction with the appropriate jumper settings on the transition module. The SIMs are small plug-in printed circuit boards which contain all the circuitry needed to convert a TTL-level port to the standard voltage levels needed by various industrystandard serial interfaces, such as EIA-232, EIA-530, etc. SIMs are available for the following configurations:

Table 3-7. SIM Type Identification

Model Number Module Type

SIM232DCE EIA-232 DCE SIM232DTE EIA-232 DTE SIM530DCE EIA-530 DCE SIM530DTE EIA-530 DTE

3-26 Computer Group Literature Center Web Site

Block Diagram

Table 3-7. SIM Type Identification (Continued)

Model Number Module Type

SIMV35DCE V.35 DCE SIMV35DTE V.35 DTE SIMX21DCE X.21 DCE SIMX21DTE X.21 DTE

For additional information about the serial interface m odules, refer to the TMCP700 Transition Module Installation and Use manual, listed in

Appendix C, Related Documentation.

http://www.motorola.com/computer/literature 3-27

4Connector Pin Assignments

MCP750HA Connectors

This chapter summarizes the pin assignments for the following groups of connectors and headers for the MCP750HA:

❏ CompactPCI Connectors (J1/J2) ❏ CompactPCI HSC/User I/O Connector (J3) ❏ Local Bus Expansion Connector (J4) ❏ User I/O Connector (J5) ❏ PCI Mezzanine Card (PMC) Connectors (J11/J12/J13/J14) ❏ Front USB Connectors (J17/J18) ❏ 10BaseT/100BaseTX Connector (J8) ❏ COM1 Connector (J15)

❏ Reset/Abort Header (J21) ❏ Debug Connector (J16) ❏ DRAM Memory Mezzanine Connector (J7) ❏ EIDE Compact FLASH Memory Connector (J20)

Common Connectors

The following tables describe connectors used with the same pin assignments by the base board.

4-1

Connector Pin Assignments

CompactPCI Connectors (J1/J2)

The MCP750HA implements a 64-bit CompactPCI interface on connectors J1 and J2. J1 is a 110 pin AMP Z-pack 2mm hard metric type A connector with keying for +3.3V or +5V. J2 is a 110 pin AMP Z-pack 2mm hard metric type B connector. Each of these connectors conform to

25 +5V REQ64_L ENUM_L +3.3V +5V 25 24 AD1 +5V VIO AD0 ACK64_L 24 23 +3.3V AD4 AD3 +5V AD2 23 22 AD7 GND +3.3V AD6 AD5 22 21 +3.3V AD9 AD8 GND CBE0_L 21 20 AD12 GND VIO AD11 AD10 20 19 +3.3V AD15 AD14 GND AD13 19 18 SERR_L GND +3.3V PAR CBE1_L 18

the CompactPCI specification. The pinout for connectors J1 and J2 are shown below.

Table 4-1. CompactPCI Connector J1

ROWA ROWB ROWC ROWD ROWE

17 +3.3V SDONE SBO_L GND PERR_L 17 16 DEVSEL_L GND VIO STOP_L LOCK_L 16 15 +3.3v FRAME_L IRDY_L BD-SEL_L TRDY_L 15

12-14 KEY AREA 12-14

11 AD18 AD17 AD16 GND CBE2_L 11 10 AD21 GND +3.3V AD20 AD19 10

9 CBE3_L No Connect

(IDSEL) 8 AD26 GND VIO AD25 AD24 8 7 AD30 AD29 AD28 GND AD27 7 6 REQ_L GND +3.3v CLK AD31 6 5 No Connect

(BRSVP1A5)

4-2 Computer Group Literature Center Web Site

No Connect

(BRSVP1B5)

AD23 GND AD22 9

RST_L GND GNT_L 5

Common Connectors

Table 4-1. CompactPCI Connector J1 (Continued)

4 No Connect

(BRSVP1A4) 3 INTA_L INTB _L INTC _L +5V INTD_L 3 2TCK +5V TMSTDO TDI2 1 +5V -12V TRST_L +12V +5V 1

HEALTHY_L VIO No Connect

(INTP)

No Connect

(INTS)

Table 4-2. CompactPCI Connector J2

ROW A ROW B ROW C ROW D ROW E

22 No Connect

(RSV)

21 CLK6 GND No Connect

20 CLK5 GND No Connect

19 GND GND No Connect

18 No Connect

(BRSVP2A18)

17 No Connect

(BRSVP2A17)

No Connect

(RSV)

No Connect

(BRSVP2B18)

GND PRST_L REQ6_L GNT6_L 17

No Connect

(RSV)

No Connect

(BRSVP2C18)

No Connect

(RSV)

No Connect

(RSV)

GND No Connect

No Connect

(RSV)

GND No Connect

No Connect

(RSV)

No Connect

(RSV)

No Connect

(RSV)

BRSVP2E18

16 No Connect

(BRSVP2A16)

15 No Connect

(BRSVP2A15) 14 AD35 AD34 AD33 GND AD32 14 13 AD38 GND VIO AD37 AD36 13 12 AD42 AD41 AD40 GND AD39 12 11 AD45 GND VIO AD44 AD43 11 10 AD49 AD48 AD47 GND AD46 10

http://www.motorola.com/computer/literature 4-3

No Connect

(BRSVP2B16)

GND FAL_L REQ5_L GNT5_L 15

DEG_L GND No Connect

(BRSVP2E16)

Connector Pin Assignments

Table 4-2. CompactPCI Connector J2 (Continued)

9 AD52 GND VIO AD51 AD50 9 8 AD56 AD55 AD54 GND AD53 8 7 AD59 GND VIO AD58 AD57 7 6 AD63 AD62 AD61 GND AD60 6

5 CBE5_L GND VIO CBE4_L PAR64 5 4 VIO No Connect

(BRSVP2B4) 3 CLK4 GND GNT3_L REQ4_L GNT4_L 3 2 CLK2 CLK3 SYSEN_L GNT2_L REQ3_L 2 1 CLK1 GND REQ1_L GNT1_L REQ2_L 1

CBE7_L GND CBE6_L 4

CompactPCI HSC/User I/O Connector (J3)

ConnectorJ3 is a 95 pin (excluding row F) AMP Z-pack 2mm hard metric type B connector. This connector routes the I/O signals for the PMC I/O and serial channels. The pin assignments for J3 are as follows (outer row F is assigned and used as ground pins but is not shown in the table):

Table 4-3. J3 User I/O Connector

ROWA ROWB ROWC ROWD ROWE

19 Reserved +12V -12V RXD3 RXD4 19 18 HSC_EJECT_L GND RXC3 GND RXC4 18 17 HSC_FLOAT MXCLK MXDI MXSYNC_L MXDO 17 16 HSC_GNT_L GND TXC3 GND TXC4 16 15 HSC_REQ_L Reserved Reserved TXD3 TXD4 15 14 +3.3V +3.3V +3.3V +5V +5V 14 13 PMCIO5 PMCIO4 PMCIO3 PMCIO2 PMCIO1 13 12 PMCIO10 PMCIO9 PMCIO8 PMCIO7 PMCIO6 12 11 PMCIO15 PMCIO14 PMCIO13 PMCIO12 PMCIO11 11 10 PMCIO20 PMCIO19 PMCIO18 PMCIO17 PMCIO16 10 9 PMCIO25 PM CIO24 PMCIO23 PMCIO22 PMCIO21 9

4-4 Computer Group Literature Center Web Site

Common Connectors

Table 4-3. J3 User I /O Connector (Continued)

8 PMCIO30 PMCIO29 PMCIO28 PMCIO27 PMCIO26 8 7 PMCIO35 PMCIO34 PMCIO33 PMCIO32 PMCIO31 7 6 PMCIO40 PMCIO39 PMCIO38 PMCIO37 PMCIO36 6 5 PMCIO45 PMCIO44 PMCIO43 PMCIO42 PMCIO41 5 4 PMCIO50 PMCIO49 PMCIO48 PMCIO47 PMCIO46 4 3 PMCIO55 PMCIO54 PMCIO53 PMCIO52 PMCIO51 3 2 PMCIO60 PMCIO59 PMCIO58 PMCIO57 PMCIO56 2 1 VIO PMCIO64 PMCIO63 PMCIO62 PMCIO61 1

Local Bus Expansion Connector (J4)

ConnectorJ4 is a 110 pin AMP Z-pack2mm hard metric type A connector. This connector routes the 64-bit local PCI bus to the backplane for expansion. The pin assignments for J4 are as follows (the outer row F is assigned and used as ground pins but is not shown in the table):

Table 4-4. J4 Local PCI Expansion Connector

ROW A ROW B ROW C ROW D ROW E

25 AD36 AD35 AD34 AD33 AD32 25 24 AD40 AD39 AD38 GND AD37 24 23 AD45 AD44 AD43 AD42 AD41 23 22 AD49 3.3V AD48 AD47 AD46 22 21 AD53 AD52 AD51 GND AD50 21 20 AD57 3.3V AD56 AD55 AD54 20 19 AD61 AD60 AD59 GND AD58 19 18 CBE4# 3.3V PAR64 AD63 AD62 18 17 REQ64# CBE7# CBE6# GND CBE5# 17 16 AD2 3.3V AD1 AD0 ACK64# 16 15 AD6 AD5 AD4 GND AD3 15 12-14 KEY AREA 12-14

http://www.motorola.com/computer/literature 4-5

Connector Pin Assignments

Table 4-4. J4 Local PCI Expansion Connector (Continued)

11 AD9 AD8 CBE0# GND AD7 11 10 AD13 5.0V AD12 AD11 AD10 10 9 PAR CBE1# AD15 GND AD14 9 8 STOP# 5.0V LOCK# P ERR# SERR# 8

7 FRAME# IRDY# TRDY# GND DEVSEL# 7 6 AD18 5.0V AD17 AD16 CBE2# 6 5 AD21 CLK AD20 GND AD19 5 4 CBE3# 5.0V No Connect AD23 AD22 4 3 AD28 AD27 AD26 AD25 AD24 3 2 GNT# REQ# AD31 AD30 AD29 2 1 INTA# INTB# INTC# INTD# RST# 1

User I/O Connector (J5)

ConnectorJ5 isa 110 pin (excluding row F) AMP Z-pack 2mm hardmetric type B connector. This connector routes the I/O signals for the IDE (primary and secondary ports), the keyboard, the mouse, the two USB ports, and the printer ports. The pin assignments for J5 are as follows (the outer row F is assigned and used as ground pins but is not shown in the table):

Table 4-5. J5 User I/O Connector

ROW A ROW B ROW C ROW D ROW E

22 Reserved GRD Reserved +5V SPKROC_L 22 21 KBDDAT KBDCLK KBAUXVCC AUXDAT AUXCLK 21 20 Reserved Reserved Reserved GND Reserved 20 19 STB_L GND UVCC0 UDATA0+ UDATA0- 19 18 AFD_L UDATA1+ UDATA1- GND UVCC1 18 17 PD2 INIT_L PD1 ERR_L PD0 17 16 PD6 PD5 PD4 PD3 SLIN_L 16 15 SLCT PE BUSY ACK_L PD7 15

4-6 Computer Group Literature Center Web Site

Common Connectors

Table 4-5. J5 User I/O Connector (Continued)

14 RTSa CTSa RIa GND DTRa 14 13 DCDa +5V RXDa DSRa TXDa 13 12 RTSb CTSb RIb +5V DTRb 12 11 DCDb GND RXDb DSRb TXDb 11 10 TR0_L WPROT_L RDATA_L HDSEL_L DSKCHG_L 10 9 MTR1_L DIR_L STEP_L WDATA_L WGATE_L 9 8 RESERVED INDEX_L MTR0_L DS1_L DS0_L 8 7 CS1FX_L CS3FX_L DA1 DASP_L RESERVED 7 6 IOCS16_L GRD PDIAG_L DA0 DA2 6 5 DMARQ IORDY DIOW_L DMACK_L DIOR_L 5 4 DD14 DD0 GND DD15 INTRQ 4 3 DD3 DD12 DD2 D D13 DD1 3 2 DD9 DD5 DD10 DD4 DD11 2 1 RESET_L DRESET_L DD7 DD8 DD6 1

PCI Mezzanine Card Connectors (J11/J12/J13/J14)

Four 64-pin connectors (J11/J12/J13/J14 on the MCP750HA) supply the interface between the base board and an optional PCI mezzanine card (PMC). The pin assignments are listed in the following two tables:

Table 4-6. PCI Mezzanine Card Connector

J11 J12

1 TCK –12V 2 1 +12V TRST 3GND PMCINTA 5PMCINTB 7PMC1P 9PMCINTD 11 GND Not Used 12 11 Pull-up +3.3V 12 13PCICLK GND 1413PCIRST

http://www.motorola.com/computer/literature 4-7

∗ PMCINTC∗ 6 5 TDI GND 6

∗ +5V 8 7 GND Not Used 8

∗ NotUsed 10 9 NotUsed NotUsed 10

∗ 43TMS TDO 4

∗ Pull-down 14

∗ 2

Connector Pin Assignments

Table 4-6. PCI Mezzanine Card Connector (Continued)

15 GND PMC1GNT∗ 16 15 +3.3V Pull-down 16 17 PMC1REQ 19 +5V AD31 2 0 19 AD30 AD29 20 21 AD28 AD27 22 21 GND AD26 22

23 AD25 GND 24 23 AD24 +3.3V 24 25 GND CBE3 27 AD22 AD21 28 27 +3 .3V AD20 28 29 AD19 +5V 30 29 AD18 GND 30 31+5V AD17 3231AD16 C/BE2 33 FRAME 35 GND IRDY 37 DEVSEL 39 GND LOCK 41 SDONE 43 PAR GND 44 43 C/BE1 45 +5V AD15 4 6 45 AD14 AD13 46 47 AD12 AD11 48 47 GND AD10 48 49 AD09 +5V 50 49 AD08 +3.3V 50 51 GND C/BE0 53 AD06 AD05 54 53 +3.3V Not Used 54 55 AD04 GND 56 55 Not Used GND 56 57+5V AD03 5857NotUsed NotUsed 58 59 AD02 AD01 60 59 GND Not Used 60 61AD00 +5V 6261ACK64 63 GND REQ64

∗ +5V 18 17 Not Used GND 18

∗ 26 25 IDSEL AD23 26

∗ 32

∗ GND 34 33 GND Not Used 34

∗ 36 35 TRDY∗ +3.3V 36

∗ +5V 3837GND STOP∗ 38

∗ 40 39 PERR∗ GND 40

∗ SBO∗ 42 41 +3.3V SERR∗ 42

∗ GND 44

∗ 52 51 AD07 Not Used 52

∗ +3.3V 62

∗ 64 63 GND Not Used 64

4-8 Computer Group Literature Center Web Site

Common Connectors

Table 4-7. PCI Mezzanine Card Connector

J13 J14

1NotUsed GND 21PMCIO1 PMCIO22 3 GND C/BE7 5C/BE6 7C/BE4

∗ C/BE5∗ 6 5 PMCIO5 PMCIO6 6 ∗ GND 8 7 PMCIO7 PMCIO8 8

9 +5V (Vio) PAR64 10 9 PMCIO9 PMCIO10 10 11 AD63 AD62 12 11 PMCIO11 PMCIO12 12 13 AD61 GND 14 13 PMCIO13 PMCIO14 14 15GND AD60 1615PMCIO15 PMCIO1616 17 AD59 AD58 18 17 PMCIO17 PMCIO18 18 19 AD57 GND 20 19 PMCIO19 PMCIO20 20 21 +5V (Vio) AD56 22 21 PMCIO21 PMCIO22 22 23 AD55 AD54 24 23 PMCIO23 PMCIO24 24 25 AD53 GND 26 25 PMCIO25 PMCIO26 26 27GND AD52 2827PMCIO27 PMCIO2828 29 AD51 AD50 30 29 PMCIO29 PMCIO30 30 31 AD49 GND 32 31 PMCIO31 PMCIO32 32 33GND AD48 3433PMCIO33 PMCIO3434 35 AD47 AD46 36 35 PMCIO35 PMCIO36 36 37 AD45 GND 38 37 PMCIO37 PMCIO38 38 39 +5V (Vio) AD44 40 39 PMCIO39 PMCIO40 40 41 AD43 AD42 42 41 PMCIO41 PMCIO42 42 43 AD41 GND 44 43 PMCIO43 PMCIO44 44 45GND AD40 4645PMCIO45 PMCIO4646 47 AD39 AD38 48 47 PMCIO47 PMCIO48 48 49 AD37 GND 50 49 PMCIO49 PMCIO50 50 51GND AD36 5251PMCIO51 PMCIO5252 53 AD35 AD34 54 53 PMCIO53 PMCIO54 54 55 AD33 GND 56 55 PMCIO55 PMCIO56 56

∗ 4 3 PMCIO3 PMCIO4 4

http://www.motorola.com/computer/literature 4-9

Connector Pin Assignments

Table 4-7. PCI Mezzanine Card Connector

57 +5V (Vio) AD32 58 57 PMCIO57 PMCIO58 58 59 Not Used Not Used 60 59 PMCIO59 PMCIO60 60 61 Not Used GND 62 61 PMCIO61 PMCIO62 62 63 GND Not Used 64 63 PMCIO63 PMCIO64 64

Front USB Connectors (J17/J18)

Two USB Series A receptacles are located at the front panel of the MCP750HA SBC. The pin assignments for these connectors are as follows:

Table 4-8. USB 0 Connector J18

1 UVCC0 2 UDATA0N 3 UDATA0P 4 GND

Table 4-9. USB 1 Connector J17

1 UVCC1 2 UDATA1N 3 UDATA1P 4 GND

10BaseT/100BaseTX Connector (J8)

The 10BaseT/100BaseTX Connector is an RJ45 connector located on the front panel of the MCP750HA SBC. The pin assignments for this connector are as follows:

4-10 Computer Group Literature Center Web Site

Table 4-10. 10BaseT/100BaseTX Connector J8

COM1 Connector (J15)

A standard DB9 receptacleis located on the frontpanel of the MCP750HA to provide the interface to the COM1 serial port. These COM1 signals are also routed to J11 on the transition module. A terminal may be connected to J15 or J11 on the transition module but not both at the same time. The pin assignments for this connector is as follows:

1TD+ 2TD3RD+ 4ACTerminated 5ACTerminated 6RD7ACTerminated 8ACTerminated

Common Connectors

Table 4-11. COM1 Connector J15

1DCD 2RXD 3TXD 4DTR 5 GND 6DSR 7RTS 8CTS 9RI

http://www.motorola.com/computer/literature 4-11

Connector Pin Assignments

Reset and Abort Header (J21)

A three-pin header is provided to facilitate remote reset and abort operations. Connection to J21 will allow external stimulation of the Reset and Abort signal lines just as if the front panel switches were depressed. The reset and abort signal lines must be asserted for a minimum time

period of 10 microseconds to assure the input will take effect. The connector pin-out is defined below.

Table 4-12. Reset/Abort Header J21

1 ABORT_L (Active low processor abort) 2 GND (Ground) 3 RESET_L (Active low board reset)

Debug Connector (J16)

A 190-pin connector (J16 on the MCP750HA base board) provides access to the processor bus (MPU bus) and some bridge/memory controller signals. It can be used for debugging purposes. The pin assignments are listed in the following table.

Table 4-13. Debug Connector (J16)

1PA0 PA1 2 3PA2 PA3 4 5PA4 PA5 6 7PA6 PA7 8 9PA8 PA9 10 11 P A10 P A11 12 13 PA12 PA13 14 15 PA14 PA15 16 17 PA16 PA17 18 19 PA18 GND PA19 20 21 PA20 PA21 22 23 PA22 PA23 24

4-12 Computer Group Literature Center Web Site

Common Connectors

Table 4-13. Debug Connector (J16) (Continued)

25 PA24 PA25 26 27 PA26 PA27 28 29 PA28 PA29 30 31 PA30 PA31 32 33 PA_PAR0 PA_PAR1 34 35 PA_PAR2 PA_PAR3 36 37 APE 39 PD0 PD1 40 41 PD2 PD3 42 43 PD4 PD5 44 45 PD6 PD7 46 47 PD8 PD9 48 49 PD10 PD11 50 51 PD12 PD13 52 53 PD14 PD15 54 55 PD16 PD17 56 57 PD18 +5V PD19 58 59 PA20 PD21 60 61 PD22 PD23 62 63 PD24 PD25 64 65 PD26 PD27 66 67 PD28 PD29 68 69 PD30 PD31 70 71 PD32 PD33 72 73 PD34 PD35 74 75 PD36 PD37 76 77 PD38 PD39 78 79 PD40 PD41 80 81 PD42 PD43 82 83 PD44 PD45 84

∗ RSRV∗ 38

http://www.motorola.com/computer/literature 4-13

Connector Pin Assignments

Table 4-13. Debug Connector (J16) (Continued)

85 PD46 PD47 86 87 PD48 PD49 88 89 PA50 PD51 90 91 PD52 PD53 92

93 PD54 PD55 94 95 PD56 GND PD57 96 97 PD58 PD59 98 99 PD60 PD61 100 101 PD62 PD63 102 103 PDPAR0 PDPAR1 104 105 PDPAR2 PDPAR3 106 107 PDPAR4 PDPAR5 108 109 PDPAR6 PDPAR7 110 111 No Connection No Connection 112 113 DPE

∗ DBDIS∗ 114

115 TT0 TSIZ0 116 117 TT1 TSIZ1 118 119 TT2 TSIZ2 120 121 TT3 No Connection 122 123 TT4 No Connection 124 125 CI 127 WT 129 GLOBAL 131 SHARED 133 AACK 135 ARTY 137 DRTY 139 TA 141 TEA 143 No Connection DBG

∗ No Connection 126

∗ No Connection 128

∗ No Connection 130 ∗ DBWO∗ 132

∗ +3.3V TS∗ 134 ∗ XATS∗ 136 ∗ TBST∗ 138

∗ No Connection 140

∗ No Connection 142

∗ 144

4-14 Computer Group Literature Center Web Site

Common Connectors

Table 4-13. Debug Connector (J16) (Continued)

145 No Connection DBB∗ 146 147 No Connection ABB 149 TCLK_OUT MPUBG-0 151 No Connection MPUBR0 153 MPUBR1 155 M PUBG1 157 WDT1TO 159 WDT2TO 161 L2BR 163 L2BG 165 CLAIM

∗ IRQ0∗ 154 ∗ MCHK∗ 156 ∗ SMI∗ 158

∗ CKSTPI∗ 160 ∗ CKSTPO∗ 162 ∗ HALTED (N/C) 164

∗ TLBISYNC∗ 166

167 No Connection TBEN 168 169 No Connection 171 No Connection 173 No Connection

∗ No Connection 170 ∗ GND No Connection 172 ∗ No Connection 174

175 No Connection NAPRUN 176 177 SRST1 179 SRESET 181 HRESET

∗ QREQ∗ 178

∗ QACK∗ 180

∗ CPUTDO 182

183 GND CPUTDI 184 185 CPUCLK1 CPUTCK 186 187 No Connection CPUTMS 188 189 No Connection CPUTRST

∗ 148

∗ 150

∗ 152

∗ 190

http://www.motorola.com/computer/literature 4-15

Connector Pin Assignments

DRAM Mezzanine Connector (J7)

A 190-pin connector (J7 on the MCP750HA base board) supplies the interface between the memory bus and the RAM300 DRAM mezzanine. The pin assignments are listed in the following table.

Table 4-14. DRAM M ezzanine Connector (J7)

1A_RAS∗ A_CAS∗ 2 3B_RAS 5C_RAS 7D_RAS 9OEL 11 WEL 13 ROMACS 15 RAMAEN RAMBEN 16 17 RAMCEN EN5VPWR 18 19 RAL0 GND RAL1 20 21 RAL2 RAL3 22 23 RAL4 RAL5 24 25 RAL6 RAL7 26 27 RAL8 RAL9 28 29 RAL10 RAL11 30 31 RAL12 RAU0 32 33 RAU1 RAU2 34 35 RAU3 RAU4 36 37 RAU5 RAU6 38 39 RAU7 RAU8 40 41 RAU9 RAU10 42 43 RAU11 RAU12 44 45 RDL0 RDL1 46 47 RDL2 RDL3 48 49 RDL4 RDL5 50

∗ B_CAS∗ 4 ∗ C_CAS∗ 6

∗ D_CAS∗ 8

∗ OEU∗ 10

∗ WEU∗ 12

∗ ROMBCS∗ 14

4-16 Computer Group Literature Center Web Site

Common Connectors

Table 4-14. DRAM Mezzanine Connector (J7) (Continued)

51 RDL6 RDL7 52 53 RDL8 RDL9 54 55 RDL10 RDL11 56 57 RDL12 +5V RDL13 58 59 RDL14 RDL15 60 61 RDL16 RDL17 62 63 RDL18 RDL19 64 65 RDL20 RDL21 66 67 RDL22 RDL23 68 69 RDL24 RDL25 70 71 RDL26 RDL27 72 73 RDL28 RDL29 74 75 RDL30 RDL31 76 77 RDL32 RDL33 78 79 RDL34 RDL35 80 81 RDL36 RDL37 82 83 RDL38 RDL39 84 85 RDL40 RDL41 86 87 RDL42 RDL43 88 89 RDL44 RDL45 90 91 RDL46 RDL47 92 93 RDL48 RDL49 94 95 RDL50 GND RDL51 96 97 RDL52 RDL53 98 99 RDL54 RDL55 100 101 RDL56 RDL57 102 103 RDL58 RDL59 104 105 RDL60 RDL61 106 107 RDL62 RDL63 108 109 CDL0 CDL1 110

http://www.motorola.com/computer/literature 4-17

Connector Pin Assignments

Table 4-14. DRAM Mezzanine Connector (J7) (Continued)

111 CDL2 CDL3 112 113 CDL4 CDL5 114 115 CDL6 CDL7 116 117 No Connection No Connection 118

119 RDU0 RDU1 120 121 RDU2 RDU3 122 123 RDU4 RDU5 124 125 RDU6 RDU7 126 127 RDU8 RDU9 128 129 RDU10 RDU11 130 131 RDU12 RDU13 132 133 RDU14 +3.3V RDU15 134 135 RDU16 RDU17 136 137 RDU18 RDU19 138 139 RDU20 RDU21 140 141 RDU22 RDU23 142 143 RDU24 RDU25 144 145 RDU26 RDU27 146 147 RDU28 RDU29 148 149 RDU30 RDU31 150 151 RDU32 RDU33 152 137 RDU18 RDU19 138 139 RDU20 RDU21 140 141 RDU22 RDU23 142 143 RDU24 RDU25 144 145 RDU26 RDU27 146 147 RDU28 RDU29 148 149 RDU30 RDU31 150 151 RDU32 RDU33 152

4-18 Computer Group Literature Center Web Site

Common Connectors

Table 4-14. DRAM Mezzanine Connector (J7) (Continued)

153 RDU34 RDU35 154 155 RDU36 RDU37 156 157 RDU38 RDU39 158 159 RDU40 RDU41 160 161 RDU42 RDU43 162 163 RDU44 RDU45 164 165 RDU46 RDU47 166 167 RDU48 RDU49 168 169 RDU50 RDU51 170 171 RDU52 GND RDU53 172 173 RDU54 RDU55 174 175 RDU56 RDU57 176 177 RDU58 RDU59 178 179 RDU60 RDU61 180 181 RDU62 RDU63 182 183 CDU0 CDU1 184 185 CDU2 CDU3 186 187 CDU4 CDU5 188 189 CDU6 CDU7 190

EIDE Compact FLASH Connector (J20)

A 50-pin Compact FLASH card header connector provides the EIDE interface to the Compact FLASH Memory Card. The pin assignments for this connector are as follows:

Table 4-15. EIDE Compact FLASH Connector J20

1 GND DATA3 2 3 DATA4 DATA5 4 5 DATA6 DATA7 6 7 DCS1A_L GND 8

http://www.motorola.com/computer/literature 4-19

Connector Pin Assignments

Table 4-15. EIDE Compact FLASH Connector J20 (Continued)

9 GND GND 10 11 GND GND 12 13 +5V GND 14 15 GND GND 16

17 GND DA2 18 19 DA1 DA0 20 21 DATA0 DATA1 22 23 DATA2 NO CONNECT 24 25 CD2_L CD1_L 26 27 DATA11 DATA12 28 29 DATA13 DATA14 30 31 DATA15 DCS3A_L 32 33 NO CONNECT DIORA_L 34 35 DIOWA_L NO CONNECT 36 37 INTRQA +5V 38 39 MASTER/SLAVE NO CONNECT 40 41 RST_L DIORDYA 42 43 NO CONNECT NO CONNECT 44 45 NO CONNECT NO CONNECT 46 47 DATA8 DATA9 48 49 DATA10 GND 50

4-20 Computer Group Literature Center Web Site

PPCBug Overview

The PPCBug firmware is the layer of software just above the hardware. The firmware provides the proper initialization for the devices on the MCP750HA baseboard upon power-up or reset.

This chapter provides information on the PPCBug and its architecture. Additionally,it describes the monitor (interactive command portion of the firmware), and provides instructions on using the PPCBug debugger and the associated special commands. A complete list of PPCBug commands is also included i n this chapter.

Chapter 6, CNFG and ENV Commands, contains information about the

CNFG and ENV commands, system calls, and other advanced user topics. For additional information about the PPCBug, refer to the PPCBug

FirmwarePackage User’s Manual,thePPCBug DiagnosticsManual, and the CPX750 High Availability PPCBug Firmware User’s Manual . Each of these manuals is listed in Appendix C, Related Documentation.

5PPCBug

PPCBug Basics

The PowerPC debug firmware (PPCBug) is a powerful evaluation and debugging tool for systems built around the Motorola PowerPC microcomputers. Facilities are available for loading and executing user programs under complete operator control for system evaluation.

The PPCBug provides a high degree of functionality, user friendliness, portability, and e ase of maintenance.

It is portable and easy to understand because it was written entirely in the C programming language, except where necessary to use assembler functions.

The PPCBug includes commands for:

5-1

PPCBug

❏ Display and modification of memory ❏ Breakpoint and tracing capabilities ❏ A powerful assembler and disassembler useful for patching

programs

❏ A self-test at power-up feature which verifies the integrity of the

system

The PPCBug consists of three parts:

❏ A command-driven, user-interactive software debugger,described

in the PPCBug Firmware Package User’s Manual, listed in

Appendix C, Related Documentation. It is also referred to as the

debugger or PPCBug.

❏ A command-driven diagnostics package for the MCP750HA

hardware, also referred to as the diagnostics. The diagnostics package is described in the PPCBug Diagnostics Manual.

❏ A user interface or debug/diagnostics monitor that accepts

commands from the system console terminal.

When using the PPCBug, you operate out of either the debugger directory or the diagnostic directory.

❏ If you are in the debugger directory, the debugger prompt

<PPC1(A)-Bug> is displayed and you have all of the debugger

commands at your disposal.

❏ If you are in the diagnostic directory, the diagnostic prompt

<PPC1(A)-Diag> is displayed and you have all of the diagnostic

commands at your disposal as well as all of the debugger commands.

Use the SD command to switch back and forth between these directories. BecausePPCBug is command-driven, it performs its variousoperations in

response to user commands entered at the keyboard. When you enter a command, PPCBug executes the command and the prompt reappears.

5-2 Computer Group Literature Center Web Site

However,if you enter acommand that causes executionof user targetcode (for example, GO), then control may or may not return to PPCBug, depending on the outcome of the user program.

Memory Requirements

PPCBug requires a maximum of 768KB of read/write memory (DRAM). The debugger allocates this space from the top of memory. For example, a system containing 64MB ($04000000) of read/write memory will place the PPCBug memory page at locations $03F80000 to $03FFFFFF.

PPCBug Implementation

PPCBug is written largely in the C programming language, providing benefits of portability and maintainability. Where necessary, assembly language has been used in the form of separately compiled program modulescontaining onlyassembler code. No mixed-languagemodules are used.

Physically, PPCBug is c ontained in two socketed 32-pin PLCC Flash devices that together provide 1MB of storage. The executable code is checksummed at every power-on or reset firmware entry, and the result (which includes a precalculated checksum contained in the Flash devices) is verified against the expected checksum.

MPU, Hardware, and Firmware Initialization

The debugger performs the MPU, hardware, and firmware initialization process.This processoccurseach time theMCP750HA is resetor powered up. The steps below represent high-level outline (not all of the detailed steps are listed):

1. Sets MPU.MSR to known value.

2. Invalidates the MPU's data/instruction caches.

3. Clears all segment registers of the MPU.

http://www.motorola.com/computer/literature 5-3

PPCBug

4. Clears all block address translation registers of the MPU.

5. Initializes the MPU-bus-to-PCI-bus bridge device.

6. Initializes the PCI-bus-to-ISA-bus bridge device.

7. Calculate the external bus clock speed of the MPU.

8. Delays for 750 milliseconds.

9. Determines the CPU board type.

10. Sizes the local read/write memory (DRAM).

11. Initializes the read/write memory controller.

12. Sets base address of memory to $00000000.

13. Retrieves the speed of read/write memory from NVRAM.

14. Initializes the read/write memory controller with the speed of read/write memory.

15. Retrieves the speed of read only memory (Flash) from NVRAM .

16. Initializes the read only memory controller with the speed of read only memory.

17. Enables the M PU's instruction cache.

18. Copies the MPU's exception vector table from $FFF00000 to $00000000.

19. Initializes the PC87307 resources’ base addresses.

20. Verifies MPU type.

21. Enable the super-scalar feature of the MPU (boards with M PC750 type chips only).

22. Initialize the Keyboard Controller (PC87307).

23. Determines the debugger's console/host ports, and initializes the appropriate devices (PC16550/GD54xx/Z85C230).

24. Displays the debugger's copyright message.

5-4 Computer Group Literature Center Web Site

MPU, Hardware, and Firmware Initialization

25. Displays any hardware initialization errors that may have occurred.

26. Checksums the debugger object, and displays a warning message if the checksum failed to verify.

27. Displays the amount of local read/write memory found.

28. Verifies the configuration data that is resident in NVRAM, and displays a warning message if the verification failed.

29. Calculatesand displays theMPU clock speed,verifies thatthe MPU clock speed matches the configuration data, and displays a warning message if the verification fails.

30. Displays the BUS clock speed, verifies that the BUS clock speed matches the configuration data, and displays a warning message if the verification fails.

31. Displays any Keyboard Controller initialization error that occurs.

32. Probes PCI bus for supported network devices.

33. Probes PCI bus for supported mass storage devices.

34. Initializes the memory/IO addresses for the supported PCI bus devices.

35. Executes Self-Test, if so configured. (Default is no Self-Test.)

36. Extinguishes the board fail LED, if there are no self-test failures or initialization/configuration errors.

37. Executes the configured boot routine, either ROMboot, Autoboot, or Network Autoboot.

38. Executes the user interface (displays the

<PPC1(A)-Diag> prompt).

<PPC1(A)-Bug> or

http://www.motorola.com/computer/literature 5-5

PPCBug

Using PPCBug

PPCBugis command-driven;it performsits variousoperations inresponse to commands that you enter at the keyboard. When the prompt appears on the screen, the debugger is ready to accept debugger commands. When the debugger is ready to accept diagnostic commands. To switch from one mode to the other, enter SD.

<PPC1(A)-Bug>

PPC1(A)-Diag> prompt appears on the screen, the

What you key in is stored in an internal buffer. Executionbegins only after you press the Return (Enter) key. This allows you to correct entry errors (if necessary) with the control characters described in the PPCBug Firmware Package User’s Manual.

After the debugger executes the command, the prompt reappears. However, if the command causes execution of user target code (for example, GO) then control m ay or may not return to the debugger, dependingon whatthe user programdoes. For example, if abreakpoint has been specified, then control returns to the debugger when the breakpointis encountered during execution of the user program. Alternately, the user programcould returnto the debuggerby means ofthe System CallHandler routine RETURN, described in the PPCBug Firmware Package User’s Manual, listed in Appendix C, Related Documentation. For additional information about this topic, refer to the GD, GO,andGT command descriptions in the PPCBug Firmware Package User’s Manual.

A debugger command is made up of the following parts:

❏ The command name in upper or lowercase, for example, MD or md. ❏ Any required arguments, as specified by command. ❏ At least one space before the first argument. Precede all other

arguments with either a space or comma.

❏ One or more options. Precede an option or a string of options with

a semicolon (;). If no option is entered, the command’s default option conditions are used.

5-6 Computer Group Literature Center Web Site

Debugger Commands

Debugger commands provide an interactive means for loading and executing applications in a controlled manner, so that they may be evaluated. The debugger includes commands for:

❏ The display and modification of memory ❏ Breakpoint and tracing capabilities

Using PPCBug

❏ Assembler and disassembler

Standard Commands

Standard debugger commands are listed in the following table. They are described in more detail in the PPCBug Firmware Package User’s Manual, listed in Appendix C, Related Documentation.

Note You can list all the available debugger commands by entering the

Command Description

AS One Line Assembler BC Block of Memory Compare BF Blockof Memory Fill BI Block of Memory Initialize BM Block of Memory Move

Help (HE) command alone. You can view the syntax (description)for a particularcommand by entering HE, followed by a space,followed by the particular command mnemoniclisted below, followed by a carriage return. Keep in mind that help is now available on both the BUG and DIAG side. In addition, issuing help on a DIAG test category will give more information about the tests in that category. The latter is accomplished by entering HE, followed by a space, followed by the test category description (for example, UART), followed by a carriage return

Table 5-1. Debugger Commands

http://www.motorola.com/computer/literature 5-7

PPCBug

Table 5-1. Debugger Commands (Continued)

Command Description

BR Breakpoint Insert NOBR Breakpoint Delete BS Block of Memory Search BV Block of Memory Verify CM Concurrent Mode

NOCM No Concurrent Mode CNFG Configure Board Information Block CS Checksum CSAR PCI Configuration Space READ Access CSAW PCI Configuration Space WRITE Access DC Data Conversion DS One Line Disassembler DU Dump S-Records ECHO Echo String ENV Set Environment GD Go Direct (Ignore Breakpoints) GEVBOOT Global Environment Variable Boot GEVDEL Global Environment Variable Delete GEVDUMP G lobal Environment Variable(s) Dump GEVEDIT Global Environment Variable Edit GEVINIT Global Environment Variable Initialization GEVSHOW Global Environment Variable(s) Display GN Go to Next Instruction GO Go Execute User Program GT Go to Temporary Breakpoint HE Help IOC I/O Control for Disk IOI I/O Inquiry IOP I/O Physical (Direct Disk Access)

5-8 Computer Group Literature Center Web Site

Motorola MCP750HA, MCP750HA-1252-F, MCP750HA-1232-F, MCP750HA-233-F, MCP750HA-366-F Installation And Use Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

About This Manual

Summary of Changes

Overview of Contents

Comments and Suggestions

Conventions Used in This Manual

Introduction

Equipment Required

Overview of Start-up Procedure

Unpacking Instructions

Hardware Configuration

MCP750HA Base Board Preparation

Flash Bank Selection (J9)

Hardware Installation

ESD Precautions

Compact FLASH Memory Card Installation

RAM300 Memory Mezzanine Installation

PMC Module Installation

MCP750HA Module Installation

System Considerations

MCP750HA Module Power Requirements

2Operating Instructions

Introduction

Applying Power

Memory Maps

Processor Memory Map

Default Processor Memory Map

PCI Local Bus Memory Map

CompactPCI Memory Map

PCI Arbitration

Interrupt Handling

DMA Channels

Sources of Reset

Endian Issues

Processor/Memory Domain

Role of the Raven ASIC

PCI Domain

PCI and Ethernet

3Functional Description

Introduction

Features

General Description

Block Diagram

Hot Swap Circuitry

CompactPCI Interface

PCI Expansion Connector (J4)

Domain Ownership

Ethernet Interface

PCI Mezzanine Interface

PC97307 ISA Super I/O Device

Asynchronous Serial Ports

Parallel Port/Printer Interface

Floppy Disk/Tape Drive Controller

Keyboard and Mouse Interface

PCI Peripheral Bus Controller (PBC)

EIDE Series Termination

Real-Time Clock/NVRAM/Watchdog Timer Function

Programmable Timers

Raven General Purpose Timers

Raven Watchdog Timers

M48T559 Watchdog Timer

Interval Timers

16-Bit Timers

Serial Communications Interface

Z8536 CIO Device

MCP750HA Board Identifier

Base Module Feature Register

Serial Port Signal Multiplexing

Signal Multiplexing (MX)

ABORT(ABT) Switch (S2)

RESET(RST) Switch (S1)

Reset and Abort Header (J21)

Front Panel Indicators (DS1 - DS4)

Fuses and Polyswitches (Resettable Fuses)

Speaker Control

MPC750 Processor

Flash Memory