MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
128K x 8 Bit Fast Static Random
Access Memory
Order this document
by MCM6726C/D
MCM6726C
The MCM6726C is a 1,048,576 bit static random access memory organized
as 131,072 words of 8 bits. Static design eliminates the need for external clocks
or timing strobes.
Output enable (G
) is a special control feature that provides increased system
flexibility and eliminates bus contention problems.
This device meets JEDEC standards for functionality and revolutionary pinout,
and is available in a 400 mil plastic small–outline J–leaded package.
• Single 5 V ± 10% Power Supply
• Fully Static — No Clock or Timing Strobes Necessary
• All Inputs and Outputs Are TTL Compatible
• Three State Outputs
• Fast Access Times: 6, 7 ns
• Center Power and I/O Pins for Reduced Noise
BLOCK DIAGRAM
A
A
A
A
A
A
A
A
ROW
DECODER
MEMORY
MATRIX
512 ROWS x 256 x 8
COLUMNS
V
CC
V
SS
WJ PACKAGE
400 MIL SOJ
CASE 857A–02
PIN ASSIGNMENT
AA
1
A
2
A
3
A
4
E
5
DQ
6
DQ
7
V
8
CC
V
9
SS
DQ
10
DQ
11
W
12
A
13
A
14
A
15
A
16
32
A
31
A
30
A
29
G
28
DQ
27
DQ
26
V
SS
25
V
CC
24
DQ
23
DQ
22
A
21
A
20
A
19
A
18
A
17
DQ
INPUT
DATA
CONTROL
DQ
E
W
G
REV 3
3/7/97
Motorola, Inc. 1997
MOTOROLA FAST SRAM
COLUMN I/O
COLUMN DECODER
AA A A
A A A A
PIN NAMES
A Address Input. . . . . . . . . . . . . . . . . . . .
E
A
W
G
DQ Data Input/Output. . . . . . . . . . . . . . .
V
CC
V
SS
Chip Enable. . . . . . . . . . . . . . . . . . . . . .
Write Enable. . . . . . . . . . . . . . . . . . . .
Output Enable. . . . . . . . . . . . . . . . . . .
+ 5 V Power Supply. . . . . . . . . . . .
Ground. . . . . . . . . . . . . . . . . . . . . . .
MCM6726C
1
TRUTH TABLE (X = Don’t Care)
G W Mode VCC Current Output Cycle
E
H X X Not Selected I
L H H Output Disabled I
L L H Read I
L X L Write I
SB1
, I
CCA
CCA
CCA
SB2
High–Z —
High–Z —
D
out
High–Z Write Cycle
Read Cycle
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating
Power Supply Voltage V
Voltage Relative to VSS for Any Pin Except
V
CC
Output Current I
Power Dissipation P
Temperature Under Bias T
Operating Temperature T
Storage Temperature — Plastic T
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
Symbol Value Unit
CC
Vin, V
out
bias
stg
out
D
A
– 0.5 to + 7.0 V
– 0.5 to VCC + 0.5 V
± 30 mA
1.5 W
– 10 to + 85 °C
0 to + 70 °C
– 55 to + 125 °C
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid application of any voltage higher than maximum
rated voltages to these high–impedance circuits.
This BiCMOS memory circuit has been designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
and transverse air flow of at least 500 linear feet
per minute is maintained.
DC OPERA TING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Typ Max Unit
Supply Voltage (Operating Voltage Range) V
Input High Voltage V
Input Low Voltage V
**VIL (min) = –0.5 V dc; VIL (min) = –2.0 V ac (pulse width ≤ 2.0 ns) for I ≤ 20.0 mA.
** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width ≤ 2.0 ns) for I ≤ 20.0 mA.
CC
IH
IL
DC CHARACTERISTICS
Parameter Symbol Min Max Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC) I
Output Leakage Current (E = VIH, V
Output Low Voltage (IOL = + 8.0 mA) V
Output High Voltage (IOH = – 4.0 mA) V
= 0 to VCC) I
out
POWER SUPPLY CURRENTS
Parameter Symbol MCM6726C–6 MCM6726C–7 Unit Notes
AC Active Supply Current (I
Active Quiescent Current (E = VIL, VCC = max, f = 0 MHz) I
AC Standby Current (E = VIH, VCC = max, f = f
CMOS Standby Current (VCC = max, f = 0 MHz, E ≥ VCC – 0.2 V,
Vin ≤ VSS + 0.2 V, or ≥ VCC – 0.2 V)
NOTES:
1. Reference AC Operating Conditions and Characterisitics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3 V, VIH = 3 V).
2. All addresses transition simultaneously low (LSB) and then high (MSB).
3. Data States are all zero.
= 0 mA) (VCC = max, f = f
out
max
) I
max
) I
CCA
CC2
SB1
I
SB2
4.5 5.0 5.5 V
2.2 —
– 0.5*
lkg(I)
lkg(O)
OL
OH
250 220 mA 1, 2, 3
100 100 mA
100 100 mA 1, 2, 3
60 60 mA
— 0.8 V
— ±1.0 µA
— ±1.0 µA
— 0.4 V
2.4 — V
VCC + 0.3**
V
MCM6726C
2
MOTOROLA FAST SRAM
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T
Address Input Capacitance C
Control Pin Input Capacitance C
Input/Output Capacitance C
= 25°C, Periodically Sampled Rather Than 100% Tested)
A
Parameter
Symbol Typ Max Unit
in
in
I/O
— 6 pF
— 6 pF
— 8 pF
AC OPERA TING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ±10%, TA = 0 to +70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .
Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time 2 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ CYCLE TIMING (See Notes 1 and 2)
Parameter Symbol Min Max Min Max Unit Notes
Read Cycle Time t
Address Access Time t
Enable Access Time t
Output Enable Access Time t
Output Hold from Address Change t
Enable Low to Output Active t
Output Enable Low to Output Active t
Enable High to Output High–Z t
Output Enable High to Output High–Z t
NOTES:
1. W
is high for read cycle.
2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3. All read cycle timings are referenced from the last valid address to the first transitioning address.
4. At any given voltage and temperature, t
to device.
5. Transition is measured 200 mV from steady–state voltage with load of Figure 1b.
6. This parameter is sampled and not 100% tested.
7. Device is continuously selected (E
8. Addresses valid prior to or coincident with E
= VIL, G = VIL).
EHQZ
max < t
going low.
ELQX
min, and t
Output Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . .
Output Load See Figure 1a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCM6726C–6 MCM6726C–7
AVAV
AVQV
ELQV
GLQV
AXQX
ELQX
GLQX
EHQZ
GHQZ
GHQZ
6 — 7 — ns 3
— 6 — 7 ns
— 6 — 7 ns
— 4 — 4 ns
2 — 2 — ns
3 — 3 — ns 4,5,6
0 — 0 — ns 4,5,6
— 3 — 3.5 ns 4,5,6
— 3 — 3.5 ns 4,5,6
max < t
min, both for a given device and from device
GLQX
OUTPUT
Z0 = 50
Ω
(a) (b)
MOTOROLA FAST SRAM
RL = 50
VL = 1.5 V
TIMING LIMITS
+5 V
480
Ω
OUTPUT
Ω
255
Ω
5 pF
The table of timing values shows either a
minimum or a maximum limit for each parameter. Input requirements are specified from
the external system point of view. Thus, address setup time is shown as a minimum
since the system must supply at least that
much time. On the other hand, responses
from the memory are specified from the device point of view. Thus, the access time is
shown as a maximum since the device never
provides data later than that time.
Figure 1. AC Test Loads
MCM6726C
3
A (ADDRESS)
READ CYCLE 1 (See Note 7)
t
AXQX
t
AVAV
Q (DATA OUT)
A (ADDRESS)
E (CHIP ENABLE)
G (OUTPUT ENABLE)
Q (DATA OUT)
t
AVQV
READ CYCLE 2 (See Note 8)
t
AVAV
t
AVQV
t
ELQV
t
ELQX
t
GLQV
t
GLQX
DATA VALID
DATA VALIDPREVIOUS DATA VALID
t
EHQZ
t
GHQZ
MCM6726C
4
MOTOROLA FAST SRAM
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
MCM6726C–6 MCM6726C–7
Parameter Symbol Min Max Min Max Unit Notes
Write Cycle Time t
Address Setup Time t
Address Valid to End of W rite t
Address Valid to End of W rite, G High t
Write Pulse Width t
Write Pulse Width, G High t
Data Valid to End of W rite t
Data Hold Time t
Write Low to Data High–Z t
Write High to Output Active t
Write Recovery Time t
NOTES:
1. A write occurs during the overlap of E
2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. Transition is measured 200 mV from steady–state voltage with load of Figure 1b.
5. This parameter is sampled and not 100% tested.
6. At any given voltage and temperature, t
low and W low.
max < t
WLQZ
min both for a given device and from device to device.
WHQX
AVAV
AVWL
AVWH
AVWH
WLWH
t
WLEH
WLWH
t
WLEH
DVWH
WHDX
WLQZ
WHQX
WHAX
6 — 7 — ns 3
0 — 0 — ns
6 — 7 — ns
6 — 7 — ns
6 — 7 — ns
6 — 7 — ns
3 — 3.5 — ns
0 — 0 — ns
— 3.5 — 3.5 ns 4,5,6
3 — 3 — ns 4,5,6
1 — 1 — ns
A (ADDRESS)
E
(CHIP ENABLE)
W
(WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
HIGH–Z
t
AVWL
WRITE CYCLE 1
t
WLQZ
t
AVAV
t
AVWH
t
WLEH
t
WLWH
t
DVWH
DATA VALID
HIGH–Z
t
WHAX
t
WHDX
t
WHQX
MOTOROLA FAST SRAM
MCM6726C
5
WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)
MCM6726C–6 MCM6726C–7
Parameter Symbol Min Max Min Max Unit Notes
Write Cycle Time t
Address Setup Time t
Address Valid to End of W rite t
Enable to End of Write t
Data Valid to End of W rite t
Data Hold Time t
Write Recovery Time t
NOTES:
1. A write occurs during the overlap of E
2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. If E
goes low coincident with or after W goes low, the output will remain in a high impedance condition.
5. If E
goes high coincident with or before W goes high, the output will remain in a high impedance condition.
low and W low.
AVAV
AVEL
AVEH
ELEH
t
ELWH
DVEH
EHDX
EHAX
6 — 7 — ns 3
0 — 0 — ns
6 — 7 — ns
5 — 6 — ns 4,5
3 — 3.5 — ns
0 — 0 — ns
0 — 0 — ns
WRITE CYCLE 2
t
AVAV
A (ADDRESS)
E
(CHIP ENABLE)
W
(WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
t
AVEL
t
AVEH
HIGH–Z
t
ELEH
t
ELWH
t
DVEH
DATA VALID
t
EHDX
t
EHAX
MCM6726C
6
MOTOROLA FAST SRAM
P ACKAGE DIMENSIONS
32–LEAD
400 MIL SOJ
CASE 857A–02
32 PL
F
0.17 (0.007) B A
N
32
1
-A-
17
16
DETAIL Z
0.17 (0.007) A B
L
G
32 PL
D
0.17 (0.007) B A
S S S
S S S
T
P
-B-
0.10 (0.004)
K
DETAIL Z
-T-
SEATING
PLANE
R
0.25 (0.010) A B
S S S
S S S
T
T
T
C
E
S RADIUS
NOTE 3
NOTE 3
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. TO BE DETERMINED AT PLANE -T-.
4. DIMENSION A & B DO NOT INCLUDE MOLD
PROTRUSION. MOLD PROTRUSION SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
5. DIMENSION A & B INCLUDE MOLD MISMATCH AND
ARE DETERMINED AT THE PARTING LINE.
INCHES MILLIMETERS
MIN MINMAX MAX
DIM
A
B
C
D
E
F
G
K
L
N
P
R
S
0.820
0.395
0.128
0.016
0.088
0.026
0.050 BSC
0.035
0.025 BSC
0.030
0.435
0.365
0.030
0.830
0.405
0.148
0.020
0.098
0.032
0.045
0.045
0.445
0.375
0.040
20.83
10.03
3.26
0.41
2.24
0.67
1.27 BSC
0.89
0.64 BSC
0.76
11.05
9.27
0.77
21.08
10.29
3.75
0.50
2.48
0.81
1.14
1.14
11.30
9.52
1.01
ORDERING INFORMATION
(Order by Full Part Number)
MCM 6726C WJ X X
Motorola Memory Prefix
Part Number
Full Part Numbers — MCM6726CWJ6 MCM6726CWJ7
MCM6726CWJ6R MCM6726CWJ7R
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
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Shipping Method (R = Tape and Reel, Blank = Rails)
Speed (6 = 6 ns, 7 = 7 ns)
Package (WJ = 400 mil SOJ)
Mfax is a trademark of Motorola, Inc.
MOTOROLA FAST SRAM
◊
MCM6726C/D
MCM6726C
7
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