Motorola MCM6709BRJ6, MCM6709BRJ8, MCM6709BRJ8R, MCM6709BRJ7, MCM6709BRJ6R Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Product Preview

64K x 4 Bit Static RAM

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by MCM6709BR/D

MCM6709BR

The MCM6709BR is a 262,144 bit static random access memory organized as
65,536 words of 4 bits. Static design eliminates the need for external clocks or
timing strobes.

Output enable (G

) is a special control feature that provides increased system

flexibility and eliminates bus contention problems.

The MCM6709BR meets JEDEC standards and is available in a revolutionary
pinout 300 mil, 28 lead plastic surface–mount SOJ package.

• Single 5 V ± 10% Power Supply

• Fully Static — No Clock or Timing Strobes Necessary

• All Inputs and Outputs are TTL Compatible

• Center Power and I/O Pins for Reduced Noise

• Three State Outputs

• Fast Access Times:

MCM6709BR–6 = 6 ns
MCM6709BR–7 = 7 ns
MCM6709BR–8 = 8 ns

BLOCK DIAGRAM

A
A
A

DQ

•

•

•

DQ

A

•

•

•

A
A
A
A
A

E

DECODER

•

•

•

CONTROL

ROW

INPUT

DATA

MEMORY MATRIX

512 ROWS x 128 x 4

COLUMNS

COLUMN I/O

COLUMN DECODER

AAAAAAA

•

•

•

J PACKAGE
300 MIL SOJ

CASE 810B–03

PIN ASSIGNMENT

V

V

DQ

CC
SS

DQ

W

1

A
A

2

A

3

A

4

E

5
6
7
8
9
10

A

11

A

12

A

13

A

14

28
27
26
25
24
23
22
21
20
19

18
17
16

15

A
A
A
A
G
DQ

V
V

DQ
A
A
A
A
NC

SS
CC

PIN NAMES

A Address Inputs. . . . . . . . . . . . . . . . . . .

W
G
E

DQ Data Input/Output. . . . . . . . . . . . . . .

V

CC

V

SS

NC No Connection. . . . . . . . . . . . . . . . .

All power supply and ground pins must
be connected for proper operation of the
device.

Write Enable. . . . . . . . . . . . . . . . . . . .

Output Enable. . . . . . . . . . . . . . . . . . .

Chip Enable. . . . . . . . . . . . . . . . . . . . . .

+ 5 V Power Supply. . . . . . . . . . . .

Ground. . . . . . . . . . . . . . . . . . . . . . .

W
G

This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.

REV 2
3/17/97

 Motorola, Inc. 1997

MOTOROLA FAST SRAM

MCM6709BR

1

TRUTH TABLE (X = Don’t Care)

E

H X X Not Selected High–Z —
L H H Read High–Z —
L L H Read D
L X L Write D

G W Mode Output Cycle

out

in

Read Cycle
Write Cycle

ABSOLUTE MAXIMUM RATINGS (See Note)

Rating

Power Supply Voltage V
Voltage Relative to VSS for Any Pin

Except V
Output Current (per I/O) I
Power Dissipation P
Temperature Under Bias T
Operating Temperature T
Storage Temperature — Plastic T

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

CC

exceeded. Functional operation should be restricted to RECOMMENDED OPER­ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.

Symbol Value Unit

CC

Vin, V

out

bias

stg

out

D

A

– 0.5 to + 7.0 V

– 0.5 to VCC + 0.5 V

± 30 mA

2.0 W

– 10 to + 85 °C

0 to + 70 °C

– 55 to + 125 °C

This device contains circuitry to protect the
inputs against damage due to high static volt­ages or electric fields; however, it is advised
that normal precautions be taken to avoid appli­cation of any voltage higher than maximum
rated voltages to this high–impedance circuit.

This BiCMOS memory circuit has been de­signed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
and transverse air flow of at least 500 linear feet
per minute is maintained.

DC OPERA TING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Typ Max Unit

Supply Voltage (Operating Voltage Range) V
Input High Voltage V
Input Low Voltage V

*VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 2.0 ns) or I ≤ 30.0 mA.

** VIL (min) = – 0.5 V dc @ 30.0 mA; VIL (min) = – 2.0 V ac (pulse width ≤ 2.0 ns) or I ≤ 30.0 mA.

CC

IH

IL

DC CHARACTERISTICS

Parameter Symbol Min Max Unit

Input Leakage Current (All Inputs, Vin = 0 to VCC) I
Output Leakage Current (E = VIH, V
Output High Voltage (IOH = – 4.0 mA) V
Output Low Voltage (IOL = 8.0 mA) V

= 0 to VCC) I

out

POWER SUPPLY CURRENTS

Parameter Symbol MCM6709BR–6 MCM6709BR–7 MCM6709BR–8 Unit Notes

AC Active Supply Current (I

f = f

)

max

AC Standby Current (E = VIH, VCC = max, f = f
CMOS Standby Current (VCC = max, f = 0 MHz,

E

≥ VCC – 0.2 V, Vin ≤ VSS, or ≥ VCC – 0.2 V)

NOTES:

1. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V, VIH = 3.0 V).

2. All addresses transition simultaneously low (LSB) and then high (MSB).

3. Data states are all zero.

= 0 mA, VCC = max,

out

max

) I

I

CCA

SB1

I

SB2

215 205 195 mA 1, 2, 3

95 85 75 mA 1, 2, 3
20 20 20 mA

4.5 5.0 5.5 V

2.2 — VCC + 0.3* V

– 0.5** — 0.8 V

lkg(I)

lkg(O)

OH

OL

— ± 1.0 µA
— ± 1.0 µA

2.4 — V
— 0.4 V

MCM6709BR
2

MOTOROLA FAST SRAM

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T

Address Input Capacitance C
Control Pin Input Capacitance(E, G, W) C
Input/Output Capacitance C

= 25°C, Periodically Sampled Rather Than 100% Tested)

A

Parameter

Symbol Max Unit

in
in

I/O

5 pF
6 pF
6 pF

AC OPERA TING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .

Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 2 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

READ CYCLES 1 AND 2 (See Notes 1 and 2)

MCM6709BR–6 MCM6709BR–7 MCM6709BR–8

Parameter Symbol Min Max Min Max Min Max Unit Notes

Read Cycle Time t
Address Access Time t
Chip Enable Access Time t
Output Enable Access Time t
Output Hold from Address Change t
Chip Enable Low to Output Active t
Output Enable Low to Output Active t
Chip Enable High to Output High–Z t
Output Enable High to Output High–Z t

NOTES:

1. W

is high for read cycle.

2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.

3. All read cycle timings are referenced from the last valid address to the first transitioning address.

4. At any given voltage and temperature, t
device and from device to device.

5. Transition is measured 200 mV from steady–state voltage with load of Figure 1b.

6. This parameter is sampled and not 100% tested.

AVAV
AVQV
ELQV
GLQV
AXQX
ELQX
GLQX
EHQZ

GHQZ

max is less than t

EHQZ

6 — 7 — 8 — ns 3
— 6 — 7 — 8 ns
— 6 — 7 — 8 ns
— 4 — 4 — 4 ns

3 — 3 — 3 — ns

3 — 3 — 3 — ns 4, 5, 6

0 — 0 — 0 — ns 4, 5, 6
— 3 — 3.5 — 3.5 ns 4, 5, 6
— 3 — 3.5 — 3.5 ns 4, 5, 6

Output Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . .

Output Load See Figure 1a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ELQX

min, and t

max is less than t

GHQZ

min, both for a given

GLQX

OUTPUT

Z0 = 50

Ω

(a) (b)

MOTOROLA FAST SRAM

RL = 50

VL = 1.5 V

+5 V

480

Ω

OUTPUT

Ω

255

Ω

5 pF

The table of timing values shows either a
minimum or a maximum limit for each param­eter. Input requirements are specified from
the external system point of view. Thus, ad­dress setup time is shown as a minimum
since the system must supply at least that
much time. On the other hand, responses
from the memory are specified from the de­vice point of view. Thus, the access time is
shown as a maximum since the device never
provides data later than that time.

TIMING LIMITS

Figure 1. AC Test Loads

MCM6709BR

3