Motorola MCM6246WJ20, MCM6246WJ17, MCM6246WJ17R2, MCM6246WJ35R2, MCM6246WJ20R2 Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

512K x 8 Bit Static Random
Access Memory

The MCM6246 is a 4,194,304 bit static random access memory organized as
524,288 words of 8 bits. Static design eliminates the need for external clocks or
timing strobes, while CMOS circuitry reduces power consumption and provides
for greater reliability .

The MCM6246 is equipped with chip enable (E
allowing for greater system flexibility and eliminating bus contention problems.
Either input, when high, will force the outputs into high impedance.

The MCM6246 is available in a 400 mil, 36–lead surface–mount SOJ package.

• Single 5 V ± 10% Power Supply

• Fast Access Time: 17/20/25/35 ns

• Equal Address and Chip Enable Access Time

• All Inputs and Outputs are TTL Compatible

• Three–State Outputs

• Power Operation: 205/200/185/170 mA Maximum, Active AC

BLOCK DIAGRAM

A
A

A
A

A
A
A
A
A
A

ROW

DECODER

MEMORY MATRIX

1024 ROWS x

4096 COLUMNS

) and output enable (G) pins,

Order this document

by MCM6246/D

MCM6246

WJ PACKAGE

400 MIL SOJ

CASE 893–01

PIN ASSIGNMENT

1

A

2

A

3

A

4

A

5

A

6

E

7

DQ

8

DQ

9

V

CC

10

V

SS

11

DQ

12

DQ

13

W

14

A

15

A
A

16

A

17

A

18

36
35
34
33
32
31
30
29
28
27
26
25
24

23
22

21
20

19

NC
A
A
A
A
G
DQ
DQ
V
V
DQ
DQ
A

A
A

A
A

NC

SS
CC

DQ

INPUT

DATA

CONTROL

DQ

E

W

G

REV 5
6/9/97

 Motorola, Inc. 1997

MOTOROLA FAST SRAM

COLUMN I/O

COLUMN DECODER

AAAAAAAAA

DQ

DQ

PIN NAMES

A Address Inputs. . . . . . . . . . . . . . . . . . .

W
G
E

DQ Data Input/Output. . . . . . . . . . . . . . .

NC No Connection. . . . . . . . . . . . . . . . .

V

CC

V

SS

+ 5 V Power Supply. . . . . . . . . . . .

Write Enable. . . . . . . . . . . . . . . . . . . .

Output Enable. . . . . . . . . . . . . . . . . . .

Chip Enable. . . . . . . . . . . . . . . . . . . . . .

Ground. . . . . . . . . . . . . . . . . . . . . . .

MCM6246

1

TRUTH TABLE (X = Don’t Care)

G W Mode I/O Pin Cycle Current

E

H X X Not Selected High–Z — I

L H H Output Disabled High–Z — I
L L H Read D
L X L Write High–Z Write I

out

Read I

SB1

, I

CCA
CCA
CCA

SB2

ABSOLUTE MAXIMUM RATINGS (See Note)

Rating

Power Supply Voltage Relative to V
Voltage Relative to VSS for Any Pin

Except V

Output Current (per I/O) I
Power Dissipation P

Temperature Under Bias T
Ambient Temperature T
Storage Temperature — Plastic T

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RA TINGS are ex-

CC

ceeded. Functional operation should be restricted to RECOMMENDED OPERAT­ING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.

SS

Symbol Value Unit

V

CC

Vin, V

out

bias

stg

out

D

A

– 0.5 to + 7.0 V

– 0.5 to VCC + 0.5 V

± 20

1.0 W

– 10 to + 85 °C

0 to + 70 °C

– 55 to + 150 °C

mA

This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is ad­vised that normal precautions be taken to avoid
application of any voltage higher than maxi­mum rated voltages to these high impedance
circuits.

This CMOS memory circuit has been de­signed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
and transverse air flow of at least 500 linear
feet per minute is maintained.

DC OPERA TING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Typ Max Unit

Supply Voltage (Operating Voltage Range) V
Input High Voltage V
Input Low Voltage V

*VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 2.0 ns).

**VIH (max) = VCC +

0.3 V dc; VIH

(max) = VCC +

2.0 V ac (pulse width

DC CHARACTERISTICS

Parameter Symbol Min Max Unit

Input Leakage Current (All Inputs, Vin = 0 to VCC) I
Output Leakage Current (E = VIH, V
Output Low Voltage (IOL = + 8.0 mA) V
Output High Voltage (IOH = – 4.0 mA) V

= 0 to VCC) I

out

POWER SUPPLY CURRENTS

Parameter Symbol Min Typ Max Unit

AC Active Supply Current (I

VCC = max) MCM6246–20: t

AC Standby Current (VCC = max, MCM6246–17: t

E

= VIH, No other restrictions on MCM6246–20: t

other inputs) MCM6246–25: t

CMOS Standby Current (E ≥ VCC – 0.2 V, Vin ≤ VSS + 0.2 V or

≥ VCC – 0.2 V) (VCC = max, f = 0 MHz)

= 0 mA, MCM6246–17: t

out

MCM6246–25: t
MCM6246–35: t

MCM6246–35: t

AVAV
AVAV
AVAV
AVAV

AVAV
AVAV
AVAV
AVAV

= 17 ns
= 20 ns
= 25 ns
= 35 ns

= 17 ns
= 20 ns
= 25 ns
= 35 ns

CC

IH

IL

≤ 2.0 ns).

I

CC

I

SB1

I

SB2

4.5 5.0 5.5 V

2.2 — VCC + 0.3** V

– 0.5*

lkg(I)

lkg(O)

OL

OH

—
—
—
—

—
—
—
—

— 10 15

— 0.8 V

— ± 1.0 µA
— ± 1.0 µA
— 0.4 V

2.4 — V

—
185
170
155

55

55

45

35

205
200
185
170

60
60
50
40

mA

mA

mA

MCM6246
2

MOTOROLA FAST SRAM

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T

Input Capacitance All Inputs Except Clocks and DQs

Input/Output Capacitance DQ C

= 25°C, Periodically Sampled Rather Than 100% Tested)

A

Parameter

E

, G, W

Symbol Typ Max Unit

C

in

C

ck

I/O

4
5

5 8 pF

6
8

AC OPERA TING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 2 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .

READ CYCLE TIMING (See Note 1)

MCM6246–17 MCM6246–20 MCM6246–25 MCM6246–35

Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes

Read Cycle Time t
Address Access Time t
Enable Access Time t
Output Enable Access Time t
Output Hold from Address

Change
Enable Low to Output Active t
Output Enable Low to Output

Active
Enable High to Output High–Z t
Output Enable High to Output

High–Z
Power Up Time t
Power Down Time t

NOTES:

1. W

is high for read cycle.

2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus conten­tion conditions during read and write cycles.

3. All read cycle timings are referenced from the last valid address to the first transitioning address.

4. Addresses valid prior to or coincident with E

5. At any given voltage and temperature, t
to device.

6. Transition is measured ± 500 mV from steady–state voltage.

7. This parameter is sampled and not 100% tested.

8. Device is continuously selected (E

AVAV
AVQV
ELQV

GLQV

t

AXQX

ELQX

t

GLQX

EHQZ

t

GHQZ

ELICCH
EHICCL

≤ VIL, G ≤ VIL).

17 — 20 — 25 — 35 — ns 2, 3
— 17 — 20 — 25 — 35 ns
— 17 — 20 — 25 — 35 ns 4
— 6 — 6 — 8 — 10 ns

5 — 5 — 5 — 5 — ns

5 — 5 — 5 — 5 — ns 5, 6, 7
0 — 0 — 0 — 0 — ns 5, 6, 7

— 8 — 8 — 10 — 12 ns 5, 6, 7
— 8 — 8 — 10 — 12 ns 5, 6, 7

0 — 0 — 0 — 0 — ns

— 17 — 20 — 25 — 35 ns

going low/E going high.

EHQZ

max t t

ELQX

min, and t

Output Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . .

Output Load See Figure 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GHQZ

max t t

min, both for a given device and from device

GLQX

pF

OUTPUT

MOTOROLA FAST SRAM

Z0 = 50

Ω

RL = 50

VL = 1.5 V

Ω

Figure 1. AC Test Load

TIMING LIMITS

The table of timing values shows either a
minimum or a maximum limit for each param­eter. Input requirements are specified from
the external system point of view. Thus, ad­dress setup time is shown as a minimum
since the system must supply at least that
much time. On the other hand, responses
from the memory are specified from the de­vice point of view. Thus, the access time is
shown as a maximum since the device never
provides data later than that time.

MCM6246

3