Datasheet MCM6209CJ35, MCM6209CJ25, MCM6209CJ15, MCM6209CJ15R2, MCM6209CJ20 Datasheet (Motorola)

MCM6209C

1

MOTOROLA FAST SRAM

64K x 4 Bit Fast Static RAM

With Output Enable

The MCM6209C is fabricated using Motorola’s high–performance silicon–gate
CMOS technology. Static design eliminates the need for external clocks or timing
strobes, while CMOS circuitry reduces power consumption and provides for
greater reliability.

This device meets JEDEC standards for functionality and pinout, and is avail­able in plastic dual–in–line and plastic small–outline J–leaded packages.

• Single 5 V ± 10% Power Supply

• Fully Static — No Clock or Timing Strobes Necessary

• Fast Access Times: 12, 15, 20, 25, and 35 ns

• Equal Address and Chip Enable Access Times

• Output Enable (G

) Feature for Increased System Flexibility and to

Eliminate Bus Contention Problems

• Low Power Operation: 135 – 165 mA Maximum AC

• Fully TTL Compatible — Three–State Output

BLOCK DIAGRAM

ROW

DECODER

INPUT

DATA

CONTROL

COLUMN I/O

COLUMN DECODER

MEMORY ARRAY

256 ROWS x

64 x 4 COLUMNS

A13
A14

A4

A1

A12

A6

A3

A2

DQ3

DQ2

DQ1

DQ0

E

W

G

A8 A11A10 A15A9A7A5A0

V

SS

V

CC

Order this document

by MCM6209C/D

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

PIN ASSIGNMENT

MCM6209C

P PACKAGE

300 MIL PLASTIC

CASE 710B–01

J PACKAGE
300 MIL SOJ

CASE 810B–03

PIN NAMES

A0 – A15 Address Input. . . . . . . . . . . . .

DQ0 – DQ3 Data Input/Data Output. . .

W Write Enable. . . . . . . . . . . . . . . . . . . .

G

Output Enable. . . . . . . . . . . . . . . . . . .

E

Chip Enable. . . . . . . . . . . . . . . . . . . . . .

NC No Connection. . . . . . . . . . . . . . . . .

V

CC

Power Supply (+ 5 V). . . . . . . . . . .

V

SS

Ground. . . . . . . . . . . . . . . . . . . . . . .

19
18
17
16
15

28
27
26
25
24
23
22
21

20

NC

A0
A1

A2
A3

A4
A5

A6
A7
A8

A9

E

G

V

SS

V

CC

A15
A14

A13
A12

A10
NC
NC

DQ0
DQ1
DQ2
DQ3

A11

10
11
12
13
14

1
2
3
4
5
6
7
8

9

W

REV 3
5/95

 Motorola, Inc. 1995

MCM6209C
2

MOTOROLA FAST SRAM

TRUTH TABLE (X = Don’t Care)

E

G W Mode VCC Current Output Cycle

H

L
L
L

X
H

L

X

X
H
H
L

Not Selected

Output Disabled

Read
Write

I

SB1

, I

SB2

I

CCA

I

CCA

I

CCA

High–Z
High–Z

D

out

High–Z

—

—
Read
Write

ABSOLUTE MAXIMUM RATINGS (See Note)

Rating

Symbol Value Unit

Power Supply Voltage V

CC

– 0.5 to + 7.0 V

Voltage Relative to VSS For Any Pin
Except V

CC

Vin, V

out

– 0.5 to VCC + 0.5 V

Output Current I

out

± 20 mA

Power Dissipation P

D

1.0 W

Temperature Under Bias T

bias

– 10 to + 85 °C

Operating Temperature T

A

0 to + 70 °C

Storage Temperature — Plastic T

stg

– 55 to + 125 °C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

exceeded. Functional operation should be restricted to RECOMMENDED OPER­ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Typ Max Unit

Supply Voltage (Operating Voltage Range) V

CC

4.5 5.0 5.5 V

Input High Voltage V

IH

2.2 —

VCC + 0.3**

V

Input Low Voltage V

IL

– 0.5*

— 0.8 V

*VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns)

**VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20 ns)

DC CHARACTERISTICS

Parameter Symbol Min Max Unit

Input Leakage Current (All Inputs, Vin = 0 to VCC) I

lkg(I)

— ± 1 µA

Output Leakage Current (E = VIH or G = VIH, V

out

= 0 to VCC) I

lkg(O)

— ± 1 µA

Standby Current (E ≥ VCC – 0.2 V*, Vin ≤ VSS + 0.2 V, or ≥ VCC – 0.2 V,
VCC = Max, f = 0 MHz)

I

SB2

— 20 mA

Output Low Voltage (IOL = 8.0 mA) V

OL

— 0.4 V

Output High Voltage (IOH = – 4.0 mA) V

OH

2.4 — V

*For devices with multiple chip enables, E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E.

POWER SUPPLY CURRENTS

Parameter Symbol – 12 – 15 – 20 – 25 – 35 Unit

AC Supply Current (I

out

= 0 mA, VCC = Max, f = f

max

) I

CCA

165 155 145 135 130 mA

Standby Current (E = VIH , VCC = Max, f = f

max

) I

SB1

55 50 45 40 35 mA

This device contains circuitry to protect the
inputs against damage due to high static volt­ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi­mum rated voltages to this high–impedance
circuit.

This CMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
and transverse air flow of at least 500 linear
feet per minute is maintained.

MCM6209C

3

MOTOROLA FAST SRAM

CAPACITANCE (f = 1 MHz, dV = 3 V, T

A

= 25°C, Periodically Sampled Rather Than 100% Tested)

Characteristic

Symbol Max Unit

Address Input Capacitance C

in

6 pF

Control Pin Input Capacitance (E, G, W) C

in

6 pF

I/O Capacitance C

I/O

8 pF

AC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .

Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 5 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . .

Output Load Figure 1A Unless Otherwise Noted. . . . . . . . . . . . . . . .

READ CYCLE (See Notes 1 and 2)

– 12 – 15 – 20 – 25 – 35

Parameter Symbol Min Max Min Max Min Max Min Max Min Max Unit Notes

Read Cycle Time t

AVAV

12 — 15 — 20 — 25 — 35 — ns 2

Address Access Time t

AVQV

— 12 — 15 — 20 — 25 — 35 ns

Enable Access Time t

ELQV

— 12 — 15 — 20 — 25 — 35 ns 3

Output Enable Access Time t

GLQV

— 6 — 8 — 10 — 12 — 15 ns

Output Hold from Address Change t

AXQX

4 — 4 — 4 — 4 — 4 — ns

Enable Low to Output Active t

ELQX

4 — 4 — 4 — 4 — 4 — ns 4, 5, 6

Enable High to Output High–Z t

EHQZ

0 6 0 8 0 9 0 10 0 10 ns 4, 5, 6

Output Enable Low to Output Active t

GLQX

0 — 0 — 0 — 0 — 0 — ns 4, 5, 6

Output Enable High to Output High–Z t

GHQZ

0 6 0 7 0 8 0 10 0 — ns 4, 5, 6

Power Up Time t

ELICCH

0 — 0 — 0 — 0 — 0 — ns

Power Down Time t

EHICCL

— 12 — 15 — 20 — 25 — 35 ns

NOTES:

1. W

is high for read cycle.

2. All timings are referenced from the last valid address to the first transitioning address.

3. Addresses valid prior to or coincident with E

going low.

4. At any given voltage and temperature, t

EHQZ

max is less than t

ELQX

min, and t

GHQZ

max is less than t

GLQX

min, both for a given device

and from device to device.

5. Transition is measured ±500 mV from steady–state voltage with load of Figure 1B.

6. This parameter is sampled and not 100% tested.

7. Device is continuously selected (E

= VIL, G ≤ VIL).

AC TEST LOADS

Figure 1A Figure 1B

The table of timing values shows either a
minimum or a maximum limit for each param­eter. Input requirements are specified from
the external system point of view. Thus, ad­dress setup time is shown as a minimum
since the system must supply at least that
much time (even though most devices do not
require it). On the other hand, responses from
the memory are specified from the device
point of view. Thus, the access time is shown
as a maximum since the device never pro­vides data later than that time.

TIMING LIMITS

OUTPUT

Z0 = 50

Ω

RL = 50

Ω

VL = 1.5 V

5 pF

+ 5 V

OUTPUT

255

Ω

480

Ω

MCM6209C
4

MOTOROLA FAST SRAM

READ CYCLE 1 (See Note 8)

Q (DATA OUT)

A (ADDRESS)

DATA VALIDPREVIOUS DATA VALID

t

AVAV

t

AXQX

t

AVQV

READ CYCLE 2 (See Notes 2 and 4)

I

SB

I

CC

t

EHQZ

t

EHICCL

DATA VALID

t

GHQZ

t

AVAV

t

ELQX

t

ELQV

E (CHIP ENABLE)

Q (DATA OUT)

A (ADDRESS)

t

ELICCH

t

AVQV

t

GLQX

t

GLQV

V

CC

SUPPLY CURRENT

HIGH–Z HIGH–Z

G (OUTPUT ENABLE)

MCM6209C

5

MOTOROLA FAST SRAM

WRITE CYCLE 1 (W Controlled, See Notes 1, 2, and 3)

– 12 – 15 – 20 – 25 – 35

Parameter Symbol Min Max Min Max Min Max Min Max Min Max Unit Notes

Write Cycle Time t

AVAV

12 — 15 — 20 — 25 — 35 — ns 3

Address Setup Time t

AVWL

0 — 0 — 0 — 0 — 0 — ns

Address Valid to End of Write t

AVWH

10 — 12 — 15 — 20 — 20 — ns

Write Pulse Width t

WLWH

,

t

WLEH

10 — 12 — 15 — 20 — 20 — ns

Write Pulse Width, G High t

WLWH

,

t

WLEH

8 — 10 — 12 — 15 — 15 — ns 4

Data Valid to End of Write t

DVWH

6 — 7 — 8 — 10 — 10 — ns

Data Hold Time t

WHDX

0 — 0 — 0 — 0 — 0 — ns

Write Low to Output High–Z t

WLQZ

0 6 0 7 0 8 0 10 0 10 ns 5, 6, 7

Write High to Output Active t

WHQX

4 — 4 — 4 — 4 — 4 — ns 5, 6, 7

Write Recovery Time t

WHAX

0 — 0 — 0 — 0 — 0 — ns

NOTES:

1. A write occurs during the overlap of E

low and W low.

2. For Output Enable devices, if G

goes low coincident with or after W goes low, the output will remain in a high impedance state.

3. All timings are referenced from the last valid address to the first transitioning address.

4. For Output Enable devices, if G

≥ VIH, the output will remain in a high impedance state

5. At any given voltage and temperature, t

WLQZ

max is less than t

WHQX

min, both for a given device and from device to device.

6. Transition is measured ±500 mV from steady–state voltage with load of Figure 1B.

7. This parameter is sampled and not 100% tested.

WRITE CYCLE 1 (W Controlled, See Note 2)

DATA VALID

t

DVWH

t

AVWL

t

AVWH

t

AVAV

t

WHAX

t

WLWH

t

WHDX

t

WLQZ

t

WHQX

HIGH–Z HIGH–Z

A (ADDRESS)

W

(WRITE ENABLE)

E (CHIP ENABLE)

Q (DATA OUT)

D (DATA IN)

t

WLEH

MCM6209C
6

MOTOROLA FAST SRAM

WRITE CYCLE 2 (E Controlled, See Notes 1, 2, and 3)

– 12 – 15 – 20 – 25 – 35

Parameter Symbol Min Max Min Max Min Max Min Max Min Max Unit Notes

Write Cycle Time t

AVAV

12 — 15 — 20 — 25 — 35 — ns 3

Address Setup Time t

AVEL

0 — 0 — 0 — 0 — 0 — ns

Address Valid to End of Write t

AVEH

10 — 12 — 15 — 20 — 20 — ns

Enable to End of Write t

ELEH

,

t

ELWH

8 — 10 — 12 — 15 — 15 — ns 4, 5

Data Valid to End of Write t

DVEH

6 — 7 — 8 — 10 — 10 — ns

Data Hold Time t

EHDX

0 — 0 — 0 — 0 — 0 — ns

Write Recovery Time t

EHAX

0 — 0 — 0 — 0 — 0 — ns

NOTES:

1. A write occurs during the overlap of E

low and W low.

2. For Output Enable devices, if G

goes low coincident with or after W goes low, the output will remain in a high impedance state.

3. All timings are referenced from the last valid address to the first transitioning address.

4. If E

goes low coincident with or after W goes low, the output will remain in a high impedance state.

5. If E

goes high coincident with or before W goes high, the output will remain in a high impedance state.

WRITE CYCLE 2 (E Controlled, See Note 2)

t

WLEH

t

EHDX

t

DVEH

t

EHAX

t

ELWH

t

ELEH

t

AVEL

t

AVEH

DATA VALID

t

AVAV

HIGH–Z

A (ADDRESS)

W

(WRITE ENABLE)

E (CHIP ENABLE)

Q (DATA OUT)

D (DATA IN)

ORDERING INFORMATION

(Order by Full Part Number)

Motorola Memory Prefix
Part Number

Package (P = Plastic DIP, J = Plastic SOJ)

Full Part Numbers — MCM6209CP15 MCM6209CJ15 MCM6209CJ15R2

MCM6209CP20 MCM6209CJ20 MCM6209CJ20R2
MCM6209CP25 MCM6209CJ25 MCM6209CJ25R2
MCM6209CP35 MCM6209CJ35 MCM6209CJ35R2

Shipping Method (R2 = Tape and Reel, Blank = Rails)
Speed (15 = 15 ns, 20 = 20 ns, 25 = 25 ns, 35 = 35 ns)

MCM 6209C X XX XX

MCM6209C

7

MOTOROLA FAST SRAM

PACKAGE DIMENSIONS

P PACKAGE

300 MIL PLASTIC

CASE 710B–01

J PACKAGE
300 MIL SOJ

CASE 810B–03

MIN MINMAX MAX

MILLIMETERS INCHES

DIM

A
B
C
D
E
F
G
J
K
L
M
N

34.55

7.12

3.81

0.39

1.15

0.21

3.18
0

°

0.51

34.79

7.62

4.57

0.53

1.39

0.30

3.42
15

°

1.01

1.360

0.280

0.150

0.015

0.045

0.008

0.125
0

°

0.020

1.370

0.300

0.180

0.021

0.055

0.012

0.135
15

°

0.040

1.27 BSC

2.54 BSC

7.62 BSC

0.050 BSC

0.100 BSC

0.300 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.

4. DIMENSION A AND B DOES NOT INCLUDE MOLD
FLASH. MAXIMUM MOLD FLASH 0.25 (0.010).

28

1

15

14

-B-

-A-

K

L

M

C

N

E

F

D

28 PL

G

J

28 PL

-T-

SEATING
PLANE

0.25 (0.010)MTSB

0.25 (0.010)MTSA

MIN MINMAX MAX

MILLIMETERS INCHES

DIM

A
B
C
D

E

F
G
H
K

L
M
N

P
R

S

0

°10°

1.27 BSC

0.64 BSC

0.050 BSC

0.025 BSC
0

°10°

18.29

7.50

3.26

0.39

2.24

0.67
—

0.89

0.76

8.38

6.60

0.77

18.54

7.74

3.75

0.50

2.48

0.81

0.50

1.14

1.14

8.64

6.86

1.01

0.720

0.295

0.128

0.015

0.088

0.026
—

0.035

0.030

0.330

0.260

0.030

0.730

0.305

0.148

0.020

0.098

0.032

0.020

0.045

0.045

0.340

0.270

0.040

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. DIMENSION A & B DO NOT INCLUDE MOLD
PROTRUSION. MOLD PROTRUSION SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.

3. CONTROLLING DIMENSION: INCH.

4. DIM R TO BE DETERMINED AT DATUM -T-.

5. 810B-01 AND -02 OBSOLETE, NEW STANDARD
810B-03.

28

1

15

14

L
G

M

K

DETAIL Z

DETAIL Z

S RAD

F

-B-

-A­P

R

N

0.10 (0.004)

SEATING PLANE

-T-

0.25 (0.010) TSB

0.18 (0.007)MTSA

0.18 (0.007) TSB

S

S

M

C

E

D

24 PL

H BRK

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters can and do vary in different
applications. All operating parameters, including “T ypicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
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against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

MCM6209C
8

MOTOROLA FAST SRAM

Literature Distribution Centers:

USA/EUROPE: Motorola Literature Distribution; P .O. Box 20912; Phoenix, Arizona 85036.
JAPAN: Nippon Motorola Ltd.; 4–32–1, Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan.
ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.

MCM6209C/D

*MCM6209C/D*

◊

CODELINE TO BE PLACED HERE