Motorola MC9S12DB128B, MC9S12DT128B, MC9S12DG128B, MC9S12DJ128B User Manual
DOCUMENT NUMBER
http://www.xinpian.net
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010-62245566 13810019655
9S12DT128BDGV1/D
MC9S12DT128B
Device User Guide
V01.07
Covers also
MC9S12DG128B, MC9S12DJ128B,
MC9S12DB128B
Original Release Date: 18 June 2001
Revised: 16 Aug 2002
Motorola, Inc
Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or
design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein;
neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where
personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized
application,Buyershallindemnify andhold Motorolaand itsofficers, employees,subsidiaries, affiliates,and distributorsharmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly orindirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part.
1
Revision History
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提供单片机解密、IC解密、芯片解密业务
010-62245566 13810019655
DOCUMENT NUMBER
9S12DT128BDGV1/D
Version
Number
V01.00
V01.01
V01.02
V01.03
V01.04
V01.05
V01.06
V01.07
Revision
Date
18 Jun
2001
23 July
2001
23 Sep
2001
12 Oct
2001
27 Feb
2002
4 Mar
2002
8 July
2002
16 Aug
2002
Effective
Date
18 June
2001
23 July
2001
23 Sep
2001
12 Oct
2001
27 Feb
2002
4 Mar
2002
22 July
2002
16 Aug
2002
Author Description of Changes
Initial version (parent doc v2.03 dug for dp256).
Updated version after review
Changed Partname, added pierce mode, updated electrical
characteristics
some minor corrections
Replaced Star12 by HCS12
Updated electrical spec after MC-Qualification (IOL/IOH), Data for
Pierce, NVM reliability
New document numbering. Corrected Typos
Increased VDD to 2.35V, removed min. oscillator startup
Removed Document order number except from Cover Sheet
Added:
Pull-up columns to signal table,
example for PLL Filter calculation,
Thermal values for junction to board and package,
BGND pin pull-up
Part Order Information
Global Register Table
Chip Configuration Summary
Modified:
Reduced Wait and Run IDD values
Mode of Operation chapter
changed leakage current for ADC inputs down to +-1uA
Corrected:
Interrupt vector table enable register inconsistencies
PCB layout for 80QFP VREGEN position
Minor corrections in table 1-1 & section 1.5.1
Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or
design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein;
neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where
personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized
application,Buyer shallindemnify andhold Motorolaand itsofficers, employees,subsidiaries, affiliates,and distributorsharmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly orindirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part.
2
MC9S12DT128B Device User Guide — V01.07
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010-62245566 13810019655
Table of Contents
Section 1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
1.5 Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.5.1 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.6 Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Section 2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
2.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
2.2 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
2.3 Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
2.3.1 EXTAL, XTAL — Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
2.3.2 RESET — External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
2.3.3 TEST — Test Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
2.3.4 XFC — PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
2.3.5 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin . . . . . . . .53
2.3.6 PAD[15] / AN1[7] / ETRIG1 — Port AD Input Pin [15] . . . . . . . . . . . . . . . . . . . . . . . .54
2.3.7 PAD[14:8] / AN1[6:0] — Port AD Input Pins [14:8]. . . . . . . . . . . . . . . . . . . . . . . . . . .54
2.3.8 PAD[7] / AN0[7] / ETRIG0 — Port AD Input Pin [7] . . . . . . . . . . . . . . . . . . . . . . . . . .54
2.3.9 PAD[6:0] / AN0[6:0] — Port AD Input Pins [6:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
2.3.10 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins . . . . . . . . . . . . . . . . . . . . . . .54
2.3.11 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . .54
2.3.12 PE7 / NOACC / XCLKS — Port E I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
2.3.13 PE6 / MODB / IPIPE1 — Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
2.3.14 PE5 / MODA / IPIPE0 — Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
2.3.15 PE4 / ECLK — Port E I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
2.3.16 PE3 / LSTRB / TAGLO — Port E I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
2.3.17 PE2 / R/W — Port E I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
2.3.18 PE1 / IRQ — Port E Input Pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
2.3.19 PE0 / XIRQ — Port E Input Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
2.3.20 PH7 / KWH7 — Port H I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
3
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2.3.21 PH6 / KWH6 — Port H I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
2.3.22 PH5 / KWH5 — Port H I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
2.3.23 PH4 / KWH4 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
2.3.24 PH3 / KWH3 / SS1 — Port H I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
2.3.25 PH2 / KWH2 / SCK1 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
2.3.26 PH1 / KWH1 / MOSI1 — Port H I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
2.3.27 PH0 / KWH0 / MISO1 — Port H I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
2.3.28 PJ7 / KWJ7 / TXCAN4 / SCL — PORT J I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . .57
2.3.29 PJ6 / KWJ6 / RXCAN4 / SDA — PORT J I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . .58
2.3.30 PJ[1:0] / KWJ[1:0] — Port J I/O Pins [1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.3.31 PK7 / ECS / ROMCTL — Port K I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.3.32 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.3.33 PM7 / BF_PSLM / TXCAN4 — Port M I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.3.34 PM6 / BF_PERR / RXCAN4 — Port M I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.3.35 PM5 / BF_PROK / TXCAN0 / TXCAN4 / SCK0 — Port M I/O Pin 5 . . . . . . . . . . . . .58
2.3.36 PM4 / BF_PSYN / RXCAN0 / RXCAN4/ MOSI0 — Port M I/O Pin 4. . . . . . . . . . . . .59
2.3.37 PM3 / TX_BF / TXCAN1 / TXCAN0 / SS0 — Port M I/O Pin 3 . . . . . . . . . . . . . . . . .59
2.3.38 PM2 / RX_BF / RXCAN1 / RXCAN0 / MISO0 — Port M I/O Pin 2. . . . . . . . . . . . . . .59
2.3.39 PM1 / TXCAN0 / TXB — Port M I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.40 PM0 / RXCAN0 / RXB — Port M I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.41 PP7 / KWP7 / PWM7 — Port P I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.42 PP6 / KWP6 / PWM6 — Port P I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.43 PP5 / KWP5 / PWM5 — Port P I/O Pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
2.3.44 PP4 / KWP4 / PWM4 — Port P I/O Pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
2.3.45 PP3 / KWP3 / PWM3 / SS1 — Port P I/O Pin 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
2.3.46 PP2 / KWP2 / PWM2 / SCK1 — Port P I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .60
2.3.47 PP1 / KWP1 / PWM1 / MOSI1 — Port P I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . .60
2.3.48 PP0 / KWP0 / PWM0 / MISO1 — Port P I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . .60
2.3.49 PS7 / SS0 — Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
2.3.50 PS6 / SCK0 — Port S I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
2.3.51 PS5 / MOSI0 — Port S I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
2.3.52 PS4 / MISO0 — Port S I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
2.3.53 PS3 / TXD1 — Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
2.3.54 PS2 / RXD1 — Port S I/O Pin 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
2.3.55 PS1 / TXD0 — Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
2.3.56 PS0 / RXD0 — Port S I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
4
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2.3.57 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
2.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
2.4.1 VDDX,VSSX — Power & Ground Pins for I/O Drivers. . . . . . . . . . . . . . . . . . . . . . . .62
2.4.2 VDDR, VSSR — Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator
62
2.4.3 VDD1, VDD2, VSS1, VSS2 — Core Power Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG . . . . . . . . . . . . . . . . . . . . .63
2.4.5 VRH, VRL — ATD Reference Voltage Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . .63
2.4.6 VDDPLL, VSSPLL — Power Supply Pins for PLL. . . . . . . . . . . . . . . . . . . . . . . . . . .63
2.4.7 VREGEN — On Chip Voltage Regulator Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Section 3 System Clock Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
3.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Section 4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
4.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
4.2 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
4.3 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
4.3.1 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
4.3.2 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
4.3.3 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
4.4.1 Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
4.4.2 Pseudo Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
4.4.3 Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
4.4.4 Run. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Section 5 Resets and Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
5.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
5.2 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
5.2.1 Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
5.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
5.3.1 I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
5.3.2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Section 6 HCS12 Core Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
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Section 7 Clock and Reset Generator (CRG) Block Description . . . . . . . . .75
7.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
7.1.1 XCLKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Section 8 Enhanced Capture Timer (ECT) Block Description. . . . . . . . . . . .75
Section 9 Analog to Digital Converter (ATD) Block Description. . . . . . . . . .75
Section 10 Inter-IC Bus (IIC) Block Description . . . . . . . . . . . . . . . . . . . . . . .75
Section 11 Serial Communications Interface (SCI) Block Description. . . . .75
Section 12 Serial Peripheral Interface (SPI) Block Description . . . . . . . . . .76
Section 13 J1850 (BDLC) Block Description. . . . . . . . . . . . . . . . . . . . . . . . . .76
Section 14 Byteflight (BF) Block Description . . . . . . . . . . . . . . . . . . . . . . . . .76
Section 15 Pulse Width Modulator (PWM) Block Description. . . . . . . . . . . .76
Section 16 Flash EEPROM 128K Block Description . . . . . . . . . . . . . . . . . . .76
Section 17 EEPROM 2K Block Description. . . . . . . . . . . . . . . . . . . . . . . . . . .76
Section 18 RAM Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Section 19 MSCAN Block Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Section 20 Port Integration Module (PIM) Block Description . . . . . . . . . . . .77
Section 21 Voltage Regulator (VREG) Block Description . . . . . . . . . . . . . . .77
Section 22 Printed Circuit Board Layout Proposal . . . . . . . . . . . . . . . . . . . .78
Appendix A Electrical Characteristics
A.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
A.1.2 Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
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A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
A.1.4 Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
A.1.6 ESD Protection and Latch-up Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
A.2 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
A.2.1 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
A.2.2 Factors influencing accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
A.2.3 ATD accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
A.3 NVM, Flash and EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
A.3.1 NVM timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
A.3.2 NVM Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
A.4 Voltage Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
A.5 Reset, Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
A.5.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
A.5.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
A.5.3 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
A.6 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
A.7 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
A.7.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
A.7.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
A.8 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
A.8.1 General Muxed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Appendix B Package Information
B.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
B.2 112-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
B.3 80-pin QFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
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List of Figures
Figure 0-1 Order Partnumber Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 1-1 MC9S12DT128B Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 1-2 MC9S12DT128B Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 2-1 Pin assignments 112 LQFP for MC9S12DT128B,MC9S12DG128B,
MC9S12DJ128B, MC9S12DB128B48
Figure 2-2 Pin Assignments in 80 QFP for MC9S12DG128B, MC9S12DJ128B Bondout . .49
Figure 2-3 PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Figure 2-4 Colpitts Oscillator Connections (PE7=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Figure 2-5 Pierce Oscillator Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Figure 2-6 External Clock Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Figure 3-1 Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Figure 22-1 Recommended PCB Layout for 112LQFP Colpitts Oscillator . . . . . . . . . . . . . . .79
Figure 22-2 Recommended PCB Layout for 80QFP Colpitts Oscillator . . . . . . . . . . . . . . . . .80
Figure 22-3 Recommended PCB Layout for 112LQFP Pierce Oscillator . . . . . . . . . . . . . . . .81
Figure 22-4 Recommended PCB Layout for 80QFP Pierce Oscillator . . . . . . . . . . . . . . . . . .82
Figure A-1 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure A-2 Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure A-3 Jitter Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure A-4 Maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure A-5 SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure A-6 SPI Master Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure A-7 SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure A-8 SPI Slave Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure A-9 General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 22-5 112-pin LQFP mechanical dimensions (case no. 987) . . . . . . . . . . . . . . . . . . .120
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List of Tables
Table 0-1 Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 0-2 Document References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Table 1-1 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
$0000 - $000F MEBI map 1 of 3 (Core User Guide) ........................................................22
$0010 - $0014 MMC map 1 of 4 (Core User Guide) ........................................................22
$0015 - $0016 INT map 1 of 2 (Core User Guide) ...........................................................23
$0017 - $0017 MMC map 2 of 4 (Core User Guide) ........................................................23
$0018 - $001B Miscellaneous Peripherals (Device User Guide, Table 1-3) ....................23
$001C - $001D MMC map 3 of 4 (Core and Device User Guide, Table 1-4) ...................23
$001E - $001E MEBI map 2 of 3 (Core User Guide) ........................................................23
$001F - $001F INT map 2 of 2 (Core User Guide) ...........................................................23
$0020 - $0027 Reserved ..................................................................................................24
$0028 - $002F BKP (Core User Guide) ...........................................................................24
$0030 - $0031 MMC map 4 of 4 (Core User Guide) ........................................................24
$0032 - $0033 MEBI map 3 of 3 (Core User Guide) ........................................................24
$0034 - $003F CRG (Clock and Reset Generator) ..........................................................25
$0040 - $007F ECT (Enhanced Capture Timer 16 Bit 8 Channels) .................................25
$0080 - $009F ATD0 (Analog to Digital Converter 10 Bit 8 Channel) ..............................28
$00A0 - $00C7 PWM (Pulse Width Modulator 8 Bit 8 Channel) .......................................29
$00C8 - $00CF SCI0 (Asynchronous Serial Interface) ......................................................31
$00D0 - $00D7 SCI1 (Asynchronous Serial Interface) ......................................................31
$00D8 - $00DF SPI0 (Serial Peripheral Interface) ............................................................32
$00E0 - $00E7 IIC (Inter IC Bus) ......................................................................................32
$00E8 - $00EF BDLC (Byte Level Data Link Controller J1850) ........................................33
$00F0 - $00F7 SPI1 (Serial Peripheral Interface) ............................................................33
$00F8 - $00FF Reserved ..................................................................................................33
$0100 - $010F Flash Control Register (fts128k2) ............................................................34
$0110 - $011B EEPROM Control Register (eets2k) ........................................................34
$011C - $011F Reserved for RAM Control Register ........................................................35
$0120 - $013F ATD1 (Analog to Digital Converter 10 Bit 8 Channel) ..............................35
$0140 - $017F CAN0 (Motorola Scalable CAN - MSCAN) ..............................................36
Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout. . . . . . . . . . .37
$0180 - $01BF CAN1 (Motorola Scalable CAN - MSCAN) ..............................................38
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$01C0 - $01FF Reserved ..................................................................................................39
$0200 - $023F Reserved ..................................................................................................39
$0240 - $027F PIM (Port Integration Module) ..................................................................40
$0280 - $02BF CAN4 (Motorola Scalable CAN - MSCAN) ..............................................42
$02C0 - $02FF Reserved ..................................................................................................43
$0300 - $035F Byteflight ..................................................................................................43
$0360 - $03FF Reserved ..................................................................................................45
Table 1-3 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Table 1-4 Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Table 2-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Table 2-2 MC9S12DT128B Power and Ground Connection Summary. . . . . . . . . . . . . . . . .61
Table 4-1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Table 4-2 Clock Selection Based on PE7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Table 4-3 Voltage Regulator VREGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Table 5-1 Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Table 22-1 Suggested External Component Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Table A-1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Table A-2 ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Table A-3 ESD and Latch-Up Protection Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Table A-4 Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Table A-5 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Table A-6 5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Table A-7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Table A-8 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Table A-9 ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Table A-10 ATD Conversion Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Table A-11 NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Table A-12 NVM Reliability Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Table A-13 Voltage Regulator Recommended Load Capacitances. . . . . . . . . . . . . . . . . . . .101
Table A-14 Startup Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Table A-15 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Table A-16 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Table A-17 MSCAN Wake-up Pulse Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Table A-18 SPI Master Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Table A-19 SPI Slave Mode Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
Table A-20 Expanded Bus Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
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Preface
The Device User Guide provides information about the MC9S12DT128B device made up of standard
HCS12 blocks and the HCS12 processor core.
This document is part of the customer documentation. A complete set of device manuals also includes the
HCS12 Core UserGuideandall the individual Block User Guides of theimplementedmodules.In a effort
to reduce redundancy all module specific information is located only in the respective Block User Guide.
If applicable, special implementation details of the module are given in the block description sections of
this document.
This document also covers the MC9S12DG128B, MC9S12DJ128B and MC9S12DB128B.
Table 0-1 shows the availability of peripheral modules on the various derivatives. For details about the
compatibility within the MC9S12D-Family refer also to engineering bulletin EB386.
Office
1
An errata exists
contact Sales
Office
Table 0-1 Derivative Differences
Modules MC9S12DT128B MC9S12DG128B MC9S12DJ128B MC9S12DB128B
# of CANs 3 2 2 2
CAN4 ✓✓✓✓
CAN1 ✓✕✕✕
CAN0 ✓✓✓✓
J1850/BDLC ✕✕ ✓ ✕
IIC ✓✓ ✓ ✕
Byteflight ✕✕ ✕ ✓
Package 112 LQFP 112 LQFP/80 QFP 112 LQFP/80 QFP 112 LQFP
Package
Code
Mask set L85D L85D L85D L85D
Temp Options M, V, C M, V, C M, V, C M, V, C
Notes
NOTES:
1.
✓: Available for this device, ✕: Not available for this device
PV PV/FU PV/FU PV
An errata exists
contact Sales
Office
An errata exists
contact Sales
Office
An errata exists
contact Sales
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The following figure provides an ordering number example for the MC9S12D128B devices.
MC9S12 DJ128B C FU
Package Option
Temperature Option
Temperature Options
C = -40˚C to 85˚C
V = -40˚C to 105˚C
M = -40˚C to 125˚C
Device Title
Package Options
Controller Family
FU = 80QFP
PV = 112LQFP
Figure 0-1 Order Partnumber Example
See Table 0-2 for names and versions of the referenced documents throughout the Device User Guide.
Table 0-2 Document References
User Guide Version Document Order Number
HCS12_V1.5 Core User Guide 1.2 HCS12COREUG
Clock and Reset Generator (CRG) Block User Guide V03 S12CRGV3/D
Enhanced Capture Timer 16 Bit 8 Channel (ECT_16B8C) Block User Guide V01 S12ECT16B8CV1/D
Analog to Digital Converter 10 Bit 8 Channel (ATD_10B8C) Block User Guide V02 S12ATD10B8CV2/D
Inter IC Bus (IIC) Block User Guide V02 S12IICV2/D
Asynchronous Serial Interface (SCI) Block User Guide V02 S12SCIV2/D
Serial Peripheral Interface (SPI) Block User Guide V02 S12SPIV2/D
Pulse Width Modulator 8 Bit 8 Channel (PWM_8B8C) Block User Guide V01 S12PWM8B8CV1/D
128K Byte Flash (FTS128K) Block User Guide V01 S12FTS128KV1/D
2K Byte EEPROM (EETS2K) Block User Guide V01 S12EETS2KV1/D
Byte Level Data Link Controller -J1850 (BDLC) Block User Guide V01 S12BDLCV1/D
Motorola Scalable CAN (MSCAN) Block User Guide V02 S12MSCANV2/D
Voltage Regulator (VREG) Block User Guide V01 S12VREGV1/D
Port Integration Module (PIM_9DT128) Block User Guide V01 S12PIMDT128V1/D
Byteflight (BF) Block User Guide V01 S12BFV1/D
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Section 1 Introduction
1.1 Overview
The MC9S12DT128B microcontroller unit (MCU) is a 16-bit device composed of standard on-chip
peripherals including a 16-bit central processing unit (HCS12 CPU), 128K bytes of Flash EEPROM, 8K
bytes of RAM, 2K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), two
serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, two 8-channel, 10-bit
analog-to-digital converters(ADC),an 8-channel pulse-width modulator(PWM),a digital Byte Data Link
Controller (BDLC), 29 discrete digital I/O channels (Port A, Port B, Port K and Port E), 20 discrete digital
I/O lines with interrupt and wakeup capability, three CAN 2.0 A, B software compatible modules
(MSCAN12), a Byteflight module and an Inter-IC Bus. The MC9S12DT128B has full 16-bit data paths
throughout. However, the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory
can be interfaced for lower cost systems. The inclusion of a PLL circuit allows power consumption and
performance to be adjusted to suit operational requirements.
1.2 Features
• HCS12 Core
– 16-bit HCS12 CPU
i. Upward compatible with M68HC11 instruction set
ii. Interrupt stacking and programmer’s model identical to M68HC11
iii.20-bit ALU
iv.Instruction queue
v. Enhanced indexed addressing
– MEBI (Multiplexed External Bus Interface)
– MMC (Module Mapping Control)
– INT (Interrupt control)
– BKP (Breakpoints)
– BDM (Background Debug Mode)
• CRG (Clock and Reset Generator)
– Choice of low current Colpitts oscillator or standard Pierce Oscillator
– PLL
– COP watchdog
– real time interrupt
– clock monitor
• 8-bit and 4-bit ports with interrupt functionality
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– Digital filtering
– Programmable rising or falling edge trigger
• Memory
– 128K Flash EEPROM
– 2K byte EEPROM
– 8K byte RAM
• Two 8-channel Analog-to-Digital Converters
– 10-bit resolution
– External conversion trigger capability
• Three 1M bit per second, CAN 2.0 A, B software compatible modules
– Five receive and three transmit buffers
– Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8x8bit
– Four separate interrupt channels for Rx, Tx, error and wake-up
– Low-pass filter wake-up function
– Loop-back for self test operation
• Enhanced Capture Timer
– 16-bit main counter with 7-bit prescaler
– 8 programmable input capture or output compare channels
– Two 8-bit or one 16-bit pulse accumulators
• 8 PWM channels
– Programmable period and duty cycle
– 8-bit 8-channel or 16-bit 4-channel
– Separate control for each pulse width and duty cycle
– Center-aligned or left-aligned outputs
– Programmable clock select logic with a wide range of frequencies
– Fast emergency shutdown input
– Usable as interrupt inputs
• Serial interfaces
– Two asynchronous Serial Communications Interfaces (SCI)
– Two Synchronous Serial Peripheral Interface (SPI)
– Byteflight
• Byte Data Link Controller (BDLC)
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• SAE J1850 Class B Data Communications Network Interface
– Compatible and ISO Compatible for Low-Speed (<125 Kbps) Serial Data Communications in
Automotive Applications
• Inter-IC Bus (IIC)
– Compatible with I2C Bus standard
– Multi-master operation
– Software programmable for one of 256 different serial clock frequencies
• 112-Pin LQFP and 80-Pin QFP package options
– I/O lines with 5V input and drive capability
– 5V A/D converter inputs
– Operation at 50MHz equivalent to 25MHz Bus Speed
– Development support
– Single-wire background debug™ mode (BDM)
– On-chip hardware breakpoints
1.3 Modes of Operation
User modes
• Normal and Emulation Operating Modes
– Normal Single-Chip Mode
– Normal Expanded Wide Mode
– Normal Expanded Narrow Mode
– Emulation Expanded Wide Mode
– Emulation Expanded Narrow Mode
• Special Operating Modes
– Special Single-Chip Mode with active Background Debug Mode
– Special Test Mode (Motorola use only)
– Special Peripheral Mode (Motorola use only)
Low power modes
• Stop Mode
• Pseudo Stop Mode
• Wait Mode
17
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1.4 Block Diagram
Figure 1-1 shows a block diagram of the MC9S12DT128B device.
18
VDDR
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VSSR
VREGEN
VDD1,2
VSS1,2
BKGD
XFC
VDDPLL
VSSPLL
EXTAL
XTAL
RESET
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
TEST
Multiplexed
Wide Bus
Multiplexed
Narrow Bus
Internal Logic 2.5V
V
DD1,2
V
SS1,2
PLL 2.5V
V
DDPLL
V
SSPLL
Figure 1-1 MC9S12DT128B Block Diagram
128K Byte Flash EEPROM
8K Byte RAM
2K Byte EEPROM
Voltage Regulator
Single-wire Background
Debug Module
Clock and
Reset
PLL
Generation
Module
XIRQ
IRQ
R/
W
LSTRB
PTE
PA7
ADDR15
DATA15
DATA7
ECLK
DDRE
MODA
MODB
XCLKS
NOACC/
Multiplexed Address/Data Bus
DDRA DDRB
PTA PTB
PA4
PA3
PA2
PA1
ADDR11
ADDR10
ADDR9
DATA11
DATA10
DATA9
DATA3
DATA2
DATA1
PA0
ADDR8
DATA8
DATA0
PA6
PA5
ADDR12
ADDR14
ADDR13
DATA12
DATA14
DATA13
DATA4
DATA6
DATA5
I/O Driver 5V
V
DDX
V
SSX
A/D Converter 5V &
Voltage Regulator Reference
V
DDA
V
SSA
Voltage Regulator 5V & I/O
V
DDR
V
SSR
CPU12
Periodic Interrupt
COP Watchdog
Clock Monitor
Breakpoints
System
Integration
Module
(SIM)
PB4
PB6
PB5
ADDR6
ADDR5
DATA6
DATA5
PB3
ADDR4
ADDR3
DATA4
DATA3
PB7
ADDR7
DATA7
PB2
PB1
ADDR2
ADDR1
DATA2
DATA1
ATD0
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Enhanced Capture
Timer
SCI0
SCI1
SPI0
BDLC
(J1850)
CAN0
PB0
CAN1
BYTEFLIGHT
ADDR0
DATA0
CAN4
IIC
MISO
MOSI
SCK
SS
SPI1
MC9S12DT128B Device User Guide — V01.07
VRH
VRL
VDDA
VSSA
PAD00
PAD01
PAD02
PAD03
PAD04
AD0
PAD05
PAD06
PAD07
PPAGE
MISO
MOSI
SCK
SS
RxB
TxB
RxCAN
TxCAN PM1
RxCAN
TxCAN
RX_BF
TX_BF
BF_PSYN
BF_PROK
BF_PERR
BF_PSLM
RxCAN
TxCAN
SDA
SCL
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
ATD1
PIX0
PIX1
PIX2
PIX3
PIX4
PIX5
ECS
IOC0
IOC1
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7
RXD
TXD
RXD
TXD
Module to Port Routing
KWJ0
KWJ1
KWJ6
KWJ7
KWP0
KWP1
KWP2
KWP3
KWP4
KWP5
KWP6
KWP7
KWH0
KWH1
KWH2
KWH3
KWH4
KWH5
KWH6
KWH7
VRH
VRL
VDDA
VSSA
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
DDRK
DDRT
DDRS
DDRM
DDRJ
DDRP
DDRH
AD1
PTK
PTT
PTS
PTM
PTJ
PTP
PTH
VRH
VRL
VDDA
VSSA
PAD08
PAD09
PAD10
PAD11
PAD12
PAD13
PAD14
PAD15
PK0
PK1
PK2
PK3
PK4
PK5
PK7
PT0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PM0
PM2
PM3
PM4
PM5
PM6
PM7
PJ0
PJ1
PJ6
PJ7
PP0
PP1
PP2
PP3
PP4
PP5
PP6
PP7
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
XADDR14
XADDR15
XADDR16
XADDR17
XADDR18
XADDR19
ECS
Signals shown in Bold are not available in the 80 Pin Package Option
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1.5 Device Memory Map
Table 1-1 and Figure 1-2 show the device memory map of the MC9S12DT128B after reset. Note that
after reset the EEPROM ($0000
($0000 - $1FFF). The bottom 1K Bytes of RAM ($0000 - $03FF) are hidden by the register space.
– $07FF) is hidden by the register space ($0000 - $03FF) and the RAM
Table 1-1 Device Memory Map
Address Module
$0000 – $0017 CORE (Ports A, B, E, Modes, Inits, Test) 24
$0018 – $0019 Reserved 2
$001A – $001B Device ID register (PARTID) 2
$001C – $001F CORE (MEMSIZ, IRQ, HPRIO) 4
$0020 – $0027 Reserved 8
$0028 – $002F CORE (Background Debug Mode) 8
$0030 – $0033 CORE (PPAGE, Port K) 4
$0034 – $003F Clock and Reset Generator (PLL, RTI, COP) 12
$0040 – $007F Enhanced Capture Timer 16-bit 8 channels 64
$0080 – $009F Analog to Digital Converter 10-bit 8 channels (ATD0) 32
$00A0 – $00C7 Pulse Width Modulator 8-bit 8 channels (PWM) 40
$00C8 – $00CF Serial Communications Interface (SCI0) 8
$00D0 – $00D7 Serial Communications Interface (SCI1) 8
$00D8 – $00DF Serial Peripheral Interface (SPI0) 8
$00E0 – $00E7 Inter IC Bus 8
$00E8 – $00EF Byte Level Data Link Controller (BDLC) 8
$00F0 – $00F7 Serial Peripheral Interface (SPI1) 8
$00F8 – $00FF Reserved 8
$0100 – $010F Flash Control Register 16
$0110 – $011B EEPROM Control Register 12
$011C – $011F Reserved 4
$0120 – $013F Analog to Digital Converter 10-bit 8 channels (ATD1) 32
$0140 – $017F Motorola Scalable CAN (CAN0) 64
$0180 – $01BF Motorola Scalable CAN (CAN1) 64
$01C0 – $01FF Reserved 64
$0200 – $023F Reserved 64
$0240 – $027F Port Integration Module (PIM) 64
$0280 – $02BF Motorola Scalable CAN (CAN4) 64
$02C0 – $02FF Reserved 64
$0300 – $035F Byteflight (BF) 96
$0360 – $03FF Reserved 160
$0000 – $07FF EEPROM array 2048
$0000 – $1FFF RAM array 8192
$4000 – $7FFF
$8000 – $BFFF Flash EEPROM Page Window 16384
Fixed Flash EEPROM array
incl. 0.5K, 1K, 2K or 4K Protected Sector at start
Size
(Bytes)
16384
20
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Table 1-1 Device Memory Map
$0000
$0400
$0800
$1000
$2000
$4000
$8000
Address Module
Fixed Flash EEPROM array
$C000 – $FFFF
incl. 0.5K, 1K, 2K or 4K Protected Sector at end
and 256 bytes of Vector Space at $FF80
Figure 1-2 MC9S12DT128B Memory Map
EXT
– $FFFF
$0000
$03FF
$0800
$0FFF
$2000
$3FFF
$4000
$7FFF
$8000
Size
(Bytes)
16384
1K Register Space
Mappable to any 2K Boundary
2K Bytes EEPROM
Mappable to any 2K Boundary
8K Bytes RAM
Mappable to any 8K Boundary
0.5K, 1K, 2K or 4K Protected Sector
16K Fixed Flash EEPROM
16K Page Window
eight * 16K Flash EEPROM Pages
$C000
$FF00
$FFFF
NORMAL
SINGLE CHIP
The address does not show the map after reset, but a useful map. After reset the map is:
$0000 – $03FF: Register Space
$0000 – $1FFF: 8K RAM
$0000 – $07FF: 2K EEPROM (not visible)
VECTORSVECTORS VECTORS
EXPANDED SPECIAL
SINGLE CHIP
$BFFF
$C000
$FFFF
$FF00
$FFFF
16K Fixed Flash EEPROM
2K, 4K, 8K or 16K Protected Boot Sector
BDM
(If Active)
21
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1.5.1 Detailed Register Map
$0000 - $000F MEBI map 1 of 3 (Core User Guide)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0000 PORTA
$0001 PORTB
$0002 DDRA
$0003 DDRB
$0004 Reserved
$0005 Reserved
$0006 Reserved
$0007 Reserved
$0008 PORTE
$0009 DDRE
$000A PEAR
$000B MODE
$000C PUCR
$000D RDRIV
$000E EBICTL
$000F Reserved
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read: 00000000
Write:
Read: 00000000
Write:
Read: 00000000
Write:
Read: 00000000
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read: 0000000
Write:
Read: 00000000
Write:
Bit 7 654321Bit 0
Bit 7 654321Bit 0
Bit 7 654321Bit 0
Bit 7 654321Bit 0
Bit 7 65432
Bit 7 6543Bit 2
NOACCE
MODC MODB MODA
PUPKE
RDPK
0
00
00
PIPOE NECLK LSTRE RDWE
PUPEE
RDPE
0
IVIS
00
00
0
PUPBE PUPAE
Bit 1 Bit 0
00
00
EMK EME
RDPB RDPA
ESTR
$0010 - $0014 MMC map 1 of 4 (Core User Guide)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0010 INITRM
$0011 INITRG
$0012 INITEE
$0013 MISC
$0014
22
MTST0
Test Only
Read:
Write:
Read: 0
Write:
Read:
Write:
Read: 0000
Write:
Read: Bit 7 654321Bit 0
Write:
RAM15 RAM14 RAM13 RAM12 RAM11
REG14 REG13 REG12 REG11
EE15 EE14 EE13 EE12
000
EXSTR1 EXSTR0 ROMHM ROMON
00
000
RAMHAL
EEON
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$0015 - $0016 INT map 1 of 2 (Core User Guide)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0015 ITCR
$0016 ITEST
Read: 0 0 0
Write:
Read:
Write:
INTE INTC INTA INT8 INT6 INT4 INT2 INT0
WRINT ADR3 ADR2 ADR1 ADR0
$0017 - $0017 MMC map 2 of 4 (Core User Guide)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0017
MTST1
Test Only
Read: Bit 7 654321Bit 0
Write:
$0018 - $001B Miscellaneous Peripherals (Device User Guide, Table 1-3)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0018 Reserved
$0019 Reserved
$001A PARTIDH
$001B PARTIDL
Read: 00000000
Write:
Read: 00000000
Write:
Read: ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8
Write:
Read: ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
Write:
$001C - $001D MMC map 3 of 4 (Core and Device User Guide, Table 1-4)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$001C MEMSIZ0
$001D MEMSIZ1
Read: reg_sw0 0 eep_sw1 eep_sw0 0 ram_sw2 ram_sw1 ram_sw0
Write:
Read: rom_sw1 rom_sw0 0000pag_sw1 pag_sw0
Write:
$001E - $001E MEBI map 2 of 3 (Core User Guide)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$001E INTCR
Read:
Write:
IRQE IRQEN
000000
$001F - $001F INT map 2 of 2 (Core User Guide)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$001F HPRIO
Read:
Write:
PSEL7 PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1
0
23
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$0020 - $0027 Reserved
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0020 -
$0027
Reserved
Read: 00000000
Write:
$0028 - $002F BKP (Core User Guide)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0028 BKPCT0
$0029 BKPCT1
$002A BKP0X
$002B BKP0H
$002C BKP0L
$002D BKP1X
$002E BKP1H
$002F BKP1L
Read:
Write:
Read:
Write:
Read: 0 0
Write:
Read:
Write:
Read:
Write:
Read: 0 0
Write:
Read:
Write:
Read:
Write:
BKEN BKFULL BKBDM BKTAG
BK0MBH BK0MBL BK1MBH BK1MBL BK0RWE BK0RW BK1RWE BK1RW
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
BK0V5 BK0V4 BK0V3 BK0V2 BK0V1 BK0V0
BK1V5 BK1V4 BK1V3 BK1V2 BK1V1 BK1V0
0000
$0030 - $0031 MMC map 4 of 4 (Core User Guide)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0030 PPAGE
$0031 Reserved
Read: 0 0
Write:
Read: 00000000
Write:
PIX5 PIX4 PIX3 PIX2 PIX1 PIX0
$0032 - $0033 MEBI map 3 of 3 (Core User Guide)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0032 PORTK
$0033 DDRK
Read:
Write:
Read:
Write:
Bit 7 654321Bit 0
Bit 7 654321Bit 0
24
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$0034 - $003F CRG (Clock and Reset Generator)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0034 SYNR
$0035 REFDV
$0036
$0037 CRGFLG
$0038 CRGINT
$0039 CLKSEL
$003A PLLCTL
$003B RTICTL
$003C COPCTL
$003D
$003E
$003F ARMCOP
CTFLG
TEST ONLY
FORBYP
TEST ONLY
CTCTL
TEST ONLY
Read: 0 0
Write:
Read: 0000
Write:
Read: 00000000
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read: 0
Write:
Read:
Write:
Read: 00000000
Write:
Read: 00000000
Write:
Read: 00000000
Write: Bit 7 654321Bit 0
RTIF PORF
RTIE
PLLSEL PSTP SYSWAI ROAWAI PLLWAI CWAI RTIWAI COPWAI
CME PLLON AUTO ACQ
WCOP RSBCK
00
RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0
SYN5 SYN4 SYN3 SYN2 SYN1 SYN0
REFDV3 REFDV2 REFDV1 REFDV0
0
LOCKIF
LOCKIE
000
LOCK TRACK
00
0
PRE PCE SCME
CR2 CR1 CR0
SCMIF
SCMIE
SCM
0
$0040 - $007F ECT (Enhanced Capture Timer 16 Bit 8 Channels)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0040 TIOS
$0041 CFORC
$0042 OC7M
$0043 OC7D
$0044 TCNT (hi)
$0045 TCNT (lo)
$0046 TSCR1
$0047 TTOV
$0048 TCTL1
$0049 TCTL2
Read:
Write:
Read: 00000000
Write: FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0
Read:
Write:
Read:
Write:
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read: Bit 7 654321Bit 0
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0
OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0
OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0
TEN TSWAI TSFRZ TFFCA
TOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0
OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4
OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0
0000
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$0040 - $007F ECT (Enhanced Capture Timer 16 Bit 8 Channels)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$004A TCTL3
$004B TCTL4
$004C TIE
$004D TSCR2
$004E TFLG1
$004F TFLG2
$0050 TC0 (hi)
$0051 TC0 (lo)
$0052 TC1 (hi)
$0053 TC1 (lo)
$0054 TC2 (hi)
$0055 TC2 (lo)
$0056 TC3 (hi)
$0057 TC3 (lo)
$0058 TC4 (hi)
$0059 TC4 (lo)
$005A TC5 (hi)
$005B TC5 (lo)
$005C TC6 (hi)
$005D TC6 (lo)
$005E TC7 (hi)
$005F TC7 (lo)
$0060 PACTL
$0061 PAFLG
$0062 PACN3 (hi)
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read: 0
Write:
Read: 000000
Write:
Read:
Write:
EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A
EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A
C7I C6I C5I C4I C3I C2I C1I C0I
TOI
C7F C6F C5F C4F C3F C2F C1F C0F
TOF
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
Bit 7 654321Bit 0
000
0000000
PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI
TCRE PR2 PR1 PR0
PAOVF PAIF
26
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$0040 - $007F ECT (Enhanced Capture Timer 16 Bit 8 Channels)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0063 PACN2 (lo)
$0064 PACN1 (hi)
$0065 PACN0 (lo)
$0066 MCCTL
$0067 MCFLG
$0068 ICPAR
$0069 DLYCT
$006A ICOVW
$006B ICSYS
$006C Reserved
$006D
$006E Reserved
$006F Reserved
$0070 PBCTL
$0071 PBFLG
$0072 PA3H
$0073 PA2H
$0074 PA1H
$0075 PA0H
$0076 MCCNT (hi)
$0077 MCCNT (lo)
$0078 TC0H (hi)
$0079 TC0H (lo)
$007A TC1H (hi)
$007B TC1H (lo)
TIMTST
Test Only
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write: ICLAT FLMC
Read:
Write:
Read: 0000
Write:
Read: 000000
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read: 000000
Write:
Read:
Write:
Read:
Write:
Read: 0
Write:
Read: 000000
Write:
Read: Bit 7 654321Bit 0
Write:
Read: Bit 7 654321Bit 0
Write:
Read: Bit 7 654321Bit 0
Write:
Read: Bit 7 654321Bit 0
Write:
Read:
Write:
Read:
Write:
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read: Bit 7 654321Bit 0
Write:
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read: Bit 7 654321Bit 0
Write:
Bit 7 654321Bit 0
Bit 7 654321Bit 0
Bit 7 654321Bit 0
MCZI MODMC RDMCL
MCZF
NOVW7 NOVW6 NOVW5 NOVW4 NOVW3 NOVW2 NOVW1 NOVW0
SH37 SH26 SH15 SH04 TFMOD PACMX BUFEN LATQ
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 654321Bit 0
0 0 0 POLF3 POLF2 POLF1 POLF0
PBEN
0000
00
PA3EN PA2EN PA1EN PA0EN
MCEN MCPR1 MCPR0
DLY1 DLY0
TCBYP
PBOVI
PBOVF
0
0
0
27
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$0040 - $007F ECT (Enhanced Capture Timer 16 Bit 8 Channels)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$007C TC2H (hi)
$007D TC2H (lo)
$007E TC3H (hi)
$007F TC3H (lo)
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read: Bit 7 654321Bit 0
Write:
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Read: Bit 7 654321Bit 0
Write:
$0080 - $009F ATD0 (Analog to Digital Converter 10 Bit 8 Channel)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0080 ATD0CTL0
$0081 ATD0CTL1
$0082 ATD0CTL2
$0083 ATD0CTL3
$0084 ATD0CTL4
$0085 ATD0CTL5
$0086 ATD0STAT0
$0087 Reserved
$0088 ATD0TEST0
$0089 ATD0TEST1
$008A Reserved
$008B ATD0STAT1
$008C Reserved
$008D ATD0DIEN
$008E Reserved
$008F PORTAD0
$0090 ATD0DR0H
$0091 ATD0DR0L
Read: 00000000
Write:
Read: 00000000
Write:
Read:
Write:
Read: 0
Write:
Read:
Write:
Read:
Write:
Read: SCF 0 ETORF FIFOR 0 CC2 CC1 CC0
Write:
Read: 00000000
Write:
Read: 00000000
Write:
Read: 00000
Write:
Read: 00000000
Write:
Read: CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0
Write:
Read: 00000000
Write:
Read:
Write:
Read: 00000000
Write:
Read: Bit7 654321BIT 0
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
Write:
Read: Bit7 Bit6 000000
Write:
ADPU AFFC AWAI ETRIGLE ETRIGP ETRIG ASCIE
S8C S4C S2C S1C FIFO FRZ1 FRZ0
SRES8 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0
DJM DSGN SCAN MULT
Bit 7 654321Bit 0
0
CC CB CA
0
ASCIF
0
SC
28
MC9S12DT128B Device User Guide — V01.07
http://www.xinpian.net
提供单片机解密、IC解密、芯片解密业务
010-62245566 13810019655
$0080 - $009F ATD0 (Analog to Digital Converter 10 Bit 8 Channel)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0092 ATD0DR1H
$0093 ATD0DR1L
$0094 ATD0DR2H
$0095 ATD0DR2L
$0096 ATD0DR3H
$0097 ATD0DR3L
$0098 ATD0DR4H
$0099 ATD0DR4L
$009A ATD0DR5H
$009B ATD0DR5L
$009C ATD0DR6H
$009D ATD0DR6L
$009E ATD0DR7H
$009F ATD0DR7L
Read: Bit15 14 13 12 11 10 9 Bit8
Write:
Read: Bit7 Bit6 000000
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
Write:
Read: Bit7 Bit6 000000
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
Write:
Read: Bit7 Bit6 000000
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
Write:
Read: Bit7 Bit6 000000
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
Write:
Read: Bit7 Bit6 000000
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
Write:
Read: Bit7 Bit6 000000
Write:
Read: Bit15 14 13 12 11 10 9 Bit8
Write:
Read: Bit7 Bit6 000000
Write:
$00A0 - $00C7 PWM (Pulse Width Modulator 8 Bit 8 Channel)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$00A0 PWME
$00A1 PWMPOL
$00A2 PWMCLK
$00A3 PWMPRCLK
$00A4 PWMCAE
$00A5 PWMCTL
$00A6
$00A7
$00A8 PWMSCLA
PWMTST
Test Only
PWMPRSC
Test Only
Read:
Write:
Read:
Write:
Read:
Write:
Read: 0
Write:
Read:
Write:
Read:
Write:
Read: 00000000
Write:
Read: 00000000
Write:
Read:
Write:
PWME7 PWME6 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0
PPOL7 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0
PCLK7 PCLK6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0
PCKB2 PCKB1 PCKB0
CAE7 CAE6 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0
CON67 CON45 CON23 CON01 PSWAI PFRZ
Bit 7 6 5 4 3 2 1 Bit 0
0
PCKA2 PCKA1 PCKA0
00
29
MC9S12DT128B Device User Guide — V01.07
http://www.xinpian.net
提供单片机解密、IC解密、芯片解密业务
010-62245566 13810019655
$00A0 - $00C7 PWM (Pulse Width Modulator 8 Bit 8 Channel)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$00A9 PWMSCLB
$00AA
$00AB
$00AC PWMCNT0
$00AD PWMCNT1
$00AE PWMCNT2
$00AF PWMCNT3
$00B0 PWMCNT4
$00B1 PWMCNT5
$00B2 PWMCNT6
$00B3 PWMCNT7
$00B4 PWMPER0
$00B5 PWMPER1
$00B6 PWMPER2
$00B7 PWMPER3
$00B8 PWMPER4
$00B9 PWMPER5
$00BA PWMPER6
$00BB PWMPER7
$00BC PWMDTY0
$00BD PWMDTY1
$00BE PWMDTY2
$00BF PWMDTY3
$00C0 PWMDTY4
$00C1 PWMDTY5
PWMSCNTA
Test Only
PWMSCNTB
Test Only
Read:
Write:
Read: 00000000
Write:
Read: 00000000
Write:
Read: Bit 7 6 5 4 3 2 1 Bit 0
Write: 00000000
Read: Bit 7 6 5 4 3 2 1 Bit 0
Write: 00000000
Read: Bit 7 6 5 4 3 2 1 Bit 0
Write: 00000000
Read: Bit 7 6 5 4 3 2 1 Bit 0
Write: 00000000
Read: Bit 7 6 5 4 3 2 1 Bit 0
Write: 00000000
Read: Bit 7 6 5 4 3 2 1 Bit 0
Write: 00000000
Read: Bit 7 6 5 4 3 2 1 Bit 0
Write: 00000000
Read: Bit 7 6 5 4 3 2 1 Bit 0
Write: 00000000
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
30
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