Motorola MC9S12C128, MC9S12GC128, MC9S12C96, MC9S12C64, MC9S12GC64 User Manual

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MC9S12C Family

Device User Guide

V01.05

Covers also

MC9S12GC Family

DOCUMENT NUMBER

9S12C128DGV1/D

Original Release Date: 25 JAN 2003

Revised: 11 FEBRUARY 2004

Motorola, Inc.

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products forany particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonableattorney fees arising out of, directly or indirectly,any claim of personal injuryor death associated with such unintended or unauthorizeduse, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal

Opportunity/Affirmative Action Employer.

©Motorola, Inc., 2002

Revision History

Device User Guide — 9S12C128DGV1/D V01.05

Version Number

00.01 25.JAN.03 25.JAN.03 Original Version. Based on C32 user guide version 01.12

00.02 07.FEB.03 07.FEB.03

00.03 25.FEB.03 25.FEB.03

00.04 15.APR.03 15.APR03

00.05 05.MAY.03 05.MAY.03

00.06 21.MAY.03 21.MAY.03

01.00 15.JUL.03 15.JUL03

01.01 12.AUG.03 12.AUG.03 Updated PARTID listing due to C128 ECO revision

01.02 20.NOV.03 20.NOV.03

01.03 27.NOV.03 27.NOV.03

01.04 27.JAN.04 27.JAN.04

01.05 11.FEB.04 11.FEB.04

Revision

Date

Effective

Date

Author Description of Changes

Enhanced PortK description Part number table revision in preface

QFP112 Emulation pinout correction Enhanced part number explanation in preface Reduced pseudo STOP current spec. for C64,C96,C128

Enhanced PortAD signal description Corrected VDDR description in 2.4.2 Revised pin leakage in electrical parameters

SPI timing parameter table correction Output drive high value reduced in 3V range PE[4:2] Pull-Up spec out of reset changed 3V Expansion bus timing parameters not tested in production Minimum bus frequency speciﬁcation increased to 0.25MHz.

Parameter classiﬁcation added to Appendix Table C-2. IOH changed to 4mA for 3V range.

LVR level deﬁned.for C32. Run IDD changed for C32. Block guide reference table updated Added PCB layout guide for Pierce oscillator conﬁguration IOL parameter updated in 3.3V range

Changed DOC number and CPU DOC reference number Included separate C32 LVI levels Changed PortM pull up reset state to enabled.

Added References to the CAN-less GC-Family No major revision number increment, since silicon functionality is not changed. Added VDDX connection in PCB layout ﬁgures 8-1.to 8-6 Added Part ID for 2L45J mask set to Part ID table

Table A-4 VDD/VDDPLL min when supplied externally now 2.35V Reference S12FTS128K1 in Preface (was S12FTS128K) Reference to CPU Guide corrected to Version2

Corrected ﬂash sector sizes for C-Family devices with >64K Flash Corrected Preface Table 0-1 16K part listing to GC16 without CAN Added PPAGE speciﬁcations to memory map diagrams Added ﬂash timing parameters for 1024 byte sector size

Device User Guide — 9S12C128DGV1/D V01.05

Table of Contents

Section 1 Introduction

1.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

1.5 Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

1.6 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

1.7 Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Section 2 Signal Description

2.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

2.2 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

2.2.1 Pin Initialization for 48 & 52 Pin LQFP bond-out versions . . . . . . . . . . . . . . . . . . 56

2.3 Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

2.3.1 EXTAL, XTAL — Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

2.3.2 RESET — External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

2.3.3 TEST / VPP — Test Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

2.3.4 XFC — PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

2.3.5 BKGD / TAGHI / MODC — Background Debug, Tag High & Mode Pin . . . . . . . 58

2.3.6 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins . . . . . . . . . . . . . . . . . . . . 58

2.3.7 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . 58

2.3.8 PE7 / NOACC / XCLKS — Port E I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

2.3.9 PE6 / MODB / IPIPE1 — Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

2.3.10 PE5 / MODA / IPIPE0 — Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

2.3.11 PE4 / ECLK— Port E I/O Pin [4] / E-Clock Output. . . . . . . . . . . . . . . . . . . . . . . . 60

2.3.12 PE3 / LSTRB — Port E I/O Pin [3] / Low-Byte Strobe (LSTRB). . . . . . . . . . . . . . 60

2.3.13 PE2 / R/W — Port E I/O Pin [2] / Read/Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

2.3.14 PE1 / IRQ — Port E input Pin [1] / Maskable Interrupt Pin . . . . . . . . . . . . . . . . . 61

2.3.15 PE0 / XIRQ — Port E input Pin [0] / Non Maskable Interrupt Pin . . . . . . . . . . . . 61

2.3.16 PAD[7:0] / AN[7:0] — Port AD I/O Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

2.3.17 PP[7] / KWP[7] — Port P I/O Pin [7]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

2.3.18 PP[6] / KWP[6]/ROMCTL — Port P I/O Pin [6] . . . . . . . . . . . . . . . . . . . . . . . . . . 61

2.3.19 PP[5:0] / KWP[5:0] / PW[5:0] — Port P I/O Pins [5:0] . . . . . . . . . . . . . . . . . . . . . 62

Device User Guide — 9S12C128DGV1/D V01.05

2.3.20 PJ[7:6] / KWJ[7:6] — Port J I/O Pins [7:6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

2.3.21 PM5 / SCK — Port M I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

2.3.22 PM4 / MOSI — Port M I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

2.3.23 PM3 / SS — Port M I/O Pin 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

2.3.24 PM2 / MISO — Port M I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

2.3.25 PM1 / TXCAN — Port M I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

2.3.26 PM0 / RXCAN — Port M I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

2.3.27 PS[3:2] — Port S I/O Pins [3:2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

2.3.28 PS1 / TXD — Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

2.3.29 PS0 / RXD — Port S I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

2.3.30 PPT[7:5] / IOC[7:5] — Port T I/O Pins [7:5] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

2.3.31 PT[4:0] / IOC[4:0] / PW[4:0]— Port T I/O Pins [4:0]. . . . . . . . . . . . . . . . . . . . . . . 63

2.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

2.4.1 VDDX,VSSX — Power & Ground Pins for I/O Drivers. . . . . . . . . . . . . . . . . . . . . 63

2.4.2 VDDR, VSSR — Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator 63

2.4.3 VDD1, VDD2, VSS1, VSS2 — Internal Logic Power Pins. . . . . . . . . . . . . . . . . . 63

2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG . . . . . . . . . . . . . . . . . . 64

2.4.5 VRH, VRL — ATD Reference Voltage Input Pins . . . . . . . . . . . . . . . . . . . . . . . . 64

2.4.6 VDDPLL, VSSPLL — Power Supply Pins for PLL. . . . . . . . . . . . . . . . . . . . . . . . 64

Section 3 System Clock Description

Section 4 Modes of Operation

4.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

4.2 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

4.3 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

4.3.1 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

4.3.2 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

4.3.3 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

4.4.1 Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

4.4.2 Pseudo Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

4.4.3 Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

4.4.4 Run. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Section 5 Resets and Interrupts

Device User Guide — 9S12C128DGV1/D V01.05

5.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

5.2 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

5.2.1 Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

5.3 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

5.3.1 Reset Summary Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

5.3.2 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Section 6 HCS12 Core Block Description

6.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

6.1.1 PPAGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

6.1.2 BDM alternate clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.1.3 Extended Address Range Emulation Implications. . . . . . . . . . . . . . . . . . . . . . . . 71

Section 7 Voltage Regulator (VREG) Block Description

7.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

7.1.1 VREGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

7.1.2 VDD1, VDD2, VSS1, VSS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Section 8 Recommended Printed Circuit Board Layout

Section 9 Clock Reset Generator (CRG) Block Description

9.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

9.1.1 XCLKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Section 10 Oscillator (OSC) Block Description

Section 11 Timer (TIM) Block Description

Section 12 Analog to Digital Converter (ATD) Block Description

12.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

12.1.1 VRL (voltage reference low). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Section 13 Serial Communications Interface (SCI) Block Description

Section 14 Serial Peripheral Interface (SPI) Block Description

Section 15 Flash Block Description

Device User Guide — 9S12C128DGV1/D V01.05

Section 16 RAM Block Description

Section 17 Pulse Width Modulator (PWM) Block Description

Section 18 MSCAN Block Description

Section 19 Port Integration Module (PIM) Block Description

Appendix A Electrical Characteristics

A.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

A.1.2 Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

A.1.4 Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

A.1.6 ESD Protection and Latch-up Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 87

A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Appendix B Electrical Specifications

B.1 Voltage Regulator Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

B.2 Chip Power-up and LVI/LVR graphical explanation. . . . . . . . . . . . . . . . . . . . . . . . . 96

B.3 Output Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

B.3.1 Resistive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

B.3.2 Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

B.4 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

B.4.1 ATD Operating Characteristics In 5V Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

B.4.2 ATD Operating Characteristics In 3.3V Range . . . . . . . . . . . . . . . . . . . . . . . . . . 99

B.4.3 Factors influencing accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

B.4.4 ATD accuracy (5V Range). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

B.4.5 ATD accuracy (3.3V Range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

B.5 NVM, Flash and EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

B.5.1 NVM timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

B.5.2 NVM Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Device User Guide — 9S12C128DGV1/D V01.05

B.6 Reset, Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

B.6.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

B.6.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

B.6.3 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

B.7 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

B.8 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Appendix C Electrical Specifications

C.1 Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

C.2 Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

C.3 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

C.3.1 General Muxed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Appendix D Package Information

D.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

D.2 80-pin QFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

D.3 52-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

D.4 48-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Appendix E Emulation Information

E.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

E.1.1 PK[2:0] / XADDR[16:14]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

E.2 112-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Device User Guide — 9S12C128DGV1/D V01.05

List of Figures

Figure 0-1 Order Part number Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 1-1 MC9S12C-Family Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 1-2 MC9S12C128 and MC9S12GC128 User configurable Memory Map . . . . . . 29

Figure 1-3 MC9S12C96 User Configurable Memory Map . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 1-4 MC9S12C64 and MC9S12GC64 User Configurable Memory Map. . . . . . . . 31

Figure 1-5 MC9S12C32 and MC9S12GC32 User Configurable Memory Map. . . . . . . . 32

Figure 1-6 MC9S12GC16 User Configurable Memory Map . . . . . . . . . . . . . . . . . . . . . . 33

Figure 2-1 Pin Assignments in 80 QFP for MC9S12C-Family . . . . . . . . . . . . . . . . . . . . 52

Figure 2-2 Pin assignments in 52 LQFP for MC9S12C-Family. . . . . . . . . . . . . . . . . . . . 53

Figure 2-3 Pin Assignments in 48 LQFP for MC9S12C-Family . . . . . . . . . . . . . . . . . . .54

Figure 2-4 PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 2-5 Colpitts Oscillator Connections (PE7=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 2-6 Pierce Oscillator Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 2-7 External Clock Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 3-1 Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 8-1 Recommended PCB Layout (48 LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 8-2 Recommended PCB Layout (52 LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 8-3 Recommended PCB Layout (80 QFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 8-4 Recommended PCB Layout for 48 LQFP Pierce Oscillator . . . . . . . . . . . . . 77

Figure 8-5 Recommended PCB Layout for 52 LQFP Pierce Oscillator . . . . . . . . . . . . . 78

Figure 8-6 Recommended PCB Layout for 80QFP Pierce Oscillator . . . . . . . . . . . . . . . 79

Figure B-1 Voltage Regulator - Chip Power-up and Voltage Drops (not scaled) . . . . . 96

Figure B-2 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure B-3 Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure B-4 Jitter Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure B-5 Maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure C-1 SPI Master Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure C-2 SPI Master Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure C-3 SPI Slave Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure C-4 SPI Slave Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure C-5 General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Figure D-1 80-pin QFP Mechanical Dimensions (case no. 841B). . . . . . . . . . . . . . . . 128

Figure D-2 52-pin LQFP Mechanical Dimensions (case no. 848D-03) . . . . . . . . . . . . 129

Device User Guide — 9S12C128DGV1/D V01.05

Figure D-3 48-pin LQFP Mechanical Dimensions (case no.932-03 ISSUE F) . . . . . . 130

Figure 19-1 Pin Assignments in 112-pin LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Figure 19-2 112-pin LQFP mechanical dimensions (case no. 987)80-pin QFP Mechanical Dimensions (case no. 841B)133

Device User Guide — 9S12C128DGV1/D V01.05

List of Tables

Table 0-2 MC9S12C-Family Package Option Summary . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 0-1 List of MC9S12C and MC9S12GC Family members. . . . . . . . . . . . . . . . . . . . 15

Table 0-3 MC9S12C-Family Part Number Coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 0-4 MC9S12GC-Family Part Number Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 0-5 Document References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 1-1 Device Register Map Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

$0000 - $000FMEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface) 34 $0010 - $0014 MMC map 1 of 4 (HCS12 Module Mapping Control) 34 $0018 - $0018 Miscellaneous Peripherals (Device User Guide) 35 $0019 - $0019 VREG3V3 (Voltage Regulator) 35 $0015 - $0016 INT map 1 of 2 (HCS12 Interrupt) 35 $0017 - $0017MMC map 2 of 4 (HCS12 Module Mapping Control) 35 $001A - $001B Miscellaneous Peripherals (Device User Guide) 35 $001C - $001D MMC map 3 of 4 (HCS12 Module Mapping Control, 36 Device User Guide) 36 $001E - $001E MEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface) 36 $001F - $001F INT map 2 of 2 (HCS12 Interrupt) 36 $0020 - $002F DBG (including BKP) map 1 of 1 (HCS12 Debug) 36 $0030 - $0031 MMC map 4 of 4 (HCS12 Module Mapping Control) 37 $0032 - $0033 MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface) 37 $0034 - $003F CRG (Clock and Reset Generator) 37 $0040 - $006F TIM (Timer 16 Bit 8 Channels) 38 $0070 - $007F Reserved 40 $0080 - $009F ATD (Analog to Digital Converter 10 Bit 8 Channel) 40 $00A0 - $00C7 Reserved 41 $00D0 - $00D7 Reserved 42 $00C8 - $00CF SCI (Asynchronous Serial Interface) 42 $00D8 - $00DF SPI (Serial Peripheral Interface) 42 $00E0 - $00FF PWM (Pulse Width Modulator) 43 $0100 - $010F Flash Control Register 44 $0110 - $013F Reserved 45 $0140 - $017F CAN (Motorola Scalable CAN - MSCAN) 45

Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout. . . . . . . . 46

Device User Guide — 9S12C128DGV1/D V01.05

$0180 - $023F Reserved 47 $0240 - $027F PIM (Port Interface Module) 47 $0280 - $03FF Reserved space 50

Table 1-3 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 1-4 Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 2-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 2-2 MC9S12C-Family Power and Ground Connection Summary . . . . . . . . . . . . . 64

Table 4-1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 4-2 Clock Selection Based on PE7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 5-1 Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 5-2 Reset Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 6-1 Device Specific Flash PAGE Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 8-1 Recommended External Component Values. . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table A-1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table A-2 ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table A-3 ESD and Latch-Up Protection Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 86

Table A-4 Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table A-5 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table A-6 5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table A-7 3.3V I/O Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table A-8 Supply Current Characteristics for MC9S12C32 . . . . . . . . . . . . . . . . . . . . . . . 93

Table A-9 Supply Current Characteristics for MC9S12C64,MC9S12C96,MC9S12C128 94

Table B-1 Voltage Regulator Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table B-2 Voltage Regulator - Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table B-3 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table B-4 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table B-5 ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table B-6 ATD Conversion Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table B-7 ATD Conversion Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table B-8 NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table B-9 NVM Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table B-10 Startup Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

Table B-11 Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

Table B-12 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

Table B-13 MSCAN Wake-up Pulse Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table C-1 Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Device User Guide — 9S12C128DGV1/D V01.05

Table C-2 SPI Master Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . .120

Table C-3 SPI Slave Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

Table C-4 Expanded Bus Timing Characteristics (5V Range). . . . . . . . . . . . . . . . . . . .124

Table C-5 Expanded Bus Timing Characteristics (3.3V Range) . . . . . . . . . . . . . . . . . .125

Device User Guide — 9S12C128DGV1/D V01.05

Preface

TheDeviceUser Guide provides information about the MC9S12C-Family as well the MC9S12GC-Family devices made up of standard HCS12 blocks and the HCS12 processor core. This document is part of the customer documentation. A completeset of device manualsalso includes the HCS12Core User Guide and all the individual Block User Guides of the implemented modules. In an effort to reduce redundancy all module specific information is located only in the respective Block User Guide. If applicable, special implementation details of the module are given in the block description sections of this document.

The C-Family and the GC-Family offer an extensive range of package, temperature and speed options. The members of the GC-Family do not feature a CAN module.

Table 0-1 shows a feature overview of the MC9S12C and MC9S12GC Family members. Table 0-2 summarizes the package option and size configuration. Table 0-3 lists the part number coding based on the package, speed and temperature and preliminary die

options for the C-Family. Table 0-4 lists the part number coding based on the package, speed and temperature and preliminary die

options for the GC-Family.

Table 0-1 List of MC9S12C and MC9S12GC Family members

Flash RAM Device CAN SCI SPI A/D PWM Timer

128K 4K

96K 4K MC9S12C96 1 1 1 8ch 6ch 8ch 64K 4K

32K 2K 16K 1K MC9S12GC16 — 1 1 8ch 6ch 8ch

MC9S12C128 1 1 1 8ch 6ch 8ch

MC9S12GC128 — 1 1 8ch 6ch 8ch

MC9S12C64 1 1 1 8ch 6ch 8ch

MC9S12GC64 — 1 1 8ch 6ch 8ch

MC9S12C32 1 1 1 8ch 6ch 8ch

MC9S12GC32 — 1 1 8ch 6ch 8ch

Table 0-2 MC9S12C-Family Package Option Summary

Package Device Part Number

48LQFP MC9S12C128 MC9S12C128 0L09S M, V, C 52LQFP MC9S12C128 MC9S12C128 0L09S M, V, C 35

80QFP MC9S12C128 MC9S12C128 0L09S M, V, C 60 48LQFP MC9S12C96 MC9S12C96 TBD M, V, C 52LQFP MC9S12C96 MC9S12C96 TBD M, V, C 35

80QFP MC9S12C96 MC9S12C96 TBD M, V, C 60

Mask

set

Options

Temp.

Flash RAM

128K 4K

96K 4K

I/O3,

Device User Guide — 9S12C128DGV1/D V01.05

Package Device Part Number

48LQFP MC9S12C64 MC9S12C64 TBD M, V, C 52LQFP MC9S12C64 MC9S12C64 TBD M, V, C 35

80QFP MC9S12C64 MC9S12C64 TBD M, V, C 60 48LQFP MC9S12C32 MC9S12C32 1L45J M, V, C 52LQFP MC9S12C32 MC9S12C32 1L45J M, V, C 35

80QFP MC9S12C32 MC9S12C32 1L45J M, V, C 60 48LQFP MC9S12GC128 MC9S12GC128 0L09S M, V, C 52LQFP MC9S12GC128 MC9S12GC128 0L09S M, V, C 35

80QFP MC9S12GC128 MC9S12GC128 0L09S M, V, C 60 48LQFP MC9S12GC128 MC9S12GC64 TBD M, V, C 52LQFP MC9S12GC128 MC9S12GC64 TBD M, V, C 35

80QFP MC9S12GC128 MC9S12GC64 TBD M, V, C 60 48LQFP MC9S12GC32 MC9S12GC32 1L45J M, V, C 52LQFP MC9S12GC32 MC9S12GC32 1L45J M, V, C 35

80QFP MC9S12GC32 MC9S12GC32 1L45J M, V, C 60 48LQFP MC9S12GC16 MC9S12GC16 1L45J M, V, C 52LQFP MC9S12GC16 MC9S12GC16 1L45J M, V, C 35

80QFP MC9S12GC16 MC9S12GC16 1L45J M, V, C 60

NOTES:

1. Maskset dependent errata can be accessed at

http://e-www.motorola.com/wbapp/sps/site/prod_summary.jsp

2. C: T

3. All C-Family derivatives feature 1 CAN, 1 SCI, 1 SPI, an 8-channel A/D, a 6-channel PWM and an 8

4. I/O is the sum of ports capable to act as digital input or output.

= 85˚C, f = 25MHz. V: TA=105˚C, f = 25MHz. M: TA= 125˚C, f = 25MHz

channel timer. The GC-Family members do not have the CAN module

Mask

set

Options

Temp.

Flash RAM

64K 4K

32K 2K

128K 4K

64K 4K

32K 2K

16K 2K

I/O3,

MC9S12 C32 (P)C FU 25

Temperature Options

C = -40˚C to 85˚C

Speed Option Package Option

Temperature Option

V = -40˚C to 105˚C M = -40˚C to 125˚C

Package Options

FU = 80QFP PB = 52LQFP

Preliminary Option

FA = 48LQFP

Speed Options

Device Title

25 = 25MHz bus 16 = 16MHz bus

Controller Famil

Figure 0-1 Order Part number Coding

Table 0-3 MC9S12C-Family Part Number Coding

Part Number

MC9S12C128CFA16 TBD -40˚C, 85˚C 48LQFP 16MHz C128 die

Mask

set

Temp. Package Speed Description

Device User Guide — 9S12C128DGV1/D V01.05

Part Number

MC9S12C128CPB16 TBD -40˚C, 85˚C 52LQFP 16MHz C128 die MC9S12C128CFU16 TBD -40˚C, 85˚C 80QFP 16MHz C128 die MC9S12C128VFA16 TBD -40˚C,105˚C 48LQFP 16MHz C128 die MC9S12C128VPB16 TBD -40˚C,105˚C 52LQFP 16MHz C128 die

MC9S12C128VFU16 TBD -40˚C, 105˚C 80QFP 16MHz C128 die MC9S12C128MFA16 TBD -40˚C,125˚C 48LQFP 16MHz C128 die MC9S12C128MPB16 TBD -40˚C,125˚C 52LQFP 16MHz C128 die MC9S12C128MFU16 TBD -40˚C, 125˚C 80QFP 16MHz C128 die

MC9S12C128CFA25 TBD -40˚C, 85˚C 48LQFP 25MHz C128 die MC9S12C128CPB25 TBD -40˚C, 85˚C 52LQFP 25MHz C128 die MC9S12C128CFU25 TBD -40˚C, 85˚C 80QFP 25MHz C128 die

MC9S12C128VFA25 TBD -40˚C,105˚C 48LQFP 25MHz C128 die

MC9S12C128VPB25 TBD -40˚C,105˚C 52LQFP 25MHz C128 die

MC9S12C128VFU25 TBD -40˚C, 105˚C 80QFP 25MHz C128 die MC9S12C128MFA25 TBD -40˚C,125˚C 48LQFP 25MHz C128 die MC9S12C128MPB25 TBD -40˚C,125˚C 52LQFP 25MHz C128 die MC9S12C128MFU25 TBD -40˚C, 125˚C 80QFP 25MHz C128 die MC9S12C96PCFA16 0L09S -40˚C, 85˚C 48LQFP 16MHz Preliminary C96 using C128 die MC9S12C96PCPB16 0L09S -40˚C, 85˚C 52LQFP 16MHz Preliminary C96 using C128 die MC9S12C96PCFU16 0L09S -40˚C, 85˚C 80QFP 16MHz Preliminary C96 using C128 die

MC9S12C96CFA16 TBD -40˚C, 85˚C 48LQFP 16MHz Final C96 using C96 die MC9S12C96CPB16 TBD -40˚C, 85˚C 52LQFP 16MHz Final C96 using C96 die MC9S12C96CFU16 TBD -40˚C, 85˚C 80QFP 16MHz Final C96 using C96 die

MC9S12C96PVFA16 0L09S -40˚C, 105˚C 48LQFP 16MHz Preliminary C96 using C128 die MC9S12C96PVPB16 0L09S -40˚C, 105˚C 52LQFP 16MHz Preliminary C96 using C128 die MC9S12C96PVFU16 0L09S -40˚C, 105˚C 80QFP 16MHz Preliminary C96 using C128 die

MC9S12C96VFA16 TBD -40˚C,105˚C 48LQFP 16MHz Final C96 using C96 die MC9S12C96VPB16 TBD -40˚C,105˚C 52LQFP 16MHz Final C96 using C96die MC9S12C96VFU16 TBD -40˚C, 105˚C 80QFP 16MHz Final C96 using C96 die

MC9S12C96PMFA16 0L09S -40˚C, 125˚C 48LQFP 16MHz Preliminary C96 using C128 die MC9S12C96PMPB16 0L09S -40˚C, 125˚C 52LQFP 16MHz Preliminary C96 using C128 die MC9S12C96PMFU16 0L09S -40˚C, 125˚C 80QFP 16MHz Preliminary C96 using C128 die

MC9S12C96MFA16 TBD -40˚C,125˚C 48LQFP 16MHz Final C96 using C96 die MC9S12C96MPB16 TBD -40˚C,125˚C 52LQFP 16MHz Final C96 using C96 die MC9S12C96MFU16 TBD -40˚C, 125˚C 80QFP 16MHz Final C96 using C96 die

MC9S12C96PCFA25 0L09S -40˚C, 85˚C 48LQFP 25MHz Preliminary C96 using C128 die MC9S12C96PCPB25 0L09S -40˚C, 85˚C 52LQFP 25MHz Preliminary C96 using C128 die MC9S12C96PCFU25 0L09S -40˚C, 85˚C 80QFP 25MHz Preliminary C96 using C128 die

MC9S12C96CFA25 TBD -40˚C, 85˚C 48LQFP 25MHz Final C96 using C96 die MC9S12C96CPB25 TBD -40˚C, 85˚C 52LQFP 25MHz Final C96 using C96 die

MC9S12C96CFU25 TBD -40˚C, 85˚C 80QFP 25MHz Final C96 using C96 die MC9S12C96PVFA25 0L09S -40˚C, 105˚C 48LQFP 25MHz Preliminary C96 using C128 die MC9S12C96PVPB25 0L09S -40˚C, 105˚C 52LQFP 25MHz Preliminary C96 using C128 die MC9S12C96PVFU25 0L09S -40˚C, 105˚C 80QFP 25MHz Preliminary C96 using C128 die

Mask

set

Temp. Package Speed Description

Device User Guide — 9S12C128DGV1/D V01.05

Part Number

MC9S12C96VFA25 TBD -40˚C,105˚C 48LQFP 25MHz Final C96 using C96 die MC9S12C96VPB25 TBD -40˚C,105˚C 52LQFP 25MHz Final C96 using C96 die MC9S12C96VFU25 TBD -40˚C, 105˚C 80QFP 25MHz Final C96 using C96 die

MC9S12C96PMFA25 0L09S -40˚C, 125˚C 48LQFP 25MHz Preliminary C96 using C128 die MC9S12C96PMPB25 0L09S -40˚C, 125˚C 52LQFP 25MHz Preliminary C96 using C128 die MC9S12C96PMFU25 0L09S -40˚C, 125˚C 80QFP 25MHz Preliminary C96 using C128 die

MC9S12C96MFA25 TBD -40˚C,125˚C 48LQFP 25MHz Final C96 using C96 die MC9S12C96MPB25 TBD -40˚C,125˚C 52LQFP 25MHz Final C96 using C96 die MC9S12C96MFU25 TBD -40˚C, 125˚C 80QFP 25MHz Final C96 using C96 die

MC9S12C64PCFA16 0L09S -40˚C, 85˚C 48LQFP 16MHz Preliminary C64 using C128 die MC9S12C64PCPB16 0L09S -40˚C, 85˚C 52LQFP 16MHz Preliminary C64 using C128 die MC9S12C64PCFU16 0L09S -40˚C, 85˚C 80QFP 16MHz Preliminary C64 using C128 die

MC9S12C64CFA16 TBD -40˚C, 85˚C 48LQFP 16MHz Final C64 using C64 die MC9S12C64CPB16 TBD -40˚C, 85˚C 52LQFP 16MHz Final C64 using C64 die

MC9S12C64CFU16 TBD -40˚C, 85˚C 80QFP 16MHz Final C64 using C64 die MC9S12C64PVFA16 0L09S -40˚C, 105˚C 48LQFP 16MHz Preliminary C64 using C128 die MC9S12C64PVPB16 0L09S -40˚C, 105˚C 52LQFP 16MHz Preliminary C64 using C128 die MC9S12C64PVFU16 0L09S -40˚C, 105˚C 80QFP 16MHz Preliminary C64 using C128 die

MC9S12C64VFA16 TBD -40˚C,105˚C 48LQFP 16MHz Final C64 using C64 die MC9S12C64VPB16 TBD -40˚C,105˚C 52LQFP 16MHz Final C64 using C64 die MC9S12C64VFU16 TBD -40˚C, 105˚C 80QFP 16MHz Final C64 using C64 die

MC9S12C64PMFA16 0L09S -40˚C, 125˚C 48LQFP 16MHz Preliminary C64 using C128 die MC9S12C64PMPB16 0L09S -40˚C, 125˚C 52LQFP 16MHz Preliminary C64 using C128 die MC9S12C64PMFU16 0L09S -40˚C, 125˚C 80QFP 16MHz Preliminary C64 using C128 die

MC9S12C64MFA16 TBD -40˚C,125˚C 48LQFP 16MHz Final C64 using C64 die MC9S12C64MPB16 TBD -40˚C,125˚C 52LQFP 16MHz Final C64 using C64 die MC9S12C64MFU16 TBD -40˚C, 125˚C 80QFP 16MHz Final C64 using C64 die

MC9S12C64PCFA25 0L09S -40˚C, 85˚C 48LQFP 25MHz Preliminary C64 using C128 die MC9S12C64PCPB25 0L09S -40˚C, 85˚C 52LQFP 25MHz Preliminary C64 using C128 die MC9S12C64PCFU25 0L09S -40˚C, 85˚C 80QFP 25MHz PreliminaryC64 using C128 die

MC9S12C64CFA25 TBD -40˚C, 85˚C 48LQFP 25MHz Final C64 using C64 die MC9S12C64CPB25 TBD -40˚C, 85˚C 52LQFP 25MHz Final C64 using C64 die

MC9S12C64CFU25 TBD -40˚C, 85˚C 80QFP 25MHz Final C64 using C64 die MC9S12C64PVFA25 0L09S -40˚C, 105˚C 48LQFP 25MHz Preliminary C64 using C128 die MC9S12C64PVPB25 0L09S -40˚C, 105˚C 52LQFP 25MHz Preliminary C64 using C128 die MC9S12C64PVFU25 0L09S -40˚C, 105˚C 80QFP 25MHz Preliminary C64 using C128 die

MC9S12C64VFA25 TBD -40˚C,105˚C 48LQFP 25MHz Final C64 using C64 die MC9S12C64VPB25 TBD -40˚C,105˚C 52LQFP 25MHz Final C64 using C64 die MC9S12C64VFU25 TBD -40˚C, 105˚C 80QFP 25MHz Final C64 using C64 die

MC9S12C64PMFA25 0L09S -40˚C, 125˚C 48LQFP 25MHz Preliminary C64 using C128 die MC9S12C64PMPB25 0L09S -40˚C, 125˚C 52LQFP 25MHz Preliminary C64 using C128 die MC9S12C64PMFU25 0L09S -40˚C, 125˚C 80QFP 25MHz Preliminary C64 using C128 die

MC9S12C64MFA25 TBD -40˚C,125˚C 48LQFP 25MHz Final C64 using C64 die MC9S12C64MPB25 TBD -40˚C,125˚C 52LQFP 25MHz Final C64 using C64 die

Mask

set

Temp. Package Speed Description

Device User Guide — 9S12C128DGV1/D V01.05

Part Number

MC9S12C64MFU25 TBD -40˚C, 125˚C 80QFP 25MHz Final C64 using C64 die

MC9S12C32CFA16 1L45J -40˚C, 85˚C 48LQFP 16MHz C32 die MC9S12C32CPB16 1L45J -40˚C, 85˚C 52LQFP 16MHz C32 die MC9S12C32CFU16 1L45J -40˚C, 85˚C 80QFP 16MHz C32 die

MC9S12C32VFA16 1L45J -40˚C,105˚C 48LQFP 16MHz C32 die MC9S12C32VPB16 1L45J -40˚C,105˚C 52LQFP 16MHz C32 die MC9S12C32VFU16 1L45J -40˚C, 105˚C 80QFP 16MHz C32 die

MC9S12C32MFA16 1L45J -40˚C,125˚C 48LQFP 16MHz C32 die MC9S12C32MPB16 1L45J -40˚C,125˚C 52LQFP 16MHz C32 die MC9S12C32MFU16 1L45J -40˚C, 125˚C 80QFP 16MHz C32 die

MC9S12C32CFA25 1L45J -40˚C, 85˚C 48LQFP 25MHz C32 die MC9S12C32CPB25 1L45J -40˚C, 85˚C 52LQFP 25MHz C32 die MC9S12C32CFU25 1L45J -40˚C, 85˚C 80QFP 25MHz C32 die

MC9S12C32VFA25 1L45J -40˚C,105˚C 48LQFP 25MHz C32 die MC9S12C32VPB25 1L45J -40˚C,105˚C 52LQFP 25MHz C32 die MC9S12C32VFU25 1L45J -40˚C, 105˚C 80QFP 25MHz C32 die

MC9S12C32MFA25 1L45J -40˚C,125˚C 48LQFP 25MHz C32 die MC9S12C32MPB25 1L45J -40˚C,125˚C 52LQFP 25MHz C32 die MC9S12C32MFU25 1L45J -40˚C, 125˚C 80QFP 25MHz C32 die

Mask

set

Temp. Package Speed Description

Table 0-4 MC9S12GC-Family Part Number Coding

Part Number

MC9S12GC128PCFA25 0L09S -40˚C, 85˚C 48LQFP 25MHz Preliminary GC128 using C128 die MC9S12GC128PCPB25 0L09S -40˚C, 85˚C 52LQFP 25MHz Preliminary GC128 using C128 die MC9S12GC128PCFU25 0L09S -40˚C, 85˚C 80QFP 25MHz Preliminary GC128 using C128 die

MC9S12GC128CFA25 TBD -40˚C, 85˚C 48LQFP 25MHz Final GC128 using GC128 die MC9S12GC128CPB25 TBD -40˚C, 85˚C 52LQFP 25MHz Final GC128 using GC128 die

MC9S12GC128CFU25 TBD -40˚C, 85˚C 80QFP 25MHz Final GC128 using GC128 die MC9S12GC128PVFA25 0L09S -40˚C, 105˚C 48LQFP 25MHz Preliminary GC128 using C128 die MC9S12GC128PVPB25 0L09S -40˚C, 105˚C 52LQFP 25MHz Preliminary GC128 using C128 die MC9S12GC128PVFU25 0L09S -40˚C, 105˚C 80QFP 25MHz Preliminary GC128 using C128 die

MC9S12GC128VFA25 TBD -40˚C, 105˚C 48LQFP 25MHz Final GC128 using GC128 die

MC9S12GC128VPB25 TBD -40˚C, 105˚C 52LQFP 25MHz Final GC128 using GC128 die

MC9S12GC128VFU25 TBD -40˚C, 105˚C 80QFP 25MHz Final GC128 using GC128 die

MC9S12GC128PMFA25 0L09S -40˚C, 125˚C 48LQFP 25MHz Preliminary GC128 using C128 die MC9S12GC128PMPB25 0L09S -40˚C, 125˚C 52LQFP 25MHz Preliminary GC128 using C128 die MC9S12GC128PMFU25 0L09S -40˚C, 125˚C 80QFP 25MHz Preliminary GC128 using C128 die

MC9S12GC128MFA25 TBD -40˚C, 125˚C 48LQFP 25MHz Final GC128 using GC128 die MC9S12GC128MPB25 TBD -40˚C, 125˚C 52LQFP 25MHz Final GC128 using GC128 die MC9S12GC128MFU25 TBD -40˚C, 125˚C 80QFP 25MHz Final GC128 using GC128 die MC9S12GC64PCFA25 0L09S -40˚C, 85˚C 48LQFP 25MHz Preliminary GC64 using C128 die MC9S12GC64PCPB25 0L09S -40˚C, 85˚C 52LQFP 25MHz Preliminary GC64 using C128 die MC9S12GC64PCFU25 0L09S -40˚C, 85˚C 80QFP 25MHz Preliminary GC64 using C128 die

Mask

set

Temp. Package Speed Description

Device User Guide — 9S12C128DGV1/D V01.05

Part Number

MC9S12GC64CFA25 TBD -40˚C, 85˚C 48LQFP 25MHz Final GC64 using GC64 die MC9S12GC64CPB25 TBD -40˚C, 85˚C 52LQFP 25MHz Final GC64 using GC64 die

MC9S12GC64CFU25 TBD -40˚C, 85˚C 80QFP 25MHz Final GC64 using GC64 die MC9S12GC64PVFA25 0L09S -40˚C, 105˚C 48LQFP 25MHz Preliminary GC64 using C128 die MC9S12GC64PVPB25 0L09S -40˚C, 105˚C 52LQFP 25MHz Preliminary GC64 using C128 die MC9S12GC64PVFU25 0L09S -40˚C, 105˚C 80QFP 25MHz Preliminary GC64 using C128 die

MC9S12GC64VFA25 TBD -40˚C, 105˚C 48LQFP 25MHz Final GC64 using GC64 die

MC9S12GC64VPB25 TBD -40˚C, 105˚C 52LQFP 25MHz Final GC64 using GC64 die

MC9S12GC64VFU25 TBD -40˚C, 105˚C 80QFP 25MHz Final GC64 using GC64 die

MC9S12GC64PMFA25 0L09S -40˚C, 125˚C 48LQFP 25MHz Preliminary GC64 using C128 die MC9S12GC64PMPB25 0L09S -40˚C, 125˚C 52LQFP 25MHz Preliminary GC64 using C128 die MC9S12GC64PMFU25 0L09S -40˚C, 125˚C 80QFP 25MHz Preliminary GC64 using C128 die

MC9S12GC64MFA25 TBD -40˚C, 125˚C 48LQFP 25MHz Final GC64 using GC64 die MC9S12GC64MPB25 TBD -40˚C, 125˚C 52LQFP 25MHz Final GC64 using GC64 die MC9S12GC64MFU25 TBD -40˚C, 125˚C 80QFP 25MHz Final GC64 using GC64 die

MC9S12GC32PCFA25 1L45J -40˚C, 85˚C 48LQFP 25MHz Preliminary GC32 using C32 die

MC9S12GC32PCPB25 1L45J -40˚C, 85˚C 52LQFP 25MHz Preliminary GC32 using C32 die MC9S12GC32PCFU25 1L45J -40˚C, 85˚C 80QFP 25MHz Preliminary GC32 using C32 die

MC9S12GC32CFA25 TBD -40˚C, 85˚C 48LQFP 25MHz Final GC32 using GC32 die

MC9S12GC32CPB25 TBD -40˚C, 85˚C 52LQFP 25MHz Final GC32 using GC32 die

MC9S12GC32CFU25 TBD -40˚C, 85˚C 80QFP 25MHz Final GC32 using GC32 die MC9S12GC32PVFA25 1L45J -40˚C,105˚C 48LQFP 25MHz Preliminary GC32 using C32 die MC9S12GC32PVPB25 1L45J -40˚C,105˚C 52LQFP 25MHz Preliminary GC32 using C32 die MC9S12GC32PVFU25 1L45J -40˚C, 105˚C 80QFP 25MHz Preliminary GC32 using C32 die

MC9S12GC32VFA25 TBD -40˚C,105˚C 48LQFP 25MHz Final GC32 using GC32 die MC9S12GC32VPB25 TBD -40˚C,105˚C 52LQFP 25MHz Final GC32 using GC32 die

MC9S12GC32VFU25 TBD -40˚C, 105˚C 80QFP 25MHz Final GC32 using GC32 die MC9S12GC32PMFA25 1L45J -40˚C,125˚C 48LQFP 25MHz Preliminary GC32 using C32 die MC9S12GC32PMPB25 1L45J -40˚C,125˚C 52LQFP 25MHz Preliminary GC32 using C32 die MC9S12GC32PMFU25 1L45J -40˚C, 125˚C 80QFP 25MHz Preliminary GC32 using C32 die

MC9S12GC32MFA25 TBD -40˚C,125˚C 48LQFP 25MHz Final GC32 using GC32 die MC9S12GC32MPB25 TBD -40˚C,125˚C 52LQFP 25MHz Final GC32 using GC32 die MC9S12GC32MFU25 TBD -40˚C, 125˚C 80QFP 25MHz Final GC32 using GC32 die

MC9S12GC16PCFA25 1L45J -40˚C, 85˚C 48LQFP 25MHz Preliminary GC16 using C32 die MC9S12GC16PCPB25 1L45J -40˚C, 85˚C 52LQFP 25MHz Preliminary GC16 using C32 die MC9S12GC16PCFU25 1L45J -40˚C, 85˚C 80QFP 25MHz Preliminary GC16 using C32 die

MC9S12GC16CFA25 TBD -40˚C, 85˚C 48LQFP 25MHz Final GC16 using GC16 die MC9S12GC16CPB25 TBD -40˚C, 85˚C 52LQFP 25MHz Final GC16 using GC16 die MC9S12GC16CFU25 TBD -40˚C, 85˚C 80QFP 25MHz Final GC16 using GC16 die

MC9S12GC16PVFA25 1L45J -40˚C,105˚C 48LQFP 25MHz Preliminary GC16 using C32 die MC9S12GC16PVPB25 1L45J -40˚C,105˚C 52LQFP 25MHz Preliminary GC16 using C32 die MC9S12GC16PVFU25 1L45J -40˚C, 105˚C 80QFP 25MHz Preliminary GC16 using C32 die

MC9S12GC16VFA25 TBD -40˚C,105˚C 48LQFP 25MHz Final GC16 using GC16 die

MC9S12GC16VPB25 TBD -40˚C,105˚C 52LQFP 25MHz Final GC16 using GC16 die

Mask

set

Temp. Package Speed Description

Device User Guide — 9S12C128DGV1/D V01.05

Part Number

MC9S12GC16VFU25 TBD -40˚C, 105˚C 80QFP 25MHz Final GC16 using GC16 die

MC9S12GC16PMFA25 1L45J -40˚C,125˚C 48LQFP 25MHz Preliminary GC16 using C32 die MC9S12GC16PMPB25 1L45J -40˚C,125˚C 52LQFP 25MHz Preliminary GC16 using C32 die MC9S12GC16PMFU25 1L45J -40˚C, 125˚C 80QFP 25MHz Preliminary GC16 using C32 die

MC9S12GC16MFA25 TBD -40˚C,125˚C 48LQFP 25MHz Final GC16 using GC16 die MC9S12GC16MPB25 TBD -40˚C,125˚C 52LQFP 25MHz Final GC16 using GC16 die MC9S12GC16MFU25 TBD -40˚C, 125˚C 80QFP 25MHz Final GC16 using GC16 die

Mask

set

Temp. Package Speed Description

Table 0-5 Document References

User Guide

HCS12 Background Debug (BDM) Block Guide V04 S12BDMV4/D

HCS12 Module Mapping Control (MMC) Block Guide V04 S12MMCV4/D

HCS12 Multiplexed External Bus Interface (MEBI) Block Guide V03 S12MEBIV3/D

Analog To Digital Converter: 10 Bit 8 Channel (ATD_10B8C) Block Guide V02 S12ATD10B8CV2/D

Clock and Reset Generator (CRG) Block Guide V04 S12CRGV4/D

Serial Communications Interface (SCI) Block Guide V02 S12SCIV2/D

Serial Peripheral Interface (SPI) Block Guide V03 S12SPIV3/D

Motorola Scalable CAN (MSCAN) Block Guide

Pulse Width Modulator: 8 bit, 6 channel (PWM_8B6C) Block Guide V01 S12PWM8B6V1/D

Timer: 16 bit, 8 channel (TIM_16B8C) Block Guide V01 S12TIM16B8CV1/D

Port Integration Module (PIM_9C32) Block Guide V01 S12C32PIMV1/D

32Kbyte Flash EEPROM (FTS32K) Block Guide V01 S12FTS32KV1/D 64Kbyte Flash EEPROM (FTS64K) Block Guide V01 S12FTS64KV1/D

128Kbyte Flash EEPROM (FTS128K1) Block Guide V01 S12FTS128K1V1/D

NOTES:

1. For the GC16 refer to the 16K flash, for the C32 and GC32 refer to the 32K flash, for the C64 and GC64 the 64K flash, for the C96 the 96K flash and C128 the 128K flash document.

2. Not available on the GC-Family members

CPU12 Reference Manual V02 S12CPUV2/D

HCS12 Debug (DBG) Block Guide V01 S12DBGV1/D

HCS12 Interrupt (INT) Block Guide V01 S12INTV1/D

Voltage Regulator (VREG) Block Guide V02 S12VREG3V3V2/D

Oscillator (OSC) Block Guide V02 S12OSCV2/D

Version Document Order Number

V02 S12MSCANV2/D

Terminology

New or invented terms, symbols, and notations

Acronyms and Abbreviations

Device User Guide — 9S12C128DGV1/D V01.05

Section 1 Introduction

1.1 Overview

The MC9S12C-Family and the MC9S12GC-Family is a 48/52/80 pin Flash-based Industrial/Automotive network control MCU family. Members of the MC9S12C-Family and the MC9S12GC-Family deliver the power and flexibility of our 16 Bit core (CPU12) family to a whole new range of cost and space sensitive, general purpose Industrial and Automotive network applications. All MC9S12C-Family and MC9S12GC-Family members are comprised of standard on-chip peripherals including a 16-bit central processing unit (CPU12), up to 128K bytes of Flash EEPROM, up to 4K bytes of RAM, an asynchronous serial communications interface (SCI), a serial peripheral interface (SPI), an 8-channel 16-bit timer module (TIM), a 6-channel 8-bit Pulse Width Modulator (PWM), an 8-channel, 10-bit analog-to-digital converter (ADC). The MC9S12C-Family members also feature a CAN 2.0 A, B software compatible module (MSCAN12). The MC9S12C-Family as well as the MC9S12GC-Family has full 16-bit data paths throughout. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. In addition to the I/O ports available in each module, up to 10 dedicated I/O port bits are available with Wake-Up capability from STOP or WAIT mode. The MC9S12C-Family and the MC9S12GC-Family devices are available in 48, 52 and 80 pin QFP packages, with the 80 Pin version pin compatible to the HCS12 A, B and D- Family derivatives.

1.2 Features

• 16-bit HCS12 CORE – HCS12 CPU

i. Upward compatible with M68HC11 instruction set ii. Interrupt stacking and programmer’s model identical to M68HC11 iii.Instruction queue

iv.Enhanced indexed addressing – MMC (memory map and interface) – INT (interrupt control) – BDM (background debug mode) – DBG12 (enhanced debug12 module, including breakpoints and change-of-flow trace buffer) – MEBI: Multiplexed Expansion Bus Interface (available only in 80 pin package version)

• Wake-up interrupt inputs – Up to 12-port bits available for wake up interrupt function with digital filtering

• Memory options – 16K or 32KByte Flash EEPROM (erasable in 512-byte sectors)

64K, 96K or 128KByte Flash EEPROM (erasable in 1024-byte sectors)

Device User Guide — 9S12C128DGV1/D V01.05

– 1K, 2K or 4K Byte RAM

• Analog-to-Digital Converters – One 8-channel module with 10-bit resolution. – External conversion trigger capability

• Available on MC9S12C-Family: One 1M bit per second, CAN 2.0 A, B software compatible module

– Five receive and three transmit buffers – Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8x8bit – Four separate interrupt channels for Rx, Tx, error and wake-up – Low-pass filter wake-up function – Loop-back for self test operation

• Timer Module (TIM) – 8-Channel Timer – Each Channel Configurable as either Input Capture or Output Compare – Simple PWM Mode – Modulo Reset of Timer Counter – 16-Bit Pulse Accumulator – External Event Counting – Gated Time Accumulation

• 6 PWM channels – Programmable period and duty cycle – 8-bit 6-channel or 16-bit 3-channel – Separate control for each pulse width and duty cycle – Center-aligned or left-aligned outputs – Programmable clock select logic with a wide range of frequencies – Fast emergency shutdown input

• Serial interfaces – One asynchronous serial communications interface (SCI) – One synchronous serial peripheral interface (SPI)

• CRG (Clock Reset Generator Module) – Windowed COP watchdog, – Real time interrupt, – Clock monitor,

Device User Guide — 9S12C128DGV1/D V01.05

– Pierce or low current Colpitts oscillator – Phase-locked loop clock frequency multiplier – Limp home mode in absence of external clock – Low power 0.5 to 16 MHz crystal oscillator reference clock

• Operating frequency – 32MHz equivalent to 16MHz Bus Speed for single chip – 32MHz equivalent to 16MHz Bus Speed in expanded bus modes – Option of 9S12C-Family: 50MHz equivalent to 25MHz Bus Speed – All 9S12GC-Family Members allow a 50MHz operting frequency.

• Internal 2.5V Regulator – Supports an input voltage range from 2.97V to 5.5V – Low power mode capability – Includes low voltage reset (LVR) circuitry – Includes low voltage interrupt (LVI) circuitry

• 48-Pin LQFP, 52-Pin LQFP or 80-Pin QFP package – Up to 58 I/O lines with 5V input and drive capability (80 pin package) – Up to 2 dedicated 5V input only lines (IRQ, XIRQ) – 5V 8 A/D converter inputs and 5V I/O

• Development support – Single-wire background debug™ mode (BDM) – On-chip hardware breakpoints – Enhanced DBG12 debug features

1.3 Modes of Operation

User modes (Expanded modes are only available in the 80 pin package version).

• Normal and Emulation Operating Modes – Normal Single-Chip Mode – Normal Expanded Wide Mode – Normal Expanded Narrow Mode – Emulation Expanded Wide Mode – Emulation Expanded Narrow Mode

• Special Operating Modes

Device User Guide — 9S12C128DGV1/D V01.05

– Special Single-Chip Mode with active Background Debug Mode – Special Test Mode (Motorola use only) – Special Peripheral Mode (Motorola use only)

• Low power modes – Stop Mode – Pseudo Stop Mode – Wait Mode

1.4 Block Diagram

Figure 1-1 MC9S12C-Family Block Diagram

Device User Guide — 9S12C128DGV1/D V01.05

VSSR

VDDR

VDDX

VSSX

VDD2

VSS2

VDD1

VSS1

BKGD

XFC

VDDPLL

VSSPLL

EXTAL

XTAL

RESET

PE0 PE1

PE2 PE3

PE4

PE5 PE6

PE7

TEST/VPP

Voltage Regulator

16K, 32K, 64K, 96K, 128K Byte Flash

1K, 2K, 4K Byte RAM

MODC

Background

Debug12 Module

Clock and Reset

PLL

Generation Module

PTE

DDRE

XIRQ IRQ

R/ LSTRB/TAGLO ECLK MODA/IPIPE0 MODB/IPIPE1 NOACC/XCLKS

HCS12

CPU

COP Watchdog

Clock Monitor

Periodic Interrupt

System

Integration

Module

(SIM)

Multiplexed Address/Data Bus

DDRA DDRB

PTA PTB

PA4

PA3

PA2

PA7

PA6

PA5

PA0

PA1

PB7

PB6

PB5

PB4

PB3

ATD

Timer Module

PWM Module

SCI

MSCAN is not available on the 9S12GC Family Members

MSCAN

PB1

PB0

SPI

PB2

IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7

PW0 PW1 PW2 PW3 PW4 PW5

VDDA

VSSA

VRH

VRL AN0

AN1 AN2 AN3 AN4 AN5 AN6 AN7

MUX

RXD

TXD

RXCAN

TXCAN

MISO

MOSI

SCK

VDDA VSSA VRH

VRL

PAD0 PAD1 PAD2 PAD3 PAD4

PTAD

DDRAD

DDRT

DDRP

Keypad Interrupt

DDRJ

Key Int

DDRS

DDRM

PTT

PTP

PTJ

PTS

PTM

PAD5 PAD6 PAD7

PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7

PP0 PP1 PP2

PP3 PP4

PP5

PP6 PP7

PJ6 PJ7

PS0 PS1

PS2 PS3

PM0 PM1 PM2 PM3 PM4 PM5

ADDR12

ADDR11

ADDR10

DATA11

DATA10

ADDR8

ADDR9

DATA8

DAT A9

Multiplexed Wide Bus

ADDR15

ADDR14

DATA15

DATA14

DATA13

ADDR13

DATA12

Internal Logic 2.5V

VDD1,2 VSS1,2

PLL 2.5V

VDDPLL

VSSPLL

ADDR4

ADDR3

ADDR2

ADDR1

ADDR7

ADDR6

DAT A7

DAT A6

ADDR5

DATA4

DAT A5

ADDR0

DAT A3

DAT A2

DAT A1

DAT A0

I/O Driver 5V

VDDX

VSSX

A/D Converter 5V

VDDA

VSSA

Voltage Regulator 5V & I/O

VDDR VSSR

Signals shown in Bold are not available on the 52 or 48 Pin Package Signals shown in

VRL is bonded internally to VSSA for 52 and 48 Pin packages

Bold Italic

are available in the 52, but not the 48 Pin Package

Device User Guide — 9S12C128DGV1/D V01.05

1.5 Device Memory Map

Table 1-1 shows the device register map of the MC9S12C-Family after reset. The following figures

(Figure 1-2, Figure 1-2, Figure 1-3 and Figure 1-4) illustrate the full device memory map with flash and RAM.

Table 1-1 Device Register Map Overview

Address Module Size

$000 - $017 CORE (Ports A, B, E, Modes, Inits, Test) 24 $018 Reserved 1 $019 Voltage Regulator (VREG) 1 $01A - $01B Device ID register 2 $01C - $01F CORE (MEMSIZ, IRQ, HPRIO) 4 $020 - $02F CORE (DBG) 16

$030 - $033 $034 - $03F Clock and Reset Generator (CRG) 12

$040 - $06F Standard Timer Module16-bit 8-channels (TIM) 48 $070 - $07F Reserved 16 $080 - $09F Analog to Digital Convert (ATD) 32 $0A0 - $0C7 Reserved 40 $0C8 - $0CF Serial Communications Interface (SCI) 8 $0D0 - $0D7 Reserved 8 $0D8 - $0DF Serial Peripheral Interface (SPI) 8 $0E0 - $0FF Pulse Width Modulator 8-bit 6 channels (PWM) 32 $100 - $10F Flash Control Register 16 $110 - $13F Reserved 48

$140 - $17F $180 - $23F Reserved 192

$240 - $27F Port Integration Module (PIM) 64 $280 - $3FF Reserved 384

NOTES:

1. External memory paging is not supported on this device (6.1.1 PPAGE).

2. Not available on MC9S12GC-Family Devices

CORE (PPAGE1)

Motorola Scalable CAN (MSCAN)

Device User Guide — 9S12C128DGV1/D V01.05

$0000 $0400

$3000

$4000

$8000

$C000

$FF00 $FFFF

VECTORS

NORMAL

SINGLE CHIP

EXT

VECTORS

EXPANDED SPECIAL

VECTORS

SINGLE CHIP

$0000

$03FF $0000

$3FFF $3000

$3FFF $4000

$7FFF

$8000

$BFFF

$C000

$FFFF

$FF00

$FFFF

1K Register Space

Mappable to any 2K Boundary

16K Fixed Flash EEPROM

4K Bytes RAM

Mappable to any 4K Boundary

16K Fixed Flash EEPROM

16K Page Window 8 * 16K Flash EEPROM Pages

16K Fixed Flash EEPROM

BDM (If Active)

The ﬁgure shows a useful map, which is not the map out of reset. After reset the map is:

$0000 - $03FF: Register Space $0000 - $0FFF: 4K RAM (only 3K visible $0400 - $0FFF)

Flash Erase Sector Size is 1024 Bytes

PAGE MAP

$3D

$3E

PPAGE

$3F

Figure 1-2 MC9S12C128 and MC9S12GC128 User configurable Memory Map

Device User Guide — 9S12C128DGV1/D V01.05

$0000 $0400

$3000

$4000

$8000

$C000

$FF00 $FFFF

VECTORS

NORMAL

SINGLE CHIP

EXT

VECTORS

EXPANDED SPECIAL

VECTORS

SINGLE CHIP

$0000

$03FF

$0000

$3FFF

$3000

$3FFF

$4000

$7FFF

$8000

$BFFF

$C000

$FFFF $FF00

$FFFF

1K Register Space

Mappable to any 2K Boundary

16K Fixed Flash EEPROM

4K Bytes RAM

Mappable to any 4K Boundary

16K Fixed Flash EEPROM

16K Page Window 6 * 16K Flash EEPROM Pages

16K Fixed Flash EEPROM

BDM (If Active)

The ﬁgure shows a useful map, which is not the map out of reset. After reset the map is:

$0000 - $03FF: Register Space $0000 - $0FFF: 4K RAM (only 3K visible $0400 - $0FFF)

Flash Erase Sector Size is 1024 Bytes

PAGE MAP

$3D

$3E

PPAGE

$3F

Figure 1-3 MC9S12C96 User Configurable Memory Map

Device User Guide — 9S12C128DGV1/D V01.05

$0000 $0400

$3000

$4000

$8000

$C000

$FF00 $FFFF

VECTORS

NORMAL

SINGLE CHIP

EXT

VECTORS

EXPANDED SPECIAL

VECTORS

SINGLE CHIP

$0000

$03FF

$0000

$3FFF

$3000

$3FFF

$4000

$7FFF

$8000

$BFFF

$C000

$FFFF $FF00

$FFFF

1K Register Space

Mappable to any 2K Boundary

16K Fixed Flash EEPROM

4K Bytes RAM

Mappable to any 4K Boundary

16K Fixed Flash EEPROM

16K Page Window 4 * 16K Flash EEPROM Pages

16K Fixed Flash EEPROM

BDM (If Active)

The ﬁgure shows a useful map, which is not the map out of reset. After reset the map is:

$0000 - $03FF: Register Space $0000 - $0FFF: 4K RAM (only 3K visible $0400 - $0FFF)

Flash Erase Sector Size is 1024 Bytes

PAGE MAP

$3D

$3E

PPAGE

$3F

Figure 1-4 MC9S12C64 and MC9S12GC64 User Configurable Memory Map

Device User Guide — 9S12C128DGV1/D V01.05

$0000 $0400

$3800

$4000

$8000

$C000

$FF00 $FFFF

VECTORS

NORMAL

SINGLE CHIP

EXT

VECTORS

EXPANDED SPECIAL

VECTORS

SINGLE CHIP

$0000

$03FF

$3800

$3FFF

$8000

$BFFF

$C000

$FFFF $FF00

$FFFF

1K Register Space

Mappable to any 2K Boundary

2K Bytes RAM

Mappable to any 2K Boundary

16K Page Window 2 * 16K Flash EEPROM Pages

16K Fixed Flash EEPROM

BDM (If Active)

The ﬁgure shows a useful map, which is not the map out of reset. After reset the map is:

$0000 - $03FF: Register Space $0800 - $0FFF: 2K RAM

Flash Erase Sector Size is 512 Bytes

PAGE MAP

$3E

PPAGE

$3F

Figure 1-5 MC9S12C32 and MC9S12GC32 User Configurable Memory Map

Device User Guide — 9S12C128DGV1/D V01.05

$0000 $0400

$3800

$4000

$8000

$C000

$FF00 $FFFF

VECTORS

NORMAL

SINGLE CHIP

EXT

VECTORS

EXPANDED SPECIAL

VECTORS

SINGLE CHIP

$0000

$03FF

$3800

$3FFF

$C000

$FFFF $FF00

$FFFF

1K Register Space

Mappable to any 2K Boundary

2K Bytes RAM

Mappable to any 2K Boundary

16K Fixed Flash EEPROM

BDM (If Active)

The ﬁgure shows a useful map, which is not the map out of reset. After reset the map is:

$0000 - $03FF: Register Space $0800 - $0FFF: 2K RAM

Flash Erase Sector Size is 512 Bytes

PAGE MAP

PPAGE

$3F

Figure 1-6 MC9S12GC16 User Configurable Memory Map

1.6 Detailed Register Map

The detailed register map of the MC9S12C Family is listed in address order below.

Device User Guide — 9S12C128DGV1/D V01.05

$0000 - $000F MEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0000 PORTA

$0001 PORTB

$0002 DDRA

$0003 DDRB

$0004 Reserved

$0005 Reserved

$0006 Reserved

$0007 Reserved

$0008 PORTE

$0009 DDRE

$000A PEAR

$000B MODE

$000C PUCR

$000D RDRIV

$000E EBICTL

$000F Reserved

Read: Write: Read: Write: Read: Write: Read: Write: Read: 00000000 Write: Read: 00000000 Write: Read: 00000000 Write: Read: 00000000 Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: 0000000 Write: Read: 00000000 Write:

Bit 7 654321Bit 0

Bit 7 65432

Bit 7 6543Bit 2

NOACCE

MODC MODB MODA

PUPKE

RDPK

PIPOE NECLK LSTRE RDWE

PUPEE

RDPE

IVIS

Bit 1 Bit 0

EMK EME

PUPBE PUPAE

RDPB RDPA

ESTR

$0010 - $0014 MMC map 1 of 4 (HCS12 Module Mapping Control)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0010 INITRM

$0011 INITRG

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Read: Write: Read: 0 Write:

RAM15 RAM14 RAM13 RAM12 RAM11

REG14 REG13 REG12 REG11

000

RAMHAL

Device User Guide — 9S12C128DGV1/D V01.05

$0010 - $0014 MMC map 1 of 4 (HCS12 Module Mapping Control)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0012 INITEE

$0013 MISC

$0014 Reserved

Read: Write: Read: 0000 Write: Read: 00000000 Write:

EE15 EE14 EE13 EE12 EE11

EXSTR1 EXSTR0 ROMHM ROMON

EEON

$0015 - $0016 INT map 1 of 2 (HCS12 Interrupt)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0015 ITCR

$0016 ITEST

Read: 0 0 0 Write: Read: Write:

INTE INTC INTA INT8 INT6 INT4 INT2 INT0

WRINT ADR3 ADR2 ADR1 ADR0

$0017 - $0017 MMC map 2 of 4 (HCS12 Module Mapping Control)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0017 Reserved

Read: 00000000 Write:

$0018 - $0018 Miscellaneous Peripherals (Device User Guide)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0018 Reserved

Read: 00000000 Write:

$0019 - $0019 VREG3V3 (Voltage Regulator)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0019 VREGCTRL

Read: 00000LVDS Write:

LVIE LVIF

$001A - $001B Miscellaneous Peripherals (Device User Guide)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$001A PARTIDH

$001B PARTIDL

Read: ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 Write: Read: ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 Write:

Device User Guide — 9S12C128DGV1/D V01.05

$001C - $001D MMC map 3 of 4 (HCS12 Module Mapping Control, Device User Guide)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$001C MEMSIZ0

$001D MEMSIZ1

Read: reg_sw0 0 eep_sw1 eep_sw0 0 ram_sw2 ram_sw1 ram_sw0 Write: Read: rom_sw1 rom_sw0 0000pag_sw1 pag_sw0 Write:

$001E - $001E MEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$001E INTCR

Read: Write:

IRQE IRQEN

000000

$001F - $001F INT map 2 of 2 (HCS12 Interrupt)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$001F HPRIO

Read: Write:

PSEL7 PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1

$0020 - $002F DBG (including BKP) map 1 of 1 (HCS12 Debug)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0020

$0021

$0022

$0023

$0024

$0025

$0026

$0027

$0028

$0029

$002A

$002B

DBGC1 read

write

DBGSC read

DBGTBH

DBGTBL read Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

- write

DBGCNT read TBF 0 CNT

- write

DBGCCX read

- write

DBGCCH read

DBGCCL read

- write

write

read

write

DBGC2 read

BKPCT0

write

DBGC3 read

BKPCT1

DBGCAX

BKP0X

DBGCAH read

BKP0H write

write

read

write

DBGEN ARM TRGSEL BEGIN DBGBRK

AF BF CF 0

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

PAGSEL EXTCMP

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 654321Bit 0

BKABEN FULL BDM TAGAB BKCEN TAGC RWCEN RWC

BKAMBH BKAMBL BKBMBH BKBMBL RWAEN RWA RWBEN RWB

PAGSEL EXTCMP

Bit 15 14 13 12 11 10 9 Bit 8

TRG

CAPMOD

Device User Guide — 9S12C128DGV1/D V01.05

$0020 - $002F DBG (including BKP) map 1 of 1 (HCS12 Debug)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$002C

$002D

$002E

$002F

DBGCAL read

BKP0L write

DBGCBX read

BKP1X write

DBGCBH read

BKP1H write

DBGCBL read

BKP1L write

Bit 7 654321Bit 0

PAGSEL EXTCMP

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 654321Bit 0

$0030 - $0031 MMC map 4 of 4 (HCS12 Module Mapping Control)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0030 PPAGE

$0031 Reserved

Write:

PIX5 PIX4 PIX3 PIX2 PIX1 PIX0

Write:

$0032 - $0033 MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Read:

(1)

Write:

Read:

Write:

Bit 7 654321Bit 0

$0032 PORTK

$0033 DDRK

NOTES:

1. Only applicable in special emulation-only bond outs, for emulation of extended memory map.

$0034 - $003F CRG (Clock and Reset Generator)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0034 SYNR

$0035 REFDV

$0036

CTFLG

TEST ONLY

$0037 CRGFLG

$0038 CRGINT

$0039 CLKSEL

$003A PLLCTL

Write:

Write:

SYN5 SYN4 SYN3 SYN2 SYN1 SYN0

REFDV3 REFDV2 REFDV1 REFDV0

Read: TOUT7 TOUT6 TOUT5 TOUT4 TOUT3 TOUT2 TOUT1 TOUT0

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

RTIF PROF

RTIE

PLLSEL PSTP SYSWAI ROAWAI PLLWAI CWAI RTIWAI COPWAI

CME PLLON AUTO ACQ

LOCKIF

LOCKIE

LOCK TRACK

PRE PCE SCME

SCMIF

SCMIE

SCM

Device User Guide — 9S12C128DGV1/D V01.05

$0034 - $003F CRG (Clock and Reset Generator)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$003B RTICTL

$003C COPCTL

$003D

$003E

FORBYP

TEST ONLY

CTCTL

TEST ONLY

$003F ARMCOP

Write:

Read:

Write:

Read:

Write:

WCOP RSBCK

RTIBYP COPBYP

RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0

000

Read: TCTL7 TCTL6 TCTL5 TCTL4 TCLT3 TCTL2 TCTL1 TCTL0

Write:

Write: Bit 7 654321Bit 0

$0040 - $006F TIM (Timer 16 Bit 8 Channels)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0040 TIOS

$0041 CFORC

$0042 OC7M

$0043 OC7D

$0044 TCNT (hi)

$0045 TCNT (lo)

$0046 TSCR1

$0047 TTOV

$0048 TCTL1

$0049 TCTL2

$004A TCTL3

$004B TCTL4

$004C TIE

$004D TSCR2

$004E TFLG1

$004F TFLG2

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0

00000000

FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0

OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0

OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 654321Bit 0

TEN TSWAI TSFRZ TFFCA

TOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0

OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4

OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0

EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A

EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A

C7I C6I C5I C4I C3I C2I C1I C0I

TOI

000

C7F C6F C5F C4F C3F C2F C1F C0F

TOF

0000000

PLLBYP

CR2 CR1 CR0

FCM

0000

TCRE PR2 PR1 PR0

Device User Guide — 9S12C128DGV1/D V01.05

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0050 TC0 (hi)

$0051 TC0 (lo)

$0052 TC1 (hi)

$0053 TC1 (lo)

$0054 TC2 (hi)

$0055 TC2 (lo)

$0056 TC3 (hi)

$0057 TC3 (lo)

$0058 TC4 (hi)

$0059 TC4 (lo)

$005A TC5 (hi)

$005B TC5 (lo)

$005C TC6 (hi)

$005D TC6 (lo)

$005E TC7 (hi)

$005F TC7 (lo)

$0060 PACTL

$0061 PAFLG

$0062 PACNT (hi)

$0063 PACNT (lo)

$0064 Reserved

$0065 Reserved

$0066 Reserved

$0067 Reserved

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Write:

Read:

Write:

Read:

Write:

Write:

Write:

Write:

Write:

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 654321Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 654321Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 654321Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 654321Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 654321Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 654321Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 654321Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 654321Bit 0

PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI

PAOVF PAIF

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 654321Bit 0

Device User Guide — 9S12C128DGV1/D V01.05

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0068 Reserved

$0069 Reserved

$006A Reserved

$006B Reserved

$006C Reserved

$006D Reserved

$006E Reserved

$006F Reserved

Write:

Write:

Write:

Write:

Write:

Write:

Write:

Write:

$0070 - $007F Reserved

$0070

- $007F

Reserved

Write:

$0080 - $009F ATD (Analog to Digital Converter 10 Bit 8 Channel)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0080 ATDCTL0

$0081 ATDCTL1

$0082 ATDCTL2

$0083 ATDCTL3

$0084 ATDCTL4

$0085 ATDCTL5

$0086 ATDSTAT0

$0087 Reserved

$0088 ATDTEST0

$0089 ATDTEST1

$008A Reserved

Write:

Write:

Read:

Write:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Write:

Write:

Write:

Write:

ADPU AFFC AWAI ETRIGLE ETRIGP ETRIG ASCIE

S8C S4C S2C S1C FIFO FRZ1 FRZ0

SRES8 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0

DJM DSGN SCAN MULT

SCF

ETORF FIFOR

0 CC2 CC1 CC0

CC CB CA

ASCIF

Device User Guide — 9S12C128DGV1/D V01.05

$0080 - $009F ATD (Analog to Digital Converter 10 Bit 8 Channel)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$008B ATDSTAT1

$008C Reserved

$008D ATDDIEN

$008E Reserved

$008F PORTAD0

$0090 ATDDR0H

$0091 ATDDR0L

$0092 ATDDR1H

$0093 ATDDR1L

$0094 ATDDR2H

$0095 ATDDR2L

$0096 ATDDR3H

$0097 ATDDR3L

$0098 ATDDR4H

$0099 ATDDR4L

$009A ATDDR5H

$009B ATDDR5L

$009C ATDDR6H

$009D ATDDR6L

$009E ATDDR7H

$009F ATDDR7L

Read: CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0

Write:

Write:

Read:

Write:

Write:

Read: Bit7 654321BIT 0

Write:

Read: Bit15 14 13 12 11 10 9 Bit8

Write:

Read: Bit7 Bit6 000000

Write:

Read: Bit15 14 13 12 11 10 9 Bit8

Write:

Read: Bit7 Bit6 000000

Write:

Read: Bit15 14 13 12 11 10 9 Bit8

Write:

Read: Bit7 Bit6 000000

Write:

Read: Bit15 14 13 12 11 10 9 Bit8

Write:

Read: Bit7 Bit6 000000

Write:

Read: Bit15 14 13 12 11 10 9 Bit8

Write:

Read: Bit7 Bit6 000000

Write:

Read: Bit15 14 13 12 11 10 9 Bit8

Write:

Read: Bit7 Bit6 000000

Write:

Read: Bit15 14 13 12 11 10 9 Bit8

Write:

Read: Bit7 Bit6 000000

Write:

Read: Bit15 14 13 12 11 10 9 Bit8

Write:

Read: Bit7 Bit6 000000

Write:

Bit 7 654321Bit 0

$00A0 - $00C7 Reserved

$00A0

- $00C7

Reserved

Write:

Device User Guide — 9S12C128DGV1/D V01.05

$00C8 - $00CF SCI (Asynchronous Serial Interface)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$00C8 SCIBDH

$00C9 SCIBDL

$00CA SCICR1

$00CB SCICR2

$00CC SCISR1

$00CD SCISR2

$00CE SCIDRH

$00CF SCIDRL

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read: TDRE TC RDRF IDLE OR NF FE PF

Write:

Write:

Read: R8

Write:

Read: R7 R6 R5 R4 R3 R2 R1 R0

Write: T7 T6 T5 T4 T3 T2 T1 T0

000

SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0

LOOPS SCISWAI RSRC M WAKE ILT PE PT

TIE TCIE RIE ILIE TE RE RWU SBK

000000

SBR12 SBR11 SBR10 SBR9 SBR8

BRK13 TXDIR

RAF

$00D0 - $00D7 Reserved

$00D0

- $00D7

Reserved

Write:

$00D8 - $00DF SPI (Serial Peripheral Interface)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$00D8 SPICR1

$00D9 SPICR2

$00DA SPIBR

$00DB SPISR

$00DC Reserved

$00DD SPIDR

$00DE Reserved

$00DF Reserved

Read:

Write:

Write:

Write:

Read: SPIF 0 SPTEF MODF 0000

Write:

Write:

Read:

Write:

Write:

Write:

SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE

MODFEN BIDIROE

SPPR2 SPPR1 SPPR0

Bit7 654321Bit0

SPISWAI SPC0

SPR2 SPR1 SPR0

Device User Guide — 9S12C128DGV1/D V01.05

$00E0 - $00FF PWM (Pulse Width Modulator)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$00E0 PWME

$00E1 PWMPOL

$00E2 PWMCLK

$00E3 PWMPRCLK

$00E4 PWMCAE

$00E5 PWMCTL

$00E6

PWMTST

Test Only

$00E7 PWMPRSC

$00E8 PWMSCLA

$00E9 PWMSCLB

$00EA PWMSCNTA

$00EB PWMSCNTB

$00EC PWMCNT0

$00ED PWMCNT1

$00EE PWMCNT2

$00EF PWMCNT3

$00F0 PWMCNT4

$00F1 PWMCNT5

$00F2 PWMPER0

$00F3 PWMPER1

$00F4 PWMPER2

$00F5 PWMPER3

$00F6 PWMPER4

Write:

Write:

Write:

Write:

PCKB2 PCKB1 PCKB0

Write:

Write:

CON45 CON23 CON01 PSWAI PFRZ

PWME5 PWME4 PWME3 PWME2 PWME1 PWME0

PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0

PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0

PCKA2 PCKA1 PCKA0

CAE5 CAE4 CAE3 CAE2 CAE1 CAE0

Write:

Write:

Read:

Write:

Read:

Write:

Bit 7 6 5 4 3 2 1 Bit 0

Write:

Write:

Read: Bit 7 6 5 4 3 2 1 Bit 0

Write: 00000000

Read: Bit 7 6 5 4 3 2 1 Bit 0

Write: 00000000

Read: Bit 7 6 5 4 3 2 1 Bit 0

Write: 00000000

Read: Bit 7 6 5 4 3 2 1 Bit 0

Write: 00000000

Read: Bit 7 6 5 4 3 2 1 Bit 0

Write: 00000000

Read: Bit 7 6 5 4 3 2 1 Bit 0

Write: 00000000

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Bit 7 6 5 4 3 2 1 Bit 0

Device User Guide — 9S12C128DGV1/D V01.05

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$00F7 PWMPER5

$00F8 PWMDTY0

$00F9 PWMDTY1

$00FA PWMDTY2

$00FB PWMDTY3

$00FC PWMDTY4

$00FD PWMDTY5

$00FE Reserved

$00FF Reserved

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Bit 7 6 5 4 3 2 1 Bit 0

Write:

Write:

$0100 - $010F Flash Control Register

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0100 FCLKDIV

$0101 FSEC

$0102 FTSTMOD

$0103 FCNFG

$0104 FPROT

$0105

FSTAT

$0106 FCMD

$0107

$0108

$0109

$010A

$010B

Reserved for

Factory Test

Reserved for

Factory Test

Reserved for

Factory Test

Reserved for

Factory Test

Reserved for

Factory Test

Read: FDIVLD

Write:

PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0

Read: KEYEN1 KEYEN0 NV5 NV4 NV3 NV2 SEC1 SEC0

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Write:

0 0 0 WRALL

CBEIE CCIE KEYACC

000

FPOPEN NV6 FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0

CBEIF

CCIF

PVIOL ACCERR

CMDB6 CMDB5

000

BKSEL1 BKSEL0

BLANK

CMDB2

CMDB0

Write:

Write:

Write:

Write:

Write:

Device User Guide — 9S12C128DGV1/D V01.05

$0100 - $010F Flash Control Register

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$010C Reserved

$010D Reserved

$010E Reserved

$010F Reserved

Write:

Write:

Write:

Write:

$0110 - $013F Reserved

$0110

- $003F

Reserved

Write:

$0140 - $017F CAN (Motorola Scalable CAN - MSCAN)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0140 CANCTL0

$0141 CANCTL1

$0142 CANBTR0

$0143 CANBTR1

$0144 CANRFLG

$0145 CANRIER

$0146 CANTFLG

$0147 CANTIER

$0148 CANTARQ

$0149 CANTAAK

$014A CANTBSEL

$014B CANIDAC

$014C Reserved

$014D Reserved

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

RXFRM

CANE CLKSRC LOOPB LISTEN

SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0

SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10

WUPIF CSCIF

WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE

00000

RXACT

CSWAI

RSTAT1 RSTAT0 TSTAT1 TSTAT0

Write:

Write:

Read:

00000

Write:

Read: 00000ABTAK2ABTAK1ABTAK0

Write:

Read:

00000

Write:

Write:

IDAM1 IDAM0

Write:

Write:

SYNCH

TIME WUPE SLPRQ INITRQ

WUPM

SLPAK INITAK

OVRIF RXF

TXE2 TXE1 TXE0

TXEIE2 TXEIE1 TXEIE0

ABTRQ2 ABTRQ1 ABTRQ0

TX2 TX1 TX0

0 IDHIT2 IDHIT1 IDHIT0

Device User Guide — 9S12C128DGV1/D V01.05

$0140 - $017F CAN (Motorola Scalable CAN - MSCAN)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$014E CANRXERR

$014F CANTXERR

$0150 -

$0153

$0154 -

$0157

$0158 -

$015B

$015C -

$015F

$0160 -

$016F

$0170 -

$017F

NOTES:

1. Not available on the MC9S12GC-Family members. Those memory locations should not be accessed.

CANIDAR0 -

CANIDAR3

CANIDMR0 -

CANIDMR3

CANIDAR4 -

CANIDAR7

CANIDMR4 -

CANIDMR7

CANRXFG

CANTXFG

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read: FOREGROUND RECEIVE BUFFER see Table 1-2

Write:

Read:

Write:

RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0

TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0

AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0

AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0

AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0

AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0

FOREGROUND TRANSMIT BUFFER see Table 1-2

Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Extended ID Read: ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21

$xxx0

$xxx1

$xxx2

$xxx3

$xxx4$xxxB

$xxxC CANRxDLR

$xxxD Reserved

$xxxE CANxRTSRH

$xxxF CANxRTSRL

$xx10

Standard ID Read: ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3

CANxRIDR0 Write:

Extended ID Read: ID20 ID19 ID18 SRR=1 IDE=1 ID17 ID16 ID15

Standard ID Read: ID2 ID1 ID0 RTR IDE=0

CANxRIDR1 Write:

Extended ID Read: ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7

Standard ID Read:

CANxRIDR2 Write:

Extended ID Read: ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR

Standard ID Read:

CANxRIDR3 Write:

CANxRDSR0 -

CANxRDSR7

Extended ID Read: CANxTIDR0 Write:

Standard ID Read:

Read: DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Write: Read: Write: Read: Write: Read: TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8 Write: Read: TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0 Write:

ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21

Write:

ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3

DLC3 DLC2 DLC1 DLC0

Device User Guide — 9S12C128DGV1/D V01.05

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Extended ID Read:

$xx11

$xx12

$xx13

$xx14$xx1B

$xx1C CANxTDLR

$xx1D CONxTTBPR

$xx1E CANxTTSRH

$xx1F CANxTTSRL

CANxTIDR1 Write:

Standard ID Read:

Extended ID Read: CANxTIDR2 Write:

Standard ID Read:

Extended ID Read: CANxTIDR3 Write:

Standard ID Read:

CANxTDSR0 -

CANxTDSR7

Write:

Write: Read: Write: Read: Write: Read: Write: Read: TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8 Write: Read: TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0 Write:

ID20 ID19 ID18 SRR=1 IDE=1 ID17 ID16 ID15

ID2 ID1 ID0 RTR IDE=0

ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7

ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DLC3 DLC2 DLC1 DLC0

PRIO7 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0

$0180 - $023F Reserved

$0180

- $023F

Reserved

Write:

$0240 - $027F PIM (Port Interface Module)

$0240 PTT

$0241 PTIT

$0242 DDRT

$0243 RDRT

$0244 PERT

$0245 PPST

$0246 Reserved

$0247 MODRR

$0248 PTS

Read:

Write:

PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0

Read: PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

DDRT7 DDRT7 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0

RDRT7 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0

PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0

PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0

Write:

Write:

MODRR4 MODRR3 MODRR2 MODRR1 MODRR0

Write:

PTS3 PTS2 PTS1 PTS0

Device User Guide — 9S12C128DGV1/D V01.05

$0249 PTIS

$024A DDRS

$024B RDRS

$024C PERS

$024D PPSS

$024E WOMS

$024F Reserved

$0250 PTM

$0251 PTIM

$0252 DDRM

$0253 RDRM

$0254 PERM

$0255 PPSM

$0256 WOMM

$0257 Reserved

$0258 PTP

$0259 PTIP

$025A DDRP

$025B RDRP

$025C PERP

$025D PPSP

$025E PIEP

$025F PIFP

$0260 Reserved

Read: 0000PTIS3 PTIS2 PTIS1 PTIS0

Write:

Write:

Write:

Write:

Write:

Write:

DDRS3 DDRS2 DDRS1 DDRS0

RDRS3 RDRS2 RDRS1 RDRS0

PERS3 PERS2 PERS1 PERS0

PPSS3 PPSS2 PPSS1 PPSS0

WOMS3 WOMS2 WOMS1 WOMS0

Write:

Write:

PTM5 PTM4 PTM3 PTM2 PTM1 PTM0

Read: 0 0 PTIM5 PTIM4 PTIM3 PTIM2 PTIM1 PTIM0

Write:

Write:

Write:

Write:

Write:

Write:

DDRM5 DDRM4 DDRM3 DDRM2 DDRM1 DDRM0

RDRM5 RDRM4 RDRM3 RDRM2 RDRM1 RDRM0

PERM5 PERM4 PERM3 PERM2 PERM1 PERM0

PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSM0

WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0

Write:

Read:

Write:

PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0

Read: PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

DDRP7 DDRP7 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0

RDRP7 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0

PERP7 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0

PPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSS0

PIEP7 PIEP6 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0

PIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0

Write:

Device User Guide — 9S12C128DGV1/D V01.05

$0261 Reserved

$0262 Reserved

$0263 Reserved

$0264 Reserved

$0265 Reserved

$0266 Reserved

$0267 Reserved

$0268 PTJ

$0269 PTIJ

$026A DDRJ

$026B RDRJ

$026C PERJ

$026D PPSJ

$026E PIEJ

$026F PIFJ

$0270 PTAD

$0271 PTIAD

$0272 DDRAD

$0273 RDRAD

$0274 PERAD

$0275 PPSAD

$0276-

$027F

Reserved

Write:

Write:

Write:

Write:

Write:

Write:

Write:

Read:

Write:

PTJ7 PTJ6

000000

Read: PTIJ7 PTIJ6 000000

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

Write:

Read:

DDRJ7 DDRJ7

RDRJ7 RDRJ6

PERJ7 PERJ6

PPSJ7 PPSJ6

PIEJ7 PIEJ6

PIFJ7 PIFJ6

PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0

PTIAD7 PTIAD6 PTIAD5 PTIAD4 PTIAD3 PTIAD2 PTIAD1 PTIJ7

000000

Write:

Read:

DDRAD7 DDRAD6 DDRAD5 DDRAD4 DDRAD3 DDRAD2 DDRAD1 DDRAD0

Write:

Read:

RDRAD7 RDRAD6 RDRAD5 RDRAD4 RDRAD3 RDRAD2 RDRAD1 RDRAD0

Write:

Read:

PERAD7 PERAD6 PERAD5 PERAD4 PERAD3 PERAD2 PERAD1 PERAD0

Write:

Read:

PPSAD7 PPSAD6 PPSAD5 PPSAD4 PPSAD3 PPSAD2 PPSAD1 PPSAD0

Write:

Write:

Device User Guide — 9S12C128DGV1/D V01.05

$0280 - $03FF Reserved space

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

$0280

- $2FF

$0300 -

$03FF

Reserved

Unimplemented

Write:

Write:

1.7 Part ID Assignments

The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses $001A and $001B after reset). The read-only value is a unique part ID for each revision of the chip. Table 1-3 shows the assigned part ID numbers.

Table 1-3 Assigned Part ID Numbers

Device Mask Set Number

MC9S12C32 0L45J $3300 MC9S12C32 1L45J $3300 MC9S12C32 2L45J $3302 MC9S12C64 TBD TBD

MC9S12C96 TBD TBD MC9S12C128 0L09S $3100 MC9S12C128 1L09S $3101 MC9S12GC16 TBD TBD MC9S12GC32 TBD TBD MC9S12GC64 TBD TBD

MC9S12GC128 TBD TBD

NOTES:

1. The coding is as follows: Bit 15-12: Major family identifier Bit 11-8: Minor family identifier Bit 7-4: Major mask set revision number including FAB transfers Bit 3-0: Minor - non full - mask set revision

Part ID

The device memory sizes are located in two 8-bit registers MEMSIZ0 and MEMSIZ1 (addresses $001C and$001D after reset). Table 1-4shows the read-only values oftheseregisters. Refer to Module Mapping and Control (MMC) Block Guide for further details.

Device Register name Value

MC9S12GC16

Table 1-4 Memory size registers

MEMSIZ0 $00 MEMSIZ1 $80

Table 1-4 Memory size registers

Device Register name Value

MC9S12C32, MC9S12GC32

MC9S12C64, MC9S12GC64

MC9S12C96

MC9S12C128, MC9S12GC128

Device User Guide — 9S12C128DGV1/D V01.05

MEMSIZ0 $00 MEMSIZ1 $80 MEMSIZ0 $01 MEMSIZ1 $C0 MEMSIZ0 $01 MEMSIZ1 $C0 MEMSIZ0 $01 MEMSIZ1 $C0

Device User Guide — 9S12C128DGV1/D V01.05

Section 2 Signal Description

2.1 Device Pinout

PP4/KWP4/PW4

PP5/KWP5/PW5

PP7/KWP7

VDDX

VSSX

PM0/RXCAN

PM1/TXCAN

PM2/MISO

PM3/SS

PM4/MOSI

PM5/SCK

PJ6/KWJ6

PJ7/KWJ7

PP6/KWP6/ROMCTL

PS3

PS2

PS1/TXD

PS0/RXD

VSSA

VRL

PW3/KWP3/PP3

PW2/KWP2/PP2 PW1/KWP1/PP1 PW0/KWP0/PP0

PW0/IOC0/PT0 PW1/IOC1/PT1 PW2/IOC2/PT2 PW3/IOC3/PT3

VDD1 VSS1

PW4/IOC4/PT4

IOC5/PT5 IOC6/PT6 IOC7/PT7

TAGHI/BKGD

MODC/

ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3

ADDR4/DATA4/PB4

80797877767574737271706968676665646362

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

21222324252627282930313233343536373839

ADDR5/DATA5/PB5

ADDR6/DATA6/PB6

ADDR7/DATA7/PB7

MC9S12C-Family

MC9S12GC-Family

VSSR

VDDR

ECLK/PE4

MODA/IPIPE0/PE5

MODB/IPIPE1/PE6

XCLKS/NOACC/PE7

RESET

VDDPLL

XFC

VSSPLL

EXTAL

XTAL

TEST/VPP

IRQ/PE1

R/W/PE2

LSTRB/TAGLO/PE3

VRH

VDDA

PAD07/AN07

PAD06/AN06

PAD05/AN05

PAD04/AN04

PAD03/AN03

PAD02/AN02

PAD01/AN01

PAD00/AN00

VSS2

VDD2

PA7/ADDR15/DATA15

PA6/ADDR14/DATA14

PA5/ADDR13/DATA13

PA4/ADDR12/DATA12

PA3/ADDR11/DATA11

PA2/ADDR10/DATA10

PA1/ADDR9/DATA9

PA0/ADDR8/DATA8

XIRQ/PE0

Signals shown in Bold are not available on the 52 or 48 Pin Package Signals shown in

Figure 2-1 Pin Assignments in 80 QFP for MC9S12C-Family

Bold Italic

are available in the 52, but not the 48 Pin Package

PW3/KWP3/PP3

PW0/IOC0/PT0 PW1/IOC1/PT1 PW2/IOC2/PT2 PW3/IOC3/PT3

VDD1

VSS1

PW4/IOC4/PT4

IOC5/PT5 IOC6/PT6 IOC7/PT7

MODC/BKGD

PB4

PP4/KWP4/PW4

PP5/KWP5/PW5

1 2 3 4 5 6 7 8 9 10 11 12 13

VDDX

VSSX

PM0/RXCAN

MC9S12C-Family

MC9S12GC-Family

PM1/TXCAN

PM2/MISO

PM3/SS

Device User Guide — 9S12C128DGV1/D V01.05

PM4/MOSI

PM5/SCK

PS1/TXD

PS0/RXD

VSSA

39 38 37 36 35 34 33 32 31 30 29 28 27

VRH VDDA PAD07/AN07

PAD06/AN06 PAD05/AN05

PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00

PA2 PA1

PA0

VSSR

VDDR

ECLK/PE4

XCLKS/PE7

* Signals shown in

RESET

VDDPLL

Bold italic

XFC

VSSPLL

are not available on the 48 Pin Package

EXTAL

XTAL

TEST/VPP

IRQ/PE1

XIRQ/PE0

Figure 2-2 Pin assignments in 52 LQFP for MC9S12C-Family

Device User Guide — 9S12C128DGV1/D V01.05

PP5/KWP5/PW5

VDDX

VSSX

PM0/RXCAN

PW0/IOC0/PT0 PW1/IOC1/PT1 PW2/IOC2/PT2 PW3/IOC3/PT3

VDD1

VSS1

PW4/IOC4/PT4

IOC5/PT5 IOC6/PT6 IOC7/PT7

MODC/BKGD

PB4

1 2 3 4 5 6 7 8 9 10 11 12

MC9S12GC-Family

PM1/TXCAN

PM2/MISO

PM3/SS

PM4/MOSI

MC9S12C-Family

PM5/SCK

PS1/TXD

PS0/RXD

VSSA

36 35 34 33 32 31 30 29 28 27 26 25

VRH VDDA PAD07/AN07

PAD06/AN06 PAD05/AN05

PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 PA0 XIRQ/PE0

VSSR

ECLK/PE4

XCLKS/PE7

VDDR

RESET

XFC

VDDPLL

VSSPLL

EXTAL

XTAL

TEST/VPP

IRQ/PE1

Figure 2-3 Pin Assignments in 48 LQFP for MC9S12C-Family

Device User Guide — 9S12C128DGV1/D V01.05

2.2 Signal Properties Summary

Table 2-1 Signal Properties

Internal Pull

Pin Name

Function 1

EXTAL — — VDDPLL NA NA

XTAL — — VDDPLL NA NA

RESET — — VDDX None None External reset pin

XFC — — VDDPLL NA NA PLL loop ﬁlter pin

TEST VPP — VSSX NA NA Test pin only

BKGD MODC

PE7 NOACC

PE6 IPIPE1 MODB VDDX

PE5 IPIPE0 MODA VDDX

PE4 ECLK — VDDX PUCR

PE3

PE2 R/

PE1 IRQ — VDDX PUCR Up Port E input, external interrupt pin PE0

PA[7:3]

PA[2:1]

PA[0]

PB[7:5]

PB[4]

PB[3:0]

PAD[7:0] AN[7:0] — VDDA

PP[7] KWP[7] — VDDX

PP[6] KWP[6] ROMCTL VDDX

PP[5] KWP[5] PW5 VDDX

Pin Name

Function 2

LSTRB TAGLO VDDX PUCR

W — VDDX PUCR

XIRQ — VDDX PUCR Up Port E input, non-maskable interrupt pin

ADDR[15:1/

DATA[15:1]

ADDR[10:9/

DATA[10:9]

ADDR[8]/

DATA[8]

ADDR[7:5]/

DATA[7:5]

ADDR[4]/

DATA[4]

ADDR[3:0]/

DATA[3:0]

Pin Name

Function 3

TAGHI VDDX Up Up Background debug, mode pin, tag signal high

XCLKS VDDX PUCR Up Port E I/O pin, access, clock select

— VDDX PUCR Disabled Port A I/O pin & multiplexed address/data

Power

Domain

— VDDX PUCR Disabled Port A I/O pin & multiplexed address/data

— VDDX PUCR Disabled Port B I/O pin & multiplexed address/data

PP[4:3] KWP[4:3] PW[4:3] VDDX

Resistor

CTRL

While

pin is low: Down

While RESET

pin is low: Down

PERAD/P

PSAD

PERP/

PPSP

PERP/

PPSP

PERP/

PPSP

PERP/

PPSP

Reset

State

RESET

Mode

Dep

Mode

Dep

Mode

Dep

Disabled Port AD I/O pins and ATD inputs

Disabled Port P I/O Pins and keypad wake-up

Disabled

Disabled Port P I/O Pin, keypad wake-up, PW5 output

Disabled Port P I/O Pin, keypad wake-up, PWM output

Description

Oscillator pins

Port E I/O pin and pipe status

Port E I/O pin, bus clock output

Port E I/O pin, low strobe, tag signal low

(1)

Port E I/O pin, R/W in expanded modes

(1)

Port P I/O Pins, keypad wake-up and ROMON enable.

Device User Guide — 9S12C128DGV1/D V01.05

Internal Pull

Pin Name

Function 1

PP[2:0] KWP[2:0] PW[2:0] VDDX

PJ[7:6] KWJ[7:6] — VDDX

PM5 SCK — VDDX

PM4

PM3

PM2

PM1 TXCAN — VDDX

PM0 RXCAN — VDDX

PS[3:2] — — VDDX

PS1 TXD — VDDX

PS0 RXD — VDDX

PT[7:5] IOC[7:5] — VDDX

PT[4:0] IOC[4:0] PW[4:0] VDDX

NOTES:

1. The PortE output buffer enable signal control at reset is determined by the PEAR register and is mode dependent. E.g. in special test mode RDWE=LSTRE=1 which enables the PE[3:2] output buffers and disables the pull-ups. Refer to S12_MEBI user guide for PEAR register details.

2. CAN functionality is not available on the MC9S12GC-Family members

Pin Name

Function 2

MOSI

SS — VDDX

MISO

Pin Name

Function 3

— VDDX

Power

Domain

Resistor

CTRL

PERP/

PPSP

PERJ/

PPSJ

PERM/

PPSM

PERM/

PPSM

PERM/

PPSM

PERM/

PPSM

PERM/

PPSM

PERM/

PPSM

PERS/

PPSS

PERS/

PPSS

PERS/

PPSS

PERT/

PPST

PERT/

PPST

Reset

State

Disabled Port P I/O Pins, keypad wake-up, PWM outputs

Disabled Port J I/O Pins and keypad wake-up

Up Port M I/O Pin and SPI SCK signal

Up Port M I/O Pin and SPI

Up Port M I/O Pin and SPI SS signal

Up Port M I/O Pin and SPI

Up Port S I/O Pins

Up Port S I/O Pin and SCI transmit signal

Up Port S I/O Pin and SCI receive signal

Disabled Port T I/O Pins shared with timer (TIM)

Disabled Port T I/O Pins shared with timer and PWM

Port M I/O Pin and CAN transmit signal

Port M I/O Pin and CAN receive signal

Description

MOSI

signal

MISO

signal

2.2.1 Pin Initialization for 48 & 52 Pin LQFP bond-out versions

Not Bonded Pins If the port pins are not bonded out in the chosen package the user should initialize the registers to be inputs with enabled pull resistance to avoid excess current consumption. This applies to the following pins:

(48LQFP): Port A[7:1], Port B[7:5], Port B[3:0], PortE[6,5,3,2], Port P[7:6], PortP[4:0], Port J[7:6], PortS[3:2]

(52LQFP): Port A[7:3], Port B[7:5], Port B[3:0], PortE[6,5,3,2], Port P[7:6], PortP[2:0], Port J[7:6], PortS[3:2]

Device User Guide — 9S12C128DGV1/D V01.05

2.3 Detailed Signal Descriptions

2.3.1 EXTAL, XTAL — Oscillator Pins

EXTAL and XTAL arethe crystal driver and external clock pins.On reset all the device clocks arederived from the EXTAL input frequency. XTAL is the crystal output.

2.3.2 RESET — External Reset Pin

RESET is an active low bidirectional control signal that acts as an input to initialize the MCU to a known start-up state. It also acts as an open-drain output to indicate that an internal failure has been detected in either the clock monitor or COP watchdog circuit. External circuitry connected to the RESET pin should not include alarge capacitance that would interfere with the ability of this signal to rise to a valid logic one within 32 ECLK cycles after the low drive is released. Upon detection of any reset, an internal circuit drives the RESET pin low and a clocked reset sequence controls when the MCU can begin normal processing.

2.3.3 TEST / VPP — Test Pin

This pin is reserved for test and must be tied to VSS in all applications.

2.3.4 XFC — PLL Loop Filter Pin

Dedicated pin used to create the PLL loop filter. See CRG BUG for more detailed information.PLL loop filter. Please ask your Motorola representative for the interactive application note to compute PLL loop filter elements. Any current leakage on this pin must be avoided.

XFC

MCU

Figure 2-4 PLL Loop Filter Connections

VDDPLLVDDPLL

Device User Guide — 9S12C128DGV1/D V01.05

2.3.5 BKGD / TAGHI / MODC — Background Debug, Tag High & Mode Pin

The BKGD / TAGHI / MODC pin is used as a pseudo-open-drain pin for the background debug communication. In MCU expanded modes of operation when instruction tagging is on, an input low on this pin during the falling edge of E-clock tags the high half of the instruction word being read into the instruction queue. It is also used as a MCU operating mode select pin at the rising edge during reset, when the state of this pin is latched to the MODC bit.

2.3.6 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins

PA7-PA0 are general purpose input or output pins,. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus. PA[7:1] pins are not available in the 48 package version. PA[7:3] are not available in the 52 pin package version.

2.3.7 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins

PB7-PB0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus. PB[7:5] and PB[3:0] pins are not available in the 48 nor 52 pin package version.

2.3.8 PE7 / NOACC / XCLKS — Port E I/O Pin 7

PE7 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC signal, when enabled, is used to indicate that the current bus cycle is an unused or “free” cycle. This signal will assert when the CPU is not using the bus.The XCLKS is an input signal which controls whether a crystal in combination with the internal Colpitts (low power) oscillator is used or whether Pierce oscillator/external clock circuitry is used. The state of this pin is latched at the rising edge of RESET. If the input is a logic low the EXTAL pin is configured for an external clock drive or a Pierce Oscillator. If input is a logic high a Colpitts oscillator circuit is configured on EXTAL and XTAL. Since this pin is an input with a pull-up device during reset, if the pin is left floating, the default configuration is a Colpitts oscillator circuit on EXTAL and XTAL.

Device User Guide — 9S12C128DGV1/D V01.05

EXTAL

CDC*

MCU

Crystal or

ceramic resonator

XTAL

VSSPLL

* Due to the nature of a translated ground Colpitts oscillator a

DC voltage bias is applied to the crystal

.Please contact the crystal manufacturer for crystal DC

Figure 2-5 Colpitts Oscillator Connections (PE7=1)

EXTAL

MCU

XTAL

Crystal or

ceramic resonator

VSSPLL

* Rs can be zero (shorted) when use with higher frequency crystals.

Refer to manufacturer’s data.

Figure 2-6 Pierce Oscillator Connections (PE7=0)

MCU

EXTAL

XTAL

not connected

CMOS-COMPATIBLE

EXTERNAL OSCILLATO

(VDDPLL-Level)

Figure 2-7 External Clock Connections (PE7=0)

Device User Guide — 9S12C128DGV1/D V01.05

2.3.9 PE6 / MODB / IPIPE1 — Port E I/O Pin 6

PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shared with the instruction queue tracking signal IPIPE1}. This pin is an input with a pull-down device which is only active when RESET is low. PE[6] is not available in the 48 / 52 pin package versions.

2.3.10 PE5 / MODA / IPIPE0 — Port E I/O Pin 5

PE5 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the instruction queue tracking signal IPIPE0}. This pin is an input with a pull-down device which is only active when RESET is low. This pin is not available in the 48 / 52 pin package versions.

2.3.11 PE4 / ECLK— Port E I/O Pin [4] / E-Clock Output

ECLK is the output connection for the internal bus clock. It is used to demultiplex the address and data in expanded modes and is used as a timing reference. ECLK frequency is equal to 1/2 the crystal frequency out of reset. The ECLK pin is initially configured as ECLK output with stretch in all expanded modes. The E clock output function depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in the MODE register and the ESTR bit in the EBICTL register. All clocks, including the E clock, are halted when the MCU is in STOP mode. It is possible to configure the MCU to interface to slow external memory. ECLK can be stretched for such accesses. Reference the MISC register (EXSTR[1:0] bits) for more information. In normal expanded narrow mode, the E clock is available for use in external select decode logic or as a constant speed clock for use in the external application system. Alternatively PE4 can be used as a general purpose input or output pin.

2.3.12 PE3 / LSTRB — Port E I/O Pin [3] / Low-Byte Strobe (LSTRB)

In all modes this pin can be used as a general-purpose I/O and is an input with an active pull-up out of reset. If the strobe function is required,it should be enabled by setting the LSTRE bit inthe PEAR register. This signal is used in write operations. Therefore external low byte writes will not be possible until this function is enabled. This pin is also used as

LSTRB function. This pin is not available in the 48 / 52 pin package versions.

the

TAGLO in Special Expanded modes and is multiplexed with

2.3.13 PE2 / R/W — Port E I/O Pin [2] / Read/Write

In all modes this pin can be used as a general-purpose I/O and is an input with an active pull-up out of reset. If the read/write function is required it should be enabled by setting the RDWE bit in the PEAR register. External writes will not be possible until enabled. This pin is not available in the 48 / 52 pin package versions.

Device User Guide — 9S12C128DGV1/D V01.05

2.3.14 PE1 / IRQ — Port E input Pin [1] / Maskable Interrupt Pin

The IRQ input provides a means of applying asynchronous interrupt requests to the MCU. Either falling edge-sensitive triggering or level-sensitive triggering is program selectable (INTCR register). always enabled and configured to level-sensitive triggering out of reset. It can be disabled by clearing IRQEN bit (INTCR register). When the MCU is reset the register. This pin is always an input and can always be read. There is an active pull-up on this pin while in reset and immediately out of reset. The pull-up can be turned off by clearing PUPEE in the PUCR register.

IRQ function is masked in the condition code

IRQ is

2.3.15 PE0 / XIRQ — Port E input Pin [0] / Non Maskable Interrupt Pin

The XIRQ input provides a means of requesting a non maskable interrupt after reset initialization. During reset, the X bit in the condition code register (CCR) is set and any interrupt is masked until MCU software enables it. Because the network. This pin is always an input and can always be read. There is an active pull-up on this pin while in reset and immediately out of reset. The pull-up can be turned off by clearing PUPEE in the PUCR register.

XIRQ input is level sensitive, it can be connected to a multiple-source wired-OR

2.3.16 PAD[7:0] / AN[7:0] — Port AD I/O Pins [7:0]

PAD7-PAD0 are general purpose I/O pins and also analog inputs for the analog to digital converter. In order to use a PAD pin as a standard I/O, the corresponding ATDDIEN register bit must be set. These bits are cleared out of reset to configure the PAD pins for A/D operation.

When the A/D converter is active in multi-channel mode, port inputs are scanned and converted irrespective of PortAD configuration. Thus PortAD pins that are configured as digital inputs or digital outputs are also converted in the A/D conversion sequence.

2.3.17 PP[7] / KWP[7] — Port P I/O Pin [7]

PP7 is a general purpose input or output pin, shared with the keypad interrupt function. When configured as an input, it can generate interrupts causing the MCU to exit STOP or WAIT mode. This pin is not available in the 48 / 52 pin package versions.

2.3.18 PP[6] / KWP[6]/ROMCTL — Port P I/O Pin [6]

PP6 is a general purpose input or output pin, shared with the keypad interrupt function. When configured as an input, it can generate interrupts causing the MCU to exit STOP or WAIT mode. This pin is not available in the 48 / 52 pin package versions. During MCU expanded modes of operation, this pin is used to enable the Flash EEPROM memory in the memory map (ROMCTL). At the rising edge of RESET, the state of this pin is latched to the ROMON bit. PP6=1 in emulation modes equates to ROMON =0 (ROM space externally mapped) PP6=0 in expanded modes equates to ROMON =0 (ROM space externally mapped)

Device User Guide — 9S12C128DGV1/D V01.05

2.3.19 PP[5:0] / KWP[5:0] / PW[5:0] — Port P I/O Pins [5:0]

PP[5:0] are general purpose input or output pins, shared with the keypad interrupt function. When configured as inputs, they can generate interrupts causing the MCU to exit STOP or WAIT mode. PP[5:0] are also shared with the PWM output signals, PW[5:0]. Pins PP[2:0] are only available in the 80 pin package version. Pins PP[4:3] are not available in the 48 pin package version.

2.3.20 PJ[7:6] / KWJ[7:6] — Port J I/O Pins [7:6]

PJ[7:6] are general purpose input or output pins, shared with the keypad interrupt function. When configured as inputs, they can generate interrupts causing the MCU to exit STOP or WAIT mode. These pins are not available in the 48 pin package version nor in the 52 pin package version.

2.3.21 PM5 / SCK — Port M I/O Pin 5

PM5 is a general purpose input or output pin and also the serial clock pin SCK for the Serial Peripheral Interface (SPI).

2.3.22 PM4 / MOSI — Port M I/O Pin 4

PM4 is a general purpose input or output pin and also the master output (during master mode) or slave input (during slave mode) pin for the Serial Peripheral Interface (SPI).

2.3.23 PM3 / SS — Port M I/O Pin 3

PM3 is a general purpose input or output pin and also the slave select pin SS for the Serial Peripheral Interface (SPI).

2.3.24 PM2 / MISO — Port M I/O Pin 2

PM2 is a general purpose input or output pin and also the master input (during master mode) or slave output (during slave mode) pin for the Serial Peripheral Interface (SPI).

2.3.25 PM1 / TXCAN — Port M I/O Pin 1

PM1 is a general purpose input or output pin and the transmit pin, TXCAN, of the CAN module if available.

2.3.26 PM0 / RXCAN — Port M I/O Pin 0

PM0 is a generalpurpose input or output pin and thereceive pin, RXCAN, of the CAN moduleif available.

Device User Guide — 9S12C128DGV1/D V01.05

2.3.27 PS[3:2] — Port S I/O Pins [3:2]

PS3 and PS2 are general purpose input or output pins. These pins are not available in the 48 / 52 pin package versions.

2.3.28 PS1 / TXD — Port S I/O Pin 1

PS1 is a general purpose input or output pin and the transmit pin,TXD, of SerialCommunication Interface (SCI).

2.3.29 PS0 / RXD — Port S I/O Pin 0

PS0 is a general purpose input or output pin and the receive pin, RXD, of Serial Communication Interface (SCI).

2.3.30 PPT[7:5] / IOC[7:5] — Port T I/O Pins [7:5]

PT7-PT5 are general purpose input or output pins. They can also be configured as the timer system input capture or output compare pins IOC7-IOC5.

2.3.31 PT[4:0] / IOC[4:0] / PW[4:0]— Port T I/O Pins [4:0]

PT4-PT0 are general purpose input or output pins. They can also be configured as the timer system input capture or output compare pins IOC4-IOC0 or as the PWM outputs PW[4:0].

2.4 Power Supply Pins

2.4.1 VDDX,VSSX — Power & Ground Pins for I/O Drivers

External power and ground for I/O drivers. Bypass requirements depend on how heavily the MCU pins are loaded.

2.4.2 VDDR, VSSR — Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator

External power and ground for the internal voltage regulator. Connecting VDDR to ground disables the internal voltage regulator.

2.4.3 VDD1, VDD2, VSS1, VSS2 — Internal Logic Power Pins

Power is supplied to the MCU through VDD and VSS. This 2.5V supply is derived from the internal voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is turned off, if VDDR is tied to ground.

Device User Guide — 9S12C128DGV1/D V01.05

2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG

VDDA, VSSA are the power supply and ground input pins for the voltage regulator reference and the analog to digital converter.

2.4.5 VRH, VRL — ATD Reference Voltage Input Pins

VRH and VRL are the reference voltage input pins for the analog to digital converter.

2.4.6 VDDPLL, VSSPLL — Power Supply Pins for PLL

Provides operating voltage and ground for the Oscillator and the Phased-Locked Loop. This allows the supply voltage to the Oscillator and PLL to be bypassed independently. This 2.5V voltage is generated by the internal voltage regulator.

Table 2-2 MC9S12C-Family Power and Ground Connection Summary

Mnemonic

VDD1

VDD2

VSS1

VSS2

VDDR 5.0 V VSSR 0 V VDDX 5.0 V

VSSX 0 V

VDDA 5.0 V Operating voltage and ground for the analog-to-digital converters and the

VSSA 0 V

VRH 5.0 V

VRL 0 V

VDDPLL 2.5 V Provides operating voltage and ground for the Phased-Locked Loop. This VSSPLL 0 V

Nominal

Voltage

2.5 V

Description

Internal power and ground generated by internal regulator. These also allow an external source to supply the core VDD/VSS voltages and bypass the internal voltage regulator. In the 48 and 52 LQFP packages VDD2 and VSS2 are not available.

External power and ground, supply to internal voltage regulator.

External power and ground, supply to pin drivers.

reference for the internal voltageregulator,allowsthe supply voltage to the A/D to be bypassed independently.

Reference voltage low for the ATD converter. In the 48 and 52 LQFP packages VRL is bonded to VSSA.

allows the supply voltage to the PLL to be bypassed independently. Internal power and ground generated by internal regulator.

NOTE:

All VSS pins must be connected together in the application. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on MCU pin load.

Section 3 System Clock Description

Device User Guide — 9S12C128DGV1/D V01.05

The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules. Figure 3-1 shows the clock connections from the CRG to all modules. Consult the CRG Block User Guide for details on clock generation.

EXTAL

XTAL

CRG

core clock

bus clock

oscillator clock

Figure 3-1 Clock Connections

S12_CORE

Flash

RAM

TIM

ATD

PIM

SCI SPI

MSCAN

Not on 9S12GC

VREG

TPM

Section 4 Modes of Operation

4.1 Overview

Eight possible modes determine the operating configuration of the MC9S12C Family. Each mode has an associated default memory map and external bus configuration controlled by a further pin.

Three low power modes exist for the device.

4.2 Chip Configuration Summary

The operating mode out ofresetis determined by the statesof the MODC, MODB, andMODApins during reset. The MODC, MODB, and MODA bits in the MODE register show the current operating mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA pins are

Device User Guide — 9S12C128DGV1/D V01.05

latched into these bits on the rising edge of the reset signal. The ROMCTL signal allows the setting of the ROMON bit in theMISC register thus controllingwhether the internal Flashis visible in thememory map. ROMON = 1 mean the Flash is visible in the memory map. The state of the ROMCTL pin is latched into the ROMON bit in the MISC register on the rising edge of the reset signal.

Table 4-1 Mode Selection

BKGD =

MODC

000X1

001 0 1 0 X 0 Special Test (Expanded Wide), BDM allowed 011 1 0 0 X 1 Normal Single Chip, BDM allowed 101

110X1

111

PE6 =

MODB

PE5 =

MODA

PP6 =

ROMCTL

01 10

00 11

ROMON

Bit

Mode Description

Special Single Chip, BDM allowed and ACTIVE. BDM is allowed in all other modes but a serial command is required to make BDM active.

Emulation Expanded Narrow, BDM allowed

Emulation Expanded Wide, BDM allowed

Normal Expanded Narrow, BDM allowed Peripheral; BDM allowed but bus operations would cause

bus conﬂicts (must not be used) Normal Expanded Wide, BDM allowed

For further explanation on the modes refer to the S12_MEBI block guide.

Table 4-2 Clock Selection Based on PE7

PE7 = XCLKS Description

1 Colpitts Oscillator selected 0 Pierce Oscillator/external clock selected

4.3 Security

The device will make available a security feature preventing the unauthorized read and write of the memory contents. This feature allows:

• Protection of the contents of FLASH,

• Operation in single-chip mode,

• Operation from external memory with internal FLASH disabled.

The user must be reminded that part of the security must lie with the user’s code. An extreme example would be user’s code that dumps the contents of the internal program. This code would defeat the purpose of security. At the same time the user may also wish to put a back door in the user’s program. An example

Device User Guide — 9S12C128DGV1/D V01.05

of this is the user downloads a key through the SCI which allows access to a programming routine that updates parameters.

4.3.1 Securing the Microcontroller

Once the user has programmed the FLASH, the part can be secured by programming the security bits located in the FLASH module. These non-volatile bits will keep the part secured through resetting the part and through powering down the part.

The security byte resides in a portion of the Flash array. Check the Flash Block User Guide for more details on the security configuration.

4.3.2 Operation of the Secured Microcontroller

4.3.2.1 Normal Single Chip Mode

This will be the most commonusage of the secured part. Everything will appear the same as if the part was not secured with the exception of BDM operation. The BDM operation will be blocked.

4.3.2.2 Executing from External Memory

The user may wish to execute from external space with a secured microcontroller. This is accomplished by resetting directly into expanded mode. The internal FLASH will be disabled. BDM operations will be blocked.

4.3.3 Unsecuring the Microcontroller

In order to unsecure the microcontroller, the internal FLASH must be erased. This can be done through an external program in expanded mode or via a sequence of BDM commands. Unsecuringis also possiblevia the Backdoor Key Access. Refer to Flash Block Guide for details.

Once the user has erased the FLASH, the part can be reset into special single chip mode. This invokes a program that verifies the erasure of the internal FLASH. Once this program completes, the user can erase and program the FLASH security bits to the unsecured state. This is generally done through the BDM, but the user could also change to expanded mode (by writing the mode bits through the BDM) and jumping to an external program (again through BDM commands). Note that if the part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be secured again.

4.4 Low Power Modes

The microcontroller features three main low power modes. Consult the respective Block User Guide for information on the module behavior in Stop, Pseudo Stop, and Wait Mode. An important source of information about the clock system is the Clock and Reset Generator User Guide (CRG).

Device User Guide — 9S12C128DGV1/D V01.05

4.4.1 Stop

Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static mode. Wake up from this mode can be done via reset or external interrupts.

4.4.2 Pseudo Stop

This mode is entered by executing the CPU STOP instruction. In this mode the oscillator is still running and the Real Time Interrupt (RTI) or Watchdog (COP) sub module can stay active. Other peripherals are turned off. This mode consumes more current than the full STOP mode, but the wake up time from this mode is significantly shorter.

4.4.3 Wait

This mode is entered by executing the CPU WAI instruction. In this mode the CPU will not execute instructions.The internal CPU signals (address and databus)willbefully static. All peripherals stay active. For further power consumption reduction the peripherals can individually turn off their local clocks.

4.4.4 Run

Although this is not a low power mode, unused peripheral modules should not be enabled in order to save power.

Section 5 Resets and Interrupts

5.1 Overview

Consult the Exception Processing section of the CPU12 Reference Manual for information.

5.2 Vectors

5.2.1 Vector Table

Table 5-1 lists interrupt sources and vectors in default order of priority.

Table 5-1 Interrupt Vector Locations

Vector Address Interrupt Source

External Reset, Power On Reset or Low

$FFFE, $FFFF

$FFFC, $FFFD Clock Monitor fail reset None COPCTL (CME, FCME) – $FFFA, $FFFB COP failure reset None COP rate select – $FFF8, $FFF9 Unimplemented instruction trap None None –

Voltage Reset (see CRG Flags Register

to determine reset source)

CCR

Mask

None None –

Local Enable

HPRIO Value

to Elevate

Device User Guide — 9S12C128DGV1/D V01.05

$FFF6, $FFF7 SWI None None – $FFF4, $FFF5 XIRQ X-Bit None – $FFF2, $FFF3 IRQ I-Bit INTCR (IRQEN) $F2 $FFF0, $FFF1 Real Time Interrupt I-Bit CRGINT (RTIE) $F0 $FFEE, $FFEF Standard Timer channel 0 I-Bit TIE (C0I) $EE $FFEC, $FFED Standard Timer channel 1 I-Bit TIE (C1I) $EC $FFEA, $FFEB Standard Timer channel 2 I-Bit TIE (C2I) $EA $FFE8, $FFE9 Standard Timer channel 3 I-Bit TIE (C3I) $E8 $FFE6, $FFE7 Standard Timer channel 4 I-Bit TIE (C4I) $E6 $FFE4, $FFE5 Standard Timer channel 5 I-Bit TIE (C5I) $E4 $FFE2, $FFE3 Standard Timer channel 6 I-Bit TIE (C6I) $E2 $FFE0, $FFE1 Standard Timer channel 7 I-Bit TIE (C7I) $E0 $FFDE, $FFDF Standard Timer overﬂow I-Bit TMSK2 (TOI) $DE $FFDC, $FFDD Pulse accumulator A overﬂow I-Bit PACTL (PAOVI) $DC $FFDA, $FFDB Pulse accumulator input edge I-Bit PACTL (PAI) $DA $FFD8, $FFD9 SPI I-Bit SPICR1 (SPIE, SPTIE) $D8

$FFD6, $FFD7 SCI I-Bit $FFD4, $FFD5

$FFD2, $FFD3 ATD I-Bit ATDCTL2 (ASCIE) $D2 $FFD0, $FFD1 $FFCE, $FFCF Port J I-Bit PIEP (PIEP7-6) $CE $FFCC, $FFCD $FFCA, $FFCB $FFC8, $FFC9 $FFC6, $FFC7 CRG PLL lock I-Bit PLLCR (LOCKIE) $C6 $FFC4, $FFC5 CRG Self Clock Mode I-Bit PLLCR (SCMIE) $C4 $FFBA to $FFC3 $FFB8, $FFB9 FLASH I-Bit FCNFG (CCIE, CBEIE) $B8

$FFB6, $FFB7 $FFB4, $FFB5 $FFB2, $FFB3 $FFB0, $FFB1

$FF90 to $FFAF $FF8E, $FF8F Port P I-Bit PIEP (PIEP7-0) $8E $FF8C, $FF8D PWM Emergency Shutdown I-Bit PWMSDN(PWMIE) $8C $FF8A, $FF8B VREG LVI I-Bit CTRL0 (LVIE) $8A $FF80 to $FF89

NOTES:

1. Not available on MC9S12GC-Family members

CAN wake-up

CAN errors

CAN receive

CAN transmit

Reserved

Reserved Reserved Reserved

Reserved

I-Bit CANRIER (WUPIE) $B6 I-Bit CANRIER (CSCIE, OVRIE) $B4 I-Bit CANRIER (RXFIE) $B2 I-Bit CANTIER (TXEIE[2:0]) $B0

Reserved

SCICR2

(TIE, TCIE, RIE, ILIE)

$D6

5.3 Resets

Resets are a subset of the interrupts featured inTable 5-1. The different sources capable of generating a system reset are summarized in Table 5-2. When a reset occurs, MCU registers and control bits are

Device User Guide — 9S12C128DGV1/D V01.05

changed to known start-up states. Refer to the respective module Block User Guides for register reset states.

5.3.1 Reset Summary Table

Table 5-2 Reset Summary

Reset Priority Source Vector

Power-on Reset 1 CRG Module $FFFE, $FFFF

External Reset 1 RESET pin $FFFE, $FFFF

Low Voltage Reset 1 VREG Module $FFFE, $FFFF

Clock Monitor Reset 2 CRG Module $FFFC, $FFFD

COP Watchdog Reset 3 CRG Module $FFFA, $FFFB

5.3.2 Effects of Reset

When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the respective module Block User Guides for register reset states. Refer to the HCS12 Multiplexed External Bus Interface (MEBI) Block Guide for mode dependent pin configuration of port A, B and E out of reset.

Refer to the PIM Block User Guide for reset configurations of all peripheral module ports. Refer to Figure 1-2 to Figure 1-5 footnotes for locations of the memories depending on the operating

mode after reset. The RAM array is not automatically initialized out of reset.

NOTE:

For devices assembled in 48-pin or 52-pinLQFP packages all non-bonded out pins should be configured as outputs after reset in order to avoid current drawn from floating inputs. Refer to

Table 2-1

for affected pins.

Section 6 HCS12 Core Block Description

Consult the individual block guides for information about the HCS12 core modules, i.e.central processing unit (CPU), interrupt module (INT), module mapping control module (MMC), multiplexed external bus interface (MEBI), debug12 module (DBG12) and background debug mode module (BDM). Where the CPU12 Reference Manual refers to cycles this is equivalent to device bus clock periods.

6.1 Device-specific information

6.1.1 PPAGE

External paging is not supported on these devices. In order to access the 16K flash blocks in the address range $8000-$BFFF the PPAGE registermust be loaded with thecorresponding value for this range.Refer to Table 6-1 for device specific page mapping.

Device User Guide — 9S12C128DGV1/D V01.05

For all devicesFlash Page 3F is visible in the $C000-$FFFF range if ROMON is set. For all devices (ecept 9S12GC16) Page 3E is also visible in the $4000-$7FFF range if ROMHM is cleared and ROMON is set. For all devices apart from MC9S12C32 Flash Page 3D is visible in the $0000-$3FFF range if ROMON is set...

Table 6-1 Device Specific Flash PAGE Mapping

Device PAGE PAGE visible with PPAGE contents

MC9S12GC16 3F $00,$01,$02,$03,$04,$05,$06,$07,$08,$09......$36,$37,$38,$39,$3A,$3B,$3C,$3D,$3E,$3F

MC9S12C32

MC9S12GC32

MC9S12C64

MC9S12GC64

MC9S12C96

MC9S12C128

MC9S12GC128

3E $00,$02,$04,$06,$08,$0A,$0C,$0E,$10,$12......$2C,$2E,$30,$32,$34,$36,$38,$3A,$3C,$3E

3F $01,$03,$05,$07,$09,$0B,$0D,$0F,$11,$13.....$2D,$2F,$31,$33,$35,$37,$39,$3B,$3D,$3F

3C $00,$04,$08,$0C,$10,$14,$18,$1C,$20,$24,$28,$2C,$30,$34,$38,$3C 3D $01,$05,$09,$0D,$11,$15,$19,$1D,$21,$25,$29,$2D,$31,$35,$39,$3D

3E $02,$06,$0A,$0E,$12,$16,$1A,$1E,$22,$26,$2A,$2E,$32,$36,$3A,$3E

3F $03,$07,$0B,$0F,$13,$17,$1B,$1F,$23,$27,$2B,$2F,$33,$37,$3B,$3F

3A $00,$02,$08,$0A,$10,$12,$18,$1A,$20,$22,$28,$2A,$30,$32,$38,$3A

3B $01,$03,$09,$0B,$11,$13,$19,$1B,$21,$23,$29,$2B,$31,$33,$39,$3B 3C $04,$0C,$14,$1C,$24,$2C,$34,$3C 3D $05,$0D,$15,$1D,$25,$2D,$35,$3D

3E $06,$0E,$16,$1E,$26,$2E,$36,$3E

3F $07,$0F,$17,$1F,$27,$2F,$37,$3F

38 $00,$08,$10,$18,$20,$28,$30,$38

39 $01,$09,$11,$19,$21,$29,$31,$39

3A $02,$0A,$12,$1A,$22,$2A,$32,$3A

3B $03,$0B,$13,$1B,$23,$2B,$33,$3B 3C $04,$0C,$14,$1C,$24,$2C,$34,$3C 3D $05,$0D,$15,$1D,$25,$2D,$35,$3D

3E $06,$0E,$16,$1E,$26,$2E,$36,$3E

3F $07,$0F,$17,$1F,$27,$2F,$37,$3F

6.1.2 BDM alternate clock

The BDM section of S12 Core User Guide reference to alternate clock is equivalent to oscillator clock.

6.1.3 Extended Address Range Emulation Implications

In order to emulate the MC9S12GC or MC9S12C-Family devices, external addressing of a 128K memory map is required. This is provided in a 112 LQFP package version which includes the 3 necessary extra external address bus signals via PortK[2:0]. This package version is for emulation only and not provided as a general production package.

The reset state of DDRK is $00, configuring the pins as inputs. The reset state of PUPKE in the PUCR register is “1” enabling the internal PortK pullups. In this reset state the pull-ups provide a defined state and prevent a floating input, thereby preventing

unnecessary current flow at the input stage.

Device User Guide — 9S12C128DGV1/D V01.05

To prevent unnecessary current flow in production package options, the states of DDRK and PUPKE should not be changed by software.

Section 7 Voltage Regulator (VREG) Block Description

Consult the VREG Block User Guide for information about the dual output linear voltage regulator.

7.1 Device-specific information

The VREG is part of the IPBus domain.

7.1.1 VREGEN

VREGEN is connected internally to VDDR.

7.1.2 VDD1, VDD2, VSS1, VSS2

In the 80 pin QFP package versions, both internal VDD and VSS of the 2.5V domain are bonded out on 2 sides of the device as two pin pairs (VDD1, VSS1 & VDD2, VSS2). VDD1 and VDD2 are connected together internally. VSS1 and VSS2 are connected together internally.

The extra pin pair enables systems using the 80 pin package to employ better supply routing and further decoupling.

Section 8 Recommended Printed Circuit Board Layout

The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the MCU itself. The following rules must be observed:

• Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins (C1 - C6).

• Central point of the ground star should be the VSSR pin.

• Use low ohmic low inductance connections between VSS1, VSS2 and VSSR.

• VSSPLL must be directly connected to VSSR.

• Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C7, C8, C11 and Q1 as small as possible.

• Do not place other signals or supplies underneath area occupied by C7, C8, C10 and Q1 and the connection area to the MCU.

• Central power input should be fed in at the VDDA/VSSA pins.

Device User Guide — 9S12C128DGV1/D V01.05

Table 8-1 Recommended External Component Values

Component Purpose Type Value

C1 VDD1 ﬁlter capapcitor ceramic X7R

220nF, 470nF C2 VDD2 ﬁlter capacitor (80 QFP only) ceramic X7R 220nF C3 VDDA ﬁlter capacitor ceramic X7R 100nF C4 VDDR ﬁlter capacitor X7R/tantalum >=100nF C5 VDDPLL ﬁlter capacitor ceramic X7R 100nF C6 VDDX ﬁlter capacitor X7R/tantalum >=100nF C7 OSC load capacitor

See PLL speciﬁcation chapter

C8 OSC load capacitor C9 PLL loop ﬁlter capacitor

See PLL speciﬁcation chapter

C10 PLL loop ﬁlter capacitor

C11 DC cutoff capacitor

Colpitts mode only, if recommended by

quartz manufacturer

R1 PLL loop ﬁlter resistor See PLL Speciﬁcation chapter

R2 / R

PLL loop ﬁlter resistor

Pierce mode only

R3 / R

PLL loop ﬁlter resistor

Q1 Quartz

NOTES:

1. In 48LQFP and 52LQFP package versions, VDD2 is not available. Thus 470nF must be connected to VDD1.

Device User Guide — 9S12C128DGV1/D V01.05

VDDX

VSSX

VDD1

VSS1

VSSA

VDDA

Note:

Oscillator in Colpitts mode.

VSSR

VDDR

C10

C11

VSSPLL VDDPLL

Figure 8-1 Recommended PCB Layout (48 LQFP)

Device User Guide — 9S12C128DGV1/D V01.05

)

NOTE: Oscillator in Colpitts mode.

VDD1

VSS1

VSSR

VDDX

VSSX

VSSA

VDDA

C10

C11

VSSPLL

VDDPLL

VDDR

Figure 8-2 Recommended PCB Layout (52 LQFP)

Device User Guide — 9S12C128DGV1/D V01.05

NOTE: Oscillator in Colpitts mode.

VDDX

)

VSSA

VDD1

VSS1

VSSX

VDDA

VSS2

VDD2

VSSR

VDDR

C10

C11

VSSPLL VDDPLL

Figure 8-3 Recommended PCB Layout (80 QFP)

Device User Guide — 9S12C128DGV1/D V01.05

VDD1

VSS1

VDDR

VSSR

VDDX

VSSX

C10

VSSA

VSSPLL

VDDPLL

VDDA

Figure 8-4 Recommended PCB Layout for 48 LQFP Pierce Oscillator

Device User Guide — 9S12C128DGV1/D V01.05

VDD1

VSS1

VSSR

VDDR

VDDX

VSSX

C10

VSSA

VSSPLL

VDDPLL

VDDA

Figure 8-5 Recommended PCB Layout for 52 LQFP Pierce Oscillator

VDDX

Device User Guide — 9S12C128DGV1/D V01.05

VDD1

VSS1

VSSR

VDDR

VSSX

VSSA

VDDA

VSS2

VDD2

VSSPLL

C10

VSSPLL

VDDPLL

Figure 8-6 Recommended PCB Layout for 80QFP Pierce Oscillator

Section 9 Clock Reset Generator (CRG) Block Description

Consult the CRG Block User Guide for information about the Clock and Reset Generator module.

9.1 Device-specific information

The CRG is part of the IPBus domain.

Device User Guide — 9S12C128DGV1/D V01.05

The Low Voltage Reset feature uses the low voltage reset signal from the VREG module as an input to the CRG module. When the regulator output voltage supply to the internal chip logic falls below a specified threshold the LVR signal from the VREG module causes the CRG module to generate a reset. Consult the VREG Block User Guide for voltage level specifications.

9.1.1 XCLKS

The XCLKS input signal is active low (see 2.3.8 PE7 / NOACC / XCLKS — Port E I/O Pin 7).

Section 10 Oscillator (OSC) Block Description

Consult the OSC Block User Guide for information about the Oscillator module.

Section 11 Timer (TIM) Block Description

Consult the TIM_16B8C Block User Guide for information about the Timer module.

Section 12 Analog to Digital Converter (ATD) Block Description

12.1 Device-specific information

12.1.1 VRL (voltage reference low)

In the 48 and 52 pin package versions, the VRL pad is bonded internally to the VSSA pin. Consult the ATD_10B8C Block User Guide for further information about the A/D Converter module.

Section 13 Serial Communications Interface (SCI) Block Description

Consult the SCI Block User Guide for information about the Asynchronous Serial Communications Interface module.

Section 14 Serial Peripheral Interface (SPI) Block Description

Consult the SPI Block User Guide for information about the Serial Peripheral Interface module.

Device User Guide — 9S12C128DGV1/D V01.05

Consult the SPI Block User Guide for information about the Synchronous Serial Communications Interface module.

Section 15 Flash Block Description

Consult the FTS16K Block User Guide for information about the Flash module for the MC9S12GC16. Consult the FTS32K Block User Guide for information about the Flash module for the MC9S12C32 or

MC9S12GC32. Consult the FTS64K Block User Guide for information about the Flash module for the MC9S12C64 or

MC9S12GC64. Consult the FTS96K Block User Guide for information about the Flash module for the MC9S12C96. Consult the FTS128K Block User Guide for information about the Flash module for the MC9S12C128or

MC9S12GC128.

Section 16 RAM Block Description

This module supports single-cycle misaligned word accesses without wait states. The MC912GC16 features a single 1K byte RAM module. The MC9S12C32 and MC9S12GC32 feature a 2K byte RAM module. The MC9S12C64, MC9S12GC64, MC9S12C96, MC9S12C128 and MC9S12GC128 versions feature a

4K byte RAM module.

Section 17 Pulse Width Modulator (PWM) Block Description

Consult the PWM_8B6C Block User Guide for information about the Pulse Width Modulator Module.

Section 18 MSCAN Block Description

Consult the MSCAN Block User Guide for information about the Motorola Scalable CAN Module. This module is not available on the MC9GC-Family Members.

Section 19 Port Integration Module (PIM) Block Description

Device User Guide — 9S12C128DGV1/D V01.05

Consult the PIM_9C32 Block User Guide for information about the Port Integration Module for all versions of the MC9DS12GC and MC9S12C-Family.

The MODRR register within the PIM allows for mapping of PWM channels to PortT in the absence of PortP pins for the low pin count packages. For the 80QFP package option it is recommended not to use MODRR since this is intended to support PWM channel availability in low pin count packages. Note that when mapping PWM channels to PortT in an 80QFP option, the associated PWM channels are then mapped to both PortP and PortT.

Device User Guide — 9S12C128DGV1/D V01.05

Appendix A Electrical Characteristics

A.1 General

NOTE:

This supplement contains the most accurate electrical information for the MC9S12C-Family microcontrollers available at the time of publication. The information should be considered

PRELIMINARY and is subject to change.

This introduction is intended to give an overview on several common topics like power supply, current injection etc.

The electrical characteristics given in this section are preliminary and should be used as a guide only. Values cannot be guaranteed by Motorola and are subject to change without notice.

The parts are specified and tested over the 5V and 3.3V ranges. For the intermediate range, generally the electrical specifications for the 3.3V range apply, but the parts are not tested in production test in the intermediate range.

A.1.1 Parameter Classification

The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate.

NOTE:

This classification will be added at a later release of the specification

P: Those parameters are guaranteed during production testing on each individual device. C: Those parameters are achieved by the design characterization by measuring a statistically relevant

sample size across process variations. They are regularly verified by production monitors. T: Those parameters are achieved by designcharacterization on a smallsample size from typicaldevices.

All values shown in the typical column are within this category. D: Those parameters are derived mainly from simulations.

A.1.2 Power Supply

The MC9S12C-Family and MC9S12GC-Family members utilize several pins to supply power to the I/O ports, A/D converter, oscillator and PLL as well as the internal logic.

The VDDA, VSSA pair supplies the A/D converter. The VDDX, VSSX pair supplies the I/O pins The VDDR, VSSR pair supplies the internal voltage regulator. VDD1, VSS1, VDD2 and VSS2 are the supply pins for the digital logic. VDDPLL, VSSPLL supply the oscillator and the PLL.

Device User Guide — 9S12C128DGV1/D V01.05

VSS1 and VSS2 are internally connected by metal. VDD1 and VDD2 are internally connected by metal. VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD protection.

NOTE:

In the following context VDD5 is used for either VDDA, VDDR and VDDX; VSS5 is used for either VSSA, VSSR and VSSX unless otherwise noted. IDD5 denotes the sum of the currents flowing into the VDDA, VDDX and VDDR pins. VDD is used for VDD1, VDD2 and VDDPLL, VSS is used for VSS1, VSS2 and VSSPLL. IDD is used for the sum of the currents flowing into VDD1 and VDD2.

A.1.3 Pins

There are four groups of functional pins.

A.1.3.1 5V I/O pins

Those I/O pins have a nominal level of 5V. This class of pins is comprised of all port I/O pins, the analog inputs, BKGD pin and theRESETinputs.The internal structure of allthose pins is identical, howeversome of the functionality may be disabled. E.g. pull-up and pull-down resistors may be disabled permanently.

A.1.3.2 Analog Reference

This class is made up by the two VRH and VRL pins. In 48 and 52 pin package versions the VRL pad is bonded to the VSSA pin.

A.1.3.3 Oscillator

The pins XFC, EXTAL, XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied by VDDPLL.

A.1.3.4 TEST

This pin is used for production testing only.

A.1.4 Current Injection

Power supply must maintain regulation within operating V operating maximum current conditions. If positive injection current (V injection current mayflow out of VDD5 and could result in external power supply going out of regulation. Insure external VDD5 load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is very low which would reduce overall power consumption.

or VDD range during instantaneous and

DD5

) is greater than I

DD5

, the

Device User Guide — 9S12C128DGV1/D V01.05

A.1.5 Absolute Maximum Ratings

Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device.

This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either V

Table A-1 Absolute Maximum Ratings

Num Rating Symbol Min Max Unit

SS5

or V

DD5

1 I/O, Regulator and Analog Supply Voltage 2

Digital Logic Supply Voltage

PLL Supply Voltage

(1)

4 Voltage difference VDDX to VDDR and VDDA 5 Voltage difference VSSX to VSSR and VSSA 6 Digital I/O Input Voltage 7 Analog Reference 8 XFC, EXTAL, XTAL inputs 9 TEST input

Instantaneous Maximum Current

Single pin limit for all digital I/O pins Instantaneous Maximum Current

Single pin limit for XFC, EXTAL, XTAL Instantaneous Maximum Current

Single pin limit for TEST

13 Operating Temperature Range (packaged) 14 Operating Temperature Range (junction) 15 Storage Temperature Range

DD5

DDPLL

∆

VDDX

∆

VSSX

RH,VRL

ILV

TEST

T T

stg

-0.3 6.5 V

-0.3 3.0 V

-0.3 0.3 V

-0.3 6.5 V

-0.3 3.0 V

-0.3 10.0 V

-25 +25 mA

-0.25 0 mA

– 40 125 °C – 40 140 °C – 65 155 °C

NOTES:

1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when the device is powered from an external source.

2. All digital I/O pins are internally clamped to V

3. These pins are internally clamped to V

4. This pin is clamped low to V

SSX

SSPLL

, but not clamped high. This pin must be tied low in applications.

and V

SSX

and V

DDPLL

DDX

, V

SSR

and V

DDR

or V

SSA

and V

DDA

Device User Guide — 9S12C128DGV1/D V01.05

A.1.6 ESD Protection and Latch-up Immunity

All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model.

A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification.

Table A-2 ESD and Latch-up Test Conditions

Model Description Symbol Value Unit

Series Resistance R1 1500 Ohm Storage Capacitance C 100 pF

Human Body

Number of Pulse per pin positive negative

Series Resistance R1 0 Ohm

3 3

Storage Capacitance C 200 pF

Machine

Latch-up

Number of Pulse per pin positive negative

Minimum input voltage limit -2.5 V Maximum input voltage limit 7.5 V

3 3

Table A-3 ESD and Latch-Up Protection Characteristics

Num C Rating Symbol Min Max Unit

1 C Human Body Model (HBM) 2 C Machine Model (MM) 3 C Charge Device Model (CDM)

Latch-up Current at 125°C

positive negative

Latch-up Current at 27°C positive negative

HBM

CDM

LAT

2000 - V

200 - V 500 - V

+100

-100

+200

-200

-mA

A.1.7 Operating Conditions

This chapter describes the operating conditions of the devices. Unless otherwise noted those conditions apply to all the following data.

Device User Guide — 9S12C128DGV1/D V01.05

NOTE:

Insteadof specifying ambient temperature all parametersarespecified for the more meaningful silicon junction temperature. For power dissipation calculations refer to Section A.1.8 Power Dissipation and Thermal Characteristics.

Table A-4 Operating Conditions

Rating Symbol Min Typ Max Unit

I/O, Regulator and Analog Supply Voltage Digital Logic Supply Voltage PLL Supply Voltage

Voltage Difference VDDX to VDDA Voltage Difference VSSX to VSSR and VSSA Oscillator

Bus Frequency Operating Junction Temperature Range

NOTES:

1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when this regulator is disabled and the device is powered from an external source.

2. Some blocks e.g. ATD (conversion) and NVMs (program/erase) require higher bus frequencies for proper operation.

(1)

DDPLL

∆

VDDX

∆

VSSX

bus

DD5

osc

2.97 5 5.5 V

2.35 2.5 2.75 V

-0.1 0 0.1 V

0.5 - 16 MHz

0.25 - 25 MHz

-40 - 140 °C

A.1.8 Power Dissipation and Thermal Characteristics

Power dissipation and thermal characteristics are closely related. The user must assure that the maximum operating junction temperature is not exceeded. The average chip-junction temperature (T obtained from:

T T P

J A

Junction Temperature, [°C]=

Ambient Temperature, [°C]=

Total Chip Power Dissipation, [W]=

Package Thermal Resistance, [°C/W]=

ΘJA•()+=

The total power dissipation can be calculated from:

INT

Chip Internal Power Dissipation, [W]=

INTPIO

)in°C can be

Device User Guide — 9S12C128DGV1/D V01.05

Two cases with internal voltage regulator enabled and disabled must be considered:

1. Internal Voltage Regulator disabled

INT

Which is the sum of all output currents on I/O ports associated with VDDX and VDDM. For R

respectively

2. Internal voltage regulator enabled

DDR

additionally contains the current flowing into the external loads with output high.

is valid:

DSON

is the current shown in Table A-8 and not the overall current flowing into VDDR, which

DSON

⋅ I

DDVDD

DSON

------------------------------------ for outputs driven high;=

INT

DDPLLVDDPLL

∑

DSON

------------ for outputs driven low;= I

DD5

DDRVDDR

VOH–

⋅ I

∑

DSON

⋅ I

⋅=

DDAVDDA

⋅=

⋅+=

DDA

⋅+=

DDA

Device User Guide — 9S12C128DGV1/D V01.05

Which is the sum of all output currents on I/O ports associated with VDDX and VDDR.

Table A-5 Thermal Package Characteristics

Num C Rating Symbol Min Typ Max Unit

Thermal Resistance LQFP48, single layer PCB Thermal Resistance LQFP48, double sided PCB with

2 internal planes

3 T Junction to Board LQFP48 4 T Junction to Case LQFP48 5 T Junction to Package Top LQFP48 6 T Thermal Resistance LQFP52, single sided PCB

Thermal Resistance LQFP52, double sided PCB with 2 internal planes

8 T Junction to Board LQFP52

9 T Junction to Case LQFP52 10 T Junction to Package Top LQFP52 11 T Thermal Resistance QFP 80, single sided PCB

12 T

Thermal Resistance QFP 80, double sided PCB with 2 internal planes

13 T Junction to Board QFP80 14 T Junction to Case QFP80 15 T Junction to Package Top QFP80

NOTES:

1. The values for thermal resistance are achieved by package simulations

2. PC Board according to EIA/JEDEC Standard 51-2

3. PC Board according to EIA/JEDEC Standard 51-7

--69

--53

30 20

--65

--49

31 17

--52

--42

28 18

C/W

A.1.9 I/O Characteristics

This section describes the characteristics of all I/O pins. All parameters are not always applicable, e.g. not all pins feature pull up/down resistances.

Device User Guide — 9S12C128DGV1/D V01.05

Table A-6 5V I/O Characteristics

Conditions are 4.5< VDDX <5.5V Termperature from -40˚C to +140˚C, unless otherwise noted

Num C Rating Symbol Min Typ Max Unit

1 P Input High Voltage

T Input High Voltage

2 P Input Low Voltage

T Input Low Voltage

3 C Input Hysteresis

V V

HYS

0.65*V

DD5

--V

- - VDD5 + 0.3 V

VSS5 - 0.3 - - V

0.35*V

250 mV

DD5

Input Leakage Current (pins in high ohmic input

10 C

11 P

12 C

mode) Vin= V

DD5

or V

SS5

Output High Voltage (pins in output mode) Partial Drive IOH= –2mA

Output High Voltage (pins in output mode) Full Drive IOH = –10mA

Output Low Voltage (pins in output mode) Partial Drive IOL = +2mA

Output Low Voltage (pins in output mode) Full Drive IOL= +10mA

Internal Pull Up Device Current, tested at V

Max.

Internal Pull Up Device Current, tested at V

Min.

Internal Pull Down Device Current, tested at V

Min.

Internal Pull Down Device Current, tested at V

Max.

13 D Input Capacitance

Injection current

14 T

Single Pin limit

Total Device Limit. Sum of all injected currents 15 P 16 P

Port P, J Interrupt Input Pulse ﬁltered

Port P, J Interrupt Input Pulse passed

PUL

PUH

PDH

PDL

ICS

ICP

PIGN

PVAL

–1 - 1 µA

– 0.8

DD5

– 0.8

DD5

--V

- - 0.8 V

- - -130 µA

-10 - - µA

- - 130 µA

10 - - µA

7-pF

-2.5

-25

- 2.5 25

3 µs

10 µs

NOTES:

1. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8 C to 12 C in the temperature range from 50 C to 125 C.

2. Refer to Section A.1.4 Current Injection, for more details

3. Parameter only applies in STOP or Pseudo STOP mode.

Device User Guide — 9S12C128DGV1/D V01.05

Table A-7 3.3V I/O Characteristics

Conditions are VDDX=3.3V +/-10%, Termperature from -40˚C to +140˚C, unless otherwise noted

Num C Rating Symbol Min Typ Max Unit

1 P Input High Voltage

T Input High Voltage

2 P Input Low Voltage

T Input Low Voltage

3 C Input Hysteresis

V V

HYS

0.65*V

DD5

- - VDD5 + 0.3 V

VSS5 - 0.3 - - V

--V

0.35*V

250 mV

DD5

Input Leakage Current (pins in high ohmic input

10 C

11 P

12 C

mode) Vin= V

DD5

or V

SS5

Output High Voltage (pins in output mode) Partial Drive IOH= –0.75mA

Output High Voltage (pins in output mode) Full Drive IOH= –4mA

Output Low Voltage (pins in output mode) Partial Drive IOL= +0.9mA

Output Low Voltage (pins in output mode) Full Drive IOL= +4.75mA

Internal Pull Up Device Current, tested at V

Max.

Internal Pull Up Device Current, tested at V

Min.

Internal Pull Down Device Current, tested at V

Min.

Internal Pull Down Device Current, tested at V

Max.

11 D Input Capacitance

12 T

Injection current Single Pin limit

Total Device Limit. Sum of all injected currents 13 P 14 P

Port P, J Interrupt Input Pulse ﬁltered

Port P, J Interrupt Input Pulse passed

PUL

PUH

PDH

PDL

ICS

ICP

PIGN

PVAL

–1 - 1 µA

DD5

– 0.4

--V

- - 0.4 V

- - –60 µA

-6 - - µA

--60µA

6--µA

-2.5

-25

7-pF

- 2.5 25

3 µs

10 µs

NOTES:

1. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8 C to 12 C in the temperature range from 50 C to 125 C.

2. Refer to Section A.1.4 Current Injection, for more details

3. Parameter only applies in STOP or Pseudo STOP mode.

Device User Guide — 9S12C128DGV1/D V01.05

A.1.10 Supply Currents

This section describes the current consumption characteristics of the device as well as the conditions for the measurements.

A.1.10.1 Measurement Conditions

All measurements are without output loads. Unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator.

A.1.10.2 Additional Remarks

In expanded modes the currents flowing in the system are highly dependent onthe load atthe address, data and control signals as well as on the duty cycle of those signals. No generally applicable numbers can be given. A very good estimate is to take the single chip currents and add the currents due to the external loads.

Device User Guide — 9S12C128DGV1/D V01.05

Table A-8 Supply Current Characteristics for MC9S12C32

Conditions are shown in Table A-4 with internal regulator enabled unless otherwise noted

Num C Rating Symbol Min Typ Max Unit

1 P Run Supply Current Single Chip

Wait Supply current

P P

VDDR<4.9V, only RTI enabled

VDDR>4.9V, only RTI enabled

Pseudo Stop Current (RTI and COP disabled)

C P C

"C" Temp Option 100˚C

C P

"V" Temp Option 120˚C

C P

"M" Temp Option 140°C

Pseudo Stop Current (RTI and COP enabled)

C C C C

Stop Current

(3)

C P C

"C" Temp Option 100˚C

C P

"V" Temp Option 120˚C

C P

"M" Temp Option 140°C

All modules enabled

(2)

(2)(3)

-40°C 27°C 85°C

105°C 125°C

-40°C 27°C 85°C

105°C 125°C

-40°C 27°C 85°C

105°C 125°C

DD5

DDW

DDPS

DDS

(1)

35 mA

3.5

2.5

340 360

500 550

450

1450

µA 590 720

1900

780

1100

4500

540

700 750

µA 880

1300

10 20

80 100 140

1000

µA 170 300

1400 350 520

4000

NOTES:

1. STOP current measured in production test at increased junction temperature, hence for Temp Option "C" the test is carried out at 100˚C although the Temperature specification is 85˚C. Similarly for "v" and "M" options the temperature used in test lies 15˚C above the temperature option specification.

2. PLL off

3. At those low power dissipation levels T

= TA can be assumed

Device User Guide — 9S12C128DGV1/D V01.05

Table A-9 Supply Current Characteristics for MC9S12C64,MC9S12C96,MC9S12C128

Conditions are shown in Table A-4 with internal regulator enabled unless otherwise noted

Num C Rating Symbol Min Typ Max Unit

1 P Run Supply Current Single Chip,

Wait Supply current

P P C

VDDR<4.9V, only RTI enabled

VDDR>4.9V, only RTI enabled

Pseudo Stop Current (RTI and COP disabled)

C P C

"C" Temp Option 100˚C

C P

"V" Temp Option 120˚C

C P

"M" Temp Option 140°C

Pseudo Stop Current (RTI and COP enabled)

C C C C

Stop Current

(3)

C P C

"C" Temp Option 100˚C

C P

"V" Temp Option 120˚C

C P

"M" Temp Option 140°C

All modules enabled

(2)

(2)(3)

-40°C 27°C 85°C

105°C 125°C

-40°C 27°C 85°C

105°C 125°C

-40°C 27°C 85°C

105°C 125°C

DD5

DDW

DDPS

DDS

(1)

45 mA

2.5

3.5

190 200

300 400

250

1400

µA 450 600

1900

650

1000

4800

370

500 590

µA 780

1200

12 25

100 130 160

1200

µA 200 350

1700 400 600

4500

NOTES:

2. PLL off

3. At those low power dissipation levels T

= TA can be assumed

Device User Guide — 9S12C128DGV1/D V01.05

Appendix B Electrical Specifications

B.1 Voltage Regulator Operating Conditions

Table B-1 Voltage Regulator Electrical Parameters

C Characteristic Symbol Min Typical Max Unit

1 P Input Voltages

Regulator Current

Reduced Power Mode Shutdown Mode

Output Voltage Core

Full Performance Mode

Low Voltage Interrupt Assert Level C32, GC32 Assert Level C64, C96,C128

Deassert Level C32, GC32 Deassert Level C64, C96, C128

Low Voltage Reset Assert Level C32, GC32 Assert Level C64, C96, C128

Low Voltage Reset Deassert Level

GC64, GC128

(2)

VDDR, A

REG

LVIA

LVID

LVRA

LVRD

2.97 — 5.5 V

— —

2.35 2.5 2.75 V

4.30

4.10

4.42

4.25

2.25

——

20 12

4.53

4.37

4.65

4.52

2.3

2.35

50 40

4.77

4.66

4.89

4.77

—V

2.55 V

µA µA

V V V V

NOTES:

1. Monitors V voltage.

2. Monitors V

3. Monitors V

NOTE:

Power-on Reset

Assert Level Deassert Level

, active only in Full Performance Mode. Indicates I/O & ADC performance degradation due to low supply

DDA

, active only in Full Performance Mode. MCU is monitored by the POR in RPM (see Figure B-1)

. Active in all modes.

PORA

PORD

0.97 —

— —

—

2.05

The electrical characteristics given in this section are preliminary and should be used as a guide only. Values in this section cannot be guaranteed by Motorola and are subject to change without notice.

V V

Device User Guide — 9S12C128DGV1/D V01.05

B.2 Chip Power-up and LVI/LVR graphical explanation

Voltage regulator sub modules LVI (low voltage interrupt), POR (power-on reset) and LVR (low voltage reset) handle chip power-up or drops of the supply voltage. Their function is described in Figure B-1.

Figure B-1 Voltage Regulator - Chip Power-up and Voltage Drops (not scaled)

PORD

LVI

POR

LVID

LVIA

LVRD

LVRA

DDA

LVI enabled LVI disabled due to LVR

LVR

B.3 Output Loads

B.3.1 Resistive Loads

The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits allows no external DC loads.

Device User Guide — 9S12C128DGV1/D V01.05

B.3.2 Capacitive Loads

The capacitive loads are specified in Table B-2. Ceramic capacitors with X7R dielectricum are required.

Table B-2 Voltage Regulator - Capacitive Loads

Num Characteristic Symbol Min Typical Max Unit

1 VDD external capacitive load C 2 VDDPLL external capacitive load C

DDext

DDPLLext

400 440 12000 nF

90 220 5000 nF

Device User Guide — 9S12C128DGV1/D V01.05

B.4 ATD Characteristics

This section describes the characteristics of the analog to digital converter. VRL is not available as a separate pin in the 48 and 52 pin versions. In this case the internal VRL pad is

bonded to the VSSA pin. The ATD is specified and tested for both the 3.3V and 5V range. For ranges between 3.3V and 5V the

ATD accuracy is generally the same as in the 3.3V range but is not tested in this range in production test.

B.4.1 ATD Operating Characteristics In 5V Range

The Table B-3 shows conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results:

VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively be clipped.

Table B-3 ATD Operating Characteristics

Conditions are shown in Table A-4 unless otherwise noted. Supply Voltage 5V-10% <= V

<=5V+10%

DDA

Num C Rating Symbol Min Typ Max Unit

Reference Potential

2C 3 D ATD Clock Frequency

5D 6 P Reference Supply current

NOTES:

1. Full accuracy is not guaranteed when differential voltage is less than 4.75V

2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks.

Differential Reference Voltage

ATD 10-Bit Conversion Period

Conv, Time at 2.0MHz ATD Clock f

ATD 8-Bit Conversion Period

Conv, Time at 2.0MHz ATD Clock f

Recovery Time (V

=5.0 Volts)

DDA

Clock Cycles

Low

High

ATDCLK

VRL VRH

VSSA

VDDA/2

VDDA

VRH-VRL 4.75 5.0 5.25 V

ATDCLK

CONV10

REC

REF

0.5 2.0 MHz

28 14

26 13

20 µs

0.375 mA

V V

Cycles

µs

Cycles

µs

B.4.2 ATD Operating Characteristics In 3.3V Range

The Table B-3 shows conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results:

≤ VRL≤ VIN≤ VRH≤ V

SSA

DDA

. This constraint exists since the sample buffer amplifier can not drive

Device User Guide — 9S12C128DGV1/D V01.05

beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively be clipped

Table B-4 ATD Operating Characteristics

Conditions are shown in Table A-4 unless otherwise noted; Supply Voltage 3.3V-10% <= V

<= 3.3V+10%

DDA

Num C Rating Symbol Min Typ Max Unit

Reference Potential

2 C Differential Reference Voltage 3 D ATD Clock Frequency

ATD 10-Bit Conversion Period

Conv, Time at 2.0MHz ATD Clock f

ATD 8-Bit Conversion Period

Conv, Time at 2.0MHz ATD Clock f

6D 7 P Reference Supply current

NOTES:

1. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample

Recovery Time (V

period of 16 ATD clocks.

=3.3 Volts)

DDA

Clock Cycles

Low

High

ATDCLK

(1)

VRH-V

ATDCLK

CONV10

CONV8

REC

REF

DDA

SSA

DDA

3.0 3.3 3.6 V

0.5 2.0 MHz

28 14

26 13

Cycles

20 µs

0.250 mA

V V

µs

B.4.3 Factors influencing accuracy

Three factors - source resistance, source capacitance and current injection - have an influenceon the accuracy of the ATD.

B.4.3.1 Source Resistance:

Due to the input pin leakage current as specified in Table A-6 in conjunction with the source resistance there will be a voltage drop from the signal source to the ATD input. The maximum source resistance R specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage current. If device or operatingconditions are less than worst case orleakage-inducederror is acceptable, larger values of source resistance is allowable.

B.4.3.2 Source capacitance

When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input voltage ≤ 1LSB, then the external filter capacitor, C

≥ 1024 * (C

INS

- C

INN

100

Motorola MC9S12C128, MC9S12GC128, MC9S12C96, MC9S12C64, MC9S12GC64 User Manual

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