MOTOROLA MC92053 Technical data
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Product Brief
MC92053
MC92053
Quad FTTC Network Framer
The MC92053 is a peripheral device composed of four parallel bidirectional TC-sublayer functional units with
UTOPIA Level 2 compliant ATM-layer ports.
MC92053 Features
• Implements the DAVIC short-range baseband asymmetrical physical layer standard
• Interfaces to an ATM-layer device using a multi-PHY UTOPIA Level 2 compliant interface
• Provides an 8-bit system interface as a generic slave device
• IEEE 1149.1 (JTAG) boundary scan test port
• 3.3 V operation with TTL compatibility on I/O pins
• Extended temperature operation: -40 to 85°C
• Available in 208 Pin Plastic Quad Flat Package
Each of the four framers:
• Provides a bit rate of up to 51.84 Mbit/sec downstream
• Controls the TIme Division Multiple Access (TDMA) among up to 4 user devices
• Supports a bit rate of up to 6.48 Mbit/s upstream, including DAVIC Bit Rates B, C, and D
• Includes serial data link interfaces for upstream and downstream frames
• Performs convolutional interleaving of the downstream payload blocks for the full range of interleaving
depths (M = 1-31) using an external 32K x 16 SRAM shared by all four framers
• Performs Reed-Solomon encoding of the downstream frames and decoding of the upstream frames
• Performs ATM cell TC functions, including HEC-based error detection and correction on the upstream data
• Includes serial data interfaces to Physical Media Devices (PMD).
Tx
UTOPIA
I/F
Rx
UTOPIA
I/F
Microprocessor
Interface
Figure 1. MC92053 Block Diagram
This document contains information on a new product.
Specifications and information herein are subject to change without notice.
MOTOROLA, INC. 1997
Framer #0
Framer #1
Framer #2
Framer #3
JTAG Controller
Data
Link
Insertion
Tx Cell
Functions
Frame
Header
Generation
Random-
izer
Random-
izer
Reed-
Solomon
Encoder
Reed-
Solomon
Encoder
Inter-
leaver
Framing
Tx
PMD
I/F
Data
Link
Extraction
Frame
Header
Interpretation
Deran-
domizer
Rx Cell
Functions
Figure 2. Framer Block Diagram
General Description
The MC92053 implements four copies of the TC sublayer of the DAVIC asymmetrical FTTC PHY specification
for network devices. The MC92053 key functional
blocks are described in the paragraphs which follow.
Tx UTOPIA Interface
The Transmit UTOPIA interface accepts ATM cells from
the ATM layer according to the UTOPIA Level 2 specification. Each cell is stored in one of the four transmit
cell FIFO’s. This block uses TXCLK provided by the
ATM layer. The FIFO’s are used for rate adaptation between TXCLK (the UTOPIA interface clock) and the device clock.
Rx UTOPIA Interface
The receive UTOPIA interface reads ATM cells from the
four receive cell FIFO’s and transfers them to the ATM
layer according to the ATM Forum UTOPIA Level 2
specification. This block uses RXCLK provided by the
ATM layer. The FIFO is used for rate adaptation between RXCLK (the UTOPIA interface clock) and the device clock.
Microprocessor Interface
The microprocessor interface is an 8-bit generic slave
interface. It is used for initializing the internal registers
and reading status registers and counters.
Reed-
Solomon
Decoder
Rx
PMD
I/F
JTAG
The MC92053 provides JTAG boundary scan.
Framers
Each of the four framers performs the TC functions for
a single user. The blocks contained in a framer are
shown in Figure 2 and are described in the paragraphs
which follow.
Tx Cell Functions
The transmit cell functions block reads ATM cells from
a transmit cell FIFO. If there are no cells available when
a downstream frame should be transmitted, the cell
functions block generates an idle cell. It calculates the
HEC value based on the ATM header of each cell and
inserts it in the fifth octet of the cell. This block also randomizes the payload of the ATM cells according to
ITU-T Recommendation I.432.
A count of the cells transferred from the transmit cell
FIFO is maintained.
Data Link Insertion Block
The data link insertion block provides direct serial access to the data link bytes of the downstream frame
headers. The data link stream for the downstream
frames is optionally inserted using an output clock pin
and an input data pin. The device ID to which the data
link stream is destined is programmable.
Motorola MC92053
2
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