MOTOROLA MC74VHCT14ADT, MC74VHCT14ADTR2, MC74VHCT14AD, MC74VHCT14ADR2 Datasheet
SEMICONDUCTOR TECHNICAL DATA
The MC74VHCT14A is an advanced high speed CMOS Schmitt inverter
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
Pin configuration and function are the same as the MC74VHCT04A, but
the inputs have hysteresis and, with its Schmitt trigger function, the
VHCT14A can be used as a line receiver which will receive slow input
signals.
The VHCT inputs are compatible with TTL levels. This device can be used
as a level converter for interfacing 3.3V to 5.0V , because it has full 5V CMOS
level output swings.
The VHCT14A input structures provide protection when voltages between
0V and 5.5V are applied, regardless of the supply voltage. The output
structures also provide protection when VCC = 0V. These input and output
structures help prevent device destruction caused by supply voltage –
input/output voltage mismatch, battery backup, hot insertion, etc.
The internal circuit is composed of three stages, including a buffer output
which provides high noise immunity and stable output. The inputs tolerate
voltages up to 7V, allowing the interface of 5V systems to 3V systems.
• High Speed: tPD = 5.5ns (Typ) at VCC = 5V
• Low Power Dissipation: ICC = 2µA (Max) at TA = 25°C
• TTL–Compatible Inputs: VIL = 0.8V; VIH = 2.0V
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2V to 5.5V Operating Range
• Low Noise: V
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
• Chip Complexity: 60 FETs or 15 Equivalent Gates
LOGIC DIAGRAM
1
= 0.8V (Max)
OLP
2
Y1A1
D SUFFIX
14–LEAD SOIC PACKAGE
CASE 751A–03
14–LEAD TSSOP PACKAGE
14–LEAD SOIC EIAJ PACKAGE
MC74VHCTXXAD
MC74VHCTXXADT
MC74VHCTXXAM
DT SUFFIX
CASE 948G–01
M SUFFIX
CASE 965–01
ORDERING INFORMATION
SOIC
TSSOP
SOIC EIAJ
FUNCTION TABLE
Inputs Outputs
A
L
H
Y
H
L
3
A2
5
A3
9
A4
11
A5
13
A6
4/99
Motorola, Inc. 1999
10
12
4
Y2
Pinout: 14–Lead Packages (Top View)
6
Y3
Y = A
8
Y4
Y5
Y6
1
VCCA6 Y6
1314 12 11 10 9 8
21 34567
A1 Y1 A2 Y2 A3 Y3 GND
A5 Y5 A4 Y4
REV 0
MC74VHCT14A
Î
Î
Î
Î
V
CC
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
OH
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
MAXIMUM RATINGS*
Symbol
V
V
I
I
I
Î
T
DC Supply Voltage
CC
V
DC Input Voltage
in
DC Output Voltage
out
I
Input Diode Current
IK
Output Diode Current
OK
DC Output Current, per Pin
out
DC Supply Current, VCC and GND Pins
CC
P
Power Dissipation in Still Air, SOIC Packages†
D
ОООООООООООО
Storage Temperature
stg
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied.
†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
V
V
T
DC Supply Voltage
CC
DC Input Voltage
in
DC Output Voltage
out
Operating Temperature, All Package Types
A
DC ELECTRICAL CHARACTERISTICS
Symbol
V
T+
Î
V
T–
Î
V
H
Î
V
OH
Î
Positive Threshold Voltage
ОООООО
Negative Threshold Voltage
ОООООО
Hysteresis Voltage
ОООООО
Minimum High–Level
Output Voltage
ОООООО
IOH = –50µA
Parameter
Parameter
Parameter
– 0.5 to + 7.0
– 0.5 to + 7.0
– 0.5 to VCC + 0.5
TSSOP Package†
ÎÎÎÎ
– 65 to + 150
V
Test Conditions
V
3.0
ОООООÎÎ
4.5
5.5
3.0
ОООООÎÎ
4.5
6.0
3.0
ОООООÎÎ
VIN = VIH or V
IOH = – 50µA
ООООО
IL
4.5
5.5
2.0
3.0
Î
4.5
Value
– 20
± 20
± 25
± 50
500
450
Min
Max
4.5
5.5
0
5.5
0
V
CC
– 40
+ 85
TA = 25°C
Min
Typ
ÎÎÎÎÎ
0.35
0.5
Î
ÎÎÎÎÎ
0.6
0.30
0.40
Î
Î
0.50
1.9
2.9
4.4
ÎÎÎ
2.0
3.0
Î
4.5
Unit
V
V
V
mA
mA
mA
mA
mW
Î
_
C
Unit
V
V
V
_
C
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
range GND v (Vin or V
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
TA ≤ 85°C
Max
Min
1.7
2.0
ÎÎÎ
2.0
0.35
0.5
0.6
1.20
0.30
1.40
0.40
1.60
Î
0.50
1.9
ÎÎÎ
2.9
4.4
This device contains protection
should be constrained to the
out
Unused inputs must always be
) v VCC.
out
TA ≤ 125°C
Max
1.6
2.0
2.0
Min
Max
1.6
ÎÎÎ
2.0
2.0
0.35
ÎÎÎ
1.20
1.40
Î
1.60
0.5
0.6
0.30
0.40
Î
0.50
ÎÎÎ
1.20
1.40
Î
1.60
1.9
ÎÎÎ
2.9
ÎÎÎ
4.4
Unit
V
Î
V
V
Î
V
Î
Î
V
Î
Î
ÎÎООООООÎООООО
I
Î
I
CCT
I
OPD
MOTOROLA VHC Data – Advanced CMOS Logic
ОООООО
ОООООО
Maximum Low–Level
OL
ОООООО
Output Voltage
ОООООО
I
Maximum Input Leakage
IN
Current
Maximum Quiescent Supply
CC
ОООООО
Current
Quiescent Supply Current
Output Leakage Current
ООООО
IOH = – 4mA
IOH = – 8mA
ООООО
VIN = VIH or V
ООООО
IOL = 50µA
ООООО
IOL = 4mA
IOL = 8mA
VIN = 5.5V or GND
VIN = VCC or GND
ООООО
Input: VIN = 3.4V
V
= 5.5V
OUT
Î
Î
IL
Î
Î
Î
0 to 5.5
Î
Î
4.5
5.5
2.0
3.0
4.5
2.58
3.94
Î
Î
Î
4.5
5.5
ÎÎÎÎÎ
5.5
ÎÎÎÎÎ
5.5
0.0
Î
Î
0.0
Î
0.0
0.0
Î
Î
Î
0.1
Î
0.1
0.1
Î
0.36
0.36
± 0.1
2.0
1.35
0.5
Î
2.48
3.80
Î
Î
Î
Î
Î
0.1
Î
0.1
0.1
Î
0.44
0.44
ÎÎÎ
± 1.0
20
ÎÎÎ
1.50
5.0
Î
2.34
3.66
Î
Î
Î
Î
Î
0.1
Î
0.1
0.1
Î
0.52
0.52
ÎÎÎ
± 1.0
40εA
ÎÎÎ
1.65
10
V
µA
mA
µA
Î
Î
Î
Î
Î
2
DL203 — Rev 1
MC74VHCT14A
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
AC ELECTRICAL CHARACTERISTICS (Input t
Symbol
t
,
PLH
t
Î
ÎÎООООООÎООООООО
C
Î
Maximum Propagation
Delay, A to Y
ОООООО
PHL
Maximum Input
IN
ОООООО
Capacitance
Parameter
VCC = 3.3 ± 0.3 V CL = 15pF
ООООООО
VCC = 5.0 ± 0.5 V CL = 15pF
ОООООООÎÎÎÎ
= tf = 3.0ns)
r
Test Conditions
CL = 50pF
CL = 50pF
TA = 25°C
Min
Typ
8.3
ÎÎÎ
10.8
5.5
ÎÎÎ
7.0
4
Max
12.8
16.3
Î
8.6
10.6
Î
10
Î
TA ≤ 85°C
Min
Max
1.0
15.0
1.0
18.5
Î
Î
ÎÎÎ
1.0
1.0
Î
10.0
12.0
Î
10
TA ≤ 125°C
Min
Max
1.0
17.0
1.0
20.5
Î
1.0
1.0
Î
ÎÎÎ
Î
11.5
13.5
Î
10ÎpF
Unit
ns
Î
Î
Typical @ 25°C, VCC = 5.0 V
C
Power Dissipation Capacitance (Note 1.)
PD
21
pF
1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
dynamic power consumption; PD = CPD V
NOISE CHARACTERISTICS (Input t
= tf = 3.0ns, CL = 50pF, VCC = 5.0 V)
r
CC
2
CC(OPR
fin + ICC VCC.
= CPD VCC fin + ICC/6 (per buffer). CPD is used to determine the no–load
)
TA = 25°C
Symbol Characteristic
V
V
V
V
OLP
OLV
IHD
ILD
Quiet Output Maximum Dynamic V
Quiet Output Minimum Dynamic V
OL
OL
Minimum High Level Dynamic Input Voltage 3.5 V
Maximum Low Level Dynamic Input Voltage 1.5 V
3.0V
1.5V
A
GND
t
PLH
Y
1.5V
t
PHL
V
OH
V
OL
DEVICE
UNDER
TEST
Typ Max
0.4 0.8 V
– 0.4 – 0.8 V
TEST POINT
OUTPUT
CL*
Unit
Figure 1. Switching Waveforms
(a) A Schmitt–Trigger Squares Up Inputs With Slow Rise and Fall Times (b) A Schmitt–Trigger Offers Maximum Noise Immunity
V
H
V
in
V
out
VHC Data – Advanced CMOS Logic
DL203 — Rev 1
*Includes all probe and jig capacitance
V
CC
V
T+
V
T–
V
H
V
in
GND
V
OH
V
out
V
OL
Figure 3. T ypical Schmitt–Trigger Applications
3 MOTOROLA
Figure 2. T est Circuit
V
CC
V
T+
V
T–
GND
V
OH
V
OL
Loading...