Datasheet MC74VHC595ML2, MC74VHC595M, MC74VHC595D, MC74VHC595DR2, MC74VHC595DT Datasheet (MOTOROLA)



SEMICONDUCTOR TECHNICAL DATA

1

REV 1

 Motorola, Inc. 1997

6/97

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  

The MC74VHC595 is an advanced high speed 8–bit shift register with an

output storage register fabricated with silicon gate CMOS technology.

It achieves high speed operation similar to equivalent Bipolar Schottky

TTL while maintaining CMOS low power dissipation.

The MC74VHC595 contains an 8–bit static shift register which feeds an

8–bit storage register.

Shift operation is accomplished on the positive going transition of the Shift
Clock input (SCK). The output register is loaded with the contents of the shift
register on the positive going transition of the Register Clock input (RCK).
Since the RCK and SCK signals are independent, parallel outputs can be
held stable during the shift operation. And, since the parallel outputs are
3–state, the VHC595 can be directly connected to an 8–bit bus. This register
can be used in serial–to–parallel conversion, data receivers, etc.

The internal circuit is composed of three stages, including a buffer output
which provides high noise immunity and stable output. The inputs tolerate
voltages up to 7V, allowing the interface of 5V systems to 3V systems.

• High Speed: f

max

= 185MHz (Typ) at VCC = 5V

• Low Power Dissipation: ICC = 4µA (Max) at TA = 25°C

• High Noise Immunity: V

NIH

= V

NIL

= 28% V

CC

• Power Down Protection Provided on Inputs

• Balanced Propagation Delays

• Designed for 2V to 5.5V Operating Range

• Low Noise: V

OLP

= 1.0V (Max)

• Pin and Function Compatible with Other Standard Logic Families

• Latchup Performance Exceeds 300mA

• ESD Performance: HBM > 2000V; Machine Model > 200V

• Chip Complexity: 328 FETs or 82 Equivalent Gates

LOGIC DIAGRAM

SERIAL

DATA

INPUT

14

11

10

12
13

SCK

SCLR

RCK

OE

SHIFT

REGISTER

STORAGE

REGISTER

15

1
2
3

4
5
6
7

9

QA
QB

QC
QD
QE
QF
QG
QH

SQH

SI

PARALLEL
DATA
OUTPUTS

SERIAL
DATA
OUTPUT



PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

RCK

OE

SI

QA

VCC

SQH

SCLR

SCK

QE

QD

QC

QB

GND

QH

QG

QF

D SUFFIX

16–LEAD SOIC PACKAGE

CASE 751B–05

DT SUFFIX

16–LEAD TSSOP PACKAGE

CASE 948F–01

ORDERING INFORMATION

MC74VHCXXXD
MC74VHCXXXDT
MC74VHCXXXM

SOIC
TSSOP
SOIC EIAJ

M SUFFIX

16–LEAD SOIC EIAJ PACKAGE

CASE 966–01

MC74VHC595

MOTOROLA VHC Data – Advanced CMOS Logic

DL203 — Rev 1

2

FUNCTION TABLE

Inputs Resulting Function

Operation

Reset

(SCLR

)

Serial

Input

(SI)

Shift
Clock
(SCK)

Reg
Clock
(RCK)

Output
Enable

(OE

)

Shift

Register

Contents

Storage
Register

Contents

Serial

Output

(SQH)

Parallel

Outputs

(QA – QH)

Clear shift register L X X L, H, ↓ L L U L U
Shift data into shift register H D ↑ L, H, ↓ L D→SRA;

SRN→SR

N+1

U SRG→SR

H

U

Registers remains
unchanged

H X L, H, ↓ X L U ** U **

Transfer shift register
contents to storage register

H X L, H, ↓ ↑ L U SRN³

STR

N

* SR

N

Storage register remains
unachanged

X X X L, H, ↓ L * U * U

Enable parallel outputs X X X X L * ** * Enabled
Force outputs into high

impedance state

X X X X H * ** * Z

SR = shift register contents D = data (L, H) logic level ↓ = High–to–Low * = depends on Reset and Shift Clock inputs
STR = storage register contents U = remains unchanged ↑ = Low–to–High ** = depends on Register Clock input

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage

– 0.5 to + 7.0

V

V

in

DC Input Voltage

– 0.5 to + 7.0

V

V

out

DC Output Voltage

– 0.5 to VCC + 0.5

V

I

IK

Input Diode Current

– 20

mA

I

OK

Output Diode Current

± 20

mA

I

out

DC Output Current, per Pin

± 25

mA

I

CC

DC Supply Current, VCC and GND Pins

± 50

mA

Î

Î

P

D

ОООООООООООО

Î

Power Dissipation in Still Air, SOIC Packages†

TSSOP Package†

ÎÎÎÎ

Î

500
450

Î

Î

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

* Absolute maximum continuous ratings are those values beyond which damage to the device

may occur. Exposure to these conditions or conditions beyond those indicated may adversely
affect device reliability . Functional operation under absolute–maximum–rated conditions is not
implied.

†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C

TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Unit

V

CC

DC Supply Voltage

2.0

5.5

V

V

in

DC Input Voltage

0

5.5

V

V

out

DC Output Voltage

0

V

CC

V

T

A

Operating Temperature, All Package Types

– 40

+ 85

_

C

tr, t

f

Input Rise and Fall Time VCC = 3.3V ±0.3V

VCC =5.0V ±0.5V00

10020ns/V

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir­cuit. For proper operation, Vin and
V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

MC74VHC595

VHC Data – Advanced CMOS Logic
DL203 — Rev 1

3 MOTOROLA

DC ELECTRICAL CHARACTERISTICS

ÎÎÎ

V

TA = 25°C

TA = – 40 to 85°C

Symbol

Parameter

Test Conditions

ÎÎÎ

V

CC

V

Min

Typ

Max

Min

Max

Unit

ÎÎ

Î

ÎÎ

Î

V

IH

ÎÎÎÎ

Î

ÎÎÎÎ

Î

Minimum High–Level
Input Voltage

ОООООО

Î

ОООООО

Î

ÎÎÎ

ÎÎ

Î

ÎÎ

Î

2.0

3.0 to

5.5

ÎÎ

Î

ÎÎ

Î

1.50

VCC x 0.7

Î

Î

Î

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

1.50

VCC x 0.7

ÎÎ

Î

ÎÎ

Î

V

ÎÎ

Î

ÎÎ

Î

V

IL

ÎÎÎÎ

Î

ÎÎÎÎ

Î

Maximum Low–Level
Input Voltage

ОООООО

Î

ОООООО

Î

ÎÎÎ

ÎÎ

Î

ÎÎ

Î

2.0

3.0 to

5.5

ÎÎ

Î

ÎÎ

Î

Î

Î

Î

Î

ÎÎ

Î

ÎÎ

Î

0.50

VCC x 0.3

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

0.50

VCC x 0.3

V

ÎÎ

Î

V

OH

ÎÎÎÎ

Î

Minimum High–Level
Output Voltage

ОООООО

Î

Vin = VIH or V

IL

IOH = – 50µA

ÎÎÎ

ÎÎ

Î

2.0

3.0

4.5

ÎÎ

Î

1.9

2.9

4.4

Î

Î

2.0

3.0

4.5

ÎÎÎÎÎ

Î

1.9

2.9

4.4

ÎÎ

Î

V

ÎÎ

Î

ÎÎ

ÎÎÎÎ

Î

ÎÎÎÎ

ОООООО

Î

ОООООО

Vin = VIH or V

IL

IOH = – 4mA
IOH = – 8mA

ÎÎÎ

ÎÎ

Î

ÎÎ

3.0

4.5

ÎÎ

Î

ÎÎ

2.58

3.94

Î

Î

Î

ÎÎ

Î

ÎÎ

ÎÎ

Î

ÎÎ

2.48

3.80

ÎÎ

Î

ÎÎ

ÎÎ

Î

ÎÎ

Î

V

OL

ÎÎÎÎ

Î

ÎÎÎÎ

Î

Maximum Low–Level
Output Voltage

ОООООО

Î

ОООООО

Î

Vin = VIH or V

IL

IOL = 50µA

ÎÎÎ

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

ÎÎ

Î

ÎÎ

Î

Î

Î

Î

Î

0.0

0.0

0.0

ÎÎ

Î

ÎÎ

Î

0.1

0.1

0.1

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

0.1

0.1

0.1

V

ÎÎÎÎÎÎÎÎОООООО

Î

Vin = VIH or V

IL

IOL = 4mA
IOL = 8mA

ÎÎÎ

ÎÎ

Î

3.0

4.5

ÎÎÎÎÎÎÎ

Î

0.36

0.36

ÎÎÎÎÎ

Î

0.44

0.44

ÎÎ

Î

I

OZ

ÎÎÎÎ

Î

Three–State Output
Off–State Current

ОООООО

Î

Vin = VIH or V

IL

V

out

= VCC or GND

ÎÎÎ

ÎÎ

Î

5.5

ÎÎÎÎÎÎÎ

Î

± 0.25

ÎÎÎÎÎ

Î

± 2.50

µA

ÎÎ

I

in

ÎÎÎÎ

Maximum Input
Leakage Current

ОООООО

Vin = 5.5V or GND

ÎÎÎ

ÎÎ

0 to 5.5

ÎÎ

Î

ÎÎ

± 0.1

ÎÎ

ÎÎ

± 1.0

µA

ÎÎ

Î

I

CC

ÎÎÎÎ

Î

Maximum Quiescent
Supply Current

ОООООО

Î

Vin = VCC or GND

ÎÎÎ

ÎÎ

Î

5.5

ÎÎÎÎÎÎÎ

Î

4.0

ÎÎÎÎÎ

Î

40.0

µA

AC ELECTRICAL CHARACTERISTICS (Input t

r

= tf = 3.0 ns)

TA = 25°C

TA = – 40 to 85°C

Symbol

Parameter

Test Conditions

Min

Typ

Max

Min

Max

Unit

ÎÎ

f

max

ОООООО

Maximum Clock Frequency
(50% Duty Cycle)

ООООООО

VCC = 3.3 ± 0.3V CL = 15pF
RL = 1kΩ CL = 50pF

ÎÎ

80
55

Î

150
130

ÎÎ

Î

70
50

ÎÎ

MHz

ÎÎÎООООООÎООООООО

Î

VCC = 5.0 ± 0.5V CL = 15pF
RL = 1kΩ CL = 50pF

ÎÎ

Î

135

95

Î

Î

185
155

ÎÎÎÎ

Î

115

85

ÎÎ

Î

ÎÎ

Î

t

PLH

,

t

PHL

ОООООО

Î

Propagation Delay,
SCK to SQH

ООООООО

Î

VCC = 3.3 ± 0.3V CL = 15pF

CL = 50pF

ÎÎÎÎ

Î

8.8

11.3

ÎÎ

Î

13.0

16.5

Î

Î

1.0

1.0

ÎÎ

Î

15.0

18.5

ns

ÎÎÎООООООÎООООООО

Î

VCC = 5.0 ± 0.5V CL = 15pF

CL = 50pF

ÎÎÎÎ

Î

6.2

7.7

ÎÎ

Î

8.2

10.2

Î

Î

1.0

1.0

ÎÎ

Î

9.4

11.4

ÎÎ

Î

t

PHL

ОООООО

Î

Propagation Delay,
SCLR

to SQH

ООООООО

Î

VCC = 3.3 ± 0.3V CL = 15pF

CL = 50pF

ÎÎÎÎ

Î

8.4

10.9

ÎÎ

Î

12.8

16.3

Î

Î

1.0

1.0

ÎÎ

Î

13.7

17.2

ns

ÎÎÎООООООÎООООООО

Î

VCC = 5.0 ± 0.5V CL = 15pF

CL = 50pF

ÎÎÎÎ

Î

5.9

7.4

ÎÎ

Î

8.0

10.0

Î

Î

1.0

1.0

ÎÎ

Î

9.1

11.1

ÎÎ

Î

t

PLH

,

t

PHL

ОООООО

Î

Propagation Delay,
RCK to QA – QH

ООООООО

Î

VCC = 3.3 ± 0.3V CL = 15pF

CL = 50pF

ÎÎÎÎ

Î

7.7

10.2

ÎÎ

Î

11.9

15.4

Î

Î

1.0

1.0

ÎÎ

Î

13.5

17.0

ns

VCC = 5.0 ± 0.5V CL = 15pF

CL = 50pF

5.4

6.9

7.4

9.4

1.0

1.0

8.5

10.5

ÎÎ

Î

t

PZL

,

t

PZH

ОООООО

Î

Output Enable Time,
OE

to QA – QH

ООООООО

Î

VCC = 3.3 ± 0.3V CL = 15pF
RL = 1kΩ CL = 50pF

ÎÎÎÎ

Î

7.5

9.0

ÎÎ

Î

11.5

15.0

Î

Î

1.0

1.0

ÎÎ

Î

13.5

17.0

ns

ÎÎÎООООООÎООООООО

Î

VCC = 5.0 ± 0.5V CL = 15pF
RL = 1kΩ CL = 50pF

ÎÎÎÎ

Î

4.8

8.3

ÎÎ

Î

8.6

10.6

Î

Î

1.0

1.0

ÎÎ

Î

10.0

12.0

MC74VHC595

MOTOROLA VHC Data – Advanced CMOS Logic

DL203 — Rev 1

4

AC ELECTRICAL CHARACTERISTICS (Input t

r

= tf = 3.0 ns)

Unit

TA = – 40 to 85°C

TA = 25°C

Test Conditions

Parameter

Symbol

Unit

Max

Min

Max

Typ

Min

Test Conditions

Parameter

Symbol

ÎÎ

Î

t

PLZ

,

t

PHZ

ОООООО

Î

Output Disable Time,
OE

to QA – QH

ООООООО

Î

VCC = 3.3 ± 0.3V CL = 50pF
RL = 1kΩ

ÎÎÎÎ

Î

12.1

ÎÎ

Î

15.7

Î

Î

1.0

ÎÎ

Î

16.2

ns

ÎÎÎООООООÎООООООО

Î

VCC = 5.0 ± 0.5V CL = 50pF
RL = 1kΩ

ÎÎÎÎ

Î

7.6

ÎÎ

Î

10.3

Î

Î

1.0

ÎÎ

Î

11.0

ÎÎ

Î

C

in

ОООООО

Î

Input Capacitance

ОООООООÎÎÎÎÎ

Î

4

ÎÎ

Î

10

ÎÎÎÎ

Î

10

pF

ÎÎ

Î

ÎÎ

Î

C

out

ОООООО

Î

ОООООО

Î

Three–State Output
Capacitance (Output in High–
Impedance State), QA – QH

ООООООО

Î

ООООООО

Î

ÎÎ

Î

ÎÎ

Î

Î

Î

Î

Î

6

ÎÎ

Î

ÎÎ

Î

Î

Î

Î

Î

ÎÎ

Î

ÎÎ

Î

10

Typical @ 25°C, VCC = 5.0V

C

PD

Power Dissipation Capacitance (Note 1.)

87

pF

1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I

CC(OPR

)

= CPD  VCC  fin + ICC. CPD is used to determine the no–load dynamic

power consumption; PD = CPD  V

CC

2

 fin + ICC  VCC.

NOISE CHARACTERISTICS (Input t

r

= tf = 3.0ns, CL = 50pF, VCC = 5.0V)

TA = 25°C

Symbol Characteristic

Typ Max

Unit

V

OLP

Quiet Output Maximum Dynamic V

OL

0.8 1.0 V

V

OLV

Quiet Output Minimum Dynamic V

OL

– 0.8 – 1.0 V

V

IHD

Minimum High Level Dynamic Input Voltage 3.5 V

V

ILD

Maximum Low Level Dynamic Input Voltage 1.5 V

TIMING REQUIREMENTS (Input t

r

= tf = 3.0ns)

V

TA = 25_C

ÎÎÎÎ

TA = – 40 to

85°C

Symbol

Parameter

V

CC

V

Typ

Limit

ÎÎÎÎ

Limit

Unit

ÎÎ

Î

t

su

ООООООООООООО

Î

Setup Time, SI to SCK

Î

Î

3.3

5.0

ÎÎÎÎÎÎÎ

Î

3.5

3.0

ÎÎÎÎ

ÎÎÎ

Î

3.5

3.0

Î

Î

ns

ÎÎ

Î

t

su(H)

ООООООООООООО

Î

Setup Time, SCK to RCK

Î

Î

3.3

5.0

ÎÎÎÎÎÎÎ

Î

8.0

5.0

ÎÎÎÎ

ÎÎÎ

Î

8.5

5.0

Î

Î

ns

ÎÎ

Î

t

su(L)

ООООООООООООО

Î

Setup Time, SCLR to RCK

Î

Î

3.3

5.0

ÎÎÎÎÎÎÎ

Î

8.0

5.0

ÎÎÎÎ

ÎÎÎ

Î

9.0

5.0

Î

Î

ns

ÎÎ

Î

t

h

ООООООООООООО

Î

Hold Time, SI to SCK

Î

Î

3.3

5.0

ÎÎÎÎÎÎÎ

Î

1.5

2.0

ÎÎÎÎ

ÎÎÎ

Î

1.5

2.0

Î

Î

ns

t

h(L)

Hold Time, SCLR to RCK

3.3

5.0

0
0

ÎÎÎÎ

0
0

ns

ÎÎ

Î

t

rec

ООООООООООООО

Î

Recovery Time, SCLR to SCK

Î

Î

3.3

5.0

ÎÎÎÎÎÎÎ

Î

3.0

2.5

ÎÎÎÎ

ÎÎÎ

Î

3.0

2.5

Î

Î

ns

ÎÎ

Î

t

w

ООООООООООООО

Î

Pulse Width, SCK or RCK

Î

Î

3.3

5.0

ÎÎÎÎÎÎÎ

Î

5.0

5.0

ÎÎÎÎ

ÎÎÎ

Î

5.0

5.0

Î

Î

ns

t

w(L)

Pulse Width, SCLR

3.3

5.0

5.0

5.0

ÎÎÎÎ

5.0

5.0

ns

MC74VHC595

VHC Data – Advanced CMOS Logic
DL203 — Rev 1

5 MOTOROLA

SCK

SQH

V

CC

GND

50%

50% V

CC

t

PLH

t

PHL

t

w

1/f

max

SCLR

SQH

SCK

t

w

50%

50% V

CC

50%

V

CC

GND

V

CC

GND

t

PHL

t

rec

Figure 1. Figure 2.

SWITCHING W AVEFORMS

RCK

QA–QH

50%

t

PLHtPHL

V

CC

GND

Figure 3.

Figure 4.

QA–QH

QA–QH

50%

50% V

CC

t

PZL

t

PLZ

t

PZHtPHZ

V

CC

GND
HIGH

IMPEDANCE

VOL +0.3V
VOH –0.3V

HIGH
IMPEDANCE

OE

50% V

CC

SI

50%

50%

SCK or RCK

V

CC

GND

VALID

t

su

t

h

Figure 5.

t

su(H)

50%

50%

V

CC

GND

V

CC

GND

SCK

RCK

V

CC

GND

t

w

Figure 6.

TEST CIRCUITS

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE
UNDER

TEST

OUTPUT

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE
UNDER

TEST

OUTPUT

CONNECT TO VCC WHEN
TESTING t

PLZ

AND t

PZL

.
CONNECT TO GND WHEN
TESTING t

PHZ

AND t

PZH

.

1 k

Ω

Figure 7. Figure 8.

50% V

CC

SCLR 50%

V

CC

GND

MC74VHC595

MOTOROLA VHC Data – Advanced CMOS Logic

DL203 — Rev 1

6

DRQ

SRA

DQ

STRA

D

Q

SRB

DQ

STRB

R

D

Q

SRC

DQ

STRC

R

D

Q

SRD

DQ

STRD

R

D

Q

SRE

DQ

STRE

R

D

Q

SRF

DQ

STRF

R

D

Q

SRG

DQ

STRG

R

D

Q

SRH

DQ

STRH

R

EXPANDED LOGIC DIAGRAM

OE

RCK

SI

SCK

SCLR

13

12

14

11

10

15

1

2

3

4

5

6

7

9

QA

QB

QC

QD

QE

QF

QG

QH

SQH

PARALLEL
DATA
OUTPUTS

MC74VHC595

VHC Data – Advanced CMOS Logic
DL203 — Rev 1

7 MOTOROLA

TIMING DIAGRAM

SCK

SI

SCLR

RCK

OE

QA

QB

QC

QD

QE

QF

QG

QH

SQH

NOTE: output is in a high–impedance state.

INPUT EQUIVALENT CIRCUIT

INPUT

MC74VHC595

MOTOROLA VHC Data – Advanced CMOS Logic

DL203 — Rev 1

8

OUTLINE DIMENSIONS

0.25 (0.010) T B A

M

S S

MIN MINMAX MAX

MILLIMETERS INCHES

DIM

A
B
C
D
F
G

J
K
M
P
R

9.80

3.80

1.35

0.35

0.40

0.19

0.10
0

°

5.80

0.25

10.00

4.00

1.75

0.49

1.25

0.25

0.25
7

°

6.20

0.50

0.386

0.150

0.054

0.014

0.016

0.008

0.004
0

°

0.229

0.010

0.393

0.157

0.068

0.019

0.049

0.009

0.009
7

°

0.244

0.019

1.27 BSC 0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

1

8

916

–A

–

–B

–

D 16 PL

K

C

G

–T

–

SEATING

PLANE

R X 45°

M

J

F

P 8 PL

0.25 (0.010) B

M M

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948F–01

ISSUE O

ÇÇ

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.18 0.28 0.007 0.011
J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC

M 0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MA TERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.

____

SECTION N–N

SEATING
PLANE

IDENT.

PIN 1

1

8

16

9

DETAIL E

J

J1

B

C

D

A

K

K1

H

G

DETAIL E

F

M

L

2X L/2

–U–

S

U0.15 (0.006) T

S

U0.15 (0.006) T

S

U

M

0.10 (0.004) V

S

T

0.10 (0.004)

–T–

–V–

–W–

0.25 (0.010)

16X REFK

N

N

MC74VHC595

VHC Data – Advanced CMOS Logic
DL203 — Rev 1

9 MOTOROLA

OUTLINE DIMENSIONS

M SUFFIX

PLASTIC SOIC EIAJ PACKAGE

CASE 966–01

ISSUE O

H

E

A

1

DIM MIN MAX MIN MAX

INCHES

––– 2.05 ––– 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.18 0.27 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059
0

0.70 0.90 0.028 0.035

––– 0.78 ––– 0.031

A

1

H

E

Q

1

L

E

_

10

_

0

_

10

_

L

E

Q

1

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MA TERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).

M

L

DETAIL P

VIEW P

c

A

b

e

M

0.13 (0.005)

0.10 (0.004)

1

16 9

8

D

Z

E

A

b

c
D
E

e

L

M

Z

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
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Mfax is a trademark of Motorola, Inc.

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MC74VHC595/D

◊