Datasheet MC74VHC541M, MC74VHC541DTR2, MC74VHC541DW, MC74VHC541ML2, MC74VHC541MEL Datasheet (MOTOROLA)
...
SEMICONDUCTOR TECHNICAL DATA
1
REV 2
Motorola, Inc. 1998
4/98
The MC74VHC541 is an advanced high speed CMOS octal bus buffer
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
The MC74VHC541 is a noninverting type. When either OE1
or OE2 are
high, the terminal outputs are in the high impedance state.
The internal circuit is composed of three stages, including a buffer output
which provides high noise immunity and stable output. The inputs tolerate
voltages up to 7V, allowing the interface of 5V systems to 3V systems.
• High Speed: tPD = 3.7ns (Typ) at VCC = 5V
• Low Power Dissipation: ICC = 4µA (Max) at TA = 25°C
• High Noise Immunity: V
NIH
= V
NIL
= 28% V
CC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2V to 5.5V Operating Range
• Low Noise: V
OLP
= 1.2V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
• Chip Complexity: 134 FETs or 33.5 Equivalent Gates
18
Y1
2
A1
17
Y2
3
A2
16
Y3
4
A3
15
Y4
5
A4
14
Y5
6
A5
13
Y6
7
A6
12
Y7
8
A7
11
Y8
9
A8
OE1
OE2
1
19
OUTPUT
ENABLES
DATA
INPUTS
NONINVERTING
OUTPUTS
LOGIC DIAGRAM
L
L
H
X
L
L
X
H
L
H
X
X
FUNCTION TABLE
Inputs
Output Y
OE1 OE2 A
L
H
Z
Z
PIN ASSIGNMENT
A5
A3
A2
A1
OE1
GND
A8
A7
A6
A4 5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
Y3
Y2
Y1
OE2
V
CC
Y8
Y7
Y6
Y5
Y4
DW SUFFIX
20–LEAD SOIC WIDE PACKAGE
CASE 751D–04
ORDERING INFORMATION
MC74VHCXXXDW
MC74VHCXXXDT
MC74VHCXXXM
SOIC WIDE
TSSOP
SOIC EIAJ
DT SUFFIX
20–LEAD TSSOP PACKAGE
CASE 948E–02
M SUFFIX
20–LEAD SOIC EIAJ PACKAGE
CASE 967–01
MC74VHC541
MOTOROLA VHC Data – Advanced CMOS Logic
DL203 — Rev 2
2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage
– 0.5 to + 7.0
V
V
in
DC Input Voltage
– 0.5 to + 7.0
V
V
out
DC Output Voltage
– 0.5 to VCC + 0.5
V
I
IK
Input Diode Current
– 20
mA
I
OK
Output Diode Current
± 20
mA
I
out
DC Output Current, per Pin
± 25
mA
I
CC
DC Supply Current, VCC and GND Pins
± 50
mA
Î
Î
P
D
ОООООООООООО
Î
Power Dissipation in Still Air, SOIC Packages†
TSSOP Package†
ÎÎÎÎ
Î
500
450
Î
Î
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
* Absolute maximum continuous ratings are those values beyond which damage to the device
may occur. Exposure to these conditions or conditions beyond those indicated may adversely
affect device reliability . Functional operation under absolute–maximum–rated conditions is not
implied.
†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage
2.0
5.5
V
V
in
DC Input Voltage
0
5.5
V
V
out
DC Output Voltage
0
V
CC
V
T
A
Operating Temperature, All Package Types
– 40
+ 85
_
C
tr, t
f
Input Rise and Fall Time VCC = 3.3V ±0.3V
VCC =5.0V ±0.5V00
10020ns/V
DC ELECTRICAL CHARACTERISTICS
ÎÎÎ
V
TA = 25°C
TA = – 40 to 85°C
Symbol
Parameter
Test Conditions
ÎÎÎ
V
CC
V
Min
Typ
Max
Min
Max
Unit
ÎÎ
Î
V
IH
ÎÎÎÎ
Î
Minimum High–Level
Input Voltage
ОООООО
Î
ÎÎÎ
ÎÎ
Î
2.0
3.0 to
5.5
ÎÎ
Î
1.50
VCC x 0.7
ÎÎÎÎÎÎÎ
Î
1.50
VCC x 0.7
ÎÎ
Î
V
ÎÎ
Î
ÎÎ
Î
V
IL
ÎÎÎÎ
Î
ÎÎÎÎ
Î
Maximum Low–Level
Input Voltage
ОООООО
Î
ОООООО
Î
ÎÎÎ
ÎÎ
Î
ÎÎ
Î
2.0
3.0 to
5.5
ÎÎ
Î
ÎÎ
Î
Î
Î
Î
Î
ÎÎ
Î
ÎÎ
Î
0.50
VCC x 0.3
ÎÎ
Î
ÎÎ
Î
ÎÎ
Î
ÎÎ
Î
0.50
VCC x 0.3
V
ÎÎ
Î
ÎÎ
Î
V
OH
ÎÎÎÎ
Î
ÎÎÎÎ
Î
Minimum High–Level
Output Voltage
ОООООО
Î
ОООООО
Î
Vin = VIH or V
IL
IOH = – 50µA
ÎÎÎ
ÎÎ
Î
ÎÎ
Î
2.0
3.0
4.5
ÎÎ
Î
ÎÎ
Î
1.9
2.9
4.4
Î
Î
Î
Î
2.0
3.0
4.5
ÎÎ
Î
ÎÎ
Î
ÎÎ
Î
ÎÎ
Î
1.9
2.9
4.4
ÎÎ
Î
ÎÎ
Î
V
ÎÎÎÎÎÎÎÎОООООО
Î
Vin = VIH or V
IL
IOH = – 4mA
IOH = – 8mA
ÎÎÎ
ÎÎ
Î
3.0
4.5
ÎÎ
Î
2.58
3.94
ÎÎÎÎÎÎÎ
Î
2.48
3.80
ÎÎ
Î
ÎÎ
Î
ÎÎ
V
OL
ÎÎÎÎ
Î
ÎÎÎÎ
Maximum Low–Level
Output Voltage
ОООООО
Î
ОООООО
Vin = VIH or V
IL
IOL = 50µA
ÎÎÎ
ÎÎ
Î
ÎÎ
2.0
3.0
4.5
ÎÎ
Î
ÎÎ
Î
Î
Î
0.0
0.0
0.0
ÎÎ
Î
ÎÎ
0.1
0.1
0.1
ÎÎ
Î
ÎÎ
ÎÎ
Î
ÎÎ
0.1
0.1
0.1
V
ÎÎ
Î
ÎÎ
Î
ÎÎÎÎ
Î
ÎÎÎÎ
Î
ОООООО
Î
ОООООО
Î
Vin = VIH or V
IL
IOL = 4mA
IOL = 8mA
ÎÎÎ
ÎÎ
Î
ÎÎ
Î
3.0
4.5
ÎÎ
Î
ÎÎ
Î
Î
Î
Î
Î
ÎÎ
Î
ÎÎ
Î
0.36
0.36
ÎÎ
Î
ÎÎ
Î
ÎÎ
Î
ÎÎ
Î
0.44
0.44
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC74VHC541
VHC Data – Advanced CMOS Logic
DL203 — Rev 2
3 MOTOROLA
DC ELECTRICAL CHARACTERISTICS
Unit
TA = – 40 to 85°C
TA = 25°C
ÎÎÎ
V
CC
V
Test Conditions
Parameter
Symbol
Unit
Max
Min
Max
Typ
Min
ÎÎÎ
V
CC
V
Test Conditions
Parameter
Symbol
ÎÎ
Î
I
in
ÎÎÎÎ
Î
Maximum Input
Leakage Current
ОООООО
Î
Vin = 5.5V or GND
ÎÎÎ
ÎÎ
Î
0 to 5.5
ÎÎÎÎÎÎÎ
Î
± 0.1
ÎÎÎÎÎ
Î
± 1.0
µA
ÎÎ
Î
I
OZ
ÎÎÎÎ
Î
Maximum Three–State
Leakage Current
ОООООО
Î
Vin = VIL or V
IH
V
out
= VCC or GND
ÎÎÎ
ÎÎ
Î
5.5
ÎÎÎÎÎÎÎ
Î
± 0.25
ÎÎÎÎÎ
Î
± 2.5
µA
I
CC
Maximum Quiescent
Supply Current
Vin = VCC or GND
ÎÎÎ
5.5
4.0
40.0
µA
AC ELECTRICAL CHARACTERISTICS (Input t
r
= tf = 3.0ns)
TA = 25°C
TA = – 40 to 85°C
Symbol
Parameter
Test Conditions
Min
Typ
Max
Min
Max
Unit
ÎÎ
Î
t
PLH
,
t
PHL
ОООООО
Î
Maximum Propagation Delay,
A to Y
ООООООО
Î
VCC = 3.3 ± 0.3V CL = 15pF
CL = 50pF
ÎÎÎÎ
Î
5.0
7.5
ÎÎ
Î
7.0
10.5
Î
Î
1.0
1.0
ÎÎ
Î
8.5
12.0
ns
VCC = 5.0 ± 0.5V CL = 15pF
CL = 50pF
3.5
5.0
5.0
7.0
1.0
1.0
6.0
8.0
ÎÎ
Î
t
PZL
,
t
PZH
ОООООО
Î
Output Enable TIme,
OE
to Y
ООООООО
Î
VCC = 3.3 ± 0.3V CL = 15pF
RL = 1kΩ CL = 50pF
ÎÎÎÎ
Î
6.8
9.3
ÎÎ
Î
10.5
14.0
Î
Î
1.0
1.0
ÎÎ
Î
12.5
16.0
ns
ÎÎÎООООООÎООООООО
Î
VCC = 5.0 ± 0.5V CL = 15pF
RL = 1kΩ CL = 50pF
ÎÎÎÎ
Î
4.7
6.2
ÎÎ
Î
7.2
9.2
Î
Î
1.0
1.0
ÎÎ
Î
8.5
10.5
t
PLZ
,
t
PHZ
Output Disable Time,
OE
to Y
VCC = 3.3 ± 0.3V CL = 50pF
RL = 1kΩ
11.2
15.4
1.0
17.5
ns
ÎÎÎООООООÎООООООО
Î
VCC = 5.0 ± 0.5V CL = 50pF
RL = 1kΩ
ÎÎÎÎ
Î
6.0
ÎÎ
Î
8.8
Î
Î
1.0
ÎÎ
Î
10.0
ÎÎ
Î
t
OSLH
,
t
OSHL
ОООООО
Î
Output to Output Skew
ООООООО
Î
VCC = 3.3 ± 0.3V CL = 50pF
(Note NO TAG)
ÎÎÎÎÎÎÎ
Î
1.5
ÎÎÎÎ
Î
1.5
ns
VCC = 5.0 ± 0.5V CL = 50pF
(Note NO TAG)
1.0
1.0
ns
C
in
Maximum Input Capacitance
4
10
10
pF
ÎÎ
Î
ÎÎ
Î
C
out
ОООООО
Î
ОООООО
Î
Maximum Three–State Output
Capacitance (Output in High
Impedance State)
ООООООО
Î
ООООООО
Î
ÎÎ
Î
ÎÎ
Î
Î
Î
Î
Î
6
ÎÎ
Î
ÎÎ
Î
Î
Î
Î
Î
ÎÎ
Î
ÎÎ
Î
pF
Typical @ 25°C, VCC = 5.0V
C
PD
Power Dissipation Capacitance (Note NO T AG)
18
pF
1. Parameter guaranteed by design. t
OSLH
= |t
PLHm
– t
PLHn
|, t
OSHL
= |t
PHLm
– t
PHLn
|.
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= CPD VCC fin + ICC/8 (per bit). CPD is used to determine the no–load
dynamic power consumption; PD = CPD V
CC
2
fin + ICC VCC.
NOISE CHARACTERISTICS (Input t
r
= tf = 3.0ns, CL = 50pF, VCC = 5.0V)
TA = 25°C
Symbol Parameter
Typ Max
Unit
V
OLP
Quiet Output Maximum Dynamic V
OL
0.9 1.2 V
V
OLV
Quiet Output Minimum Dynamic V
OL
– 0.9 – 1.2 V
V
IHD
Minimum High Level Dynamic Input Voltage 3.5 V
V
ILD
Maximum Low Level Dynamic Input Voltage 1.5 V
MC74VHC541
MOTOROLA VHC Data – Advanced CMOS Logic
DL203 — Rev 2
4
Figure 1.
V
CC
GND
A
Y
t
PLH
OE1 or OE2
50%
V
CC
GND
Y
t
PZL
Y
t
PZH
HIGH
IMPEDANCE
VOL +0.3V
VOH –0.3V
HIGH
IMPEDANCE
t
PLZ
t
PHZ
50% V
CC
50% V
CC
t
PHL
50%
Figure 2.
SWITCHING WAVEFORMS
50% V
CC
50%
CL*
*Includes all probe and jig capacitance
TEST
POINT
DEVICE
UNDER
TEST
OUTPUT
TEST CIRCUITS
Figure 3. Figure 4.
CL*
*Includes all probe and jig capacitance
TEST
POINT
DEVICE
UNDER
TEST
OUTPUT
1k
Ω
CONNECT TO VCC WHEN
TESTING t
PLZ
AND t
PZL
.
CONNECT TO GND WHEN
TESTING t
PHZ
AND t
PZH
.
INPUT EQUIVALENT CIRCUIT
INPUT
MC74VHC541
VHC Data – Advanced CMOS Logic
DL203 — Rev 2
5 MOTOROLA
OUTLINE DIMENSIONS
DW SUFFIX
PLASTIC SOIC WIDE PACKAGE
CASE 751D–04
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
–A–
–B–
20
1
11
10
S
A
M
0.010 (0.25) B
S
T
D20X
M
B
M
0.010 (0.25)
P10X
J
F
G
18X
K
C
–T–
SEATING
PLANE
M
R
X 45
_
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 12.65 12.95 0.499 0.510
B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
D 0.35 0.49 0.014 0.019
F 0.50 0.90 0.020 0.035
G 1.27 BSC 0.050 BSC
J 0.25 0.32 0.010 0.012
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 10.05 10.55 0.395 0.415
R 0.25 0.75 0.010 0.029
__
__
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948E–02
ISSUE A
DIMAMIN MAX MIN MAX
INCHES
6.60 0.260
MILLIMETERS
B 4.30 4.50 0.169 0.177
C 1.20 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.27 0.37 0.011 0.015
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
M 0 8 0 8
____
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
110
1120
PIN 1
IDENT
A
B
–T–
0.100 (0.004)
C
D
G
H
SECTION N–N
K
K1
JJ1
N
N
M
F
–W–
SEATING
PLANE
–V–
–U–
S
U
M
0.10 (0.004) V
S
T
20X REFK
L
L/2
2X
S
U0.15 (0.006) T
DETAIL E
0.25 (0.010)
DETAIL E
6.40 0.252
––– –––
S
U0.15 (0.006) T
MC74VHC541
MOTOROLA VHC Data – Advanced CMOS Logic
DL203 — Rev 2
6
OUTLINE DIMENSIONS
M SUFFIX
PLASTIC SOIC EIAJ PACKAGE
CASE 967–01
ISSUE O
DIM MIN MAX MIN MAX
INCHES
––– 2.05 ––– 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.18 0.27 0.007 0.011
12.35 12.80 0.486 0.504
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
––– 0.81 ––– 0.032
A
1
H
E
Q
1
L
E
_
10
_
0
_
10
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MA TERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
H
E
A
1
L
E
Q
1
_
c
A
Z
D
E
20
110
11
b
M
0.13 (0.005)
e
0.10 (0.004)
VIEW P
DETAIL P
M
L
A
b
c
D
E
e
L
M
Z
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