Datasheet MC74LVXT8051DR2, MC74LVXT8051DT, MC74LVXT8051DTR2, MC74LVXT8051D Datasheet (MOTOROLA)

MC74LVXT8051

Analog Multiplexer / Demultiplexer

High–Performance Silicon–Gate CMOS

The MC74LVXT8051 utilizes silicon–gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. This analog multiplexer/demultiplexer controls analog voltages that may vary across the complete power supply range (from VCC to GND).

The LVXT8051 is similar in pinout to the high–speed HC4051A and the metal–gate MC14051B. The Channel–Select inputs determine which one of the Analog Inputs/Outputs is to be connected by means of an analog switch to the Common Output/Input. When the Enable pin is HIGH, all analog switches are turned off.

The Channel–Select and Enable inputs are compatible with TTL–type input thresholds. The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic–level translator from 3.0V CMOS logic to 5.0V CMOS Logic or from 1.8V CMOS logic to 3.0V CMOS Logic while operating at the higher–voltage power supply .

The MC74LVXT8051 input structure provides protection when voltages up to 7V are applied, regardless of the supply voltage. This allows the MC74L VXT8051 to be used to interface 5V circuits to 3V circuits.

This device has been designed so that the ON resistance (Ron) is more linear over input voltage than Ron of metal–gate CMOS analog switches.

• Fast Switching and Propagation Speeds

• Low Crosstalk Between Switches

• Diode Protection on All Inputs/Outputs

• Analog Power Supply Range (V

• Digital (Control) Power Supply Range (V

• Improved Linearity and Lower ON Resistance Than Metal–Gate

Counterparts

• Low Noise

• In Compliance With the Requirements of JEDEC Standard No. 7A

LOGIC DIAGRAM

MC74LVXT8051

Single–Pole, 8–Position Plus Common Off

13

X0

14

X1

15

ANALOG

INPUTS/

OUTPUTS

CHANNEL

SELECT

INPUTS

X2 X3 X4 X5 X6 X7

ENABLE

12

1

DEMULTIPLEXER

5 2 4

11

A

10

B

9

C

6

– GND) = 2.0 to 6.0 V

CC

MULTIPLEXER/

– GND) = 2.0 to 6.0 V

3

COMMON

X

OUTPUT/ INPUT

PIN 16 = V PIN 8 = GND

CC

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16–LEAD SOIC

D SUFFIX

CASE 751B

16–LEAD TSSOP

DT SUFFIX CASE 948F

PIN CONNECTION AND

MARKING DIAGRAM (Top View)

V

X2 X1 X0 X3 A B C

CC

1516 14 13 12 11 10

21 34567

X4 X6 X X7 X5 Enable NC GND

For detailed package marking information, see the Marking Diagram section on page 1 1 of this data sheet.

9

8

FUNCTION TABLE – MC74LVXT8051

Control Inputs

Select

Enable

L L L L L L L L

H

X = Don’t Care

CBA

L

L L L L

H H H H X

L

H

L

H

L

H

L

H

X

ON Channels

X0 X1 X2 X3 X4 X5 X6 X7

NONE

ORDERING INFORMATION

Device Package Shipping

MC74L VXT8051D SOIC 48 Units/Rail MC74L VXT8051DR2 SOIC MC74L VXT8051DT TSSOP 96 Units/Rail MC74L VXT8051DTR2 TSSOP

2500 Units/Reel

 Semiconductor Components Industries, LLC, 1999

March, 2000 – Rev . 2

1 Publication Order Number:

MC74LVXT8051/D

MC74LVXT8051

Î

ÎÎ

ÎÎ ÎÎ

ÎÎ

Î

ÎÎ

Î

MAXIMUM RATINGS*

Symbol

V

ÎÎ

T

Positive DC Supply Voltage (Referenced to GND)

CC

Analog Input Voltage

IS

V

Digital Input Voltage (Referenced to GND)

in I

DC Current, Into or Out of Any Pin

P

Power Dissipation in Still Air, SOIC Package†

D

ОООООООООООО

Storage Temperature Range

stg

T

Lead Temperature, 1 mm from Case for 10 Seconds

L

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C

TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

Symbol

V

VIO*

T

tr, t

ÎÎ

*For voltage drops across switch greater than 1.2 V (switch on), excessive VCC current may

be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.

Positive DC Supply Voltage (Referenced to GND)

CC

Analog Input Voltage

IS

Digital Input Voltage (Referenced to GND)

in

Static or Dynamic Voltage Across Switch Operating Temperature Range, All Package Types

A

Input Rise/Fall Time

f

(Channel Select or Enable Inputs)

ООООООООООООО

Parameter

TSSOP Package†

VCC = 3.3 V ± 0.3 V VCC = 5.0 V ± 0.5 V

Value

– 0.5 to + 7.0 – 0.5 to VCC + 0.5 – 0.5 to VCC + 0.5

–20 500

450

ÎÎÎ

– 65 to + 150

260

Min

Max

2.0

6.0

0.0

V

CC

GND

V

CC

1.2

– 55

+ 85

Î

0

100

Î

0

20

Unit

mA

mW

Î

_

Unit

_

ns/V

Î

This device contains protection

V V V

circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and V

should be constrained to the

out

range GND v (Vin or V

C C

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).

) v VCC.

out

Unused outputs must be left open.

V V V V

C

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2

MC74LVXT8051

V

CC

ООООООООО

Î

ÎÎÎÎ

Î

DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND)

Symbol Parameter Condition

V

I

in

I

CC

DC ELECTRICAL CHARACTERISTICS Analog Section

Symbol

ÎÎ

R

on

ÎÎ

ÎÎÎОООООООÎООООООО

∆R

on

ÎÎ

I

off

I

on

Minimum High–Level Input

IH

Voltage, Channel–Select or Enable Inputs

Maximum Low–Level Input

IL

Voltage, Channel–Select or Enable Inputs

Maximum Input Leakage Current, Channel–Select or Enable Inputs

Maximum Quiescent Supply Current (per Package)

ООООООО

Parameter

Maximum “ON” Resistance

ООООООО

Maximum Difference in “ON” Resistance Between Any Two

ООООООО

Channels in the Same Package Maximum Off–Channel Leakage

Current, Any One Channel

Maximum Off–Channel Leakage Current, Common Channel

Maximum On–Channel Leakage Current, Channel–to–Channel

Ron = Per Spec 3.0

Vin = VCC or GND 5.5 ± 0.1 ± 1.0 ± 1.0 µA

Channel Select, Enable and VIS = VCC or GND; VIO = 0 V

Test Conditions

ООООООО

Vin = VIL or V VIS = VCC to GND

ООООООО

|IS| v 10.0 mA (Figures 1, 2) Vin = VIL or V

VIS = VCC or GND (Endpoints)

IH

|IS| v 10.0 mA (Figures 1, 2) Vin = VIL or V

VIS = 1/2 (VCC – GND)

ООООООО

IH

|IS| v 10.0 mA Vin = VIL or VIH;

VIO = VCC or GND; Switch Off (Figure 3)

Vin = VIL or VIH; VIO = VCC or GND; Switch Off (Figure 4)

Vin = VIL or VIH; Switch–to–Switch = VCC or GND; (Figure 5)

V

4.5

5.5

4.5

5.5

Guaranteed Limit

–55 to 25°C ≤85°C ≤125°C

1.2

2.0

0.53

0.8

1.2

2.0

0.53

0.8

1.2

2.0

0.53

0.8

5.5 4 40 160 µA

Guaranteed Limit

V

CC

ÎÎ

3.0

4.5

ÎÎ

5.5

3.0

4.5

ÎÎ

5.5

3.0

4.5

ÎÎ

5.5

– 55 to

V

25_C

ÎÎ

40 30

ÎÎ

25 30

25

ÎÎ

20 15

8.0

ÎÎ

8.0

v

85_C

Î

45 32

Î

28 35

28

Î

25 20

12

Î

12

v

125_C

ÎÎ

50 37

ÎÎ

30 40

35

ÎÎ

30 25

15

ÎÎ

15

5.5 0.1 0.5 1.0 µA

5.5 0.2 2.0 4.0

5.5 0.2 2.0 4.0 µA

Unit

Î

V

Ω

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3

MC74LVXT8051

V

CC

AC CHARACTERISTICS (C

Symbol Parameter

t

,

PLH

t

PHL

t

PLH

t

PHL

t

PLZ

t

PHZ

t

PZL

t

PZH

C

I/O

Maximum Propagation Delay , Channel–Select to Analog Output (Figure 9)

,

Maximum Propagation Delay , Analog Input to Analog Output (Figure 10)

,

Maximum Propagation Delay , Enable to Analog Output (Figure 11)

,

Maximum Propagation Delay , Enable to Analog Output (Figure 11)

Maximum Input Capacitance, Channel–Select or Enable Inputs 10 10 10 pF

in

Maximum Capacitance Analog I/O 35 35 35 pF (All Switches Off) Common O/I 130 130 130

= 50 pF, Input tr = tf = 3 ns)

L

V

–55 to 25°C ≤85°C ≤125°C

2.0

3.0

4.5

5.5

2.0

3.0

4.5

5.5

2.0

3.0

4.5

5.5

2.0

3.0

4.5

5.5

Feedthrough 1.0 1.0 1.0

Guaranteed Limit

30 20 15 15

4.0

3.0

1.0

1.0 30

20 15 15

20 12

8.0

35 25 18 18

6.0

5.0

2.0

2.0 35

25 18 18

25 14 10 10

40 30 22 20

8.0

6.0

2.0

2.0 40

30 22 20

30 15 12 12

Unit

ns

C

PD

Power Dissipation Capacitance (Figure 13)*

*Used to determine the no–load dynamic power consumption: PD = CPD V

2

f + ICC VCC.

CC

Typical @ 25°C, VCC = 5.0 V

45

pF

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4

MC74LVXT8051

V

CC

0dB

V

f

dB

ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)

Symbol Parameter Condition

BW Maximum On–Channel Bandwidth

or Minimum Frequency Response (Figure 6)

— Off–Channel Feedthrough Isolation

(Figure 7)

— Feedthrough Noise.

Channel–Select Input to Common I/O (Figure 8)

— Crosstalk Between Any Two

Switches (Figure 12)

THD Total Harmonic Distortion

(Figure 14)

*Limits not tested. Determined by design and verified by qualification.

fin = 1MHz Sine Wave; Adjust fin Voltage to Obtain

m at Meter Reads –3dB; RL = 50Ω, CL = 10pF

fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm at V

IS

Vin ≤ 1MHz Square Wave (tr = tf = 3ns); Adjust R at Setup so that IS = 0A; Enable = GND RL = 600Ω, CL = 50pF

fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm at V

IS

fin = 1kHz, RL = 10kΩ, CL = 50pF THD = THD

; Increase

OS

fin = 10kHz, RL = 600Ω, CL = 50pF

fin = 1.0MHz, RL = 50Ω, CL = 10pF

fin = 10kHz, RL = 600Ω, CL = 50pF

fin = 1.0MHz, RL = 50Ω, CL = 10pF

measured

in

RL = 10kΩ, CL = 10pF

– THD

VIS = 2.0VPP sine wave VIS = 4.0VPP sine wave VIS = 5.0VPP sine wave

Frequency Until

source

V

3.0

4.5

5.5

3.0

4.5

5.5

3.0

4.5

5.5

3.0

L

4.5

5.5

3.0

4.5

5.5

3.0

4.5

5.5

3.0

4.5

5.5

3.0

4.5

5.5

Limit*

25°C

80 80 80

–50 –50 –50

–37 –37 –37

25 105 135

35 145 190

–50 –50 –50

–60 –60 –60

0.10

0.08

0.05

Unit

MHz

mV

dB

PP

dB

%

40 35

30 25 20 15

, ON RESISTANCE (OHMS)

10

on

R

5

0

0 1.0 2.0 3.0 4.0

VIN, INPUT VOLTAGE (VOLTS)

125°C

85°C

25°C

–55°C

Figure 1a. T ypical On Resistance, VCC = 3.0 V

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5

MC74LVXT8051

30

25

20

15

10

, ON RESISTANCE (OHMS)

on

R

5

0

0 1.0 2.0 4.03.0 5.0

VIN, INPUT VOLTAGE (VOLTS)

125°C

85°C

25°C

–55°C

20

15

10

, ON RESISTANCE (OHMS)

on

R

5

0

0 1.0 2.0 3.0 4.0 5.0 6.0

VIN, INPUT VOLTAGE (VOLTS)

Figure 1b. T ypical On Resistance, VCC = 4.5 V Figure 1c. Typical On Resistance, VCC = 5.5 V

PLOTTER

PROGRAMMABLE

POWER SUPPLY

+–

MINI COMPUTER

DEVICE

UNDER TEST

DC ANALYZER

V

CC

125°C

85°C

25°C

–55°C

ANALOG IN COMMON OUT

GND

Figure 2. On Resistance T est Set–Up

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6

MC74LVXT8051

V

CC

V

CC

OFF OFF

16

COMMON O/I

GND

V

CC

A

NC

V

IH

6 8

Figure 3. Maximum Off Channel Leakage Current,

Any One Channel, Test Set–Up

V

CC

GND V

CC

A

ON

OFF

ANALOG I/O

16

COMMON O/I

V

CC

N/C

V

CC

V

CC

OFF OFF

16

COMMON O/I

GND

V

CC

ANALOG I/O

V

IH

6 8

Figure 4. Maximum Off Channel Leakage Current,

Common Channel, Test Set–Up

V

CC

0.1µF

f

in

16

ON

OS

CL*

dB

METER R

L

V

IL

6 8

Figure 5. Maximum On Channel Leakage Current,

Channel to Channel, T est Set–Up

V

f

in

VIL or V

0.1µF

IH

V

IS

R

L

6 8

CHANNEL SELECT

*Includes all probe and jig capacitance

OFF

CC

16

OS

CL*

dB

METER R

L

Figure 7. Off Channel Feedthrough Isolation,

T est Set–Up

6 8

*Includes all probe and jig capacitance

Figure 6. Maximum On Channel Bandwidth,

T est Set–Up

V

CC

16

11

V

IH

V

IL

Vin ≤ 1 MHz

tr = tf = 3 ns

R

L

ANALOG I/O

R

L

ON/OFF OFF/ON

6 8

CHANNEL SELECT

*Includes all probe and jig capacitance

Figure 8. Feedthrough Noise, Channel Select to

Common Out, Test Set–Up

COMMON O/I

R

L

V

CC

TEST POINT

CL*

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7

CHANNEL

SELECT

ANALOG

OUT

t

PLH

50%

MC74LVXT8051

V

CC

GND

t

PHL

V

CC

ANALOG I/O

V

CC

16

ON/OFF OFF/ON

6 8

CHANNEL SELECT

*Includes all probe and jig capacitance

COMMON O/I

TEST POINT

CL*

Figure 9a. Propagation Delays, Channel Select

to Analog Out

ANALOG

OUT

IN

t

PLH

50%

Figure 10a. Propagation Delays, Analog In

to Analog Out

t

ENABLE

ANALOG

OUT

ANALOG

OUT

f

50%

t

PZL

t

PZH

t

PLZ

t

PHZ

r

Figure 11a. Propagation Delays, Enable to

Analog Out

90% 50% 10%

10%

90%

t

PHL

V

CC

GND HIGH

IMPEDANCE

V

OL

V

OH

HIGH IMPEDANCE

V

CC

GND

Figure 9b. Propagation Delay , Test Set–Up Channel

Select to Analog Out

V

CC

16

ANALOG I/O

ON

6 8

*Includes all probe and jig capacitance

COMMON O/I

TEST POINT

CL*

Figure 10b. Propagation Delay , Test Set–Up

Analog In to Analog Out

POSITION 1 WHEN TESTING t

1 2

V

CC

1 2

V

IH

V

IL

POSITION 2 WHEN TESTING t

ANALOG I/O

ENABLE

ON/OFF

6 8

V

16

CC

PHZ PLZ

AND t

1kΩ

PZH

PZL

TEST POINT

CL*

Figure 11b. Propagation Delay, Test Set–Up

Enable to Analog Out

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8

MC74LVXT8051

V

IS

R

0.1µF

L

R

L

6

f

in

ON

OFF

16

R

L

CL*

V

OS

R

L

CL*

V

CC

ANALOG I/O

ON/OFF OFF/ON

6 8

CC

A

16

COMMON O/I

11

NC

V

CC

8

*Includes all probe and jig capacitance

Figure 12. Crosstalk Between Any T wo

Figure 13. Power Dissipation Capacitance,

Switches, T est Set–Up

dB

–100

0 –10 –20 –30 –40 –50

–60 –70 –80 –90

FUNDAMENTAL FREQUENCY

1.0 2.0 3.125

V

IS

0.1µF

f

in

6 8

V

CC

16

ON

*Includes all probe and jig capacitance

V

OS

TO

DISTORTION

CL*

METER

R

L

CHANNEL SELECT

Test Set–Up

DEVICE SOURCE

FREQUENCY (kHz)

Figure 14a. T otal Harmonic Distortion, Test Set–Up Figure 14b. Plot, Harmonic Distortion

APPLICATIONS INFORMATION

The Channel Select and Enable control pins should be at VCC or GND logic levels. VCC being recognized as a logic high and GND being recognized as a logic low. In this example:

VCC = +5V = logic high

GND = 0V = logic low

The maximum analog voltage swing is determined by the supply voltage VCC. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below GND. In this example, the difference between VCC and GND is five volts. Therefore, using the configuration of Figure 15, a maximum analog signal of five volts peak–to–peak can be controlled. Unused analog inputs/outputs may be left floating (i.e., not

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connected). However, tying unused analog inputs and outputs to VCC or GND through a low value resistor helps minimize crosstalk and feedthrough noise that may be picked up by an unused switch.

Although used here, balanced supplies are not a requirement. The only constraints on the power supplies are that:

VCC – GND = 2 to 6 volts

When voltage transients above VCC and/or below GND are anticipated on the analog channels, external Germanium or Schottky diodes (Dx) are recommended as shown in Figure 16. These diodes should be able to absorb the maximum anticipated current surges during clipping.

9

MC74LVXT8051

+5V

0V

+3V

GND

V

CC

D

16

D

GND

x

ANALOG

SIGNAL

V

+5V

16

11 10

9

ANALOG

SIGNAL

TO EXTERNAL LSTTL COMPATIBLE CIRCUITRY 0 to VIH DIGITAL SIGNALS

ON

6 8

+5V

0V

CC

D

GND

x

ON/OFF

x

8

Figure 15. Application Example Figure 16. External Germanium or

Schottky Clipping Diodes

ANALOG

SIGNAL

ON/OFF

6 8

16

11 10

9

+3V

ANALOG

SIGNAL

+3V

GND

1.8V – 2.5V

CIRCUITRY

+5V

GND

ANALOG

SIGNAL

ON/OFF

6 8

16

11 10

9

+5V

ANALOG

SIGNAL

+5V

GND

+5V

1.8V – 2.5V

CIRCUITRY

ENABLE

MC74VHCT1GT50 BUFFERS

VCC = 3.0V

a. Low V oltage Logic Level Shifting Control b. 2–Stage Logic Level Shifting Control

Figure 17. Interfacing to Low Voltage CMOS Outputs

11

A

10

B

9

C

6

LEVEL

SHIFTER

LEVEL

SHIFTER

LEVEL

SHIFTER

LEVEL

SHIFTER

13

X0

14

X1

15

X2

12

X3

1

X4

5

X5

2

X6

Figure 18. Function Diagram, L VXT8051

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10

4

X7

3

X

MC74LVXT8051

MARKING DIAGRAMS

(Top View)

–T

SEATING

–

PLANE

1516 14 13 12 11 10

LVXT8051

9

1516 14 13 12 11 10

LVXT

9

8051

AWLYWW*

21 34567

16–LEAD SOIC

D SUFFIX

CASE 751B

8

AL YW*

21 34567

16–LEAD TSSOP

DT SUFFIX CASE 948F

8

*See Applications Note #AND8004/D for date code and traceability information.

P ACKAGE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

–A

–

916

–B

P 8 PL

1

–

8

0.25 (0.010) B

M M

G

K

R X 45°

F

C

J

D

16 PL

0.25 (0.010) T B A

M

S S

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

MILLIMETERS INCHES

MIN MINMAX MAX

DIM

A

9.80

B

3.80

C

1.35

D

0.35

F

0.40

G J

0.19

K

0.10

M

0°

P

5.80

R

0.25

10.00

4.00

1.75

0.49

1.25

1.27 BSC 0.050 BSC

0.25

0.25 7°

6.20

0.50

0.386

0.150

0.054

0.014

0.016

0.008

0.004

0.229

0.010

0.393

0.157

0.068

0.019

0.049

0.009

0.009 7°

0°

0.244

0.019

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11

0.10 (0.004)

–T–

SEATING PLANE

L

U0.15 (0.006) T

PIN 1 IDENT.

U0.15 (0.006) T

D

S

2X L/2

S

MC74LVXT8051

P ACKAGE DIMENSIONS

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948F–01

ISSUE O

16X REFK

T

U

B

–U–

S

H

N

S

J

N

DETAIL E

J1

0.25 (0.010)

F

K

K1

SECTION N–N

M

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–.

INCHESMILLIMETERS

–W–

DIM MIN MAX MIN MAX

A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C ––– 1.20 ––– 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.18 0.28 0.007 0.011 J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC M 0 8 0 8

____

0.10 (0.004) V

16

1

M

9

8

A

–V–

C

G

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12

MC74L VXT8051/D

Datasheet MC74LVXT8051DR2, MC74LVXT8051DT, MC74LVXT8051DTR2, MC74LVXT8051D Datasheet (MOTOROLA)

Specifications and Main Features

Frequently Asked Questions

User Manual