MOTOROLA MC74LCX646DWR2, MC74LCX646DTR2 Datasheet
SEMICONDUCTOR TECHNICAL DATA
1
REV 2
Motorola, Inc. 1996
11/96
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The MC74LCX646 is a high performance, non–inverting octal
transceiver/registered transceiver operating from a 2.7 to 3.6V supply.
High impedance TTL compatible inputs significantly reduce current
loading to input drivers while TTL compatible outputs offer improved
switching noise performance. A VI specification of 5.5V allows
MC74LCX646 inputs to be safely driven from 5V devices. The
MC74LCX646 is suitable for memory address driving and all TTL level
bus oriented transceiver applications.
Data on the A or B bus will be clocked into the registers as the
appropriate clock pin goes from a LOW–to–HIGH logic level. Output
Enable (OE
) and DIR pins are provided to control the transceiver outputs.
In the transceiver mode, data present at the high impedance port may be
stored in either the A or the B register or in both. The select controls (SBA,
SAB) can multiplex stored and real–time (transparent mode) data. The
direction control (DIR) determines which bus will receive data when the
enable OE
is active LOW. In the isolation mode (OE HIGH), A data may
be stored in the B register or B data may be stored in the A register. Only
one of the two buses, A or B, may be driven at one time.
• Designed for 2.7 to 3.6V V
CC
Operation
• 5V T olerant — Interface Capability With 5V TTL Logic
• Supports Live Insertion and Withdrawal
• I
OFF
Specification Guarantees High Impedance When VCC = 0V
• LVTTL Compatible
• LVCMOS Compatible
• 24mA Balanced Output Sink and Source Capability
• Near Zero Static Supply Current in All Three Logic States (10µA)
Substantially Reduces System Power Requirements
• Latchup Performance Exceeds 500mA
• ESD Performance: Human Body Model >2000V; Machine Model >200V
Pinout: 24–Lead Package (Top View)
2324 22 21 20 19 18
21 34567
V
CC
17
8
16
9
15
10
CBA SBA OE
B0 B1 B2 B3 B4 B5
CAB SAB DIR A0 A1 A2 A3 A4 A5 A6
14
11
13
12
B6 B7
A7 GND
DW SUFFIX
PLASTIC SOIC
CASE 751E–04
DT SUFFIX
PLASTIC TSSOP
CASE 948H–01
24
1
24
1
SD SUFFIX
PLASTIC SSOP
CASE 940D–03
24
1
LOW–VOLTAGE CMOS
OCTAL TRANSCEIVER/
REGISTERED TRANSCEIVER
PIN NAMES
Function
Side A Inputs/Outputs
Side B Inputs/Outputs
Clock Pulse Inputs
Select Control Inputs
Output Enable Inputs
Pins
A0–A7
B0–B7
CAB, CBA
SAB, SBA
DIR, OE
LOGIC DIAGRAM
C
D
Q
OE
DIR
CBA
SBA
SAB
CAB
C
D
Q
A0
B0
1 of 8 Channels
To 7 Other Channels
1
3
21
22
2
23
MC74LCX646
MOTOROLA LCX DATA
BR1339 — REV 3
2
FUNCTION TABLE
Inputs
Data Ports
OE DIR CAB CBA SAB SBA An Bn
O
perating Mode
H X Input Input
↑ ↑ X X X X Isolation, Hold Storage
↑ ↑ X X l
h
X
X
X
X
l
h
Store A and/or B Data
L H Input Output
↑ X* L X L
H
L
H
Real Time A Data to B Bus
H X X QA Stored A Data to B Bus
↑ X* L X l
h
L
H
Real Time A Data to B Bus; Store A Data
H X L
H
QA
QA
Clock A Data to B Bus; Store A Data
L L Output Input
X* ↑ X L L
H
L
H
Real Time B Data to A Bus
X H QB X Stored B Data to A Bus
X* ↑ X L L
H
l
h
Real Time B Data to A Bus; Store B Data
X H QB
QB
L
H
Clock B Data to A Bus; Store B Data
H = High Voltage Level; h = High Voltage Level One Setup Time Prior to the Low–to–High Clock Transition; L = Low Voltage Level; l = Low Voltage Level One Setup
Time Prior to the Low–to–High Clock T ransition; X = Don’t Care; ↑ = Low–to–High Clock Transition; ↑
= NOT Low–to–High Clock Transition; QA = A input storage register;
QB = B input storage register; * = The clocks are not internally gated with either the Output Enables or the Source Inputs. Therefore, data at the A or B ports may be
clocked into the storage registers, at any time. For ICC reasons, Do Not Float Inputs.
MC74LCX646
LCX DATA
BR1339 — REV 3
3 MOTOROLA
BUS APPLICATIONS
BUS A
BUS B
OELDIR
L
CABXCBAXSABXSBA
L
Real Time Transfer – Bus B to
Bus A
BUS A
BUS B
OELDIR
H
CABXCBAXSABLSBA
X
Real Time Transfer – Bus A to
Bus B
BUS B
OE
X
X
H
DIR
X
X
X
CAB
↑
X
↑
CBA
X
↑
↑
SAB
X
X
X
SBA
X
X
X
Store Data from Bus A, Bus B or
Busses A and B
BUS A
BUS B
OE
L
L
DIR
L
H
CAB
X
H or L
CBA
H or L
X
SAB
X
H
SBA
H
X
Transfer Storage Data to Bus A
or Bus B
BUS A
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