Motorola MC74LCX16373DT Datasheet
SEMICONDUCTOR TECHNICAL DATA
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The MC74LCX16373 is a high performance, non–inverting 16–bit
transparent latch operating from a 2.7 to 3.6V supply. The device is byte
controlled. Each byte has separate Output Enable and Latch Enable
inputs. These control pins can be tied together for full 16–bit operation.
High impedance TTL compatible inputs significantly reduce current
loading to input drivers while TTL compatible outputs offer improved
switching noise performance. A VI specification of 5.5V allows
MC74LCX16373 inputs to be safely driven from 5V devices.
The MC74LCX16373 contains 16 D–type latches with 3–state
5V–tolerant outputs. When the Latch Enable (LEn) inputs are HIGH, data
on the Dn inputs enters the latches. In this condition, the latches are
transparent, i.e., a latch output will change state each time its D input
changes. When LE is LOW, the latches store the information that was
present on the D inputs a setup time preceding the HIGH–to–LOW
transition of LE. The 3–state outputs are controlled by the Output Enable
(OEn
) inputs. When OE is LOW, the outputs are enabled. When OE is
HIGH, the standard outputs are in the high impedance state, but this does
not interfere with new data entering into the latches.
• Designed for 2.7 to 3.6V V
• 5.4ns Maximum t
pd
• 5V T olerant — Interface Capability With 5V TTL Logic
• Supports Live Insertion and Withdrawal
• I
Specification Guarantees High Impedance When VCC = 0V
OFF
• LVTTL Compatible
• LVCMOS Compatible
• 24mA Balanced Output Sink and Source Capability
• Near Zero Static Supply Current in All Three Logic States (20µA)
Substantially Reduces System Power Requirements
• Latchup Performance Exceeds 500mA
• ESD Performance: Human Body Model >2000V; Machine Model >200V
Operation
CC
LOW–VOLTAGE
CMOS 16–BIT
TRANSPARENT LATCH
PLASTIC TSSOP PACKAGE
PIN NAMES
Pins
OEn
LEn
D0–D15
O0–O15
DT SUFFIX
CASE 1201–01
Function
Output Enable Inputs
Latch Enable Inputs
Inputs
Outputs
11/96
Motorola, Inc. 1996
1
REV 1
MC74LCX16373
V
CC
GND
V
CC
O15
LOGIC DIAGRAM
1
LE1OE1
481
D0O0
472
D1O1
463
GNDGND
454
D2O2
445
D3O3
436
V
427
CC
D4O4
418
D5O5
409
GND
3910
D6O6
3811
D7O7
3712
D8O8
3613
D9O9
3514
GNDGND
3415
D10O10
3316
D11O11
3217
V
3118
CC
D12O12
3019
D13O13
2920
GNDGND
2821
D14O14
2722
D15
2623
LE2OE2
2524
OE1
LE1
D0
D1
D2
D3
D4
D5
D6
D7
48
47
46
44
43
41
40
38
37
nLE
D
nLE
D
nLE
D
nLE
D
nLE
D
nLE
D
nLE
D
nLE
D
2
3
5
6
8
9
11
12
O0
O1
O2
O3
O4
O5
O6
O7
Q
Q
Q
Q
Q
Q
Q
Q
OE2
LE2
D8
D9
D10
D11
D12
D13
D14
D15
24
25
36
35
33
32
30
29
27
26
nLE
D
nLE
D
nLE
D
nLE
D
nLE
D
nLE
D
nLE
D
nLE
D
13
14
16
17
19
20
22
23
O8
O9
O10
O11
O12
O13
O14
O15
Q
Q
Q
Q
Q
Q
Q
Q
Inputs Outputs Inputs Outputs
LE1 OE1 D0:7 O0:7 LE2 OE2 D8:15 O8:15
X H X Z X H X Z
H L L L H L L L
H L H H H L H H
L L X O0 L L X O0
H = High V oltage Level; L = Low V oltage Level; Z = High Impedance State; X = High or Low Voltage Level and T ransitions Are Acceptable, for I
reasons, DO NOT FLOAT Inputs
MOTOROLA LCX DATA
2
BR1339 — REV 3
CC
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