Motorola MC74LCX16240ADT Datasheet
SEMICONDUCTOR TECHNICAL DATA
1
REV 0
Motorola, Inc. 1996
8/96
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The MC74LCX16240A is a high performance, inverting 16–bit buffer
operating from a 2.7 to 3.6V supply . The device is nibble controlled. Each
nibble has separate Output Enable inputs which can be tied together for
full 16–bit operation. High impedance TTL compatible inputs significantly
reduce current loading to input drivers while TTL compatible outputs offer
improved switching noise performance. A VI specification of 5.5V allows
MC74LCX16240A inputs to be safely driven from 5V devices. The
LCX16240A is suitable for memory address driving and all TTL level bus
oriented transceiver applications.
Current drive capability is 24mA at the outputs. The Output Enable
(OEn
) inputs, when HIGH, disable the outputs by placing them in a HIGH
Z condition.
• Designed for 2.7 to 3.6V V
CC
Operation
• 4.9ns Maximum t
pd
• 5V T olerant — Interface Capability With 5V TTL Logic
• Supports Live Insertion and Withdrawal
• I
OFF
Specification Guarantees High Impedance When VCC = 0V
• JEDEC Standard JESD–36 Compatible
• LVTTL Compatible
• LVCMOS Compatible
• 24mA Balanced Output Sink and Source Capability
• Near Zero Static Supply Current in All Three Logic States (20µA)
Substantially Reduces System Power Requirements
• Latchup Performance Exceeds 500mA
• ESD Performance: Human Body Model >2000V; Machine Model >200V
The MC74LCX16240A contains sixteen inverting buffers with 3–state
5V–tolerant outputs. The device is nibble controlled with each nibble
functioning identically, but independently. The control pins may be tied
together to obtain full 16–bit operation. The 3–state outputs are controlled
by an Output Enable (OEn
) input for each nibble. When OEn is LOW, the
outputs are on. When OEn
is HIGH, the outputs are in the high
impedance state.
LOW–VOLTAGE
CMOS 16–BIT BUFFER
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 1201–01
PIN NAMES
Function
Output Enable Inputs
Inputs
Outputs
Pins
OEn
D0–D15
O0
–O15
MC74LCX16240A
MOTOROLA LCX DATA
BR1339 — REV 3
2
LOGIC DIAGRAM
481
OE2
OE1
472
D0O0
463
D1O1
454
GNDGND
445
D2O2
436
D3O3
427
V
CC
V
CC
418
D4O4
409
D5O5
3910
GNDGND
3811
D6O6
3712
D7O7
3613
D8O8
3514
D9
O9
3415
GNDGND
3316
D10O10
3217
D11O11
3118
V
CC
V
CC
3019
D12O12
2920
D13O13
2821
GNDGND
2722
D14O14
2623
D15O15
2524
OE3
OE4
OE1
OE2
D0:3
D4:7
O0:3
O4:7
OE3
OE4
D8:11
D12:15
O8:11
O12:15
One of Four
1
48
25
24
OE1 D0:3 O0:3 OE2 D4:7 O4:7 OE3 D8:11 O8:11 OE4 D12:15 O12:15
L L H L L H L L H L L H
L H L L H L L H L L H L
H X Z H X Z H X Z H X Z
H = High Voltage Level; L = Low V oltage Level; Z = High Impedance State; X = High or Low Voltage Level and T ransitions Are Acceptable, for I
CC
reasons, DO NOT FLOAT Inputs
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